JP2003077287A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which while data rewriting can be electrically performed, memory size can be reduced, and manufacturing cost can be reduced. SOLUTION: The nonvolatile semiconductor memory is provided with a plurality of cell transistors CT11, CT12,..., a plurality of transistors for selection ST1, ST2,..., row lines, column lines, a first decoder 37 and a second decoder 39. The transistor for selection selects (n) pieces (n>=2) of the same column out of the plurality of cell transistors. Control gate lines of cell transistors of the same row out of a plurality of cell transistors are connected respectively to the row lines. The transistors for selection are connected to the column lines. The first decoder supplies decode-signals W11, W12,... to each control gate of cell transistors of the same row via the row lines. The second decoder supplies decode-signals X1, X2,... to the transistors for selection, and selectively controls conduction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device of this type, that is, a memory cell of an EEPROM, electrons are injected into a floating gate through an oxide film having a thickness of about 100 Å which is much thinner than a gate oxide film. Data is rewritten by releasing it. Figure 1
4 is a symbol diagram of a cell transistor that constitutes such a memory cell, where the control gate voltage is V _CG , the drain voltage is V _D , the source voltage is V _S , and the drain current is I _{D. The} drain current _{ID with} respect to _CG exhibits the characteristics shown in FIG. In FIG. 15, a curve 11 is a characteristic in an initial state, and a curve 12 is a characteristic when electrons are injected into the floating gate, and the threshold voltage is increased by the injection of electrons. Further, the curve 13 is a characteristic in a state where electrons are emitted from the floating gate, and the threshold voltage is lowered and becomes negative due to the emission of electrons. In memory cells using such cell transistors, curves 12 and 13 above are used.
"0" and "1" of data are stored by utilizing the characteristic of.

FIG. 16 is an EEPRO constructed by arranging the cell transistors shown in FIG. 14 in a matrix.
The circuit configuration example of M is shown, and EE currently on the market
The PROM has many such circuit configurations. As shown,
A selection MOS transistor ST is connected in series to each cell transistor CT, and one memory cell 14 is composed of two transistors CT and ST.

In the above structure, when injecting electrons into the floating gate of the cell transistor CT, the gate of the selection transistor ST and the cell transistor C are selected.
The high voltage V _G , V _CG is applied to the control gate of T, and the column line 15 is set to 0V. On the other hand, when electrons are emitted, the gate of the selection transistor ST and the column line 15 are set to a high voltage, and the control gate of the cell transistor CT is set to 0V. As a result, a high voltage is applied to the drain of the cell transistor CT, and electrons are emitted from the floating gate to the drain.

FIG. 17A is a pattern plan view of a region 16 surrounded by a chain line in the circuit shown in FIG.
FIG. 1 shows a cross-sectional structure taken along the line AA ′ of FIG.
7 (b). 17A and 17B, portions corresponding to those in FIG. 16 are denoted by the same reference numerals, 17 is a source region of the cell transistor CT, 18 is a drain of the cell transistor CT and a selection transistor ST. Source region, 19 is a drain region of the selection transistor ST,
20 is a floating gate of the cell transistor CT, 21 is a control gate of the cell transistor CT, and 22 is a selection transistor S.
A gate of T, a thin oxide film portion 23, and a contact portion 24 between the column line 15 and the selecting transistor ST.

However, in the above-mentioned structure, one memory cell is formed by two transistors.
There is a drawback that the memory cell size becomes large and the chip cost becomes high. Therefore, attention has been paid to a so-called UVEPROM, which is an ultraviolet erasable non-volatile semiconductor memory device capable of forming one memory cell with one transistor. U
Since a VEPROM has one memory cell formed by only one transistor, a chip having the same area can obtain a capacity twice as large as that of an EEPROM, and the same memory scale (capacity) can reduce the chip size. Because you can, E
It has a higher penetration rate than EPROM. However, UVE
When injecting electrons into a memory cell, the PROM requires a large current because a current is passed through the channel to generate hot electrons near the drain and inject them into the floating gate. Therefore, an external power supply for programming is required. On the other hand, in the EEPROM, electrons are emitted and injected from the floating gate by utilizing the tunnel effect, so that data can be written with a high voltage from the booster circuit provided in the chip. Therefore, there is an advantage that it can be used with a single power source of 5V. UVEPROM is
While the memory cells of the entire chip must be erased at the same time, the EEPROM also has an advantage that data can be rewritten for each memory cell depending on the method of configuring the memory cell array.

As described above, the EEPROM and the UVEPRO
M has merits and demerits, but if the memory size of the EEPROM can be reduced to a size comparable to that of the UVEPROM and the cost can be reduced, it can be used with a single power supply of 5 V, so it can be said that it is easy for users to use.

[0008]

As described above, the conventional EEPROM has the advantage that it can be operated by a single power source, and the UVEPROM has the advantage that data can be rewritten for each memory cell one by one. There is a problem that the memory cell size becomes larger and the cost becomes higher than that.

The present invention has been made in view of the above circumstances. An object of the present invention is to make it possible to electrically rewrite data while reducing the memory cell size and reducing the cost. A semiconductor memory device.

[0010]

That is, a nonvolatile semiconductor memory device of the present invention has a plurality of cell transistors each having a floating gate and a control gate and storing data in accordance with the charge accumulation state of the floating gate. A selection transistor having one end connected to the n cell transistors for selecting n (n ≧ 2) in the same column of the plurality of cell transistors, and the same row of the plurality of cell transistors. Row lines to which the control gates of the cell transistors are connected, column lines to which the other ends of the selection transistors are connected, and control signals to the control gates of the cell transistors in the same row through the row lines. And a second decoder for supplying a decode signal to the selection transistor to selectively control conduction. The groups of the n cell transistors and the selection transistors connected to the n cell transistors, which are arranged in different rows, are provided with the decode signals independently of each other by the first decoder. The supplied, non-selected groups are characterized by being unaffected by the selected groups.

According to the above-mentioned structure, it is possible to electrically rewrite data but to reduce the memory cell size and to reduce the cost.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the memory cell section and its peripheral circuit section. The output D of the data input circuit 25 is supplied to the gate of an N-channel type MOS transistor 26 whose one end is connected to the high voltage power supply Vp. A selection transistor ST and cell transistors CT1 to CT4 are provided between the other end of the transistor 26 and the ground point (reference potential).
Are connected in series. A signal X1 for selecting the cell transistors CT1 to CT4 is supplied to the gate of the selecting transistor ST, and the cell transistors CT1 to CT4 are selected.
Signals W1 to W4 for selecting these cell transistors CT1 to CT4 are respectively provided on the control gates of CT4.
Is supplied. At the connection point (node N1) between the transistor 26 and the selecting transistor ST, an N-channel MOS transistor 27 is conductively controlled by a signal R which becomes "1" level during reading and "0" level during programming.
Is connected to one end of the transistor 27, and the other end of the transistor 27 is connected to the input end of the data detection circuit 28. Further, between the input end side node N2 of the data detection circuit 28 and the power supply V, a P-channel type MOS whose gate is connected to this node N2.
A transistor 29 is connected as a load for reading.

Although a combination of the selection transistor ST and the cell transistors CT1 to CT4 is referred to as a memory cell for convenience sake, this memory cell is different from a general memory cell, and one memory cell has four bits (serial connection). Data of the number corresponding to the number of cell transistors) is stored, which is equivalent to four conventional memory cells.

The operation of the above arrangement will be described below. FIG. 2 is a timing chart of each signal during programming in the circuit of FIG. First, the signal R is set to the "0" level to turn off the transistor 27, the signals X1 and W1 to W4 are set to the high voltage level at the time t0, and as shown in FIGS. The thin oxide film of the cell transistor shown (film thickness 100
Electrons are injected into the floating gates of the cell transistors CT1 to CT4 via (33) Angstroms. The signals W4 to W1 are sequentially set to 0 V at the next timings t1 to t4. When the signals W1 to W4 are set to 0V and the data D output from the data input circuit 25 is at "1" level, the transistor 26 is turned on, and the transistor 26 and the selection transistor are selected from the high voltage power supply Vp. A high voltage is applied to the drain of the corresponding cell transistor via ST, and electrons are emitted from the floating gate due to the tunnel effect. In FIG. 2, when the signals W3 and W1 are set to 0V, the data D is at "1" level (time t2 to t3, time t4 to t5.
), Electrons injected into the floating gates of the cell transistor CT3 and the cell transistor CT1 are emitted. What is important here is not the application of 0 V to the control gate and the high voltage to the drain, but the strength of the electric field in the region where the tunnel effect occurs, and the electric field which selectively causes the tunnel effect is applied to each cell transistor. As a result, data is selectively programmed in each cell transistor. For example,
Since the cell transistor CT4 does not have an electric field that causes the tunnel effect in the region where the tunnel effect occurs after the time t1, the transfer of electrons in the floating gate is not performed.

During the time t0 to t1, the electrons injected into the floating gates of the cell transistors CT1 to CT4 are
Time t1 to t2, time t2 to t3, time t3 to t4
Between the cell transistors CT1 to CT depending on whether the data D is at "1" level or "0" level between time t4 and time t5.
Programming is performed depending on whether or not electrons are emitted from the floating gate of 4.

At the timing between times t1 and t2, the signals X1 and W1 to W3 are set to the high voltage level, and the selection transistor ST and the cell transistors CT1 to CT are set.
3 turns on. At this time, the signal W4 is set to 0V, and the data D is at the "0" level.
Is off and no high voltage is applied to the cell transistor CT4, so that electrons injected into the floating gate of the cell transistor CT4 are not emitted.

At the timing between times t2 and t3, the signals X1 and W1 and W2 are set to the high voltage level, and the selection transistor ST and the cell transistors CT1 and CT are set.
2 turns on. At this time, the signal W3 is set to 0V, and the data D is at the "1" level.
Is turned on, and a high voltage is applied to the cell transistor CT3. At this time, since 0V is applied to the control gate of the cell transistor CT3, the electric field applied to the thin insulating film is increased and the tunnel effect occurs, so that the electrons injected into the floating gate of the cell transistor CT3 are emitted. It At this time, the transistor 26 and the cell transistor CT
Since the cell transistor CT3 exists between the cell transistor 4 and the cell 4, the cell transistor CT4 is not subjected to a high voltage, and only the cell transistor CT3 is programmed.

At the timing between times t3 and t4, signals X1 and W1 are at a high voltage level and signals W2 and W4 are at 0V.
Is set to. At this time, since the data D is at "0" level, the transistor 26 is turned off and the cell transistor CT
Since a high voltage is not applied to 2, the electrons injected into the floating gate of this cell transistor CT2 are not emitted.

At the timing between times t4 and t5, the signal X1 is set to the high voltage level, the signals W1 to W4 are set to 0V, and the selection transistor ST is turned on. At this time, since the data D is at "1" level, the transistor 26 is turned on, and a high voltage is applied to the cell transistor CT1, so that the electric field applied to the thin insulating film is increased and the tunnel effect occurs. The electrons injected into the floating gate of CT1 are emitted. At this time, the transistor
Since the cell transistor CT1 is present between 26 and the cell transistors CT2 to CT4, a high voltage is not applied to the cell transistors CT2 to CT4.
Only the cell transistor CT1 is programmed.

On the other hand, at the time of reading data, the signals R and X1 are set to "1" level, and the control gate of the cell transistor to be read is set to 0V. At this time, the gates of the other cell transistors are set to the "1" level. The timing chart of FIG. 3 is for sequentially reading data from the cell transistors CT4 to CT1, and between the time t0 and t1, the cell transistor CT4
From the cell transistor CT3 between the times t1 and t2, from the cell transistor CT2 between the times t2 and t3, the time t3
, T4, data is read from the cell transistor CT1. If the signal W1 is set to 0V and the signals W2 to W4 are set to "1" level, the cell transistor C
Data is read from T1. Assuming that the programming is performed as described above, since electrons are emitted from the floating gate of the cell transistor CT1, the threshold voltage thereof is negative and the signal W1 is turned on even when the signal W1 is 0V. Since the control gates of the other cell transistors CT2 to CT4 are at "1" level, they are in the ON state. Therefore, all the cell transistors CT1 to CT4 are turned on,
The potential of the node N2 drops. This is the data detection circuit 28
Then, the data is read from the cell transistor CT1. In addition, the signal W2 becomes 0V and the cell transistor C
When T2 is selected, this cell transistor CT2
Since electrons remain injected into the control gate,
If it is V, it is turned off. Therefore, the node N2 is charged by the transistor 29, which charges the data detection circuit 28.
Detect by. It is necessary to set the threshold voltages of the cell transistors CT1 to CT4 in a state where electrons are injected so that they are turned on when the control gates thereof reach the "1" level.

FIGS. 4 (a) to 4 (c) show a structural example of a transistor suitable for the cell transistors CT1 to CT4 in FIG. 1, in which a part of the insulating film on the channel region is thinned to about 100 angstroms. The cell size is reduced by forming an oxide film. (A) is a pattern plan view, (b) is a sectional view taken along the line BB 'in (a), and (c) is a sectional view taken along the line CC' in (a). Here, 30 is a P-type silicon substrate, 31 and 32 are N ⁺ -type sources,
The drain region, 33 is a thin oxide film, 34 is a floating gate, and 35 is a control gate.

FIGS. 5A and 5B show another example of the structure suitable for the cell transistors CT1 to CT4 in FIG. 1, in which the entire insulating film on the channel region is thinly oxidized to about 100 angstroms. It is formed of the film 33. 5, the same parts as those in FIG. 4 are designated by the same reference numerals, (a) is a pattern plan view, and (b) is a C of FIG.
It is sectional drawing which followed the C'line.

FIGS. 6 (a) and 6 (b) show still another configuration example suitable for the cell transistors CT1 to CT4 in FIG. 1, in which a part of the channel region is a depletion type transistor. FIG. 7A is a plan view of the pattern, and FIG. 8B is a sectional view taken along the line BB ′ of FIG. With such a configuration, even if the cell transistor has a threshold voltage at which the cell transistor does not turn on even when a “1” level signal is supplied to the control gate due to too much electron injection,
^The source / drain region 31, due to the ⁻ type impurity region 36,
Current is flowing because 32 are connected. To read data from the cell transistor having such a configuration, when a "0" level potential is applied to the control gate, the difference in the amount of current generated depending on whether or not electrons are injected into the floating gate is detected. By.

FIG. 7 shows a configuration example of a non-volatile semiconductor memory device configured by arranging the memory cells described above in a matrix. In FIG. 7, reference numeral 37 is a row decoder, 38 is a first column decoder, 39 is a second column decoder, and the data input / output lines IO1 to IO8 are connected to the circuits surrounded by the alternate long and short dash line in FIG. It Above row decoder
37 indicates signals X1, X2, ..., Signals W11, W12 ,.
n, signals W21, W22, ..., W2n are output to select the row direction of the memory cell array. Further, the column decoder 38 outputs signals Y1, Y2, ..., Ym to selectively control conduction of the column selection MOS transistors Q1 to Qm to input data to one of the memory cell blocks B1 to Bm. It is for supplying data to be programmed or for deriving read data via the output lines IO1 to IO8. On the other hand, the column decoder 39 outputs signals Z2 to Z2.
This is for sequentially designating the memory cell blocks B1 to Bm during programming by outputting m to selectively control conduction of the depletion type array division MOS transistors QD2 to QDm.

In the structure as described above, the programming is performed from the memory cell located far from the row decoder 27. FIG. 8 is a timing chart of each signal during this programming. That is, programming is performed from the memory cell connected to the signal line X1 of the memory cell block Bm.
In this program, signals X1, Ym, Z2 to Zm
As a result, a high voltage is applied. In this state, the signal W11-
W1n is set to a high voltage to inject electrons into the floating gates of all cell transistors. Next, the signals W1n to W11 are sequentially set to the "0" level. At this time, when the control gate is at the "0" level, the program data is transferred to the data input / output lines IO1 to IO8, the column selection transistor Qm,
Electrons are emitted only when a high voltage is applied to the drain through the selection transistor STm and the selection transistor STm, and data is programmed in each cell transistor.

FIG. 9 shows a timing chart at the time of reading. Signal X, which corresponds to the memory cell to be selected,
Y becomes "1" level. In addition, one of the signals W11 to W1n corresponding to each cell transistor of the selected memory cell is selected.
One becomes "0" level, and all the control gates of non-selected cell transistors become "1" level. by this,
Data is read as in the case of FIG.

FIG. 10 is a truth table summarizing the levels of the signals W11 to W1n. When the input data I is at "1" level, all the signals W11 to W1n are at "1" level. Electrons are injected into the floating gate of the transistor. Further, when the data I is at "0" level and R is at "0" level, the program is individually performed, and when R is at "1" level, the data is read.

FIG. 11 shows the signals X1, X2, and
A truth table of W11 to W14 and W21 to W24 is shown for three addresses A0 to A2. In this example, at the time of reading, for example, if X1 = 0, the signals W11 to W
Although all 14 are set to the "0" level, one of W11 to W14 may be set to the "0" level as in the case of X1 = 1.

FIG. 12 shows another embodiment of the present invention, in which a signal φ between the cell transistor CT4 in FIG. 1 and the ground point is set to a "0" level during programming and a "1" level during reading. An N-channel type MOS transistor 40 whose conduction is controlled is provided. 12
1, the same components as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted. With this configuration, when a high voltage is applied to the drain during programming,
Even if there is a leak current from the cell transistors CT1 to CT4, the leak current can be interrupted by the transistor 40, so that the drain potential can be prevented from lowering and the program characteristic can be prevented from being deteriorated. The transistor 40 may be shared by a plurality of cell blocks.

FIG. 13 shows another configuration example when the circuit of FIG. 1 is formed in a matrix. This circuit corresponds to one of the memory cell blocks B1 to Bm shown in FIG. 7, and in such a structure, the MOS transistors QT1, QT2 controlled by the signals X1, X2, ... At the control gates of the cell transistors. , And the signals are input through these transistors QT1, QT2, ..., Therefore, the signals Z2, Z3, ..., Z which are input to the memory blocks corresponding to the signals W11, W12 ,.
If the signals W1n1, ..., W121, W111 input to the corresponding memory blocks are set to a high voltage by taking the logic of m or the like, it is possible to freely program from any memory block. At this time, if the two-layer aluminum wiring is used and the signals W111, W121, ..., W1n1 are wired by the second aluminum wiring, the chip size is increased by increasing the wiring of the signals W111, W121, ..., W1n1. Is less.

Further, a latch circuit is provided for each column line so that data to be written in these latch circuits is latched so that each column line can be latched based on the latched data in one row of memory cells. By setting the potential to a high potential or to 0 V, all the memory cells on all the column lines for one row can be programmed, so that the array dividing MOS transistors QD2 to QDm shown in FIG. 7 can be omitted.

[0032]

As described above, according to the present invention,
It is possible to obtain a nonvolatile semiconductor memory device in which data can be electrically rewritten, the memory cell size can be reduced, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG.

4 is a diagram showing a configuration example of a cell transistor in the circuit of FIG.

5 is a diagram showing a configuration example of a cell transistor in the circuit of FIG.

6 is a diagram showing a configuration example of a cell transistor in the circuit of FIG.

7 is a diagram showing a configuration example of a memory formed by arranging the cell transistors of FIG. 1 in a matrix.

8 is a timing chart for explaining the operation of the circuit shown in FIG.

9 is a timing chart for explaining the operation of the circuit shown in FIG.

10 is a diagram showing the level of each signal in the circuit of FIG.

11 is a diagram showing the level of each signal in the circuit of FIG.

FIG. 12 is a diagram for explaining another embodiment of the present invention.

FIG. 13 is a diagram for explaining another embodiment of the present invention.

FIG. 14 is a diagram showing a symbol of a cell transistor.

15 is a diagram showing control gate voltage-drain current characteristics of the cell transistor shown in FIG.

16 is a diagram showing a circuit configuration example of an EEPROM configured by using the cell transistor of FIG.

FIG. 17 is a diagram showing a pattern configuration example of the circuit of FIG. 16;

[Explanation of symbols]

ST ... Selection transistors, CT1 to CT4 ... Cell transistors, 40 ... Transistors cut off during programming, 37 ... Row decoder, 38 ... First column decoder, 39 ... Second
Column decoder, IO1 to IO8 ... Data input / output line, Q1
~ Qm ... column selection transistors, QD2 ~ QDm ... array division transistors, QT1, QT2, ... transistors,
B1 to Bm ... Memory cell block (memory cell array), X1, X2, ..., Y1 to Ym, W11 to W1n, W21
~ W2n, W111 ~ W1n1 ... signals.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 H01L 29/78 371 29/792 F term (reference) 5B025 AA01 AD02 5F083 EP02 EP23 EP72 EP76 ER02 ER03 ER05 ER14 ER15 GA09 LA05 LA21 5F101 BA24 BA35 BB05 BC02 BC11 BD15 BD34 BE02 BE05 BE07

Claims (4)

[Claims] 1. Each has a floating gate and a control gate,
One end of each of the plurality of cell transistors that stores data in accordance with the charge accumulation state of the floating gate, and the n number of cell transistors that select n (n ≧ 2) in the same column of the plurality of cell transistors. The connected selection transistor, a row line to which the control gates of the cell transistors in the same row among the plurality of cell transistors are respectively connected, a column line to which the other end of the selection transistor is connected, and the same A first decoder for supplying a decode signal to the respective control gates of the cell transistors in the row via the row line, and a second decoder for supplying the decode signal to the selecting transistor to selectively control conduction. And the selection transistors connected to the n cell transistors and arranged in different rows. The group consisting of transistors is supplied with the decode signal independently by the first decoder, and the non-selected group is prevented from being affected by the selected group. Storage device. 2. A column decoder for selecting the column to which the other ends of the corresponding selection transistors in the same column of the groups arranged in the different rows are connected. The non-volatile semiconductor memory device according to claim 1. 3. The column selection transistor according to claim 2, further comprising a column selection transistor, one end of which is connected to the column line to select the column, and a signal from the column decoder is supplied to a gate of the column selection transistor. Non-volatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the other ends of the corresponding column select transistors are connected to each other.