JPH1145589A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the current of memory cells and to improve the data read-out speed by setting the supply voltage to a selected transistor(TR) side memory cell control gate lower than the supply voltage to a switching TR side memory cell at the time of reading out for the purpose of checking after writing. SOLUTION: A voltage generating means 101 outputs a signal VR set at 1 at the time of check reading-out after writing and the voltage meeting the connection position of the memory cell selected up to address input signals A0, A1. When the signal VR turns into the 1, the TRs 1 to 5 turn on and the potentials at nodes A to D are set successively lower with the node A at the highest in a voltage generating section 103. Any of the TRs 7 and 8, 9 and 10, 11 and 12, 13 and 14 turn on in the combination of the address input signals A0, A1 and the potentials of the nodes D to A select the memory cells M1 to M4 and the check reading out is executed in a decoding means 102. The ordinary read-out time is when the signal VR is 0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reading data from a NAND flash EEPROM.

[0002]

2. Description of the Related Art A NAND type EEPROM has a configuration as shown in FIG. 2 and includes a selection transistor STr1, a plurality of memory cells M1 to M4 connected in series, and a switching transistor STr2. It is arranged and integrated like this. NAND type EEPROM
In the OM, the logic “1” of the data stored in the memory cell
And logic "0" are stored in association with the positive and negative threshold voltages of the memory cells. Whether to have such a positive threshold voltage or a negative threshold voltage is determined by the accumulation state of electrons in the floating gate,
When electrons are injected into the floating gate, the threshold voltage becomes positive, and when electrons are emitted from the floating gate, the threshold voltage becomes negative. The injection and emission of electrons into the floating gate depends on the first between the floating gate and the channel region.
Through the gate insulating film using the tunnel effect.

In a NAND type EEPROM, when reading data, the control gate of a selected memory cell is set to logic "0" and the control gate of an unselected memory cell is set to logic "1". Memory cells having a negative threshold voltage are turned on even when the control gate is at logic "0", and memory cells having a positive threshold voltage are turned off when the control gate is at logic "0". Data is read depending on whether the selected memory cell is on or off. The control gate of the unselected memory cell is set to logic "1", and the unselected memory cell is set to the ON state regardless of whether the threshold voltage is positive or negative. That is, NAND type EEPR
In the OM, since the memory cells are connected in series, a non-selected memory cell is always turned on, and depending on whether the selected memory cell is on or off, a current flows through the memory cells connected in series. The data stored in the memory cell selected by flowing or not flowing is read.

In data writing, electrons are emitted from the floating gates of all the memory cells, the threshold voltages of all the memory cells are made negative, and then electrons are selectively injected into the floating gates of the memory cells. Do. When reading data,
An unselected memory cell whose control gate is set to logic "1" as described above must be set to an on state even if its threshold voltage is positive. Reading is performed to check whether the injection amount is appropriate. If the injection amount is not sufficient, the injection of electrons and the reading for checking are repeatedly performed so as to inject more electrons. At the time of normal reading, if the control gate of the selected memory cell is set to 0 V for reading, for example, a voltage higher than 0 V is supplied to the control gate of the selected memory cell at the time of reading for checking. Do it. If the memory cell is off when a voltage higher than 0 V is supplied, the amount of injected electrons is determined to be appropriate and no more electrons are injected. Therefore, at the time of normal reading, if 0 V is supplied to this memory cell, the memory cell is completely turned off and a predetermined margin can be obtained.
The voltage applied to the control gate of the selected memory cell at the time of reading for checking does not change according to the memory cell, and the same voltage is applied when data is read from any memory cell. Therefore, assuming an ideal case, all the memory cells into which electrons have been injected have the same threshold voltage.

Considering normal data reading, for example, in FIG. 2, the threshold voltage of the memory cell M4 is negative, the threshold voltages of the memory cells M1 to M3 are positive, and the memory cell M4 is selected. And At the time of data reading, the memory cell M1,
A current flows toward the reference potential through M2, M3, and M4 and further through the switching transistor STr2. Therefore, the potential of the source VS3 of the memory cell M3 is higher than the potential of the source VS4 of the memory cell M4, and the potential of the memory cell M2 is higher than the potential of the source VS3 of the memory cell M3.
Is higher, the potential of the source VS1 of the memory cell M1 is higher than the potential of the source VS2 of the memory cell M2. FIG. 4 shows a relationship between the substrate potential VB of the transistor and the threshold voltage Vth. As is clear from FIG. 4, since the memory cells M1 to M4 have different substrate effects, when data is read, the memory cell M1 has the highest source potential and the memory cell M1 having the largest potential difference between the source potential and the substrate potential. The threshold voltage Vth1 is the highest, and then decreases in the order of the memory cell M2 and the memory cell M3. This is determined by whether or not the memory cell to which a predetermined voltage is applied to the control gate at the time of reading of the check is turned off. Therefore, when it is determined that the reading of the check is OK, no current flows through the memory cell. This is because the source of the memory cell becomes 0 V and the substrate effect does not occur.

[0006]

As described above, the conventional N
In the AND type flash EEPROM, at the time of check reading after writing, reading is performed by applying the same voltage to the gate of the memory cell. Therefore, when a current flows through the memory cell during normal reading, electrons are injected into the floating gate. In a memory cell, there is a problem that the threshold voltage becomes higher as the memory cell is connected to the selection transistor side.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and reduces the threshold voltage of a memory cell, which rises due to the substrate effect at the time of reading data, lower than that of a conventional memory cell. It is intended to increase the data read speed.

[0008]

According to the first aspect of the present invention, there is provided at least two memory cells each having a floating gate and a control gate and storing data according to the amount of charge of the floating gate. Comprises a memory block connected in series between a first terminal and a second terminal, and in order to check whether data has been written to the memory cell when writing data to the memory cell. , When a read operation is performed according to a state of forming a current path from the first terminal to the second terminal via the at least two memory cells, a memory on the second terminal side of the current path When writing data to a cell,
A potential V2 applied to the gate of the memory cell for performing a read operation for confirming whether or not data has been written to the memory cell; and a data to the memory cell on the first terminal side of the current path. A nonvolatile memory characterized in that the relationship with the potential V1 applied to the gate of this memory cell is V1 <V2 in order to perform a read operation for confirming whether data has been written in this memory cell at the time of writing. Provide a semiconductor memory. For this reason, in the memory cell after data writing, the threshold voltage of the memory cell connected to the first terminal side should be set lower than the threshold voltage of the memory cell connected to the second terminal side. Can be.

Further, in the invention according to claim 2, claim 1
In the invention according to the first aspect, when a potential applied to the gates of the first and second memory cells is V3 when normal data is read from the memory cell, V3 <V1 <V2. Provided is a nonvolatile semiconductor memory. For this reason, it is possible to increase the read margin of the threshold voltage during normal data read.

According to a third aspect of the present invention, there is provided a memory block having a floating gate and a control gate, wherein a plurality of memory cells are connected in series to store data according to the amount of charge in the floating gate; A selection transistor for controlling a connection between one end of the block and a read potential supply terminal, a switching transistor for controlling a connection between the other end of the memory block and a reference potential terminal, and a write unit for writing data to the memory cell. When reading data from the memory cell, selectively switching between a first read mode and a second read mode for reading data from the memory cell to determine whether data has been written to the memory cell. And a reading unit capable of selecting at the time of reading in the second reading mode. The potential supplied to the control gate of the selected memory cell is higher than the potential supplied to the control gate of the memory cell selected at the time of reading in the first read mode, and constitutes the memory block. When the memory cell arranged on the switching transistor side is selected from among the memory cells, the potential supplied to the control gate of the selected memory cell is changed when the memory cell arranged on the selection transistor side is selected. A nonvolatile semiconductor memory is controlled to be higher than a potential supplied to a control gate of a selected memory cell. Therefore, at the time of data writing, the threshold voltage of the memory cell connected to the selection transistor can be set lower than the threshold voltage of the memory cell connected to the switching transistor.

In the invention according to claim 4, claim 3
In the invention according to the above, when data is read from the memory cell at the time of reading in the second read mode, the potential supplied to the control gate of the selected memory cell is set to the potential of the memory cell constituting the memory block. The memory cell is set so as to become lower in order from the memory cell connected to the switching transistor to the memory cell connected to the selection transistor. For this reason, the threshold voltage of the memory cell in which writing is completed is set so as to gradually decrease from the one connected to the switching transistor side to the one connected to the selection transistor side.

Further, in the invention according to claim 5, according to claim 3,
In the inventions according to the fourth to fourth aspects, the reading means generates a voltage to be supplied to the selected memory cell, and selects the selection transistor and the memory cell and generates a voltage at a control gate thereof by the voltage generating means. And a decoder for supplying a selected voltage, wherein the voltage generator generates a voltage corresponding to a connection position of a selected memory cell at the time of reading in the second read mode. Provided is a nonvolatile semiconductor memory. Therefore, the voltage generated by the voltage generator can be applied to the control gate of the memory cell by the decoder.

[0013] In the invention according to claim 6, according to claim 5,
In the invention according to the invention, the voltage generation means includes a voltage generation unit that generates a plurality of voltages and a decoding unit that selects a voltage corresponding to a memory cell selected from the plurality of voltages. Provided is a nonvolatile semiconductor memory. Therefore, the output voltage of the voltage generating means has a value corresponding to the connection position of the selected memory cell.

In the invention according to claim 7, claim 6
7. The nonvolatile semiconductor memory according to claim 6, wherein when reading in said first read mode, said decoding section is in a non-selected state and supplies a reference potential to said decoder means. I do. Therefore, at the time of the first read, the decoder means applies a read voltage (ground potential) lower than the read voltage in the second read mode to the control gate of the selected memory cell. Can be.

[0015]

FIG. 1 shows an embodiment of the present invention. Memory cells M1 to M4 shown in FIG. 1 are selected by address input signals A0 and A1 as shown in FIG. When the address input signals A0 and A1 are both "0" level, the memory cell M1 is selected. When A0 is "1" and A1 is "0", the memory cell M2 is selected and A0 is "0".
When A1 is "1", the memory cell M3 is selected, and when both the address input signals A0 and A1 are at "1" level, the memory cell M4 is selected. In this embodiment, an example is shown in which four memory cells are connected in series. However, the number of memory cells is not limited to four, and may be an arbitrary number such as eight or sixteen. The number of address input signals can also be changed depending on the number.

As shown in FIG. 1, a nonvolatile memory device according to the present invention comprises a voltage generator 101 and a decoder 102.
The output of the decoder means 102 includes the control gates of the memory cells M1 to M4 and the selection transistor STr.
1. Applied to the gate of the switching transistor STr2. Further, the voltage generation means 101 is
3 and a decoding unit 104.

The voltage generating means 101 outputs a voltage corresponding to the connection position of the selected memory cell in accordance with the signal VR set to "1" and the address input signals A0 and A1 at the time of checking and reading after writing. The decoder 102 applies the output voltage output from the voltage generator 101 to the control gate of the selected memory cell according to the address input signal.

The operation of the voltage generating means 101 will be described below in detail. In the voltage generator 103, when the signal VR becomes "1", the transistors 1, 2, 3, 4, and 5 are turned on, and the potentials of the nodes A, B, C, and D are the highest, and the next is B. , C, D are set in this order. Decoding section 1
At 04, when the signals A0 and A1 are both at the "0" level, the inverted signals / A0 and / A1 are both at the "1" level, so that the transistors 7 and 8 are turned on and the lowest node D through this transistor. The potential is the decoder means 102
Supplied to That is, the memory cell M1 directly connected to the selection transistor is supplied with the lowest potential to the control gate and is checked and read. When A0 is "1" and A1 is "0", since the signal / A1 is "1", the transistors 9 and 10 are turned on, the next higher potential is supplied to the decoder, and the memory cell M2 is selected and checked. Reading is performed. When the signal A0 is "0" and A1 is "1", the signal / A0 is "1" and the transistor 11,
12 turns on, the second highest potential at the node B is supplied to the decoder, the memory cell M3 is selected, and the check reading is performed. Address input signals A0 and A1 are both "1"
At the time of the level, the transistors 13 and 14 are both turned on, so that the highest potential at the node A is supplied to the decoder,
The memory cell M4 is selected, and the check reading is performed. At this time, since the inverted signal / VR of the signal VR is "0", the transistor 6 is turned off. When the signal VR is "0", during normal reading, the transistors 1 to 5 are turned off, the transistor 6 to which the "1" level signal / VR is supplied is turned on, and the ground potential is supplied to the decoder means 102. Is done.

Next, the operation of the decoder means 102 will be described in detail. When one of the decode signals Si for selecting the selection transistor STr1 becomes "1", a "1" level signal is supplied to the gate of the selection transistor STr1 via the inverters I1 and I2, and the selection transistor STr1 is turned on. Since the signal / P is "1" at the time of reading,
The switching transistor STr2 also turns on. “1”
The N-channel transistor 15 to which the signal Si of the level is supplied to the gate is turned on, and the P-channel transistor 16 to which the "0" level signal of the output of the inverter I1 to which the signal Si is input is also turned on.
The output of the decoding unit D1 to which 0 and A1 are input is supplied to the memory cell M1 through the transistors 15 and 16.
Similarly, the N-channel transistor 17 to which the gate of the signal Si of “1” is supplied is turned on, and the P-channel transistor 18 to which the signal of “0” level of the output of the inverter I1 to which the signal Si is input is also supplied. When turned on, the output of the decoding unit D2 to which the address signals / A0 and A1 are input is supplied to the memory cell M2 through the transistors 17 and 18.
Supplied to The N-channel transistor 19 to which the signal Si of “1” level is supplied to the gate is turned on, and the signal Si
Is also supplied, the P-channel transistor 20 to which the signal of the output of the inverter I1 at the "0" level is supplied is also turned on. M3. The N-channel transistor 21 to which the signal Si of the “1” level is supplied to the gate is turned on, and the P-channel transistor 22 to which the “0” level signal of the output of the inverter I1 to which the signal Si is input is also turned on. The output of the decoding unit D4 to which the address signals / A0 and / A1 are input is supplied to the memory cell M4 through the transistors 21 and 22. Since the N-channel transistors 23 to 26 whose gates are supplied with the "0" level signal of the output of the inverter I1 to which the signal Si is input are turned off, the memory cells M1 to M4 include the decoding units D1 to D
4 is controlled by the output potential.

When the signals A0 and A1 are both at "0" level, the transistors 27 and 28 are both turned off, so that the node d becomes "1" and the transistor 29 is turned on. For this reason, the voltage at the node D is supplied to the control gate of the memory cell 1 from the transistors 7 and 8 that are turned on at this time through the transistor 29, and reading for checking is performed. At this time, since the transistors 31, 36, 39, and 40 are on, the nodes a to c are "0", the transistors 33, 37, and 41 are off, and the transistors 34, 38,
Reference numeral 42 turns on, and the power supply voltage is supplied to the control gates of the memory cells M2 to M4.

When A0 is "1" and A1 is "0", since the signal / A0 is "0", both the transistors 31 and 32 are turned off, so that the node c becomes "1" and the transistor 33 is turned on. I do. Therefore, through the transistor 33,
At this time, the voltage at the node C is supplied to the control gate of the memory cell M2 from the transistors 9 and 10 which are turned on, and reading for checking is performed. At this time, since the transistors 27, 35, 36, and 40 are on, the nodes a,
b and d become “0”, and the transistors 29, 37, 41
Is turned off, the transistors 30, 38, and 42 are turned on, and the power supply voltage is supplied to the control gates of the memory cells M1, M3, and M4. Similarly, when the signal A0 is "0" and A1 is "1", the voltage at the node B is supplied to the control gate of the memory cell M3 through the transistors 11, 12, 37, 19 and 20, and the address input signals A0 and A1 Are both "1" level, the highest potential of the node A is supplied to the control gate of the memory cell M4 through the transistors 13, 14, 41, 21, and 22, the memory cell M4 is selected and the check reading is performed.

At the time of normal reading, since the signal VR becomes "0", the transistors 1 to 5 are turned off, and the signal V
The transistor 6 to which the inverted signal / VR of "1" level signal is supplied is turned on, the ground potential is supplied to the decoder, and the ground potential is supplied to the control gate of the selected memory cell.

When the selection transistor whose signal Si is "0" is not selected, this "0" level signal is supplied to the gate of the selection transistor through the inverters I1 and I2, so that the selection transistor is turned off. 15 to 22 are also turned off. At this time, since the output of the inverter I1 is "1", the transistors 23 to 26 supplied with this output to the gate are turned on, and the transistor 23
The ground potential is applied to the control gates of the memory cells M1 to M4 through 3 to 26.

As described above, by making the voltage supplied to the control gate of the memory cell on the selection transistor side lower than the voltage supplied to the memory cell on the switching transistor side when reading for checking after writing is performed, The threshold voltage of the memory cell into which the electrons are injected is lower in the memory cell connected to the selection transistor than in the memory cell connected to the switching transistor. In the present embodiment, the memory cell M1
When electrons are injected into all of the memory cells M4 to M4, the threshold value of the memory cell is set so that M4 becomes the highest, and the threshold value becomes lower in the order of M3 to M1. Therefore, at the time of data reading, the threshold voltage after the rise due to the body effect can be made lower than before, so that the current flowing through the memory cell on the selection transistor side increases, and the data reading speed improves. . In addition, since the voltage applied to the memory cell at the time of reading for checking after writing is set higher than the voltage applied to the memory cell at the time of normal reading, a margin at the time of reading can be increased as in the related art. .

In the present invention, as described above, the voltage supplied to the control gate of the memory cell on the selection transistor side when reading for checking is made lower than the voltage supplied to the memory cell on the switching transistor side. It is a feature that such control is performed, and it goes without saying that the control is not limited to the embodiment as long as the control is performed in this manner.

[0026]

As described above, according to the present invention, the voltage supplied to the control gate of the memory cell on the selection transistor side when reading for checking is changed to the voltage supplied to the memory cell on the switching transistor side. Lower than the threshold voltage of the memory cell into which electrons are injected, so that the threshold voltage of the selection transistor side is lower than that of the switching transistor side. The increased threshold voltage becomes lower than before, so that the current flowing through the memory cell increases and the data reading speed can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a configuration of a NAND type nonvolatile semiconductor memory device.

FIG. 3 is a diagram showing connections of memory cells of a NAND type nonvolatile semiconductor memory device.

FIG. 4 is a diagram showing a relationship between a substrate voltage and a threshold voltage of a transistor.

[Explanation of symbols]

STr1 selection transistor STr2 switching transistor M1 to M4 memory cell 101 voltage generating means 102 decoder means 103 voltage generating section 104 decoding section

Claims (7)

[Claims] At least two memory cells each having a floating gate and a control gate and storing data according to an amount of charge of the floating gate are connected in series between a first terminal and a second terminal. A memory block, wherein when writing data to the memory cell, the first and second terminals are connected to the second terminal from the first terminal to check whether data is written to the memory cell. When performing a read operation based on the state of formation of a current path through a memory cell, when writing data to a memory cell on the second terminal side of the current path, it is checked whether data has been written to this memory cell. Potential V2 applied to the gate of the memory cell to perform a read operation for reading data from the memory cell on the first terminal side of the current path. A nonvolatile memory characterized in that a relationship with a potential V1 applied to the gate of the memory cell is V1 <V2 in order to perform a read operation for confirming whether data is written in the memory cell at the time of data writing. Semiconductor memory. 2. The method according to claim 1, wherein the potential applied to the gates of the first and second memory cells is V3 <V1 <V2 when normal data is read from the memory cells. The nonvolatile semiconductor memory according to claim 1. 3. A memory block having a floating gate and a control gate, in which a plurality of memory cells for storing data according to the amount of charge in the floating gate are connected in series, one end of the memory block and a read potential supply terminal. A selection transistor for controlling connection between the memory cell, a switching transistor for controlling connection between the other end of the memory block and a reference potential terminal, writing means for writing data to the memory cell, and reading data from the memory cell. A read unit that can selectively switch between a first read mode and a second read mode for reading data from the memory cell to determine whether data has been written to the memory cell. The control gate of the memory cell selected at the time of reading in the second read mode. A potential supplied to the control gate of the memory cell selected at the time of reading in the first read mode, and the switching among the memory cells constituting the memory block is performed. The potential supplied to the control gate of the selected memory cell when the memory cell disposed on the transistor side is selected is the potential of the memory cell selected when the memory cell disposed on the selected transistor side is selected. A nonvolatile semiconductor memory controlled to be higher than a potential supplied to a control gate. 4. When data is read from the memory cell at the time of reading in the second reading mode,
The potential supplied to the control gate of the selected memory cell is sequentially changed from the memory cell connected to the switching transistor of the memory cells constituting the memory block to the memory cell connected to the selected transistor. 4. The nonvolatile semiconductor memory according to claim 3, wherein the setting is made lower. 5. The read means includes a voltage generation means for generating a voltage to be supplied to the selected memory cell, and a selection transistor and the memory cell which are selected and generated by the voltage generation means on a control gate thereof. 4. A decoder for supplying a voltage, wherein the voltage generator generates a voltage corresponding to a connection position of a selected memory cell at the time of reading in the second read mode. 5. The nonvolatile semiconductor memory according to any one of claims 1 to 4. 6. The voltage generating means includes a voltage generating section for generating a plurality of voltages and a decoding section for selecting a voltage corresponding to a memory cell selected from the plurality of voltages. The nonvolatile semiconductor memory according to claim 5. 7. The non-volatile semiconductor memory according to claim 6, wherein at the time of reading in said first read mode, said decoding section is in a non-selected state, and supplies a reference potential to said decoder means.