JP3499706B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device. 2. Description of the Related Art Generally, in a semiconductor memory device of this type, that is, a so-called EEPROM memory cell, electrons are injected into a floating gate through an oxide film of about 100 angstroms, which is much thinner than a gate oxide film. The data is rewritten by releasing or releasing. FIG.
4 is a symbol diagram of a cell transistor constituting such a memory cell. The control gate voltage is V _CG , the drain voltage is V _D , the source voltage is V _S , and the drain current is I.
_Assuming that _D , the drain current _{ID with} respect to the control gate voltage _VCG exhibits characteristics as shown in FIG. In FIG. 15, a curve 11 is a characteristic in an initial state, and a curve 12 is a characteristic when electrons are injected into the floating gate, and the threshold voltage is increased by the injection of electrons. Curve 13 is a characteristic in a state where electrons are emitted from the floating gate, and the threshold voltage is lowered due to the emission of electrons and becomes negative. In a memory cell using such a cell transistor, data “0” and “1” are stored using the characteristics of the curves 12 and 13. FIG. 16 shows an EEPRO in which the cell transistors shown in FIG. 14 are arranged in a matrix.
M shows an example of the circuit configuration of the currently available EE
PROM has many such circuit configurations. As shown
A selection MOS transistor ST is connected in series to each cell transistor CT, and one memory cell 14 is composed of two transistors CT and ST. In the above configuration, when electrons are injected into the floating gate of the cell transistor CT, the gate of the selection transistor ST and the cell transistor C
The high voltages V _G and V _CG are applied to the control gate of T, and the column line 15 is set to 0V. On the other hand, when emitting electrons, the gate of the selection transistor ST and the column line 15 are set to a high voltage, and the control gate of the cell transistor CT is set to 0V. As a result, a high voltage is applied to the drain of the cell transistor CT, and electrons are emitted from the floating gate to the drain. FIG. 17A is a pattern plan view of a region 16 surrounded by a chain line in the circuit shown in FIG.
FIG. 1 shows a cross-sectional configuration along the line AA ′ in FIG.
This is shown in FIG. 17A and 17B, parts corresponding to those in FIG. 16 are denoted by the same reference numerals, 17 is a source region of the cell transistor CT, 18 is a drain of the cell transistor CT, and 18 of the selection transistor ST. A source region, 19 is a drain region of the selection transistor ST,
20 is a floating gate of the cell transistor CT, 21 is a control gate of the cell transistor CT, and 22 is a selection transistor S.
The gate of T, 23 is a thin oxide film portion, and 24 is a contact portion between the column line 15 and the selection transistor ST. However, in the above-described configuration, one memory cell is formed by two transistors.
There is a disadvantage that the memory cell size increases and the chip cost increases. For this reason, an ultraviolet-erasable nonvolatile semiconductor memory device that can form one memory cell with one transistor, that is, a so-called UVEPROM, has attracted attention. U
In a VEPROM, one memory cell is formed by only one transistor, so that a chip having the same area can obtain twice the capacity of an EEPROM, and a chip having the same memory size (capacity) can have a smaller chip size. E
The penetration rate is higher than EPROM. However, UVE
When injecting electrons into a memory cell, a PROM requires a large current because a current flows through a channel to generate hot electrons near a drain and inject them into a floating gate. For this reason, an external power supply for programming is required. On the other hand, the above-mentioned EEPROM emits and injects electrons from the floating gate using the tunnel effect, so that data can be written with a high voltage from a booster circuit provided in the chip. Therefore, there is an advantage that a single power supply of 5 V can be used. Also, UVEPROM is
While the memory cells of the entire chip must be erased at the same time, the EEPROM has an advantage that data can be rewritten one memory cell at a time depending on the configuration of the memory cell array. As described above, the EEPROM and the UVEPRO
M has advantages and disadvantages. However, if the memory size of the EEPROM can be reduced to a size comparable to that of the UVEPROM and the cost can be reduced, it can be said that it can be used with a single power supply of 5 V, so that it is easy for users to use. As described above, the conventional EEPROM has an advantage that it can be operated with a single power supply, and has an advantage that data can be rewritten one memory cell at a time. However, there is a problem that the memory cell size is larger than the UVEPROM and the cost is higher. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile memory capable of reducing the size of a memory cell and reducing the cost while electrically rewriting data. To provide a nonvolatile semiconductor memory device. That is, in a nonvolatile semiconductor memory device according to one embodiment of the present invention, a current path is connected in series.
Are connected, each having a floating gate and a control gate, and a plurality of cell transistors for storing data in response to the charge storage state of the floating gate, of the plurality Serutoranjisu
Cell having selection transistor for selecting data
And each of the above memory cells is arranged in a matrix.
And each cell transistor in the same row is connected to one of a plurality of row lines.
Connected in common and selected transistors of the same row
A plurality of memory cell blocks, each of which has one end connected in common to one of a plurality of column lines and is configured to program or output data of a plurality of bits corresponding to the plurality of cell transistors in parallel; Selecting means including a row decoder for selecting the row line and a column decoder for selecting the column line to select one of the memory cell blocks and a plurality of the cell transistors in the memory cell block; Memory cell block 1
Initialization means for electrically initializing the storage data of the cell transistors in one memory cell block to be the same storage data; and memory cells initialized by the initialization means and selected by the selection means Program means for programming the plurality of bits of data in the plurality of cell transistors in a block in parallel; [0011] [0012] [0013] [0014] [0015] [0016] [0017] The nonvolatile semiconductor memory device according to one embodiment of the invention, the first row line is connected to the control gates A memory cell having a plurality of electrically programmable cell transistors having current paths connected in series, and a selection transistor for selecting the plurality of cell transistors, is formed by being arranged in a matrix in the row and column directions. are, each program or the output of the data of a plurality of bits corresponding to a plurality of the cell transistors is performed in parallel, a memory cell array including a plurality of memory cell blocks, prior to the program, in the memory cell block The storage data of the cell transistors in all the above memory cells is converted to the same storage data. Initialization means for electrically initializing the storage data of the memory cells in the memory cell block, wherein each of the cell transistors comprises a source / drain region and a source / drain region between the source / drain regions. A first insulating film provided on the channel region and having a thickness capable of causing a tunnel effect; a floating gate provided on the first insulating film; and a second insulating film provided on the floating gate And the control gate provided on the second insulating film, and after electrically initializing the storage data of the memory cells in the memory cell block by the initialization means, By injecting or emitting electrons to the floating gate through the first insulating film on the region, the data of the plurality of bits corresponding to the plurality of cell transistors is arranged in parallel. A plurality of memory cells, which are programmed and read out of stored data corresponding to the plurality of bits of data based on a conduction state or a cutoff state of a channel region of the cell transistor according to an amount of electrons in the floating gate. Are performed in parallel by the data detection circuit. According to the above configuration, the memory cell size can be reduced and the cost can be reduced while data can be electrically rewritten. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory cell section and its peripheral circuit section. An output D of a data input circuit 25 is supplied to the gate of an N-channel MOS transistor 26 whose one end is connected to a high voltage power supply Vp. You. A selection transistor ST and cell transistors CT1 to CT4 are connected in series between the other end of the transistor 26 and a ground point (reference potential). A signal X1 for selecting the cell transistors CT1 to CT4 is supplied to the gate of the selection transistor ST, and the control gates of the cell transistors CT1 to CT4 are respectively connected to the cell transistors CT1 to CT4.
Signals W1 to W4 for selecting CT4 are supplied.
At the connection point (node N1) between the transistor 26 and the selection transistor ST, one end of an N-channel MOS transistor 27 which is controlled to be conductive by a signal R which is at "1" level during reading and "0" level during programming is provided. Connected
The other end of the transistor 27 is connected to the input end of the data detection circuit 28. A gate is connected between the input terminal node N2 of the data detection circuit 28 and the power supply V.
Is connected as a load at the time of reading. Here, for convenience, a combination of the selection transistor ST and the cell transistors CT1 to CT4 is referred to as a memory cell. Unlike a general memory cell, this memory cell is composed of four bits (one connected in series) in one memory cell. (The number of bits corresponding to the number of cell transistors), which is equivalent to four conventional memory cells. Next, the operation of the above configuration will be described. FIG. 2 is a timing chart of each signal at the time of programming in the circuit of FIG. First, the signal R is set to the "0" level to turn off the transistor 27, and at time t0, the signals X1 and W1 to W4 are set to the high voltage level. The thin oxide film of the cell transistor shown (film thickness 100
Electrons are injected into the floating gates of the cell transistors CT1 to CT4 via the Angstrom 33). The signals W4 to W1 are sequentially set to 0 V at the next timings t1 to t4. When these signals W1 to W4 are set to 0V, if the data D output from the data input circuit 25 is at "1" level, the transistor 26 is turned on, and the transistor 26 and the selection transistor are switched from the high voltage power supply Vp. A high voltage is applied to the drain of the corresponding cell transistor via ST, and electrons are emitted from the floating gate by the tunnel effect. In FIG. 2, when the signals W3 and W1 are set to 0V, the data D is at the "1" level (time t2 to t3, time t4 to t5).
), The electrons injected into the floating gates of the cell transistors CT3 and CT1 are released. What is important here is not the application of 0 V to the control gate and the application of a high voltage to the drain, but the strength of the electric field in the region where the tunnel effect occurs. The electric field where the tunnel effect occurs selectively is applied to each cell transistor. Thus, data is selectively programmed in each cell transistor. For example,
Since the cell transistor CT4 does not become an electric field where a tunnel effect occurs in a region where the tunnel effect occurs after the time t1, no electron is transferred between the floating gate and the cell transistor CT4. Between the times t0 and t1, the electrons injected into the floating gates of the cell transistors CT1 to CT4 are:
Time t1 to t2, time t2 to t3, time t3 to t4
Cell transistors CT1 to CT1 depending on whether the data D is "1" level or "0" level during the time t4 to t5.
The program is performed depending on whether or not electrons are emitted from the floating gate of FIG. At the timing between times t1 and t2, signals X1 and W1 through W3 are set to the high voltage level, and selection transistor ST and cell transistors CT1 through CT2 are set.
3 turns on. At this time, the signal W4 is set to 0 V, and the data D is at the "0" level.
Is off, and no high voltage is applied to the cell transistor CT4, so that the electrons injected into the floating gate of the cell transistor CT4 are not emitted. At the timing between the times t2 and t3, the signals X1 and W1 and W2 are set to the high voltage level, and the selection transistor ST and the cell transistors CT1 and CT3 are set.
2 turns on. At this time, the signal W3 is set to 0 V, and the data D is at the "1" level.
Is turned on, and a high voltage is applied to the cell transistor CT3. At this time, since 0 V is applied to the control gate of the cell transistor CT3, the electric field applied to the thin insulating film becomes large and a tunnel effect occurs, and electrons injected into the floating gate of the cell transistor CT3 are emitted. You. At this time, the transistor 26 and the cell transistor CT
Since the cell transistor CT3 exists between the cell transistor CT4 and the cell transistor CT4, no high voltage is applied to the cell transistor CT4, and programming is performed only on the cell transistor CT3. At the timing between times t3 and t4, signals X1 and W1 are at a high voltage level, and signals W2 through W4 are at 0V.
Is set to At this time, since the data D is at "0" level, the transistor 26 is turned off and the cell transistor CT
Since no high voltage is applied to 2, the electrons injected into the floating gate of this cell transistor CT 2 are not emitted. At the timing between times t4 and t5, the signal X1 is set to the high voltage level, the signals W1 to W4 are set to 0 V, and the selection transistor ST is turned on. At this time, since the data D is at the "1" level, the transistor 26 is turned on, and a high voltage is applied to the cell transistor CT1, so that the electric field applied to the thin insulating film becomes large and a tunnel effect occurs. The electrons injected into the floating gate of CT1 are emitted. At this time, the transistor
Since the cell transistor CT1 exists between 26 and the cell transistors CT2 to CT4, no high voltage is applied to the cell transistors CT2 to CT4.
Programming is performed only on cell transistor CT1. On the other hand, when data is read, signals R and X1 are set to "1" level, and the control gate of the cell transistor to be read is set to 0V. At this time, the gates of the other cell transistors are set to “1” level. The timing chart of FIG. 3 is for the case where data is sequentially read from the cell transistors CT4 to CT1, and between the time t0 and t1, the data is read from the cell transistor CT4.
From the cell transistor CT3 between the times t1 and t2, and from the cell transistor CT2 between the times t2 and t3, the time t3
, T4, data is read from the cell transistor CT1. If the signal W1 is set to 0V and the signals W2 to W4 are set to "1" level, the cell transistor C
Data is read from T1. If the programming has been performed as described above, since electrons are emitted from the floating gate of the cell transistor CT1, the threshold voltage thereof is negative, and the transistor is turned on even when the signal W1 is 0V. The control gates of the other cell transistors CT2 to CT4 are at the "1" level and are in the ON state. Therefore, all the cell transistors CT1 to CT4 are turned on,
The potential of the node N2 drops. This is used as the data detection circuit 28
To read data from the cell transistor CT1. Also, the signal W2 becomes 0V and the cell transistor C
When T2 is selected, the cell transistor CT2
Since the electrons are still injected into the
If it is V, it is turned off. Therefore, the node N2 is charged by the transistor 29, which is connected to the data detection circuit 28.
To detect. The threshold voltages of the cell transistors CT1 to CT4 in the state where electrons have been injected need to be set so as to be turned on when the control gates thereof become "1" level. FIGS. 4A to 4C show an example of the structure of a transistor suitable for the cell transistors CT1 to CT4 in FIG. 1. A part of the insulating film on the channel region is made as thin as about 100 angstroms. The cell size is reduced by forming an oxide film. (A) is a plan view of the pattern, (b) is a cross-sectional view taken along line BB 'of (a), and (c) is a cross-sectional view taken along line CC' of (a). Where 30 is a P-type silicon substrate, 31 and 32 are N + -type sources,
The drain region, 33 is a thin oxide film, 34 is a floating gate, and 35 is a control gate. FIGS. 5A and 5B show another example of a structure suitable for the cell transistors CT1 to CT4 shown in FIG. 1. In FIG. 5A, all the insulating films on the channel region are thinly oxidized to about 100 angstroms. The film 33 is formed. In FIG. 5, the same parts as those in FIG. 4 are denoted by the same reference numerals, (a) is a plan view of the pattern, and (b) is a view of FIG.
It is sectional drawing which followed the -C 'line. FIGS. 6A and 6B show still another configuration example suitable for the cell transistors CT1 to CT4 in FIG. 1, and a part of the channel region is a depletion type transistor. (A) is a plan view of the pattern, and (b) is a cross-sectional view taken along line BB 'of (a). In such a configuration, even if the amount of injected electrons is too large and the cell transistor has a threshold voltage at which the cell transistor is not turned on even when a signal of the “1” level is supplied to the control gate, the N
-The source / drain regions 31,
Since 32 is connected, current flows. In reading data from the cell transistor having such a configuration, when a potential of “0” level is applied to the control gate, a difference in the amount of current caused by whether or not electrons are injected into the floating gate is detected. Performed by FIG. 7 shows a configuration example of a nonvolatile semiconductor memory device in which the above-mentioned memory cells are arranged in a matrix. In FIG. 7, reference numeral 37 denotes a row decoder, 38 denotes a first column decoder, and 39 denotes a second column decoder. Data input / output lines IO1 to IO8 are connected to circuits surrounded by a dashed line in FIG. You. The above row decoder
37 are signals X1, X2,..., Signals W11, W12,.
n, signals W21, W22,..., W2n are output to select the row direction of the memory cell array. The column decoder 38 outputs signals Y1, Y2,..., Ym to selectively control conduction of the column selection MOS transistors Q1 to Qm, thereby inputting data to one of the memory cell blocks B1 to Bm. This is for supplying data to be programmed via output lines IO1 to IO8 or for deriving read data. On the other hand, the column decoder 39 outputs signals Z2 to Z
m to selectively designate the memory cell blocks B1 to Bm at the time of programming by selectively controlling conduction of the depletion type array divided MOS transistors QD2 to QDm. In the above configuration, programming is performed from a memory cell located far from row decoder 27. FIG. 8 is a timing chart of each signal at the time of this programming. That is, programming is performed from the memory cells connected to the signal line X1 of the memory cell block Bm.
In this program, the signals X1, Ym, Z2 to Zm
And a high voltage is applied. In this state, first, the signals W11 to W11 are output.
By setting W1n to a high voltage, electrons are injected into the floating gates of all the cell transistors. Next, the signals are sequentially set to "0" level from the signals W1n to W11. At this time, when the control gate is at the "0" level, the program data is transferred to the data input / output lines IO1 to IO8, the column selection transistors Qm
Electrons are emitted only when a high voltage is applied to the drain via the respective selection transistors STm, and data is programmed in the individual cell transistors. FIG. 9 shows a timing chart at the time of reading, and the signals X and X corresponding to the selected memory cell are shown.
Y becomes "1" level. Also, one of the signals W11 to W1n corresponding to each cell transistor of the selected memory cell is selected.
One is at the “0” level, and the control gates of the unselected cell transistors are all at the “1” level. by this,
Data is read out as in the case of FIG. FIG. 10 summarizes the levels of the signals W11 to W1n in a truth table. When the input data I is at the "1" level, the signals W11 to W1n are all at the "1" level and the cell Electrons are injected into the floating gate of the transistor. When the data I is at the "0" level and the R is at the "0" level, programming is performed individually, and when the R is at the "1" level, the data is read. FIG. 11 shows each signal X1, X2,
The truth tables of W11 to W14 and W21 to W24 are shown for three addresses A0 to A2. In this example, when reading, for example, if X1 = 0, the signals W11 to W11
Although all 14 are set to the "0" level, one of W11 to W14 may be set to the "0" level as in the case of X1 = 1. FIG. 12 shows another embodiment of the present invention. A signal .phi. Between the cell transistor CT4 and the ground point in FIG. 1 which becomes "0" level at the time of programming and "1" level at the time of reading is shown. An N-channel MOS transistor 40 whose conduction is controlled is provided. FIG.
In FIG. 1, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. According to such a configuration, when a high voltage is applied to the drain during programming,
Even if there is a leak current from the cell transistors CT1 to CT4, the leak current can be cut off by the transistor 40, so that a decrease in the drain potential can be prevented and the deterioration of the program characteristics can be prevented. The transistor 40 may be shared by a plurality of cell blocks. FIG. 13 shows another example of the structure when the circuit of FIG. 1 is formed in a matrix. This circuit corresponds to one of the memory cell blocks B1 to Bm in FIG. 7, and in such a configuration, MOS transistors QT1, QT2 controlled by signals X1, X2,. ,.., And the signals are input via these transistors QT1, QT2,..., The signals Z2, Z3,.
If the signals W1n1,..., W121, W111 inputted to the corresponding memory blocks by taking logic with m and the like become high voltage, any memory block can be freely programmed. At this time, if the signals W111, W121,..., W1n1 are wired by the second layer of aluminum wiring using aluminum two-layer wiring, the chip size increases due to the increase in the wiring of the signals W111, W121,. Need less. A latch circuit is provided for each column line, and data to be written into these latch circuits is latched. Based on the latched data of the memory cells for one row, a latch circuit is provided for each column line. If the potential is set to a high potential or 0 V, all the memory cells on all the column lines for one row can be programmed, so that the array dividing MOS transistors QD2 to QDm shown in FIG. 7 can be omitted. As described above, according to the present invention,
A nonvolatile semiconductor memory device that can reduce the size of a memory cell and reduce costs while electrically rewriting data can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a nonvolatile semiconductor memory device according to one embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1; FIG. 3 is a timing chart for explaining the operation of the circuit of FIG. 1; FIG. 4 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1; FIG. 5 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1; FIG. 6 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1; FIG. 7 is a diagram showing a configuration example of a memory formed by arranging the cell transistors of FIG. 1 in a matrix. FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7; FIG. 9 is a timing chart for explaining the operation of the circuit of FIG. 7; FIG. 10 is a diagram showing the level of each signal in the circuit of FIG. 7; FIG. 11 is a diagram showing the level of each signal in the circuit of FIG. 7; FIG. 12 is a diagram for explaining another embodiment of the present invention. FIG. 13 is a view for explaining another embodiment of the present invention. FIG. 14 is a diagram showing a symbol of a cell transistor. FIG. 15 is a graph showing control gate voltage-drain current characteristics of the cell transistor shown in FIG. 14; FIG. 16 is a diagram showing a circuit configuration example of an EEPROM configured by using the cell transistors of FIG. 14; FIG. 17 is a diagram showing a pattern configuration example of the circuit of FIG. 16; [Explanation of Symbols] ST: selection transistor, CT1 to CT4: cell transistor, 40: transistor cut off during programming, 37: row decoder, 38: first column decoder, 39: second
Column decoders, IO1 to IO8 ... data input / output lines, Q1
ＱQm: column selection transistor, QD2 to QDm: array division transistor, QT1, QT2,.
B1 to Bm ... memory cell block (memory cell array), X1, X2, ..., Y1 to Ym, W11 to W1n, W21
~ W2n, W111 ~ W1n1 ... signals.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/788 29/792

Claims (1)

(57) [Claims] Current path connected in series, each having a floating gate and a control gate, and a plurality of cell transistors for storing data in response to the charge storage state of the floating gate, these double
A selection transistor for selecting the number of cell transistors;
A memory cell having, each said memory cells are arranged in a matrix, each
Each cell transistor in the same row is commonly connected to one of the plurality of row lines, and each of the selection transistors in the same column is connected to one of the plurality of row lines .
A plurality of memory cell blocks, one end of which is commonly connected to one of the plurality of column lines, and a plurality of bits of data corresponding to the plurality of cell transistors are programmed or output in parallel; Selecting means including the memory cell block and a row decoder for selecting the row line and a column decoder for selecting the column line to select the plurality of cell transistors in the memory cell block; and the plurality of memories Initialization means for electrically initializing the storage data of the cell transistors in one memory cell block of the cell block so as to be the same storage data; and initialization by the initialization means and selection by the selection means The plurality of bits of data are stored in parallel in the plurality of cell transistors in the selected memory cell block. Nonvolatile semiconductor memory device characterized by comprising a program means for grams. 2. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said row lines in each of said plurality of memory cell blocks are provided independently for each of said memory cell blocks. 3. The nonvolatile memory according to claim 1, wherein a column line of at least one of the memory cell blocks is spaced apart from a column line of at least one of the other memory cell blocks in a row direction. Semiconductor storage device. 4. 4. The device according to claim 1, wherein the initialization unit equalizes data stored in all the cell transistors in the one memory cell block before programming by the programming unit. 5. Nonvolatile semiconductor memory device. 5. Data input / output connected to each memory cell block
5. The apparatus according to claim 1, further comprising a force line.
A nonvolatile semiconductor memory device according to any one of the above items . 6. The data input / output lines are each bit of the plurality of bits.
Provided corresponding to the selected by the selection means
Before the selected cell transistor in the memory cell block
The data is programmed via the data input / output line and
Selection of the memory cell block selected by the selection means.
From the selected cell transistor via the data input / output line.
6. The data is read out as follows.
10. The nonvolatile semiconductor memory device according to claim 1. 7. The data input / output lines are each bit of the plurality of bits.
Provided corresponding to the selected by the selection means
In the selected cell transistor of the memory cell block,
Data through the data input / output line and the selected column line
Is programmed, and the menu selected by the selecting means is
Select from the selected cell transistors in the memory cell block.
Data is transmitted via the selected column line and the data input / output line.
The nonvolatile semiconductor memory device according to claim 5, wherein the nonvolatile semiconductor memory device is read . 8. The data input / output lines and the respective memory cell blocks;
Between the memory cells selected by the selection means
Select the column line of the block and connect it to the data input / output line
Switching control by the signal from the column decoder
Characterized by further comprising a first switch means.
The nonvolatile semiconductor memory device according to claim 5 , wherein: 9. A function for selecting the column line of each memory cell block.
Number of column selection transistors and the above column selection transistors
The columns included in the plurality of memory cell blocks via
Connected to one of the lines and through another column select transistor
And one of the column lines included in another memory cell block
Further comprising a data input line connected to said Gyode
A coder outputs a decoded signal that selects the row line
And the column decoder is decoded to select the column line.
To the gate of the column selection transistor.
The method according to any one of claims 1 to 4, wherein
On-board nonvolatile semiconductor memory device. 10. Select the row line of each memory cell block
Signal lines, the row lines of each of the memory cell blocks, and the
And a second switch means provided between the first switch and the signal line.
10. The method according to claim 1, wherein
The nonvolatile semiconductor memory device according to any one of the first to third aspects. 11. 11. The nonvolatile semiconductor memory device according to claim 10, wherein a row line of each of said memory cell blocks is selected by a signal from said signal line via said second switch means in an ON state. 12. A first aluminum wiring layer and a second aluminum wiring layer, wherein the signal line is formed by a first aluminum wiring layer or a second aluminum wiring layer; The nonvolatile semiconductor memory device according to claim 10 , wherein: 13. A first row line is connected to each control gate, respectively.
A current path is connected in series, and a memory cell having a plurality of electrically programmable cell transistors and a selection transistor for selecting the plurality of cell transistors is formed by being arranged in a matrix in the row and column directions. A memory cell array including a plurality of memory cell blocks, in each of which a plurality of bits of data corresponding to a plurality of the cell transistors are programmed or output in parallel, and a memory cell array including a plurality of memory cell blocks before the programming. Initialization means for electrically initializing the storage data of the memory cells in the memory cell block by making the storage data of the cell transistors in the memory cells equal to the same storage data. The cell transistor has source and drain regions,
A first insulating film provided on the channel region between the source and drain regions and having a thickness capable of causing a tunnel effect; a floating gate provided on the first insulating film; and a first insulating film provided on the floating gate. The second insulating film, and the second
And said control gate provided on said insulating film. After the storage means of said memory cell in said memory cell block is electrically initialized by said initialization means, By injecting or emitting electrons into the floating gate through the insulating film, the plurality of bits of data corresponding to the plurality of cell transistors are programmed in parallel, and the amount of electrons in the floating gate is reduced. Reading the stored data in parallel by a plurality of data detection circuits provided corresponding to the plurality of bits of data, based on the conduction state or the interruption state of the channel region of the cell transistor in accordance with the readout state. Semiconductor memory device. 14． The selection transistor has one end connected to a column line.
A gate is connected to a second row line and the plurality of cell
The transistor is connected between the other end of the selection transistor and a reference potential.
A cell transistor and a selection circuit, which are connected in series between
The first row line and the
A row decoder for supplying a decode signal via a second row line
14. The nonvolatile semiconductor memory device according to claim 13, further comprising: 15. For each of the memory cell blocks,
One end of the first block is provided corresponding to the first row line.
Is connected to the first row line, and the other end is connected to the row decoder.
Switch means to which the decode signal is supplied.
And controlling the switch means to a conductive state.
A predetermined level of the decode signal is supplied to the first row.
A plurality of cell transistors corresponding to the plurality of cell transistors.
The plurality of bits of data in parallel,
The transistor or a plurality of the above
Output from the transistor.
15. The nonvolatile semiconductor memory according to claim 14, wherein: 16. The selection transistor has one end connected to a column line.
A gate is connected to a second row line and the plurality of cell
The transistor is connected between the other end of the selection transistor and a reference potential.
Connected in series with each other through the second row line to each of the selection transistors.
A first decoder for supplying a decoded signal to the
One row line is supplied with a decode signal from the first decoder.
Decoding via a switching controlled transistor
A second decoder for supplying a row signal and a corresponding column line
Input the above multi-bit data to
To output the above multi-bit data from the column line,
A column decoder for selecting a column line.
14. The non-volatile semiconductor storage device according to claim 13, wherein 17. 14. The semiconductor device according to claim 13, wherein a current path is provided between one end of a plurality of cell transistors connected in series and a reference potential, the transistor being cut off during programming.
16. The non-volatile semiconductor storage device according to any one of the above items .