JP3462493B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device. 2. Description of the Related Art Generally, in a semiconductor memory device of this type, that is, a memory cell of an EEPROM, electrons are injected into a floating gate through an oxide film of about 100 angstroms, which is much thinner than a gate oxide film. The data is rewritten by releasing or releasing. FIG.
4 is a symbol diagram of a cell transistor constituting such a memory cell. Assuming that the control gate voltage is V _CG , the drain voltage is V _D , the source voltage is V _S , and the drain current is _ID , the control gate voltage V _The drain current _{ID with} respect to _CG has characteristics as shown in FIG. In FIG. 15, a curve 11 is a characteristic in an initial state, and a curve 12 is a characteristic when electrons are injected into the floating gate. The threshold voltage is increased by the injection of electrons. Further, a curve 13 shows a characteristic in a state where electrons are emitted from the floating gate, and the threshold voltage is lowered due to the emission of electrons and becomes negative. In a memory cell using such a cell transistor, the above curves 12 and 13
The data "0" and "1" are stored by utilizing the characteristic of "1". FIG. 16 shows an EEPRO having the cell transistors shown in FIG. 14 arranged in a matrix.
M shows an example of the circuit configuration of the EE which is currently commercially available.
PROM has many such circuit configurations. As shown
A selection MOS transistor ST is connected in series to each cell transistor CT, and one memory cell 14 is composed of two transistors CT and ST. In the above configuration, when electrons are injected into the floating gate of the cell transistor CT, the gate of the selection transistor ST and the cell transistor C
A high voltage _V G to the control gates _T, then to apply a _{V CG,} set the column lines 15 to 0V. On the other hand, when emitting electrons, the gate of the selection transistor ST and the column line 15 are set to a high voltage, and the control gate of the cell transistor CT is set to 0V. As a result, a high voltage is applied to the drain of the cell transistor CT, and electrons are emitted from the floating gate to the drain. FIG. 17A is a pattern plan view of a region 16 surrounded by a chain line in the circuit shown in FIG.
FIG. 1 shows a cross-sectional configuration along the line AA ′ in FIG.
This is shown in FIG. 17A and 17B, portions corresponding to those in FIG. 16 are denoted by the same reference numerals, 17 is a source region of the cell transistor CT, 18 is a drain of the cell transistor CT, and 18 of the selection transistor ST. A source region, 19 is a drain region of the selection transistor ST,
20 is a floating gate of the cell transistor CT, 21 is a control gate of the cell transistor CT, and 22 is a selection transistor S.
The gate of T, 23 is a thin oxide film portion, and 24 is a contact portion between the column line 15 and the selection transistor ST. However, in the above-described configuration, since one memory cell is formed by two transistors,
There is a disadvantage that the memory cell size increases and the chip cost also increases. For this reason, an ultraviolet-erasable nonvolatile semiconductor memory device that can form one memory cell with one transistor, that is, a so-called UVEPROM, has attracted attention. U
In a VEPROM, one memory cell is formed of only one transistor, so that a chip having the same area can obtain twice the capacity of an EEPROM, and a chip having the same memory size (capacity) requires a smaller chip size. E
The penetration rate is higher than EPROM. However, UVE
A PROM requires a large current because a current flows through a channel when electrons are injected into a memory cell, and hot electrons are generated near a drain and injected into a floating gate. For this reason, an external power supply for programming is required. On the other hand, since the above-mentioned EEPROM emits and injects electrons from the floating gate using the tunnel effect, data can be written at a high voltage from a booster circuit provided in the chip. Therefore, there is an advantage that a single power supply of 5 V can be used. Also, UVEPROM is
While the memory cells of the entire chip must be erased at the same time, the EEPROM has an advantage that data can be rewritten one memory cell at a time depending on the configuration of the memory cell array. As described above, the EEPROM and the UVEPRO
M has advantages and disadvantages. However, if the memory size of the EEPROM can be reduced to a size similar to that of the UVEPROM and the cost can be reduced, it can be said that it can be used with a single power supply of 5 V, so that it is easy for the user to use. As described above, the conventional EEPROM has an advantage that it can be operated with a single power supply, and has an advantage that data can be rewritten one memory cell at a time. However, there is a problem that the memory cell size is larger than the UVEPROM and the cost is higher. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile memory capable of reducing the size of a memory cell and reducing the cost while electrically rewriting data. To provide a nonvolatile semiconductor memory device. [0010] That is, according to the present invention, there is provided one embodiment of the present invention.
A nonvolatile semiconductor memory device according to an aspect, having a plurality of cell transistors each having a floating gate and a control gate, and storing data according to a charge accumulation state of the floating gate,
Selecting n number of the same column among the plurality of cell transistors (n ≧ 2), the n number of the cell selection transistor having one end to the transistor is connected, in the same row of said plurality of cell transistors A decode signal is supplied to the row line to which the control gate of the cell transistor is connected, the column line to which the other end of the selection transistor is connected, and each control gate of the cell transistor in the same row via the row line. A first decoder for supplying the selected transistor and a second decoder for supplying a decode signal to the selection transistor to selectively control conduction, and the n cells arranged in different rows group of the connected selection transistor to transistor and the n-number of cell transistors, each said decode signal from the first decoder independently It is supplied to a selected said Guru
Loop is provided between the first decoder and the row line.
When the switching transistor is turned on,
And the decoded signal from the first decoder is
Through the switching transistor that is turned on.
Connected to the switched switching transistor
The non-selected group supplied to the line is the first data.
The switching provided between the coder and the row line
The first decoupling is performed by turning off the transistor.
Between the first decoder and the row line.
The decoded signal from the switched off switch
Not supplied to the row line connected to the transistor
Thus, it is characterized in that it is not affected by the selected group. According to the above configuration, the memory cell size can be reduced and the cost can be reduced while data can be electrically rewritten. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a memory cell section and its peripheral circuit section. An output D of a data input circuit 25 is supplied to the gate of an N-channel MOS transistor 26 whose one end is connected to a high voltage power supply Vp. A selection transistor ST and cell transistors CT1 to CT4 are provided between the other end of the transistor 26 and a ground point (reference potential).
Are connected in series. A signal X1 for selecting the cell transistors CT1 to CT4 is supplied to the gate of the selection transistor ST.
Signals W1 to W4 for selecting these cell transistors CT1 to CT4 are supplied to the control gate of CT4, respectively.
Is supplied. At the connection point (node N1) between the transistor 26 and the selection transistor ST, an N-channel MOS transistor 27 that is controlled to be conductive by a signal R which is at "1" level during reading and "0" level during programming.
And the other end of the transistor 27 is connected to the input end of the data detection circuit 28. Further, a P-channel MOS transistor having a gate connected to the node N2 is connected between the input terminal node N2 of the data detection circuit 28 and the power supply V.
The transistor 29 is connected as a load for reading. Here, for convenience, the combination of the selection transistor ST and the cell transistors CT1 to CT4 is referred to as a memory cell. However, this memory cell is different from a general memory cell, and one memory cell has 4 bits (connected in series). (The number of bits corresponding to the number of cell transistors used), and is equivalent to four conventional memory cells. Next, the operation of the above configuration will be described. FIG. 2 is a timing chart of each signal at the time of programming in the circuit of FIG. First, the signal R is set to the "0" level to turn off the transistor 27, and at time t0, the signals X1 and W1 to W4 are set to the high voltage level. The thin oxide film of the cell transistor shown (film thickness 100
Electrons are injected into the floating gates of the cell transistors CT1 to CT4 via the 3333. The signals W4 to W1 are sequentially set to 0 V at the next timings t1 to t4. When these signals W1 to W4 are set to 0V, if the data D output from the data input circuit 25 is at "1" level, the transistor 26 is turned on, and the transistor 26 and the selection transistor are switched from the high voltage power supply Vp. A high voltage is applied to the drain of the corresponding cell transistor via ST, and electrons are emitted from the floating gate by the tunnel effect. In FIG. 2, when the signals W3 and W1 are set to 0V, the data D is at the "1" level (time t2 to t3, time t4 to t5).
), The electrons injected into the floating gates of the cell transistors CT3 and CT1 are released. What is important here is not the application of 0 V to the control gate and the application of a high voltage to the drain, but the strength of the electric field in the region where the tunnel effect occurs, and the application of the electric field where the tunnel effect occurs selectively to each cell transistor. Thus, data is selectively programmed in each cell transistor. For example,
Since the cell transistor CT4 does not become an electric field where the tunnel effect occurs in the region where the tunnel effect occurs after the time t1, no electron is exchanged with the floating gate. Between times t0 and t1, the electrons injected into the floating gates of the cell transistors CT1 to CT4 are:
Between times t1 and t2, between times t2 and t3, and between times t3 and t4
Cell transistors CT1 to CT1 depending on whether data D is at "1" level or "0" level during time t4 to t5.
The program is performed depending on whether or not electrons are emitted from the floating gate of FIG. At the timing between times t1 and t2, signals X1 and W1 through W3 are set to a high voltage level, and select transistor ST and cell transistors CT1 through CT2 are set.
3 turns on. At this time, the signal W4 is set to 0 V, and the data D is at the "0" level.
Is off, and no high voltage is applied to the cell transistor CT4, so that the electrons injected into the floating gate of the cell transistor CT4 are not emitted. At the timing between times t2 and t3, the signals X1 and W1 and W2 are set to the high voltage level, and the selection transistor ST and the cell transistors CT1 and CT3 are set.
2 turns on. At this time, the signal W3 is set to 0 V and the data D is at the "1" level.
Is turned on, and a high voltage is applied to the cell transistor CT3. At this time, since 0 V is applied to the control gate of the cell transistor CT3, the electric field applied to the thin insulating film increases, causing a tunnel effect, and the electrons injected into the floating gate of the cell transistor CT3 are emitted. You. At this time, the transistor 26 and the cell transistor CT
Since the cell transistor CT3 exists between the cell transistor CT4 and the cell transistor CT4, a high voltage is not applied to the cell transistor CT4, and programming is performed only on the cell transistor CT3. At the timing between times t3 and t4, signals X1 and W1 are at a high voltage level, and signals W2 through W4 are at 0V.
Is set to At this time, since the data D is at the “0” level, the transistor 26 is turned off and the cell transistor CT is turned off.
Since no high voltage is applied to 2, the electrons injected into the floating gate of this cell transistor CT2 are not emitted. At the timing between times t4 and t5, the signal X1 is set to the high voltage level, the signals W1 to W4 are set to 0 V, and the selection transistor ST is turned on. At this time, since the data D is at the "1" level, the transistor 26 is turned on, and a high voltage is applied to the cell transistor CT1, so that the electric field applied to the thin insulating film becomes large and a tunnel effect occurs. The electrons injected into the floating gate of CT1 are emitted. At this time, the transistor
Since the cell transistor CT1 exists between the cell transistor CT2 and the cell transistors CT2 to CT4, no high voltage is applied to the cell transistors CT2 to CT4.
Programming is performed only on cell transistor CT1. On the other hand, when data is read, signals R and X1 are set to "1" level, and the control gate of the cell transistor to be read is set to 0V. At this time, the gates of the other cell transistors are set to "1" level. The timing chart of FIG. 3 shows a case where data is sequentially read from the cell transistors CT4 to CT1, and between the time t0 and t1, the data is read from the cell transistor CT4.
From the cell transistor CT3 between the times t1 and t2, and from the cell transistor CT2 between the times t2 and t3, the time t3
, T4, data is read from the cell transistor CT1. Now, assuming that the signal W1 is set to 0V and the signals W2 to W4 are set to "1" level, the cell transistor C
Data is read from T1. If the programming is performed as described above, since electrons are emitted from the floating gate of the cell transistor CT1, the threshold voltage thereof is negative and the threshold voltage is turned on even when the signal W1 is 0V. The control gates of the other cell transistors CT2 to CT4 are at the "1" level and are on. Therefore, all the cell transistors CT1 to CT4 are turned on,
The potential of the node N2 drops. This is used as the data detection circuit 28
To read data from the cell transistor CT1. Also, the signal W2 becomes 0V and the cell transistor C
When T2 is selected, the cell transistor CT2
Since the electrons are still injected into the
If it is V, it is turned off. Therefore, the node N2 is charged by the transistor 29, which is connected to the data detection circuit 28.
To detect. Note that the threshold voltages of the cell transistors CT1 to CT4 in the state where electrons are injected need to be set so as to be turned on when the control gates thereof become "1" level. FIGS. 4A to 4C show an example of the structure of a transistor suitable for the cell transistors CT1 to CT4 shown in FIG. 1. A part of the insulating film on the channel region is made as thin as about 100 angstroms. It is formed of an oxide film to reduce the cell size. (A) is a plan view of the pattern, (b) is a cross-sectional view taken along line BB 'of (a), and (c) is a cross-sectional view taken along line CC' of (a). Where 30 is a P-type silicon substrate, 31 and 32 are N ⁺ -type sources,
The drain region, 33 is a thin oxide film, 34 is a floating gate, and 35 is a control gate. FIGS. 5A and 5B show another example of a structure suitable for the cell transistors CT1 to CT4 in FIG. 1. In FIG. 5A, all the insulating films on the channel region are thinly oxidized to about 100 angstroms. The film 33 is formed. In FIG. 5, the same portions as those in FIG. 4 are denoted by the same reference numerals, (a) is a plan view of the pattern, and (b) is a view of FIG.
It is sectional drawing which followed the -C 'line. FIGS. 6A and 6B show still another example of the structure suitable for the cell transistors CT1 to CT4 in FIG. 1, and a part of the channel region is a depletion type transistor. (A) is a plan view of the pattern, and (b) is a cross-sectional view taken along line BB 'of (a). In such a configuration, even if the amount of injected electrons is too large and the cell transistor has a threshold voltage at which the cell transistor is not turned on even when a signal of the “1” level is supplied to the control gate, the N voltage is not increased.
^The source / drain regions 31,
Since 32 is connected, current flows. In reading data from the cell transistor having such a configuration, when a potential of "0" level is applied to the control gate, a difference in the amount of current caused by whether or not electrons are injected into the floating gate is detected. Performed by FIG. 7 shows a configuration example of a nonvolatile semiconductor memory device in which the above-mentioned memory cells are arranged in a matrix. In FIG. 7, reference numeral 37 denotes a row decoder, 38 denotes a first column decoder, and 39 denotes a second column decoder. Data input / output lines IO1 to IO8 are connected to circuits surrounded by a dashed line in FIG. You. The above row decoder
37 are signals X1, X2,..., Signals W11, W12,.
n, signals W21, W22,..., W2n are output to select the row direction of the memory cell array. The column decoder 38 outputs signals Y1, Y2,..., Ym to selectively control conduction of the column selection MOS transistors Q1 to Qm, thereby inputting data to one of the memory cell blocks B1 to Bm. This is for supplying data to be programmed via output lines IO1 to IO8, or for deriving read data. On the other hand, the column decoder 39 outputs signals Z2 to Z2.
m to selectively designate the memory cell blocks B1 to Bm at the time of programming by selectively controlling conduction of the depletion type array divided MOS transistors QD2 to QDm. In the above configuration, programming is performed from a memory cell located far from row decoder 27. FIG. 8 is a timing chart of each signal at the time of this programming. That is, programming is performed from the memory cells connected to the signal line X1 of the memory cell block Bm.
In this program, the signals X1, Ym, Z2 to Zm
And a high voltage is applied. In this state, first, the signals W11 to W11 are output.
With W1n set to a high voltage, electrons are injected into the floating gates of all cell transistors. Next, the signals are sequentially set to "0" level from the signal W1n to the signal W11. At this time, when the control gate is at the "0" level, the program data is transferred to the data input / output lines IO1 to IO8, the column selection transistor Qm,
Electrons are emitted only when a high voltage is applied to the drain via the selection transistor STm, and data is programmed in each cell transistor. FIG. 9 shows a timing chart at the time of reading, and the signals X and X corresponding to the selected memory cell are shown.
Y becomes "1" level. Also, one of the signals W11 to W1n corresponding to each cell transistor of the selected memory cell is selected.
One is at the “0” level, and the control gates of the unselected cell transistors are all at the “1” level. by this,
Data is read out as in the case of FIG. FIG. 10 summarizes the levels of the signals W11 to W1n in a truth table. When the input data I is at the "1" level, the signals W11 to W1n are all at the "1" level and the cell Electrons are injected into the floating gate of the transistor. When the data I is at the "0" level and the R is at the "0" level, programming is performed individually, and when the R is at the "1" level, the data is read. FIG. 11 shows each signal X1, X2,
The truth tables of W11 to W14 and W21 to W24 are shown for three addresses A0 to A2. In this example, at the time of reading, for example, if X1 = 0, the signals W11-W
Although all 14 are set to the "0" level, one of W11 to W14 may be set to the "0" level as in the case of X1 = 1. FIG. 12 shows another embodiment of the present invention. A signal .phi. Between the cell transistor CT4 and the ground point in FIG. 1 which becomes "0" level at the time of programming and "1" level at the time of reading is shown. An N-channel MOS transistor 40 whose conduction is controlled is provided. FIG.
In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. According to such a configuration, when a high voltage is applied to the drain during programming,
Even if there is a leakage current from the cell transistors CT1 to CT4, the leakage current can be cut off by the transistor 40, so that a decrease in the drain potential can be prevented and the deterioration of the program characteristics can be prevented. The transistor 40 may be shared by a plurality of cell blocks. FIG. 13 shows another configuration example when the circuit of FIG. 1 is formed in a matrix. This circuit corresponds to one of the memory cell blocks B1 to Bm in FIG. 7, and in such a configuration, MOS transistors QT1, QT2 controlled by signals X1, X2,. ,.., And the signals are input via these transistors QT1, QT2,..., The signals Z2, Z3,.
If the signals W1n1,..., W121 and W111 inputted to the corresponding memory blocks by taking logic with m and the like become high voltage, any memory block can be freely programmed. At this time, if the signals W111, W121,..., W1n1 are wired by the aluminum wiring of the second layer using a two-layer aluminum wiring, the chip size is increased by increasing the wiring of the signals W111, W121,. Need less. A latch circuit is provided for each column line, and data to be written into these latch circuits is latched. Based on the latched data of the memory cells for one row, a latch circuit is provided for each column line. If the potential is set to a high potential or 0 V, all the memory cells on all the column lines for one row can be programmed, so that the array dividing MOS transistors QD2 to QDm shown in FIG. 7 can be omitted. As described above, according to the present invention,
A nonvolatile semiconductor memory device that can reduce the size of a memory cell and reduce costs while electrically rewriting data can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a nonvolatile semiconductor memory device according to one embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1; FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 1; FIG. 4 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1; FIG. 5 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1; FIG. 6 is a diagram showing a configuration example of a cell transistor in the circuit of FIG. 1; FIG. 7 is a diagram showing a configuration example of a memory formed by arranging the cell transistors of FIG. 1 in a matrix. FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7; FIG. 9 is a timing chart for explaining the operation of the circuit of FIG. 7; FIG. 10 is a diagram showing the level of each signal in the circuit of FIG. 7; FIG. 11 is a diagram showing the level of each signal in the circuit of FIG. 7; FIG. 12 is a diagram for explaining another embodiment of the present invention. FIG. 13 is a view for explaining another embodiment of the present invention. FIG. 14 is a diagram showing a symbol of a cell transistor. FIG. 15 is a diagram showing a control gate voltage-drain current characteristic of the cell transistor shown in FIG. 14; FIG. 16 is a diagram showing a circuit configuration example of an EEPROM configured using the cell transistors of FIG. 14; FIG. 17 is a diagram showing an example of a pattern configuration of the circuit of FIG. 16; [Description of Symbols] ST: transistors for selection, CT1 to CT4: cell transistors, 40: transistors cut off during programming, 37: row decoder, 38: first column decoder, 39: second
Column decoders, IO1 to IO8 ... data input / output lines, Q1
ＱQm: column selection transistor, QD2 to QDm: array division transistor, QT1, QT2,.
B1 to Bm ... memory cell block (memory cell array), X1, X2, ..., Y1 to Ym, W11 to W1n, W21
~ W2n, W111 ~ W1n1 ... signals.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification symbol FI H01L 29/788 H01L 29/78 371 29/792 (58) Investigated field (Int.Cl. ⁷ , DB name) G11C 16/02 H01L 21/8247 H01L 27/10 H01L 29/788

Claims (1)

(57) [Claims] A plurality of cell transistors each having a floating gate and a control gate, and storing data according to the charge storage state of the floating gate; and n (n ≧ 2) in the same column among the plurality of cell transistors. selecting, the n number of the cell selection transistor having one end to the transistor is connected, and the row line control gates of the same row of the cell transistors of the plurality of cell transistors are connected, the selection transistor A column line to which the other end is connected, a first decoder for supplying a decode signal to each control gate of the cell transistors in the same row via the row line, and a decode signal to the select transistor And a second decoder for selectively controlling conduction, and wherein the n cell transistors and the n number of n transistors are arranged in different rows. The group of the connected selection transistor Le transistors, each said first decoder
The decode signal is independently supplied, it is selected from
The group includes the first decoder and the row line.
The switching transistor provided between them is turned on
Thus, the decoded signal from the first decoder
Signal passes through the above-mentioned switching transistor.
Connected to the turned on switching transistor
It is supplied to that the row line, the non-selected said group, said
The switch provided between the first decoder and the row line.
When the switching transistor is turned off,
1 between the first decoder and the row line.
The decode signal from the decoder is
Supplied to the row line connected to the switching transistor
A non-volatile semiconductor memory device that is not affected by the selected group. 2. A column decoder for selecting the column to which the other ends of the corresponding selection transistors in the same column of the group arranged in the different rows are connected to each other. 2. The nonvolatile semiconductor memory device according to 1. 3. 3. The nonvolatile semiconductor memory according to claim 2, further comprising a column selection transistor having one end connected to the column line for selecting the column, and a gate supplied with a signal from the column decoder. apparatus. 4. Having a predetermined number of the above groups in the row direction,
Memory consisting of the above groups having a predetermined number in the column direction
A plurality of cell blocks are further provided, and the switching
The transistor and the column selection transistor are
Each of the above memory cells is provided corresponding to a recell block.
Each of the column lines of the block has the column selection transistor
One end is connected to each column of each memory cell block.
Each memory of the column select transistor connected to a line
4. The nonvolatile semiconductor memory device according to claim 3, wherein the other ends of the corresponding column selection transistors between the cell blocks are connected to each other.