JP2003076340A - Method for driving display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving method of a display device capable of realizing pseudo HV (horizontal and vertical) inversion drive without enlarging the capacity of a memory in a timing controller IC. SOLUTION: In a timing controller IC 160, a video signal which is inputted serially from the outside is rearranged in a two-pixel unit and it is made to be outputted as serial video signals of every polarity and in DACs (digital-to- analog converters) 140, 150, the serial video signals of every polarity are made to be rearranged into parallel video signals corresponding to output orders of every polarity by latching the video signals before they are subjected respectively to digital-to-analog conversion.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a polysilicon T
The present invention relates to a driving method of an active matrix type liquid crystal display device composed of FT.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device composed of polysilicon TFTs, a video signal is supplied to a signal bus line on a glass substrate and distributed to a plurality of column electrodes at regular time intervals. For example, in the V line inversion drive, the distribution is performed such that the potentials of the adjacent column electrodes have opposite polarities for each frame.

In the liquid crystal display device by the V line inversion drive as described above, when a black window is displayed on the halftone background, crosstalk (hereinafter, vertical stroke) appearing at the top and bottom of the window screen becomes a problem. As one of the methods for improving this vertical stroke, for example, Japanese Patent Publication No. 6
Japanese Patent Laid-Open No. 3-48077 discloses a liquid crystal display device by pseudo HV inversion driving.

[0004]

The above-mentioned pseudo HV
In order to realize the inversion driving, it is necessary to rearrange the output order of the video signal for each horizontal period. However, when the rearrangement of the output order of the video signals is performed by the timing controller IC, it is necessary to increase the capacity of the memory in the timing controller IC.
There arises a problem that an increase in power consumption and an increase in cost due to an increase in IC chip size cannot be avoided.

The timing controller IC is
The control circuit performs a process of converting a serial video signal for each color of R (red), G (green), and B (blue) supplied from the outside into a serial video signal for each polarity. The video signals rearranged here are digital-analog converted by a D / A converter, and then output to a drive circuit for the column electrodes.

An object of the present invention is to provide a driving method for a display device which can realize pseudo HV inversion driving without increasing the capacity of the memory in the timing controller IC.

[0007]

In order to solve the above-mentioned problems, the invention of claim 1 provides a plurality of display pixels arranged in a matrix, a plurality of row electrodes arranged between rows of the plurality of display pixels, A plurality of column electrodes arranged between the columns of the plurality of display pixels, and a video signal supplied to the column electrodes by electrically connecting between the column electrodes and the display pixels by a row selection signal supplied to the row electrodes. A display device comprising a plurality of pixel selection elements for writing in the display pixels, wherein the display pixels in each column are alternately connected to one or the other of the column electrodes on both sides via the pixel selection elements. In the driving method described above, a process of rearranging a serial video signal supplied from the outside in units of two pixels to obtain a serial video signal of each polarity, and a serial video signal of each polarity rearranged in the process are polarized. Every Characterized in that it comprises a sorting processing in parallel image signals corresponding to the forces order.

In a preferred mode, the display device supplies a row electrode drive circuit for supplying a row selection signal to the row electrodes, and a video signal having an opposite polarity to every other one of the column electrodes. A column electrode drive circuit that switches polarity and output order at a predetermined cycle, a timing controller IC that rearranges a serial video signal supplied from the outside into a serial video signal of each polarity, and the rearranged video signals in parallel. And a D / A converter for rearranging the video signal and converting the data format of the video signal from digital to analog, rearranging the serial video signal supplied from the outside in units of two pixels and serializing for each polarity. The timing controller executes the processing for converting the video signal into a different video signal, and outputs the serial video signal for each polarity rearranged in the above processing for each polarity. And executes a sorting process to parallel image signals corresponding to the order by the D / A converter.

According to a second aspect of the present invention, in the processing of rearranging the parallel video signals according to the first aspect, processing for changing a relationship between the input of the serial video signal and the output order of the parallel video signal is performed. It is characterized by being included.

In a preferred mode, a normal mode and a signal switching mode are set in the process of rearranging the parallel video signals, and in the normal mode, the serial video signals are rearranged in the order of inputting RGB signals, In the switching mode, when rearranging in the order of inputting RGB,
It is characterized in that the relationship of the output pin of the DAC output signal with respect to the DAC input signal is shifted by one pin.

According to a third aspect of the present invention, in the first or second aspect, the data format of the parallel video signal is converted from digital to analog following the process of rearranging the parallel video signals. .

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the driving method of a display device according to the present invention is applied to a driving method of a liquid crystal display device which performs display by pseudo HV inversion drive will be described below. However, in the present embodiment, a case will be described as an example in which the screen is divided into four and eight pixels are simultaneously written into each block, each of which has an analog signal.

FIG. 4 is a circuit configuration diagram of the liquid crystal display device according to the present embodiment. The liquid crystal display device 100 includes a display pixel section 110 having a plurality of display pixels 10, a row electrode drive circuit 120, a column electrode drive circuit 130, and a DAC 14.
0, DAC150 and timing controller IC16
It is composed of 0s.

Here, the display pixel section 110, the row electrode drive circuit 120, and the column electrode drive circuit 130 are described as a liquid crystal display device with a built-in drive circuit integrally formed on an array substrate (not shown). The circuit 120 and the column electrode drive circuit 130 may be arranged on an external drive circuit board (not shown) like the DACs 140 and 150 and the timing controller IC 160.

The display pixel section 110 is composed of a plurality of display pixels 10 arranged in a matrix. Column electrodes 11 are arranged between the columns of the plurality of display pixels 10, and row electrodes 12 are arranged between the rows. A pixel switch (TFT) 13 as a pixel selection element is arranged at each intersection of both electrodes.

The pixel switches 13 in each column are alternately connected to one or the other of the column electrodes 11 on both sides thereof in order to perform the pseudo HV inversion drive. The pixel switch 13 has a source electrode connected to the column electrode 11 and a drain electrode connected to the pixel electrodes 14 arranged in a matrix. When a row selection signal is applied to the gate electrode of the pixel switch 13 from a row electrode drive circuit 120, which will be described later, the row electrode 12 and the pixel electrode 14 are electrically connected and the column electrode 1
The analog video signal sampled at 1 is written to the pixel electrode 14.

On the other hand, the counter electrode 15 arranged to face the pixel electrode 14 is formed on a counter substrate (not shown). A common circuit (or a timing controller IC, not shown) is connected to the counter electrode 15 through a common wiring 17.
A constant common voltage is supplied from 160). A liquid crystal layer 16 is provided between the pixel electrode 14 and the counter electrode 15.
Is held. An auxiliary capacitance (not shown) is electrically connected in parallel to the pixel electrode 14 in order to stabilize the potential relationship with the counter electrode 15.

The row electrode drive circuit 120 is composed of a shift register and a buffer circuit (not shown), and supplies a row selection signal to each row electrode 12 based on a vertical clock signal and a vertical start signal supplied from the timing controller IC 160. .

The column electrode drive circuit 130 is composed of a shift register, a signal bus line, an analog switch and the like, which are not shown. Analog switch is pixel switch 1
The same TFT as that of No. 3 has its source electrode connected to the signal bus line, its drain electrode connected to the column electrode 11, and its gate connected to the output of the shift register. The shift register is a timing controller I
A column selection signal is output based on the horizontal clock signal and horizontal start signal supplied from C160. When the column selection signal is applied to the gate electrode of the analog switch, the signal bus line is electrically connected to the column electrode 11, and the analog video signal supplied to the signal bus line is sampled by the column electrode 11. It Here, in order to perform the pseudo HV inversion drive, every other column electrodes 11 are supplied with video signals of opposite polarities, and the polarities of the video signals supplied to the respective column electrodes 11 are inverted every frame. Further, the output order of the signals is switched every horizontal scanning period (1H). The polarity and output order of the video signal supplied to the column electrode 11 will be described later.

The timing controller IC 160 rearranges a serial video signal (controller input signal) supplied from the outside in units of two pixels, as will be described later, and outputs the serial video signal for each polarity. Similarly, it also generates and outputs various clock signals and start signals for driving the row electrode drive circuit 120 and the column electrode drive circuit 130 based on the reference clock signal supplied from the outside.

In the present embodiment, as described above, the analog video signal is simultaneously written in 8 pixels in each divided block. Therefore, the timing controller IC 160 has 8 pixels of R (red), G (green), B
Each (blue) video signal is serially input in three systems. It should be noted that one pixel is composed of three sub-pixels of R, G, and B, and a video signal for eight pixels (24 signal inputs)
, R is R1, R2 ... R8, G is G1, G2 ... G
8 and B, B1, B2 ... B8 are serially input. Rearrangement of video signals in the timing controller IC 160 will be described later with a specific example.

The DAC (positive polarity) 140 and the DAC (negative polarity) 150 respectively convert the data formats of the positive polarity and negative polarity video signals output from the timing controller IC 160 from digital to analog, and the column electrode drive circuit. The signal is supplied to a signal bus line (not shown) of 130. Each D
The AC is composed of a latch circuit (not shown) that temporarily holds the input video signal, a DAC main circuit that converts the data format from digital to analog, and the like.

In this embodiment, the serial video signals (DAC input signals) sorted by polarity in the timing controller IC 160 are sequentially latched by the latch circuit and are sorted into parallel video signals according to the output sequence for each polarity. After the replacement, the DAC main circuit converts the data format from digital to analog, and outputs the parallel video signals (DAC output signals) at the same time. The output order means the order of arrangement of video signals output in parallel.

The rearrangement of video signals as described above has two modes, a normal mode and a signal switching mode, which will be described later. When the normal mode is set, the video signals are rearranged in the RGB input order, and when the signal switching mode is set, the DAC output signal corresponding to the DAC input signal is rearranged. The process of shifting the relationship of the output pins by 1 pin is performed. The rearrangement in these two modes will be described later.

Next, a driving method in the case of performing the pseudo HV inversion drive in the liquid crystal display device 100 configured as described above will be described.

FIG. 2 is an explanatory diagram showing the relationship between the DAC output signal and the column electrode in the pseudo HV line inversion drive of this embodiment. FIG. 2 shows a connection relationship between the display pixels 10 arranged in a matrix and the plurality of column electrodes 11 arranged between the columns, and R shown in each display pixel 10 is shown.
The symbols 1, G1, B1, etc. indicate the written DAC output signals.

Further, FIG. 2A shows an odd frame, FIG.
(B) shows the polarity of each column electrode 11 in an even frame. The column electrodes 11 to which the positive polarity DAC output signal is supplied are indicated by symbols such as P1, P2, P3, etc., and the column electrodes 11 to which the negative polarity DAC output signal is supplied are N1, N2, and so on.
It is shown by a code such as N3 .... The polarity of the video signal supplied to the column electrode 11 is inverted in each of the odd frame and the even frame, and the output order is odd write lines (1H, 3H, 5H, ...) And even write lines (2
H, 4H, 6H, ...). The output order of video signals in each frame and each write line is as follows.

(A) Odd frame odd number write line Positive DAC output signal (P): R1, B1, G2, R3, B3, G4, R5, B5, G6, R7, B7, G8 Negative DAC output signal (N): G1, R2, B2, G3, R4, B4, G5, R6, B6, G7, R8, B8 Even write line Positive DAC output signal (P): B8, G1, R2, B2, G3, R4, B4, G5, R6, B6, G7, R8 Negative DAC output signal (N): R1, B1, G2, R3, B3, G4, R5, B5, G6, R7, B7, G8 (B) Even Frame odd write line Positive DAC output signal (P): G1, R2, B2, G3, R4, B4, G5, R6, B6, G7, R8, B8 Negative DAC output signal (N): R1, B1 , G2, R3, B3, G4, R5, B5, G6, R7, B7, G8 Even write line Positive DAC output signal (P): R1, B1, G2, R3, B3, G4, R5, B5, G6 , R7, B7, G8 Negative DAC output signal (N): B8, G1, R2, B2, G3, R4, B4, G5, R6, B6, G7, R8 Fig.2 (A), (B) In, the rightmost column electrode and the leftmost column electrode have the same wiring.

FIG. 1 is an explanatory diagram showing a procedure of rearranging video signals in the timing controller IC and each DAC. FIG. 1A shows an odd-numbered frame and an odd-numbered write line.
FIG. 1B shows an even-numbered write line in an odd-numbered frame, FIG.
(C) is an even frame and an odd write line, FIG.
(D) shows rearrangement on even write lines in even frames.

As shown in FIG. 1, in the timing controller IC 160, the video signals serially input in the three systems of R, G and B are rearranged according to each frame and write line. The sort here is
One pixel unit (for example, R
1, B1, G2 / R3, B3, G4 / R5, B5, G6
...), and one pixel unit (for example, G1, R2, B2 / G3, R4, B4 / G) for the negative polarity DAC 150.
5, R6, B6 ...). In this case, since the rearrangement may be performed in units of 2 pixels in total, the memory required for the timing controller IC 160 is 2 pixels in total. The output from the timing controller IC 160 is positive, negative, R1, R3, R5 ..., B1, B3, B.
.., G2, G4, G6, ..., Three systems of serial DAC input signals.

Next, in the DACs 140 and 150, the three serial DAC input signals rearranged by the timing controller IC 160 are sequentially latched by a latch circuit (not shown) and arranged in parallel video signals according to the output order of each polarity. Can be replaced.

FIG. 3 is an explanatory diagram showing a procedure for rearranging video signals in the positive and negative DACs. FIG. 3A shows the procedure when the normal mode is set, and FIG. 3B shows the procedure when the signal switching mode is set. Moreover, FIG. 3 (A), (B)
1, I01, I02, I03, I04 indicating the DAC input signal (and the DAC output signal) are, for example, R in FIG.
It corresponds to 1, R3, R5 and R7. Also, S1, S
2 indicates the DAC output pin number.

In the normal mode of FIG. 3A, the video signals are rearranged in the order of each input. That is, the input order of each system is I01, I02, I03 ..., I11, I12, I
13 ..., I21, I22, I23 ..., I01, I11, I21, I02, I12, I2 in each input order.
The rearrangement of 2 ... is performed. Then, analog conversion is performed and parallel video signals arranged as described above are output. Further, in the signal switching mode of FIG. 3B, the video signals are rearranged in the same input order as in the normal mode, but the processing of shifting the relationship between the DAC input signal and the output pin of the DAC output signal by one pin is performed. . That is,
The DAC output signal is output from the output pin shifted by one pin from the original position, and I24, I01, I11, I21 ...
Will be rearranged.

In the signal switching mode, the positive polarity DAC 140 of the odd frame and the even write line of FIG. 1B is used.
1 and the even frames and the even write lines of FIG. 1D are set in the negative polarity DAC 150. In other sorts, the normal mode is set.

The result of the rearrangement as described above is as described in each write line of each frame in FIG. For example, in the odd-numbered write line of the odd-numbered frame in FIG. 1A, R1, B1, and G are used as positive polarity video signals.
2, R3 ... Are output and G1, G1 is output as a negative video signal.
R2, B2 ... Are output. By writing every other positive or negative video signal to the column electrode 11, as shown in FIG. 2A, R1 (P1), G1 (N1),
Video signals such as B1 (P2), R2 (N2) ... Are supplied to the odd write lines (1H, 3H, etc.).

According to the pseudo HV inversion drive of the above embodiment, the rearrangement of the video signals is performed by the timing controller IC.
Not only this, but also the positive / negative DAC is performed, so that the pseudo HV inversion drive can be realized without increasing the capacity of the memory in the timing controller IC. Therefore, there is no increase in cost due to an increase in power consumption of the timing controller IC and an increase in the chip size of the IC, and the vertical stroke, which has been a problem in the V line inversion drive, is improved and good display quality is obtained. It becomes possible.

By the way, under the same conditions as in the above embodiment, when all the video signals are rearranged by the timing controller IC, the rearrangement must be carried out in units of 8 pixels in total of positive and negative signals. Therefore, the total required memory is 8 pixels. On the other hand, in the present embodiment, since the rearrangement may be performed in units of two pixels in total of positive and negative, the timing controller I
The memory required for C is 2 pixels in total, and the memory capacity can be reduced to 1/4.

[0038]

As described above, according to the driving method of the display device of the present invention, the pseudo H level is achieved without increasing the capacity of the memory in the timing controller IC.
V inversion drive can be realized. As a result, it is possible to improve the vertical stroke and obtain good display quality without increasing the cost.

[Brief description of drawings]

1A to 1D are timing controller ICs.
And an explanatory diagram showing a procedure of rearranging video signals in each DAC.

2A and 2B are explanatory diagrams showing a relationship between a DAC output signal and a column electrode in the pseudo HV line inversion drive of the embodiment.

3 (A) and 3 (B) are explanatory diagrams showing a procedure of rearranging video signals in a positive / negative DAC.

FIG. 4 is a circuit configuration diagram of a liquid crystal display device according to an embodiment.

[Explanation of symbols]

10 ... Display pixel, 11 ... Column electrode, 12 ... Row electrode, 100
... liquid crystal display device, 110 ... display pixel portion, 120 ... row electrode drive circuit, 130 ... column electrode drive circuit, 140 ... DAC
(Positive polarity), 150 ... DAC (negative polarity), 160 ... Timing controller IC

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 680 G09G 3/20 680G H04N 5/66 102 H04N 5/66 102B F term (reference) 2H093 NC22 NC24 NC34 ND15 ND39 ND54 5C006 AA22 AF23 AF25 AF82 BB14 BB16 BC11 BC16 FA44 FA47 5C058 AA06 BA01 BA26 BB25 5C080 AA10 BB06 CC03 DD10 DD22 DD25 DD26 FF11 JJ02 JJ06

Claims (3)

[Claims] 1. A plurality of display pixels arranged in a matrix, a plurality of row electrodes arranged between rows of the plurality of display pixels, a plurality of column electrodes arranged between columns of the plurality of display pixels, The display of each column is provided with a plurality of pixel selection elements for electrically connecting the column electrode and the display pixel by a row selection signal supplied to a row electrode to write the video signal supplied to the column electrode to the display pixel. In a method of driving a display device in which pixels are alternately connected to one or the other of the column electrodes on both sides via the pixel selection element, a serial video signal supplied from the outside is output in units of two pixels. And a process of rearranging the serial video signals of each polarity into serial video signals, and a process of rearranging the rearranged serial video signals of each polarity into parallel video signals according to the output order of each polarity. And a method for driving a display device. 2. The process of rearranging to the parallel video signal includes a process of changing the output order of the parallel video signal with respect to the input of the serial video signal. Driving method of display device. 3. The drive of the display device according to claim 1, wherein the data format of the parallel video signal is converted from digital to analog subsequent to the processing of rearranging the parallel video signals. Method.