JP2003068872A - Semiconductor device having high dielectric strength - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having high dielectric strength which is not deteriorated in its dielectric strength even when it is used under a high temperature condition. SOLUTION: This semiconductor device having high dielectric strength comprises a semiconductor region 2, a diffusion region 6 for contact, a isolation diffusion region 4, a field insulation film 16, a metal electrode 25 electrically connected to the diffusion region 6 for contact and a plurality of plate electrodes 18a, 19a formed under the floating condition. Parts (25-1, 25-2) of the metal electrode 25 extend on an interlayer insulation film 34 located on the plate electrodes 18a, 19a and the parts (25-1, 25-2) of the metal electrode and plate electrodes 18a, 19 are respectively capacitance-coupled. The CMOS circuits (7 to 11), resistor (13) and capacitor (12) are respectively provided in a semiconductor region 2 surrounded by the diffusion region 6 for contact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device. In particular, it relates to a high breakdown voltage semiconductor device for controlling an inverter.

[0002]

2. Description of the Related Art FIG. 16 shows an illumination inverter control system as an example of using a conventional high voltage semiconductor device for inverter control. FIG. 16 shows a schematic configuration of the lighting inverter control system.

The lighting inverter control system shown in FIG. 16 includes an LC resonance circuit including a fluorescent lamp 100 and a fluorescent lamp 1.
High voltage power NchMOS for supplying electric power to 00
FET 101, 102 and high breakdown voltage power NchMOSF
High voltage side drive circuit 105 for driving the ET 101
And a low voltage side drive circuit 106 for driving the high breakdown voltage power MOSFET 102. The high voltage side drive circuit 105 is composed of a high voltage semiconductor device for controlling an inverter. High voltage power NchMOS
The FETs 101 and 102 are discrete elements. The lighting inverter control system further includes a high breakdown voltage diode 104 and a capacitor 103 for supplying a high voltage side drive circuit power source voltage V2, a high voltage power source terminal 110 for driving a fluorescent lamp, and a low voltage side. It has a drive circuit power supply terminal 107 and an output terminal 109 for driving a fluorescent lamp.

V1 applied to the high-voltage power supply terminal 110 for driving a fluorescent lamp is a DC voltage obtained by rectifying an AC power supply, which is a high voltage of about 600 V at maximum. On the other hand, V3 applied to the low voltage side drive circuit power supply terminal 107 is the power supply voltage of the low voltage side drive circuit, and is usually a low voltage of about 15V.
Then, V2 applied to the power supply terminal 108 for the high voltage side drive circuit is the low voltage side drive circuit voltage V3, the high breakdown voltage diode 104, the capacitor 103, and the high breakdown voltage power NchMO.
It is a voltage defined by S101 and S102, and is a high breakdown voltage power-ON / OFF of NchMOS 101 and 102.
According to the operation, from the voltage of V3 of about 15V, (V
1 + V3) high voltage range up to about 615V.

Next, an outline of the operation of the lighting inverter control system will be described.

First, in the initial state where V3 = 15V and V1 = 600V are applied, the fluorescent lamp driving output terminal voltage V4 is usually set to a state close to the GND potential. Therefore, in this state, the capacitor 103 is charged by the forward operation of the high breakdown voltage diode 104, and V
2 is set to a value obtained by subtracting the forward voltage of the high breakdown voltage diode 104 from V3 = 15V.

Next, the high voltage N
The ch power MOSFET 102 is set to the OFF state, and the high voltage power MOS is controlled by the high voltage side control signal.
The FET 101 is set to the ON state. As a result, the capacitor of the LC resonance circuit including the fluorescent lamp 100 is charged. At this time, the output terminal voltage V4 for driving the fluorescent lamp is set to a potential (V1 = 600V) from near the GND potential by turning on the high withstand voltage power MOSFET 101.
1 to a voltage obtained by subtracting the ON voltage of the high breakdown voltage power NchMOSFET 101). At that time, capacitor 1
03 is charged, the potential difference between V2 and V4, which is the substantial power supply voltage of the high-voltage side drive circuit, is the initial voltage V.
3 = 15V potential (V3 to high withstand voltage diode 10
4 minus the forward voltage). In this way, V2 rises from a potential of V3 = about 15V to a potential of (V1 + V3) = 615V.

After that, the high withstand voltage power NchMOS 101 is turned off by the high voltage side control signal, and the high withstand voltage power NchMO is set by the low voltage side control signal.
Since S102 is set to the ON state, the fluorescent lamp 100 is discharged. At this time, the output terminal voltage V4 for driving the fluorescent lamp is
Since the high breakdown voltage power NchMOS 102 is turned on, the potential around V1 = 600V (the potential obtained by subtracting the ON voltage of the high breakdown voltage power NchMOS 101 from V1) is approximated to the GND potential (from the GND potential to the high breakdown power Nc).
The potential drops to the sum of the ON voltage of the hMOS 102).
At this time, since the capacitor 103 is charged, the potential difference between V2 and V4, which is the substantial power supply voltage of the high voltage side drive circuit, is a potential of V3 = 15V (V3 minus the forward voltage of the high breakdown voltage diode 104). Voltage) can be maintained. In this way, V2 is (V1 + V3) = 6
The potential drops from about 15 V to V3 = about 15 V.

The above-described operation is one cycle operation when the LC resonance circuit including the fluorescent lamp is charged and discharged.

In recent years, a low-voltage side drive circuit of an inverter control system used in the field of lighting (reference numeral 10 in FIG. 16).
6), the high voltage side driving circuit (reference numeral 105 in FIG. 16) and other control circuits are being integrated.
This type of high voltage side drive circuit (reference numeral 105 in FIG. 16) is a circuit block generally called a floating block, and the power supply terminal 108 is not biased to a fixed potential and is in a floating state. FIG. 17 shows a sectional structure when the floating blocks are integrated.

The floating block shown in FIG. 17 includes a P-type semiconductor substrate 1, a semiconductor region 2 containing a low concentration of N-type impurities formed on the substrate, an N-type buried diffusion region 3, and an element. P-type isolation diffusion region 4 for electrically isolating the space
A high-concentration contact N-type diffusion region 6 for applying the potential of the power supply terminal 108 to the semiconductor region 2, a metal electrode 25 for applying a potential to the semiconductor region 2, the isolation diffusion region 4 and the P-type semiconductor substrate. 1 has a metal electrode 33 for applying a potential.

A thin oxide film 15 and a thick oxide film 16 are formed between the isolation diffusion region 4 and the N-type diffusion region 6, and the oxide film 15 and 16 have the same potential as the metal electrode 33. Set plate electrode 17b made of polysilicon,
An electrically floating plate electrode 18b made of polysilicon and a plate electrode 19b made of polysilicon connected to the metal electrode 25 are formed. An interlayer insulating film 34 is formed on the plate electrodes 17b, 18b, 19b, and an electrically floating metal electrode 40 and a metal electrode 41 are formed on the interlayer insulating film 34. ing. Then, the metal electrode 40/4
A surface protective film 35 is formed on top of No. 1, and a sealing resin 36 is further formed.

In the structure shown in FIG. 17, elements such as a CMOS, a capacitor and a resistor that form a high voltage side drive circuit are formed in a region surrounded by the contact N-type diffusion region 6. The region in which this element is formed will be referred to as a "high voltage side drive circuit element region".

In the high voltage side drive circuit element region shown in FIG. 17, NchM forming a part of the high voltage side drive circuit.
OS P-type body diffusion region 7 and P-type body diffusion region 7
The N-type source and drain diffusion regions (8, 9) of the NchMOS and the polysilicon gate electrode 22 of the NchMOS formed inside are formed. The N-type source and drain diffusion regions (8, 9) are connected to NchMOS source and drain metal electrodes (26, 27).
Also, a PchMOS forming a part of the high voltage side drive circuit
P-type source and drain diffusion regions (10, 11) of
PchMOS polysilicon gate electrode 23 and Pch
The source and drain metal electrodes (28, 29) of the MOS are also formed. These form a CMOS transistor element (CMOS inverter).

Further, a P-type diffusion region 12 which is one electrode of the capacitance element, a metal electrode 30 which is connected to the P-type diffusion region 12 and a polysilicon electrode 24 which is the other electrode of the capacitance element are provided. Are formed, and these form a capacitive element. Further, a P-type diffused resistor 13 forming a part of the high voltage side drive circuit and metal electrodes 31 and 32 of the P-type diffused resistor 13 are also formed. By these,
A resistance element is formed.

In the structure shown in FIG. 17, the metal electrode 2
5, the power supply voltage V2 for the high voltage side drive circuit shown in FIG. 16 is applied, and the metal electrode 33 connected to the separation diffusion region 4 is applied with the GND potential. Also, CM
N-channel MOS P-type body diffusion region 7 that constitutes the OS
Becomes the potential of V4 of the high voltage side drive circuit.

As can be understood from the above description of the operation of the inverter control system for lighting, the metal electrode 25 to which V2 is applied, the plate electrode 19b made of polysilicon, and the N-type diffusion region 6 for contact have a low voltage of about 15V. Voltage to a high voltage of about 615V. On the other hand, FIG.
In FIG. 17, the potential of V4 is P of NchMOS.
Since it becomes the potential of the type body diffusion region 7, the potential of the P type body diffusion region 7 changes from near the GND potential to a potential of about V1 = 600V. At that time, the metal electrode 25, the plate electrode 19b made of polysilicon, the high concentration diffusion region 6 and the N
The potential difference of the P-type body diffusion region 7 of the chMOS is 15V.
The potential difference is maintained to some extent.

Therefore, the PN between the P-type semiconductor substrate 1 and the P-type isolation diffusion region 4 and the low concentration N-type semiconductor region 2 is formed.
A high voltage of about 615 V is applied to the junction. FIG. 17
In the configuration shown in, the plate electrodes 17b, 18b,
Numeral 19b is a kind of field plate, and the potential from the metal electrode 25 to the plate electrode 17b is changed by capacitive coupling with the floating metal electrodes 40 and 41 formed further on the interlayer insulating film 34 formed thereon. It has a role of dividing the potential so that the potential distribution on the surface of the semiconductor region 2 is not locally concentrated.

FIG. 18 shows a plane structure of the floating block shown in FIG. In order to make the drawing easy to see, plate electrodes 17b, 18b made of polysilicon,
19b, the metal electrodes 25, 33, 40, 41 and the N-type diffusion region 6 for contact are only shown.

Plate electrodes 17b and 1 made of polysilicon
Each of 8b and 19b has a substantially rectangular annular shape having a predetermined width and a corner portion having an arc shape. The shape of the metal electrodes 25, 33, 40, 41 located above the plate electrodes 17b, 18b, 19b has a predetermined width,
In addition, the corner portion has a substantially rectangular ring shape having an arc shape. However, part of it has been cut off. Metal wiring 49 for propagating the high-voltage side control signal is arranged in the cut-out portion. And the metal electrode 2
In the region surrounded by 5 and the N-type diffusion region 6 for contact, an element for the high voltage side drive circuit is arranged.

Next, how the high breakdown voltage semiconductor device is realized by the structure shown in FIGS. 17 and 18 will be described. FIG. 19 shows the parasitic capacitance in the configuration shown in FIG. On the other hand, FIG.
In the high breakdown voltage semiconductor device having the configuration shown in FIG.
The potential distribution when V) is given is shown. In FIG. 20,
Equipotential lines for each potential are indicated by broken lines.

As shown in FIG. 19, the plate electrode 17b
Between the floating metal electrode 40 and the floating capacitance C1
, A parasitic capacitance C2 exists between the floating metal electrode 40 and the plate electrode 18b, a parasitic capacitance C3 exists between the plate electrode 18b and the floating metal electrode 41, and the floating metal electrode 41
A parasitic capacitance C4 exists between the plate electrode 19b and the plate electrode 19b. The potential of the plate electrode 18b is set by the voltage dividing action of the series connection circuit by these parasitic capacitances C1 to C4, and the appropriate potential distribution is given to the semiconductor region 2. In this way, an appropriate potential distribution can be given, so that a high breakdown voltage semiconductor device is realized. Note that FIG.
The parasitic capacitances C5 and C6 generated between the sealing resin 36 and the inner sealing resin 36 are considered not to exist normally, which will be described later.

Next, refer to FIG. FIG. 20 is a schematic diagram for explaining the concept of the potential distribution of the conventional high breakdown voltage semiconductor device at room temperature. The inventor of the present application has confirmed that the potential distribution shown in FIG. 20 and the result of the simulation performed by the inventor of the present application show similar tendencies.

In the potential distribution shown in FIG. 20, 0 (V) is applied to the P type semiconductor substrate 1, the P type isolation diffusion region 3, the plate electrode 17b and the metal electrode 33, and the N type diffusion region 6,
The case where 600 (V) is applied to the plate electrode 19b and the metal electrode 25 is illustrated. As can be seen from FIG. 20, the same 6 as the N-type diffusion region 6 is formed on the plate electrode 19b.
When a high potential of 00 (V) is applied, the plate electrode 18
An intermediate potential between 600 (V) and 0 (V) is applied to b. As a result, the equipotential lines representing the potential distribution in the semiconductor region 2 are in the vertical direction and have substantially equal intervals. As a result, the electric field concentration in the semiconductor region 2 can be relaxed, and the high breakdown voltage characteristic can be maintained.

[0025]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
A high voltage of (V) or more, for example 600 (V), is applied to the metal electrode 2.
5 is operated at a high temperature of 150 ° C. with the ambient voltage applied to No. 5, the breakdown voltage between the metal electrode 25 and the metal electrode 33 (see FIG.
6, the phenomenon occurs that the breakdown voltage between the terminal 108 for applying V2 and GND is deteriorated. This phenomenon is
It can be reproduced by a life test called a high temperature bias test. In the high temperature bias test, when the applied voltage of the metal electrode 25 is increased, the breakdown voltage deterioration becomes remarkable, and when the applied voltage is lowered, the breakdown voltage deterioration tends to decrease.

Regarding the breakdown voltage deterioration between the metal electrode 25 and the GND in the high temperature bias test, the mechanism thereof has not been clarified yet and it cannot be inferred. However, the following can be inferred.

Generally, a semiconductor chip is sealed with a sealing resin so that moisture does not penetrate into the resin package. However, the novolac epoxy resin that is generally used as a sealing resin has 0.9% to 1.6%.
% Hydroxyl group OH is contained, and this hydroxyl group OH is activated at a high temperature, so that the sealing resin 36, which is generally considered as an insulator, is in a semi-insulating state (state in which it conducts with high resistance). .

Generally, in a high breakdown voltage semiconductor device, a semiconductor chip is molded with a sealing resin 36, and a space between a plurality of external terminals (not shown) and a plurality of pads (not shown) on the semiconductor chip is provided. Are connected by metal wires (not shown). A ground potential of 0 (V), a power supply voltage of 600 (V), and a control signal are applied to these metal wires. Therefore, if the sealing resin 36 is in a semi-insulating state for the above-mentioned reason. , 600 (V) and 0 (V)
It is presumed that an intermediate potential between and is given to the surface of the surface protective film 35. Depending on the layout of the semiconductor chip, for example, a grounding pad (not shown) is provided on the side of the insulated gate transistor on the semiconductor chip, and a power supply pad (not shown) is separated from it. If it is provided at a different position, the sealing resin 36 on the insulated gate transistor may have an intermediate potential of about 100 (V). Taking this into consideration, it is assumed that the interface between the surface protection film 35 of the semiconductor chip and the sealing resin 36 has a potential of 100 (V) during the high temperature bias test. The inventor of the present application examined whether such a situation would occur.

The potential distribution during the high temperature bias test will be described below with reference to FIG. Figure 21
FIG. 21 is a diagram assuming a potential distribution during a high temperature bias test in a high temperature state under the same bias condition as described in FIG. 20. In FIG. 21, the equipotential lines are indicated by broken lines.

In the state shown in FIG. 21, the floating metal electrode 40 has the parasitic capacitances C1 and C2 described above.
In addition to the above, there is a parasitic capacitance C5 formed between the sealing resin 36 (see FIG. 19). Also, regarding the floating metal electrode 41, the above-mentioned parasitic capacitance C
In addition to C3 and C4, there is a parasitic capacitance C6 formed between the sealing resin 36. Therefore, when the parasitic capacitances C5 and C6 have the same capacitance value as the parasitic capacitances C1 to C4, the sealing resin 36 is used during the high temperature bias test.
Is in a semi-insulating state, and the locations on the floating metal electrodes 40 and 41 in the sealing resin 36 are 100 (V), the potential of the floating metal electrode 41, which was about 450 (V) at room temperature, changes to the parasitic capacitance. It is lowered to about 300 (V) due to the influence of C6. Similarly, at room temperature, about 1
The potential of the floating metal electrode 40, which was 50 (V), drops to about 130 (V) due to the influence of the parasitic capacitance C5.
Accordingly, the potential of the plate electrode 18b, which was about 300 (V) at room temperature, drops to about 200 (V). As a result, as shown in FIG. 21, among the equipotential lines that cross the interface between the semiconductor region 2 and the oxide film 16, 200
(V) The above portion is inclined toward the N-type diffusion region 6,
The potential on the oxide film 16 side at the interface becomes a negative potential with respect to the surface of the N-type semiconductor region 2.

At the interface between the N-type semiconductor region 2 and the oxide film 16, if the oxide film 16 side has a negative potential in a high temperature atmosphere, the bonds such as Si--H and Si--OH at the interface are destroyed, It has been reported that positive fixed charges are generated (a book "Reliability Technology for Semiconductor Devices" published by Nikkan Giren Publishing Co., Ltd.). When such a phenomenon occurs, the semiconductor region 2
When positive fixed charges are generated at the interface between the oxide film 16 and the oxide film 16, negative movable charges are also generated in the oxide film 16. Then, the negative mobile charges in the oxide film 16 are attracted to the positive high potential of the metal electrode 25 with the passage of time, and a region in the oxide film 16 in which a large amount of negative charges is distributed is generated near the metal electrode 25.
A region where a large amount of positive fixed charges are distributed occurs at the place where the negative movable charges are generated. That is, since many negative charges exist at the interface in the oxide film 16 near the metal electrode 25,
The holes in the semiconductor region 2 are attracted, and the surface of the N-type semiconductor region 2 is inverted to P-type to become the P-type inversion layer 43. In the region where the positive fixed charges remain, electrons in the semiconductor region 2 are attracted, the electron density in the semiconductor region 2 locally increases, and the N-type storage layer 4 is formed near the surface of the semiconductor region 2.
2.

In this way, when the P-type inversion layer 43 and the N-type storage layer 42 shown in FIG. 21 are formed on the surface of the semiconductor region 2, the N-type diffusion region 6 of the P-type inversion layer 43 is formed. Electric field concentration occurs in the vicinity. It is considered that such electric field concentration deteriorates the breakdown voltage of the high breakdown voltage semiconductor device with time.

Next, a high voltage semiconductor device as a second conventional example will be described with reference to FIGS. 22 shows a cross section of a main part of a high voltage semiconductor device of the second conventional example, and FIG. 23 shows parasitic capacitance in the configuration shown in FIG. 22 and 23, the same parts as those of the first conventional example (FIG. 17) are designated by the same reference numerals and the description thereof will be omitted.

The high breakdown voltage semiconductor device shown in FIG. 22 is designed to have a high breakdown voltage by providing P-type guard ring regions 44 and 45. The difference between the second conventional example shown in FIG. 22 and the first conventional example shown in FIG. 17 is that the second conventional example does not have floating metal electrodes (40 and 41 in FIG. 17). And that P-type guard ring regions 44 and 45 are formed in the N-type semiconductor region 2.

As shown in FIG. 23, in the conventional semiconductor device, a parasitic capacitance C7 exists between the plate electrode 17b and the guard ring region 44, and a parasitic capacitance C8 exists between the guard ring region 44 and the plate electrode 18b. Exists, a parasitic capacitance C9 exists between the plate electrode 18b and the guard ring region 45, and a parasitic capacitance C10 exists between the guard ring region 45 and the plate electrode 19b. A voltage applied between the metal electrode 25 and the metal electrode 33 is divided by a series circuit of these parasitic capacitances C7 to C10, and the potentials of the guard ring regions 44 and 45 and the plate electrode 18b are set. At least, at room temperature, there is no problem in thinking so.

In this structure, when the high temperature bias test is performed as in the first conventional example, the sealing resin 36 is in a semi-insulating state, and as a result, the surface of the surface protective film 35 is 600.
It has an intermediate potential between (V) and 0 (V). If the intermediate potential becomes a low potential of about 100 (V), there is a parasitic capacitance C11 between the sealing resin 36 and the plate electrode 18b. For example, at room temperature, about 300 (V). The potential of the plate electrode 18b becomes about 20.
It happens that it drops to 0 (V). Then, as shown in FIG. 22, a P-type inversion layer 43 is formed between the guard ring regions 44 and 45, and the guard ring regions 44 and 4 are formed.
5 is conducted, and the breakdown voltage of the high breakdown voltage semiconductor device is lowered.

The present invention has been made in view of the above points, and its main purpose is to provide a high breakdown voltage semiconductor device having excellent reliability in which the breakdown voltage does not deteriorate even when used at high temperatures. is there.

[0038]

A high breakdown voltage semiconductor device according to the present invention comprises a second conductivity type semiconductor device formed on a first conductivity type semiconductor substrate.
A conductive type semiconductor region, a second conductive type contact diffusion region formed in the semiconductor region, and formed in the semiconductor region so as to be separated from the contact diffusion region and surround the contact diffusion region. A first conductive type isolation diffusion region, a field insulating film formed on the semiconductor region located between the isolation diffusion region and the contact diffusion region, and the contact diffusion region electrically And a plurality of plate electrodes formed in a floating state on the field insulating film so as to be separated from the contact diffusion region and surround the contact diffusion region when viewed from the substrate normal direction. And an interlayer insulating film formed on the field insulating film and the plurality of plate electrodes. It extends on the interlayer insulating film located on each of the plate electrodes, with each of the part and the plurality of plate electrodes of the metal electrode,
A CMOS circuit and one or both of a resistor and a capacitor are provided in the second conductive type semiconductor region which is capacitively coupled to each other and is surrounded by the second conductive type contact diffusion region. ing.

In a preferred embodiment, the high breakdown voltage semiconductor device is a high breakdown voltage semiconductor device for inverter control including a high voltage side driving circuit, and the high voltage side driving circuit is
It includes the CMOS circuit and one or both of the resistor and the capacitor.

In a preferred embodiment, the metal electrode has a plurality of metal electrodes as a part of the metal electrode, and at least one of the plurality of metal electrodes is the same as the metal electrode. It has a narrower width than the plate electrode that is capacitively coupled.

In a preferred embodiment, the metal electrode covers the entire upper surface of the plate electrode located closest to the contact diffusion region among the plurality of plate electrodes via the interlayer insulating film. Have parts.

In a preferred embodiment, the metal electrode has a plurality of metal electrodes as a part of the metal electrode, and a width of each of the plurality of metal electrodes is different from that of the contact diffusion region. It becomes narrower as it goes away.

In a preferred embodiment, a plurality of first-conductivity-type guard ring regions are formed above the semiconductor regions below the plurality of plate electrodes, respectively.

In a preferred embodiment, the second conductivity type is provided at a position corresponding to the high voltage side driving circuit element region between the first conductivity type semiconductor substrate and the second conductivity type semiconductor region. Embedded regions are formed.

Another high breakdown voltage semiconductor device according to the present invention is an insulating layer formed on a semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type disposed on the insulating layer, and the semiconductor region. A second-conductivity-type contact diffusion region formed in the semiconductor device, an isolation insulating region formed in the semiconductor region so as to surround the contact diffusion region and be separated from the contact diffusion region, and the isolation. Field insulating film formed on the semiconductor region located between the insulating region for contact and the diffusion region for contact, a metal electrode electrically connected to the diffusion region for contact, and the diffusion region for contact A plurality of plate electrodes formed in a floating state on the field insulating film so as to be spaced apart from each other and surround the contact diffusion region when viewed from the substrate normal direction. A field insulating film and an interlayer insulating film formed on the plurality of plate electrodes, wherein a part of the metal electrode is on the interlayer insulating film on each of the plurality of plate electrodes. The part of the metal electrode and each of the plurality of plate electrodes are capacitively coupled to each other and are surrounded by the second conductivity type contact diffusion region. The type semiconductor region is provided with a CMOS circuit and one or both of a resistor and a capacitor.

In a preferred embodiment, the high breakdown voltage semiconductor device is a high breakdown voltage semiconductor device for inverter control including a high voltage side drive circuit, and the high voltage side drive circuit is
It includes the CMOS circuit and one or both of the resistor and the capacitor.

In a preferred embodiment, the metal electrode has a plurality of ring-shaped metal electrodes as a part of the metal electrode, and at least one of the plurality of ring-shaped metal electrodes is the ring-shaped metal electrode. It has a narrower width than the plate electrode capacitively coupled to the metal electrode.

In a preferred embodiment, the metal electrode is a portion of the plurality of plate electrodes which covers the entire upper surface of the plate electrode located closest to the drain diffusion region via the interlayer insulating film. have.

In a preferred embodiment, the metal electrode has a plurality of annular metal electrodes as a part of the metal electrode, and the lateral width of each of the plurality of annular metal electrodes is the drain diffusion region. It becomes narrower as it gets away from.

In a preferred embodiment, a plurality of first conductivity type guard ring regions are formed above the semiconductor regions located below the plurality of plate electrodes, respectively.

Still another high breakdown voltage semiconductor device according to the present invention is for a second conductivity type semiconductor region formed on a first conductivity type semiconductor substrate and for a second conductivity type contact formed in the semiconductor region. A diffusion region, a field insulating film formed on the semiconductor region, a metal electrode electrically connected to the contact diffusion region, and a metal electrode electrically separated from the contact diffusion region and viewed from the substrate normal direction. A plurality of plate electrodes formed in a floating state on the field insulating film so as to surround the contact diffusion region; and an interlayer insulating film formed on the field insulating film and the plurality of plate electrodes. And a part of the metal electrode extends on the interlayer insulating film located on each of the plurality of plate electrodes, and the part of the metal electrode and the part of the metal electrode are provided. A plurality of plate electrodes, each of which is capacitively coupled to each other. In the second conductivity type semiconductor region surrounded by the second conductivity type contact diffusion region, any of a CMOS circuit, a resistor and a capacitor is provided. One or both are provided.

In a preferred embodiment, the surface protection film is further formed on the metal electrode and the interlayer insulating film, and the sealing resin portion is formed on the surface protection film.

In a preferred embodiment, the surface protection film is a multi-layer film including an upper layer made of a polyimide resin and an insulating layer made of an inorganic material as a lower layer.

According to the high breakdown voltage semiconductor device of the present invention, a part of the metal electrode extends on the interlayer insulating film located on each of the plurality of plate electrodes formed in a floating state on the field insulating film. A part of the metal electrode and each of the plurality of plate electrodes are capacitively coupled to each other. Therefore, the capacitance series circuit configured by this capacitance coupling divides the potential of the semiconductor region portion immediately below the plate electrode and the potential of the metal electrode on the interlayer insulating film located on the plate electrode, and the potential of the floating state is reduced. It is possible to apply an appropriate bias voltage to the plate electrode. As a result, the P-type inversion layer that is likely to occur on the surface of the semiconductor region can be suppressed, so that the withstand voltage of the high withstand voltage semiconductor device including one or both of the resistance and the capacitance can be secured even at a high temperature. Therefore, a high breakdown voltage semiconductor device having excellent reliability can be realized.

When the plate electrode on the highest potential side of the plurality of plate electrodes is entirely covered with the metal electrode via the interlayer insulating film, the surface protective film which is easily subjected to stress causes insulation failure. Also, a stable potential can be applied to the lower semiconductor region. Therefore, not only the breakdown voltage deterioration at high temperature can be prevented, but also the breakdown voltage defect due to the insulation defect of the surface protective film can be prevented.

[0056]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the drawings below,
For simplicity of description, components having substantially the same function are designated by the same reference numeral. In the following embodiment, 1
Description will be made focusing on a high breakdown voltage semiconductor device having a breakdown voltage of 00 V or higher (for example, 500 to 800 V). In addition,
The present invention is not limited to the embodiments below. (First Embodiment) A high breakdown voltage semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 schematically shows a cross-sectional structure of the high breakdown voltage semiconductor device of this embodiment, and FIG. 2 schematically shows a planar structure of the high breakdown voltage semiconductor device of this embodiment. In FIG. 2, only the plate electrode and the metal electrode made of polysilicon and the N-type diffusion region for contact are shown for the sake of clarity.

In the high breakdown voltage semiconductor device shown in FIG. 1, the plate electrodes 18a and 19a and a part (25) of the metal electrode 25 provided via the interlayer insulating film 34 located on the plate electrodes 18a and 19a.
-1, 25-2) are capacitively coupled to each other to prevent the breakdown voltage from deteriorating at a high temperature. The mechanism for preventing the breakdown voltage from deteriorating at high temperatures will be described later. The high breakdown voltage semiconductor device of the present embodiment is configured by using the PN junction separation technique, and includes the plate electrodes 18a and 19a.
a and a portion (25-1, 25-2) of the metal electrode 25, inside the high voltage side drive circuit element region located inside (central portion), any of the CMOS circuit (CMOS transistor), the resistance and the capacitance. A high voltage side drive circuit is formed by one or both of them. As shown in FIG. 2, the high voltage side drive circuit in the high voltage side drive circuit element region can be controlled by the high voltage side control signal via the metal wiring 49. This high voltage side drive circuit, in combination with the low voltage side drive circuit of the inverter control system,
An inverter control system can be constructed. The inverter control system including the high-voltage side drive circuit can be used for various applications using the inverter control circuit, such as lighting, PDP, and motor.

In this embodiment, the low voltage side drive circuit (106 in FIG. 16) of the inverter control system is formed in the region outside the PN junction separating metal wiring 33, and the high voltage side drive circuit is formed. The circuit and the low voltage side drive circuit are included in one chip IC. However, the configuration is not limited to this, and the high voltage side drive circuit and the low voltage side drive circuit may be configured separately.

The configuration of the high breakdown voltage semiconductor device of this embodiment will be described in more detail. The high breakdown voltage semiconductor device of this embodiment has a P-type semiconductor substrate 1 and a semiconductor region 2 formed by introducing a low-concentration N-type impurity into the semiconductor substrate 1. In this embodiment, the semiconductor region 2 is formed on the substrate 1 (including the substrate surface). Semiconductor region 2
A contact diffusion region 6 formed by introducing a high-concentration N-type impurity is formed on the surface of the N-type buried region 3 at the center of the interface between the semiconductor substrate 1 and the semiconductor region 2. Are formed. Further, in the semiconductor region 2, a separation diffusion region 4 formed by introducing a P-type impurity is formed so as to be separated from the N-type diffusion region 6 and surround the N-type diffusion region 6. In the low-concentration N-type semiconductor region 2 surrounded by the high-concentration N-type diffusion region 6, high voltage side drive circuit elements such as CMOS, capacitors, and resistors are arranged.

A thin oxide film 15 is formed on the isolation diffusion region 4, and a plate electrode 17a made of doped polysilicon is formed on the oxide film 15. A thick oxide film (field insulating film) 16 is formed on the semiconductor region 2 located between the isolation diffusion region 4 and the high concentration N-type diffusion region 6. A plurality of plate electrodes 18 a and 19 a are formed on the field insulating film 16 so as to be separated from the N-type diffusion region 6 and surround the N-type diffusion region 6 when viewed from the substrate normal direction. Each of the plate electrodes 18a and 19a is in an electrically floating state and is made of doped polysilicon. An interlayer insulating film 34 made of an oxide film or a nitride film is formed on the oxide films 15 and 16 and the plate electrodes 17a, 18a and 19a.

In the separation diffusion region 4, a separation metal electrode 33 is formed.
Are connected. In addition, the N-type diffusion region 6 for contact
A metal electrode 25 is connected to. A part (25-1, 25-2) of the metal electrode 25 is a plate electrode 18a,
19a extending on the interlayer insulating film 34 located on each of the 19a, and a part of the metal electrode 25 (25-1, 25-
2) and the plate electrodes 18a and 19a are capacitively coupled to each other.

The parts 25-1 and 25 of the metal electrode 25 are
-2 is electrically connected to the contact N-type diffusion region 6 through the connecting portion 25-3 and the metal electrode body (25). Furthermore, the metal electrode 25 (25-1 to 25-
3), the interlayer insulating film 34 so as to cover the metal electrodes 26 to 33.
A surface protective film 35 is formed on the top surface, and a sealing resin 36 for molding the surface protection film 35 is formed thereon.

The surface protective film 35 of this embodiment is, for example,
It is composed of silicate glass, silicon nitride, and polyimide resin. Alternatively, the surface protection film 35 may be configured by a combination thereof, or the surface protection film 35 may be configured as a laminated film. When the surface protective film 35 is formed as a laminated film, it is preferable to form an insulating layer made of a polyimide resin on the upper layer. In that case, in the lower layer,
An insulating layer (for example, a silicate glass layer or a silicon nitride layer) made of an inorganic material is formed. Examples of the polyimide resin include a polyamide resin, a polyamideimide resin, a polyamic acid resin (a precursor of a polyimide resin), and the like. The sealing resin 36 of this embodiment is made of, for example, novolac epoxy resin.

Unlike the novolac epoxy resin, the polyimide resin maintains a high insulating property even at a high temperature (150 ° C.), so that it can be utilized as a reliable organic insulating film. Further, as compared with the inorganic insulating film formed by the CVD method, the polyimide resin has an advantage that the film thickness thereof can be easily controlled. For example, the film thickness can be easily increased by increasing the viscosity of the precursor of the polyimide resin or by applying the precursor twice. Therefore, when the surface protective film 35 is composed of a polyimide resin layer or a multilayer film having a polyimide resin layer as the uppermost layer, for example, the thickness of the surface protective film can be easily controlled. can do. Surface protective film 35
When the thickness is increased, the capacitive coupling between the plate electrodes 18a and 19a and the sealing resin 36 can be reduced, so that the effect of preventing the breakdown voltage at high temperature can be further increased.

The semiconductor region 2 in this embodiment is formed by introducing a low concentration N-type impurity, and
An N type buried diffusion layer 3 exists at the interface between the P type semiconductor substrate 1 and the N type semiconductor region 2. The presence of the N-type buried diffusion region 3 causes a breakdown phenomenon in the PN junction between the locally-provided buried diffusion region 3 and the semiconductor substrate 1, and the applied voltage applied to the drain of the insulated gate transistor. Can be limited, resulting in static electricity,
The withstand voltage against surges caused by power surges, lightning strikes, etc. can be increased. In addition, when the depletion layer extending from the junction surface with the P-type semiconductor substrate 1 into the N-type semiconductor region 2 reaches the P-type diffusion layer (for example, 7, 12, 13) forming the high voltage side drive circuit, the so-called so-called Due to the punch-through phenomenon, the P-type semiconductor substrate 1 is removed from the P-type diffusion layer (for example, 7, 12, 13).
There is a problem that current leaks to the
The buried buried diffusion layer 3 also has a role of preventing such a defect.

However, in the present embodiment, the configuration in which the N-type buried diffusion layer 3 is provided has been described, but the N-type buried diffusion layer 3 may be omitted. In that case, an N-type epitaxial layer may be grown on the P-type semiconductor substrate 1, or an N-type well may be selectively formed on the P-type semiconductor substrate 1 and the N-type well may be used as a semiconductor. It may be used as the area 2. When the N-type well is used as the semiconductor region 2, it is possible to form the CMOS, the capacitance, and the resistance in the semiconductor region 2 of the N-type well without forming the isolation region (separation diffusion region) 4. .

When the N-type epitaxial layer is grown on the P-type semiconductor substrate 1, the thickness of the N-type epitaxial layer is made relatively large so that the P-type semiconductor substrate 1 and the N-type epitaxial substrate 1 are formed.
The depletion layer extending from the junction surface with the N-type epitaxial layer into the N-type epitaxial layer constitutes the high voltage side drive circuit.
It may be arranged so as not to reach the mold diffusion layer (for example, 7, 12, 13). When selectively forming the N-type well in the P-type semiconductor substrate 1, the N-type well is formed relatively deeply and the N-type well is formed from the junction surface between the P-type semiconductor substrate 1 and the N-type well layer. It suffices that the depletion layer extending in the well layer does not reach the P-type diffusion layer (eg, 7, 12, 13).

The breakdown voltage described above mainly relates to the initial breakdown voltage of the high breakdown voltage semiconductor device. The operating principle by which the initial withstand voltage can be maintained even in the life test in the high temperature bias state will be described below.

As shown in FIG. 3, there is a parasitic capacitance Ca1 between the plate electrode 18a and the semiconductor region 2, and a parasitic capacitance Ca between the plate electrode 19a and the semiconductor region 2.
There are two. A parasitic capacitance Cb1 exists between the plate electrode 18a and the metal electrode 25-1, and a parasitic capacitance Cb2 exists between the plate electrode 19a and the metal electrode 25-2. Then, a parasitic capacitance Cc1 exists between the metal electrode 25-1 and the sealing resin 36, and a parasitic capacitance Cc2 exists between the metal electrode 25-2 and the sealing resin 36. The metal electrode 25-
1, 25-2, the applied voltage V2 = 60 to the metal electrode 25
Since 0 (V) is applied, parasitic capacitances Cc1 and Cc2
Does not affect the plate electrodes 18a and 19a. Therefore, parasitic capacitances Ca1, Ca2, Cb1, C
Consider the effect of b2.

The potential of the plate electrode 18a is divided by the series circuit of Ca1 and Cb1 by dividing the potential difference between the potential of the semiconductor region 2 located directly below it and the voltage V2 = 600 (V) of the metal electrode 25. It becomes an electric potential. Further, the potential of the plate electrode 19a is a potential obtained by dividing the potential difference between the potential of the semiconductor region 2 located immediately below it and the voltage 600 (V) of the metal electrode 25 by the series circuit of Ca2 and Cb2. . Based on this, the description will be further continued below.

In the high breakdown voltage semiconductor device of this embodiment, in a region between the isolation diffusion region 4 and the contact N-type diffusion region 6 where the N-type buried diffusion region 3 is absent, a so-called RESURF technique is used. To secure the initial breakdown voltage. The principle will be described below.

Usually, isolation diffusion region 4 and semiconductor substrate 1
Is set to 0 (V), the high-voltage side drive circuit voltage V2 is applied to the metal electrode 25. The applied voltage V2 is 0 (V)
It gradually raises from, and when the V2 is still low,
The depletion layer formed by the PN junction between the P-type isolation diffusion region 4 and the N-type semiconductor region 2 extends from the isolation diffusion region 4 toward the semiconductor region 2 toward the contact N-type diffusion region 6. At the same time, PN between the N-type semiconductor region 2 and the semiconductor substrate 1
The depletion layer also extends from the junction.

When the voltage is further increased, the N-type semiconductor region 2
The portion where the N-type buried diffusion region 3 is absent is filled with a depletion layer and is in a so-called fully depleted state. In the fully depleted state, the electric field concentration caused by the shape of the depletion layer is relaxed, so that the potential distribution becomes uniform, and as a result, the breakdown voltage is improved. A technique for relaxing the electric field and ensuring the breakdown voltage of the semiconductor device by depleting the semiconductor region is called a resurf technique. According to this technique, when the distance in the lateral direction is long, the potential difference per unit distance is small and the electric field strength is small, so that higher breakdown voltage characteristics can be obtained.

In the configuration shown in FIGS. 1 to 3, the metal electrode 2
Even if a voltage of V2 = 600 (V) is applied to 5, the distance between the separation diffusion region 4 and the contact N-type diffusion region 6 is set so that depletion is not performed in the vicinity of the contact N-type diffusion region 6 in FIG. The secured high-voltage device is designed. In this structure, PN is formed in the depletion layer.
The potential changes depending on the distance from the junction, and the undepleted portion has the same potential.

As can be seen from the above, FIGS.
In the structure shown in FIG.
The potential of the portion of the semiconductor region 2 located immediately below the plate electrode 19a closest to the drain voltage is about 500 (V), which is slightly lower than the drain voltage. Further, the potential of the portion of the semiconductor region 2 located immediately below the plate electrode 18a near the separation diffusion region 4 between the separation diffusion region 4 and the contact N-type diffusion region 6 is less than half the V2 applied voltage 600 (V). The potential becomes a little and becomes about 240 (V).

When the potential of the plate electrode 18a described above is verified based on these, the potential is the potential of the semiconductor region 2 portion immediately below the plate electrode 18a (about 240 V).
And the potential difference from the voltage 600 (V) of the metal electrode 25-1 is divided by the series circuit of Ca1 and Cb1 to obtain a potential of about 420 (V). Also, the plate electrode 19a
The potential difference between the potential of the semiconductor region 2 immediately below the potential (about 500 V) and the voltage 600 (V) of the metal electrode 25-2 was divided by a series circuit of Ca2 and Cb2. Since it becomes the electric potential, it becomes about 550 (V).
A conceptual diagram of the potential distribution under the same conditions as this is shown in FIG. FIG. 4 shows the potential distribution when 600 V is applied to the metal electrode 25, which is 0 V, 100 V, 200 V,
Equipotential lines of 300V, 400V, 500V and 600V are indicated by broken lines. The potential distribution shown in FIG. 4 shows the same tendency as the result of the simulation performed by the inventor of the present application.

As shown in FIG. 21, in the conventional structure, a high voltage of 500 (V) or higher (for example, 600 V).
Is applied to the metal electrode 25 while operating at a high temperature of 150 ° C., the withstand voltage between the metal electrode 25 and the metal electrode 33 (in FIG. 16, the withstand voltage between the terminal 108 to which V2 is applied and the GND). Phenomenon occurs.

However, in the high breakdown voltage semiconductor device of the present embodiment, similarly, a high voltage of 500 (V) or more (for example, 600 V) is applied to the metal electrode 25 while operating at a high temperature of 150 ° C. However, the potential distribution as shown in FIG. 4 is maintained, and the metal electrode 25 and the metal electrode 33 are
The breakdown voltage does not deteriorate during this period. The reason is that, in the present embodiment, the metal electrode 25 is formed even on the interlayer insulating film 34 immediately above each of the plurality of plate electrodes (18a, 19a).
Since the plate electrodes (18a, 19a) and the metal electrodes (25-1, 25-2) are capacitively coupled to each other, they are hardly affected by upper layers of the surface protective film 35 and above. Because you can.

As can be understood from FIG. 4, at the interface between the oxide film 16 and the semiconductor region 2, the oxide film 16 side has a high potential over almost the entire region of the semiconductor region 2. Therefore, even if the high temperature bias test is performed, negative movable charges are not generated unlike the conventional example. Therefore, it is possible to prevent the P-type inversion layer from being generated, and it is possible to eliminate the concern that the initial breakdown voltage deteriorates in the high temperature bias test.

That is, in the high breakdown voltage semiconductor device of the present embodiment, the metal electrode 25 is extended to the interlayer insulating film 34 immediately above each of the plurality of plate electrodes (18a, 19a), and the plate electrode (18a, 19a) and a metal electrode (2
5-1 and 25-2) are capacitively coupled, the plate electrodes (18a, 19a) and the metal electrode (2
5-1, 25-2) and the parasitic capacitance between the semiconductor region 2 immediately below the plate electrode (18a, 19a) and the parasitic capacitance between the plate electrode, The potential of (18a, 19a) can be determined, and the influence of the upper layers of the surface protective film 35 and above can be hardly influenced. As a result, the semiconductor region 2 is formed on each plate electrode (18a, 19a) in the floating state.
A higher potential than that of the metal electrode 25 and the metal electrode 33 can be stably applied even in the high temperature bias reliability test.
It is possible to realize a high breakdown voltage semiconductor device in which the breakdown voltage between them (in FIG. 16, the breakdown voltage between the power supply terminal 108 for applying V2 and GND) does not deteriorate.

In the configuration of the present embodiment described above, the lateral width of the plate electrodes 18a and 19a and the metal electrodes 25-1 and 25-.
The width of 2 is made equal. In this configuration, C
Since the voltage is divided into about 1/2 by the series circuit of a1 and Cb1, the difference between the potential of the plate electrode 18a and the potential of the semiconductor region 2 located immediately below the plate electrode 18a is about 180 (V).
Becomes In some cases, because of the large difference voltage,
There is a possibility that the electric field concentration becomes large near the edge of the plate electrode 18a near the plate electrode 17a and the initial withstand voltage cannot be sufficiently secured. Therefore, in order to avoid this problem, modification such as the following second embodiment may be performed so as to reduce the potential difference between the plate electrode and the semiconductor region. (Second Embodiment) FIG. 5 schematically shows a cross-sectional structure of a high breakdown voltage semiconductor device according to a second embodiment. In the present embodiment, unlike the first embodiment, the metal electrodes 25-1, 25
The horizontal width of -2 is configured to be 1/2 times that of the plate electrodes 18a and 19a.

When the high breakdown voltage semiconductor device according to the second embodiment is verified in the same manner as that of the first embodiment, in the structure of the present embodiment, the potential (about 240 V) of the semiconductor region 2 in the portion located immediately below the plate electrode 18a is determined. , The potential difference from the voltage 600 (V) of the metal electrode 25-1 is divided by the series circuit of Ca1 and Cb1 to obtain the plate electrode 18a and the semiconductor region 2.
Since there is a potential difference (about 120 V) with the plate electrode 1
8a is about 360 (V). Also, the plate electrode 1
When the potential of 9a is verified, the potential becomes about 530 (V). This is because the potential of the plate electrode 19a is the same as the potential of the semiconductor region 2 immediately below the plate electrode 19a (about 500V).
The potential difference between the voltage of 5-2 and 600 (V) is Ca2 and Cb.
This is because the potential is divided by the series circuit of 2.

A conceptual diagram of the potential distribution under the same conditions as
It is also shown in FIG. The broken lines in FIG. 5 represent equipotential lines. The potential distribution shown in FIG. 5 shows the same tendency as the result of the simulation performed by the inventor of the present application.

As can be understood from FIG. 5, at the interface between the oxide film 16 and the semiconductor region 2, the oxide film 16 side has a high potential over almost the entire region of the semiconductor region 2. As a result, it is possible to prevent the P-type inversion layer from being generated and prevent the breakdown voltage from being deteriorated in the high temperature bias test. Moreover, the metal electrode 25-1,
Compared with the experimental result of the above-described first embodiment in which the horizontal width of 25-2 is equal to that of the plate electrodes 18a and 19a,
The experimental result of this embodiment in which the horizontal widths of 5-1 and 25-2 are halved is the plate electrode 17 of the plate electrode 18a.
It was found that the electric field concentration at the end near a can be relaxed. Specifically, an initial breakdown voltage of about 200 (V) higher than that of the example of Embodiment 1 was obtained with the configuration of this embodiment, and the initial breakdown voltage was about 700 (V).

In this embodiment, the plate electrodes (18a,
19a) and the metal electrodes (25-1, 25-2) are more capacitively coupled to the plate electrodes (18a, 19a) and the semiconductor region 2 than to the capacitive coupling.
The potential difference between the plate electrodes (18a, 19a) and the semiconductor region 2 immediately therebelow can be reduced, and as a result, electric field concentration at the end of the plate electrode 18a near the plate electrode 17a can be relaxed, and the initial breakdown voltage can be reduced. Can be sufficiently secured. Moreover, the breakdown voltage does not deteriorate even in the high temperature bias test.

The conditions used in the experiments conducted by the inventor of the present invention in Embodiments 1 and 2 are as follows: the P-type semiconductor substrate 1 has a resistivity of 50 Ω · cm, and the N-type semiconductor region 2 has , Resistivity 5 Ω · cm, thickness 15 μm, N
The buried diffusion region 3 of the mold has a peak impurity concentration of 1 × 10 ¹⁵ (cm ⁻³ ) and a width of about 8 μm in the depth direction. The thickness of the thick oxide film (field oxide film) 16 was 2 μm. The interlayer insulating film 34 includes a 1.2 μm thick CVD film and a 1.8 μm film containing 8.5 wt% phosphorus.
It has a two-layer structure in which a thick CVD film is laminated. The surface protection film 35 is 0.5 μm containing 4.0 wt% phosphorus.
A two-layer structure in which a thick CVD film and a 1.0 μm nitride film were stacked was used. The experiment under these conditions provided good results in which the breakdown voltage between the metal electrode 25 and the metal electrode 33 (the breakdown voltage between the terminal 108 and GND in FIG. 16) was not deteriorated in the high temperature bias test. .

In the second embodiment, the metal electrode 2
5-1 and 25-2 have a width half that of the plate electrodes 18a and 19a located immediately below them, but the withstand voltage required for the semiconductor device is low (for example, about 500V).
If so, a slightly wider width (for example, 2/3 times) may be used. Conversely, if a higher breakdown voltage is required, a slightly thinner width (for example, 1/4 times) may be set. Good.

The structure of the second embodiment described above is based on the premise that the insulating property of the surface protective film 35 can be ensured in any situation, and the metal electrodes 25-1 and 25 are provided.
The horizontal width of -2 is uniformly (1/2 times) narrower than the horizontal width of the plate electrodes 18a and 19a. However, in the case of this configuration, if a defect of the surface protective film 35 occurs and the insulation property is impaired, there is a possibility that the plate electrode 19a on the high potential side is easily affected by the defect. Therefore, in order to avoid this inconvenience, a modification such as the following third embodiment may be performed. (Third Embodiment) FIG. 6 schematically shows a cross-sectional structure of a main part of a high breakdown voltage semiconductor device according to a third embodiment. Unlike the second embodiment, the present embodiment has a configuration in which the ratio of the capacitive coupling between the plate electrode and the metal electrode and the capacitive coupling with the semiconductor region 2 is different for each plate electrode. With this configuration, even if the insulating property of the surface protective film 35 is impaired, it is possible to reduce the influence on the plate electrode 19a on the high potential side.

In the structure shown in FIG. 6, the lateral width of the annular metal electrode 25-1 is set to 1/2 the width of the plate electrode 18a, and the lateral width of the annular metal electrode 25-2 is increased. That is, the width of the annular metal electrode 25-2 is widened so that the entire upper surface of the plate electrode 19a located closest to the N-type diffusion region 6 is covered with the interlayer insulating film 34. Regarding other points, the first embodiment
Since it is the same as that of and 2, the description thereof will be omitted.

As in the present embodiment, the annular metal electrode 25
-2 is wider than the plate electrode 19a located in the lower layer, the plate electrode 19a and the metal electrode 2
Since the value of the parasitic capacitance Cb2 between 5-2 and 5-2 is almost the same, it is possible to obtain substantially the same action and effect as in the above embodiment.

Further, the width of the metal electrode 25-2 in FIG. 6 is further widened to be integrated with the drain metal electrode 25 to form a metal electrode 25-4 as shown in FIG. 7, which is similar to the above embodiment. It is possible to obtain various actions and effects. Note that FIG. 7 is a modification of the configuration shown in FIG. 6, and is the same as the configuration shown in FIG. 6 except that the metal electrode 25-4 and the P-type guard ring regions 44 and 45 are provided. Is. P
The function of the mold guard ring regions 44 and 45 will be described later. In FIG. 7, the P-type guard ring region 4
It is also possible to adopt a configuration in which 4, 45 are not provided.

In the structure shown in FIG. 7, since the upper layer of the plate electrode 19a in the floating state is completely covered with the metal electrode 25-4, even if a defect occurs in the surface protection film 35 and the insulation failure occurs. Since the drain voltage is applied to the metal electrode 25-4, the influence of the insulation failure is blocked by the metal electrode 25-4, and the plate electrode 1 located in the lower layer portion is blocked.
There is no adverse effect on 9a or the portion of the semiconductor region 2 located immediately below it.

On the other hand, the plate electrode 18a in the floating state formed near the isolation diffusion region 4 has a parasitic capacitance Ca1 with the semiconductor region 2 and an annular metal electrode 25-1.
The potential is determined by the voltage division by the series circuit with the parasitic capacitance Cb1 between and. Then, since the lateral width of the metal electrode 25-1 is 1/2 of the lateral width of the plate electrode, Ca1 / Cb1
Is about double, and the potential of the plate electrode 18a is
The potential is set to be slightly higher than the potential of the semiconductor region 2 portion immediately below. Therefore, the P-type inversion layer does not occur on the surface of the semiconductor region 2, and therefore the breakdown voltage does not deteriorate even when the life test such as the high temperature bias test is performed. In addition, the potential of the surface of the semiconductor region 2 is set to the metal electrodes 25-1 and 25-1.
Since it is gradually lowered by -2 (or 25-4), local electric field concentration is avoided and a high initial breakdown voltage is obtained.

Even if a defect occurs in the surface protective film 35, the metal electrode 25-1 is connected to the metal electrode 25, so that the applied potential can be maintained without being affected by the insulation failure. it can. Also, due to poor insulation, the metal electrode 2
When the peripheral portion of 5-1 has conductivity, the conductive portion has the same potential as the metal electrode 25-1, and as a result,
The parasitic capacitance Cb1 is equivalently increased, and the potential of the plate electrode 18a is set slightly higher. That is, even if the surface protection film 35 susceptible to stress causes insulation failure, if the insulation failure is of a small degree, it is possible to realize a highly reliable high breakdown voltage semiconductor device that hardly affects reliability. You can

In the above-described embodiment (FIGS. 1 to 7), two plate electrodes (18) in a floating state are used.
However, the present invention is not limited to this. For example, it is possible to further increase the number of plate electrodes to be three or four, and provide each metal electrode on the upper layer. FIG. 8 is a modification of the embodiment shown in FIG. 7, in which the number of plate electrodes is increased to 5, and the number of P-type guard ring regions is increased to 4. Even in the case of experimenting with this configuration, the breakdown voltage between the metal electrode 25 and the metal electrode 33 (terminal 108 in FIG.
Good results were obtained in which the withstand voltage between the gate and GND did not deteriorate.

The conditions of the configuration shown in FIG. 8 are exemplified as follows. The P-type semiconductor substrate 1 has a resistivity of 50Ω.
cm, and the N-type semiconductor region 2 has a resistivity of 5
N type buried diffusion region 3 with Ω · cm thickness of 20 μm
Has an impurity concentration peak of 1 × 10 ¹⁵ (cm ⁻³ ) and a width of about 8 μm in the depth direction. The P-type guard ring regions 44, 45, 46, 47 are 5 × 10
^It has an impurity surface concentration of ¹⁶ (cm ^-3 ) and a junction depth of 5μ.
m. By the way, in the structure in which the P-type guard ring region is not arranged, the N-type semiconductor region 2 has a resistivity of 5 or less.
Ω · cm, thickness 15μm, set the thickness thin,
It is necessary to make it easier to deplete the peripheral portion of the semiconductor region 2 so that the resurf technique can be utilized.

Thick oxide film (field oxide film) 1
The thickness of 6 was 2 μm. The interlayer insulating film 34 is 1.2
1. A CVD film having a thickness of μm and containing phosphorus of 8.5 wt%.
A two-layer structure was formed by laminating a CVD film having a thickness of 8 μm. The surface protection film 35 has a two-layer structure in which a 0.5 μm thick CVD film containing 4.0 wt% phosphorus and a 1.0 μm nitride film are stacked. Plate electrode 17a,
N-type polysilicon electrodes doped with phosphorus were used as 18a, 19a, 20a, and 21a. The thickness of each plate electrode in the cross section shown in FIG. 8 is 0.5 μm, and the width is
It is 18 μm. The distance between each plate electrode is 3μ.
m. The metal electrodes 25-1, 25-2, 25-4 are
An Al electrode added with 1% of Si is used, and its thickness is 1.2 μm. The horizontal width of the metal electrodes 25-1 and 25-2 is 7 μm, and the overlap between the metal electrode 25-4 and the plate electrode 20a is 6 μm. The configuration of the present embodiment shown in FIG. 8 is considered by the inventor of the present application to be the most preferable for ensuring the merging of breakdown voltages, and the above conditions are considered to be the best by the inventor of the present application. The conditions of the structures shown in FIGS. 4 and 5 which are simplified for explaining the principle are slightly different from the above-described dimensions and the like.

The following modifications can also be made. For example, if the lateral widths of the plurality of metal electrodes are gradually narrowed each time they are separated from the contact N-type diffusion region 6, the electric field concentration can be more relaxed, a high initial withstand voltage can be secured, and the insulation of the surface protective film can be ensured. It is possible to make it less susceptible to defects. That is, in the case of such a configuration, the farther away from the N-type diffusion region 6, the greater the capacitive coupling between the plate electrode and the semiconductor region 2, so that the potential difference between the plate electrode and the semiconductor region becomes smaller. Therefore, the electric field concentration can be reduced over the entire semiconductor region, and as a result, the initial breakdown voltage can be increased. Moreover, the breakdown voltage does not deteriorate even in the high temperature bias test.

In the above embodiment, a part (25-1, etc.) of the metal electrode 25 is formed in a substantially rectangular ring shape. However, as shown in FIG. 9, the high voltage side drive circuit element region is formed in a substantially circular shape and the substrate is A part of the metal electrode 25 may be configured to be radial when viewed from the normal direction. That is, a part of the metal electrode 25 and the plate electrodes 18a and 19a may be made to intersect with each other. Even with this configuration,
Similar to the above-described embodiment, it is possible to prevent the generation of negative movable charges during the high temperature bias test, and suppress the deterioration of the initial withstand voltage. Further, as shown in FIG. 10, by thickening a part of the base of the metal electrode 25 that extends radially, even if the insulating property of the surface protective film 35 is impaired, the influence on the plate electrode on the high potential side is affected. Can be made smaller.

Further, even if the high voltage side drive circuit element region is substantially rectangular, as shown in FIG.
It is also possible to form a part of the radial pattern. Also in this configuration, in order to reduce the influence on the plate electrode on the high potential side even if the insulating property of the surface protection film 35 is impaired, a part of the radially extending metal electrode 25 should be thick at the root. Is preferred. (Fourth Embodiment) Next, a high breakdown voltage semiconductor device according to a fourth embodiment will be described with reference to FIG. FIG. 12 schematically shows a cross-sectional structure of a main part of the high breakdown voltage semiconductor device of this embodiment. This embodiment is different from the above embodiment having a PN junction isolation structure in that it has a dielectric isolation structure. The same points will be omitted to simplify the description.

The high breakdown voltage semiconductor device of this embodiment has a structure in which the periphery of the semiconductor region 2 is completely surrounded by an insulator by using the dielectric isolation method. That is, the semiconductor region 2 is formed on the bonding oxide film 37 formed on the P-type semiconductor substrate 1, the trench groove is formed around the semiconductor region 2, and the isolation oxide film 38 is formed in the trench groove. And the polysilicon layer 39 are buried.

Next, the operation of this configuration will be described. Normally, the plate electrode 17a, the semiconductor substrate 1, and the N-type semiconductor region 48 are set to the ground potential, and the high-voltage side drive circuit power supply voltage V2 is applied to the metal electrode 25.

In the structure shown in FIG. 12, the metal electrode 2
When the voltage V2 of No. 5 is gradually increased, the isolation oxide film 38
A depletion layer spreads laterally from the N-type diffusion region 6 to the N-type diffusion region 6, while a depletion layer spreads upward from the bonding oxide film 37. The breakdown voltage of the high breakdown voltage semiconductor device is maintained while the spread of the depletion layer changes according to the magnitude of the voltage V2 of the metal electrode 25. When the depletion layer hits a high-concentration N-type impurity region such as the N-type diffusion region 6 and the electric field strength increases, a breakdown phenomenon occurs.

As described above, the resurf technique can be applied to the structure of the present embodiment in which the method of separating the semiconductor region 2 is changed, similarly to the structure of the first embodiment. Further, if the structure on the semiconductor region 2 is the same as that of the second or third embodiment, the reliability regarding the breakdown voltage (particularly, the life test by high temperature bias) can be further improved. When the dielectric isolation structure as in this embodiment is adopted, the parasitic capacitance between the semiconductor region 2 and the semiconductor substrate 1 can be made extremely small, so that both high frequency characteristics or high speed switching characteristics and high withstand voltage characteristics can be achieved. Since a semiconductor device satisfying the above conditions can be realized, there are great advantages. (Fifth Embodiment) Next, a high breakdown voltage semiconductor device according to a fifth embodiment will be described with reference to FIG. FIG. 13 schematically shows the cross-sectional structure of the main part of the high breakdown voltage semiconductor device of this embodiment. The high breakdown voltage semiconductor device of the present embodiment is the same as the plate electrode 18a in the configuration of the second embodiment shown in FIG.
Guard ring regions 44 and 45 are added to the semiconductor region 2 located immediately below 19a. The other points are the same as the configuration of the second embodiment, and are omitted to simplify the description.

In the structure of this embodiment, the P-type impurity is diffused into the semiconductor region 2 located between the isolation diffusion region 4 and the contact N-type diffusion region 6 to form the guard ring regions 44 and 45. Are formed. The guard ring region 44 is located immediately below the plate electrode 18a,
On the other hand, the guard ring region 45 is located immediately below the plate electrode 19a.

When the guard ring regions 44 and 45 are formed between the isolation diffusion region 4 and the contact N-type diffusion region 6, P of the P-type isolation diffusion region 4 and the N-type semiconductor region 2 is formed.
When the depletion layer generated at the N-junction spreads in the lateral direction, it can stick to the depletion layer spreading from the guard ring regions 44 and 45 to increase the curvature of the entire depletion layer. The breakdown voltage can be significantly improved.

In the present embodiment, the plate electrode 18
a, 19a and the parasitic capacitance Cb1, Cb between the metal electrode 25 and
The potentials of the plate electrodes 18a and 19a are determined by the series circuit of b2 and the parasitic capacitances Ca1 and Ca2 between the plate electrodes 18a and 19a and the surfaces of the guard ring regions 44 and 45. The surface potential of the plate electrode 1 and the surface potential of the semiconductor region 2
The potential of 8a and 19a can be set to a high potential. As a result, the oxide film 1 is higher than the potential on the surface of the semiconductor region 2.
It is possible to increase the potential on the 6 side and prevent the P-type inversion layer from being formed on the surface of the N-type semiconductor region 2 during the high temperature bias test. This makes it possible to obtain excellent reliability such that the initial breakdown voltage does not deteriorate.

It is possible to make the following modifications to the configuration shown in FIG. FIG. 14A is the same as FIG.
9 shows a modified example of the configuration shown in FIG. 3, which has a structure in which the semiconductor region 2 is dielectrically separated. More specifically, in the high breakdown voltage semiconductor device shown in FIG. 14A, the SOI film in which the bonding oxide film 37 is formed on the P-type semiconductor substrate 1 and the N-type semiconductor region 2 is arranged on the SOI film 37 is formed. The substrate is used. A separation groove is formed in the SOI substrate, and a separation oxide film 38 and a polysilicon layer 39 are buried in the separation groove. Since the structure is basically the same as that shown in FIG. 11 except that the semiconductor region 2 is separated by a dielectric, the description of the same points will be omitted.

Even when the dielectric isolation structure is adopted, the PN
The fact that the RESURF technology can be utilized in the same manner as in the junction separation structure is as described in Embodiment 4 above.
The withstand voltage characteristics of the configuration shown in FIG. 11 are almost the same as those of the configuration shown in FIG. Therefore, by adopting the dielectric isolation structure, it is possible to realize a high breakdown voltage semiconductor device that satisfies both the reliability of high breakdown voltage characteristics and the high frequency characteristics.

Furthermore, the configuration shown in FIG.
It is also possible to have a configuration as shown in B. FIG. 14B
In the configuration shown in FIG. 14, the metal electrode 25-2 closest to the N-type diffusion region 6 in FIG. 14A is integrated with the metal electrode 25.

With such a structure, the N-type diffusion region 6 is formed.
On the plate electrode 19a closest to the metal electrode 25-4
Completely, the plate electrode 19a can be brought to a potential close to the drain voltage. As a result, the surface protective film 3
Even if 5 causes insulation failure, it is possible to prevent adverse effects on the lower layer portion. Further, the horizontal width of the annular metal electrode 25-1 located in the upper layer of the plate electrode 18a is 1/2 of the horizontal width of the plate electrode 18a near the separation diffusion region 4.
Since the number is doubled, it is possible to increase the capacitive coupling with the semiconductor region 2 portion immediately below. As a result, the potential difference from the semiconductor region 2 portion can be prevented from becoming too large, local electric field concentration can be avoided, and the initial breakdown voltage can be increased. Further, even if the surface protective film 35 causes insulation failure and the peripheral portion of the metal electrode 25-1 becomes conductive, the parasitic capacitance becomes equivalently large, and the potential of the plate electrode 18a becomes slightly large. Since it is only set to, there is an advantage that the reliability with respect to high breakdown voltage is hardly impaired.

In the above-described embodiment, the example in which the semiconductor region 2 is formed together with the separation region (separation diffusion region, separation groove, etc.) is shown, but the separation region is not always necessary, and the semiconductor region is not provided. 2 to form a semiconductor region 2
It is also possible to form a semiconductor element (CMOS circuit, resistance, capacitance) in the. To form the semiconductor region 2 without the isolation region, for example, the processes shown in FIGS. 15A to 15C may be performed.

First, as shown in FIG. 15A, for example, a resist 101 is formed on a low-concentration P-type semiconductor substrate 1, and then low-energy ion implantation is performed on the semiconductor substrate 1 using the resist 101 as a mask. Two-stage ion implantation including high-energy ion implantation is performed. The dotted line 115 in FIG. 15A represents the implantation position for high energy ion implantation, and the dotted line 116 represents the implantation position for low energy ion implantation. After that, when heat treatment is performed, FIG.
N-type well region (semiconductor region) 2 as shown in (b)
Can be obtained.

After that, ion implantation is performed using the resist 102 as a mask and heat treatment is performed, as shown in FIG. 15C, a diffusion region 118 (for example, a P-type diffusion layer 7 as a P-type well). Should be formed. After the N-type well region (semiconductor region) 2 is formed in this way, a semiconductor element can be formed in the N-type well region (semiconductor region) 2 by using a known technique. The device structure as described in the embodiment can be realized.

When the N-type well region 2 of the present embodiment is formed, for example, when phosphorus is used as the N-type impurity,
Phosphorus is implanted at a shallow position from the surface of the semiconductor substrate by low-energy ion implantation with an acceleration energy of 70 KeV to 300 KeV, and an acceleration energy of 500 KeV to
Heat treatment may be performed after phosphorus is ion-implanted at a deep position from the surface of the semiconductor substrate by high-energy ion implantation of 5 MeV.

When the technique described with reference to FIGS. 15A to 15C is used, it is not necessary to use an epitaxial layer and / or it is not necessary to form an isolation region surrounding the semiconductor region 2. The number can be greatly simplified, and as a result, the manufacturing cost can be significantly reduced.

Further, when a plurality of semiconductor devices are manufactured on the same substrate based on the technique shown in FIGS. 15A to 15C, as shown in FIG. Between the regions 2-1, 2-2, electrical isolation will be performed only by the low-concentration P-type semiconductor substrate 1. In the device having this structure, when a high potential is applied to the metal wiring (not shown) formed on the surface of the semiconductor substrate 1, the surface of the semiconductor substrate 1 located immediately below the metal wiring is inverted into N type. As a result, an N-type inversion layer is likely to occur. Then, a leak current easily flows between the N-type well regions 2-1 and 2-2 (x in FIG. 15D), so that electrical isolation between transistors is likely to be incomplete.

However, this problem of electrical isolation can be solved by ensuring a sufficient separation distance x between the N-type well regions 2-1 and 2-2. Therefore, if the separation distance x for the output transistor to which a high potential is applied is increased and the separation distance x for the small signal processing transistor having a high integration ratio is decreased, the integration degree of the semiconductor device (IC) is increased. Electrical isolation can be achieved without loss.

Further, as shown in FIG. 15E, the P-type high-concentration isolation diffusion region 119 is formed on the surface between the N-type well regions 2-1 and 2-2 so that the electrical conductivity can be improved. The problem of static separation can be solved. When the high-concentration isolation diffusion regions 119 (119-1 and 119-2) are formed in this manner, the N-type inversion is formed on the surface of the semiconductor substrate 1 located immediately below the metal wiring regardless of the applied voltage to the metal wiring (not shown). It is possible to prevent the formation of layers. Therefore, even if the distance x between the plurality of output transistors (semiconductor regions 2-1 and 2-2) to which a high voltage is applied is reduced, good electrical insulation can be obtained, and the high breakdown voltage semiconductor It is possible to increase the degree of integration of the device.

Although the preferred examples of the present invention have been described above, the description is not a limitation and, of course, various modifications are possible.

[0121]

According to the high breakdown voltage semiconductor device of the present invention, a part of the metal electrode extends on the interlayer insulating film located on each of the plurality of plate electrodes formed in a floating state on the field insulating film. Since a part of the metal electrode and each of the plurality of plate electrodes are capacitively coupled to each other, a highly reliable high breakdown voltage semiconductor device in which breakdown voltage does not deteriorate even when used at high temperature is provided. be able to.
When the high breakdown voltage semiconductor device of the present invention is a high breakdown voltage semiconductor device for inverter control including a high voltage side drive circuit, it is possible to configure an inverter control system having excellent reliability even when used at high temperatures. .

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view showing a main-portion cross-sectional structure of a high breakdown voltage semiconductor device according to a first embodiment.

FIG. 2 is a main-portion plan view showing the main-portion planar structure of the high breakdown voltage semiconductor device according to the first embodiment;

FIG. 3 is a sectional view for explaining a parasitic capacitance of the high breakdown voltage semiconductor device according to the first embodiment.

FIG. 4 is a sectional view for explaining a potential distribution of the high breakdown voltage semiconductor device according to the first embodiment.

FIG. 5 is a main-portion cross-sectional view showing a main-portion cross-sectional structure and potential distribution of the high breakdown voltage semiconductor device according to the second embodiment;

FIG. 6 is a main-portion cross-sectional view showing the main-portion cross-sectional structure of the high breakdown voltage semiconductor device according to the third embodiment;

FIG. 7 is a main-portion cross-sectional view showing a main-portion cross-sectional structure of a modification of the third embodiment.

FIG. 8 is a main-portion cross-sectional view showing a main-portion cross-sectional structure of a modification of the third embodiment.

FIG. 9 is a plan view showing a planar structure of a modified example of the third embodiment.

FIG. 10 is a plan view showing a planar structure of a modified example of the third embodiment.

FIG. 11 is a plan view showing a planar structure of a modified example of the third embodiment.

FIG. 12 is a main-portion cross-sectional view showing the main-portion cross-sectional structure of the high breakdown voltage semiconductor device according to the fourth embodiment;

FIG. 13 is a main-portion cross-sectional view showing the main-portion cross-sectional structure of the high breakdown voltage semiconductor device according to the fifth embodiment;

FIG. 14A is a main-portion cross-sectional view showing the main-portion cross-sectional structure of a modification of the fifth embodiment.

FIG. 14B is a main-portion cross-sectional view showing the main-portion cross-sectional structure of a modification of the fifth embodiment.

15A to 15C are process cross-sectional views for explaining a method of forming a semiconductor region 2 without an isolation region. (D) is a cross-sectional view schematically showing a structure in which electrical isolation is performed only by the semiconductor substrate 1, and (e) is a cross-sectional view schematically showing a structure in which the high concentration separation diffusion region 109 is formed. It is a figure.

FIG. 16 is a schematic configuration diagram of a lighting inverter control system, which is an example of an inverter control system.

FIG. 17 is a cross-sectional view of a main part showing a cross-sectional structure of a main part of a first conventional example.

FIG. 18 is a main-portion plan view showing a main-portion planar structure of a first conventional example.

FIG. 19 is a sectional view for explaining a parasitic capacitance of a first conventional example.

FIG. 20 is a cross-sectional view for explaining a potential distribution at room temperature in the first conventional example.

FIG. 21 is a cross-sectional view for explaining the breakdown voltage deterioration during a high temperature bias test in the first conventional example.

FIG. 22 is a cross-sectional view for explaining deterioration of breakdown voltage of a high breakdown voltage semiconductor device which is a second conventional example.

FIG. 23 is a cross-sectional view for explaining a parasitic capacitance of a high breakdown voltage semiconductor device which is a second conventional example.

[Explanation of symbols]

1 P-type semiconductor substrate 2 N-type semiconductor region 3 N-type buried diffusion region 4 P-type isolation diffusion region 6 N-type high-concentration diffusion region 7 Body diffusion region of high-voltage side drive circuit NchMOS 8 High-voltage side drive circuit NchMOS Source diffusion region 9 high voltage side drive circuit NchMOS drain diffusion region 10 high voltage side drive circuit PchMOS source diffusion region 11 high voltage side drive circuit PchMOS drain diffusion region 12 high voltage side drive circuit MOS capacitance P-type diffusion region for electrode 13 High-voltage side P-type diffusion resistor for drive circuit 15 Thin oxide film 16 Thick oxide film 18a, 18b, 19a, 20a, 21a Plate electrodes 17a, 17b, 19b in floating state Plate electrode 22 High-voltage side Gate electrode 23 of drive circuit NchMOS 23 Gate electrode 24 of high voltage side drive circuit PchMOS 24 Electrode 25 of MOS capacitor for pressure side drive circuit Metal electrode 25-1, 25-2 for applying potential to N-type semiconductor region 2 Metal electrode 25-3 connected to 25 Metal electrode 25, 25-1, 25- Connecting part 25-4 for connecting 2 to the metal electrode 26 extended to cover the plate electrode 19a for applying a potential to the semiconductor region 2 Source metal electrode 27 of NchMOS for high voltage side drive circuit High voltage side drive NchMOS drain metal electrode for circuit 28 PchMOS source metal electrode for high voltage side drive circuit 29 PchMOS drain metal electrode for high voltage side drive circuit 30 High voltage side drive circuit MOS capacitor metal electrodes 31, 32 High voltage side drive Metal electrode 33 for circuit resistor 33 Metal electrode 34 for applying a potential to the P-type isolation diffusion region and P-type substrate 34 Interlayer insulating film 35 Surface protection film 36 Sealing Resin 37 Laminating Oxide Film 38 Separation Oxide Film 39 Polysilicon Layer 40, 41 Floating Metal Electrode 42 N-type Storage Layer 43 P-type Inversion Layer 44, 45, 46, 47 P-type Guard Ring Diffusion Region 48 N-type Semiconductor Region 49 Metal wiring 101, 102 for high-voltage side control signal High-voltage Nch power MOS transistor 103 Capacitor 104 High-voltage diode 105 High-voltage side drive circuit block (floating block) 106 Low-voltage side drive circuit block 107 Low-voltage side Driving circuit power source terminal 108 High voltage side driving circuit power source terminal 109 Fluorescent lamp driving output terminal 110 Fluorescent lamp driving high voltage terminal

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 27/092 F Term (Reference) 5F032 AA35 AA44 AA47 AB01 AC01 AC04 CA01 CA03 CA14 CA17 CA24 5F048 AA04 AA05 AA07 AB10 AC03 AC06 AC10 BA02 BA12 BB05 BE03 BF11 BG14 BH01 BH04 BH05 BH07

Claims (19)

[Claims] 1. A second conductivity type semiconductor region formed on a first conductivity type semiconductor substrate, a second conductivity type contact diffusion region formed in the semiconductor region, and a contact diffusion region A first-conductivity-type isolation diffusion region formed in the semiconductor region so as to be spaced apart and to surround the contact diffusion region; and the semiconductor region located between the isolation diffusion region and the contact diffusion region. A field insulating film formed on the contact diffusion region, a metal electrode electrically connected to the contact diffusion region, a metal electrode electrically connected to the contact diffusion region, and surrounding the contact diffusion region as viewed from the substrate normal direction. A plurality of plate electrodes formed in a floating state on the field insulating film, and formed on the field insulating film and the plurality of plate electrodes. An interlayer insulating film formed, a part of the metal electrode extends on the interlayer insulating film located on each of the plurality of plate electrodes,
The part of the metal electrode and each of the plurality of plate electrodes are capacitively coupled to each other, and in the second conductivity type semiconductor region surrounded by the second conductivity type contact diffusion region, A high breakdown voltage semiconductor device provided with a CMOS circuit and one or both of a resistor and a capacitor. 2. The high withstand voltage semiconductor device is a high withstand voltage semiconductor device for inverter control including a high voltage side drive circuit, and the high voltage side drive circuit is any one of the CMOS circuit, the resistor and the capacitor. The high breakdown voltage semiconductor device according to claim 1, comprising one or both. 3. The metal electrode has a plurality of metal electrodes as a part of the metal electrode, and at least one of the plurality of metal electrodes is capacitively coupled to the metal electrode. The high breakdown voltage semiconductor device according to claim 1, which has a width smaller than that of the plate electrode. 4. The metal electrode has a portion that covers all of the upper surfaces of the plate electrodes located closest to the contact diffusion region among the plurality of plate electrodes with the interlayer insulating film interposed therebetween. The high breakdown voltage semiconductor device according to claim 1, further comprising: 5. The metal electrode has a plurality of metal electrodes as a part of the metal electrode, and a lateral width of each of the plurality of metal electrodes becomes narrower as the distance from the contact diffusion region increases. Claim 1
4. The high breakdown voltage semiconductor device according to any one of 1 to 4. 6. The plurality of guard ring regions of the first conductivity type are formed above the semiconductor region located below each of the plurality of plate electrodes.
The high breakdown voltage semiconductor device according to any one of 1. 7. A buried region of the second conductivity type is provided at a position corresponding to a high-voltage side drive circuit element region between the first conductivity type semiconductor substrate and the second conductivity type semiconductor region. The high breakdown voltage semiconductor device according to claim 1, which is formed. 8. The method according to claim 1, further comprising a surface protection film formed on the metal electrode and the interlayer insulating film, and a sealing resin portion formed on the surface protection film. The high breakdown voltage semiconductor device described in one. 9. The surface protection film according to claim 8, wherein the surface protection film is a multilayer film including an upper layer made of a polyimide resin and an insulating layer made of an inorganic material as a lower layer. High voltage semiconductor device. 10. An insulating layer formed on a semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type arranged on the insulating layer, and a semiconductor layer of a second conductivity type formed on the semiconductor region. A contact diffusion region; an isolation insulating region formed in the semiconductor region so as to be separated from the contact diffusion region and surround the contact diffusion region; the isolation insulating region and the contact diffusion region. A field insulating film formed on the semiconductor region located between the contact diffusion region and a metal electrode electrically connected to the contact diffusion region; As seen, a plurality of plate electrodes formed in a floating state on the field insulating film so as to surround the contact diffusion region, and the field insulating film and the front electrode. And an interlayer insulating film formed on the plurality of plate electrodes, a part of the metal electrode is extended onto the interlayer insulating film located on each of said plurality of plate electrodes,
The part of the metal electrode and each of the plurality of plate electrodes are capacitively coupled to each other, and the second conductive type semiconductor region surrounded by the second conductive type contact diffusion region has a CMOS A circuit and either or both of a resistor and a capacitor are provided,
High voltage semiconductor device. 11. The high withstand voltage semiconductor device is a high withstand voltage semiconductor device for inverter control including a high voltage side drive circuit, and the high voltage side drive circuit is any one of the CMOS circuit, the resistor and the capacitor. The high breakdown voltage semiconductor device according to claim 10, comprising one or both. 12. The metal electrode has a plurality of annular metal electrodes as a part of the metal electrode, and at least one of the plurality of annular metal electrodes is capacitively coupled with the annular metal electrode. 12. The high breakdown voltage semiconductor device according to claim 10, which has a width smaller than that of the plate electrode. 13. The metal electrode has a portion that covers the entire upper surface of the plate electrode located closest to the drain diffusion region among the plurality of plate electrodes via the interlayer insulating film. 13. The high breakdown voltage semiconductor device according to claim 10. 14. The metal electrode has a plurality of annular metal electrodes as a part of the metal electrode, and the lateral width of each of the plurality of annular metal electrodes becomes narrower as the distance from the drain diffusion region increases. Claim 1
The high breakdown voltage semiconductor device according to any one of 0 to 13. 15. The plurality of guard ring regions of the first conductivity type are formed above the semiconductor region located below each of the plurality of plate electrodes. The high breakdown voltage semiconductor device according to. 16. The method according to claim 10, further comprising a surface protective film formed on the metal electrode and the interlayer insulating film, and a sealing resin portion formed on the surface protective film.
5. The high breakdown voltage semiconductor device according to any one of 5. 17. The surface protective film is a multilayer film including an upper layer made of a polyimide resin and an insulating layer made of an inorganic material in a lower layer than the upper layer.
6. The high breakdown voltage semiconductor device according to item 6. 18. A semiconductor region of a second conductivity type formed on a semiconductor substrate of a first conductivity type, a diffusion region for a contact of the second conductivity type formed in the semiconductor region, and a semiconductor region on the semiconductor region. The formed field insulating film, the metal electrode electrically connected to the contact diffusion region, and the metal electrode that is separated from the contact diffusion region and surrounds the contact diffusion region when viewed from the substrate normal direction. A plurality of plate electrodes formed in a floating state on the field insulating film, and an interlayer insulating film formed on the field insulating film and the plurality of plate electrodes, a part of the metal electrode, Extending on the interlayer insulating film located on each of the plurality of plate electrodes,
The part of the metal electrode and each of the plurality of plate electrodes are capacitively coupled to each other, and in the second conductivity type semiconductor region surrounded by the second conductivity type contact diffusion region, A high breakdown voltage semiconductor device provided with a CMOS circuit and one or both of a resistor and a capacitor. 19. The high breakdown voltage according to claim 18, further comprising a surface protective film formed on the metal electrode and the interlayer insulating film, and a sealing resin portion formed on the surface protective film. Semiconductor device.