JP2003068781A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003068781A
JP2003068781A JP2001253431A JP2001253431A JP2003068781A JP 2003068781 A JP2003068781 A JP 2003068781A JP 2001253431 A JP2001253431 A JP 2001253431A JP 2001253431 A JP2001253431 A JP 2001253431A JP 2003068781 A JP2003068781 A JP 2003068781A
Authority
JP
Japan
Prior art keywords
semiconductor chip
tab
semiconductor device
pads
inner leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001253431A
Other languages
Japanese (ja)
Inventor
Masahiko Endo
雅彦 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Yonezawa Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Yonezawa Electronics Co Ltd filed Critical Hitachi Ltd
Priority to JP2001253431A priority Critical patent/JP2003068781A/en
Publication of JP2003068781A publication Critical patent/JP2003068781A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To relax restriction in design of a semiconductor device. SOLUTION: A semiconductor chip 2 having a plurality of pads 2a arranged along with four sides 2c formed in the periphery is die-mounted so as to make the angle of 45 deg. against the arrangement direction of a plurality of inner leads extending to the outside from the periphery of the semiconductor chip 2. Thereby, since a clearance between adjacent wires 7 in the vicinity of a corner of the semiconductor chip 2 can be enlarged, it becomes possible to relax the restriction in the bonding pad pitch of a semiconductor chip 2 without changing the positions of the inner leads of a lead frame.

Description

【発明の詳細な説明】 【０００１】 【発明の属する技術分野】本発明は、半導体製造技術に
関し、特に、狭ピッチに伴うワイヤボンディングの高密
度化に適用して有効な技術に関する。 【０００２】 【従来の技術】以下に説明する技術は、本発明を研究、
開発するに際し、本発明者によって検討されたものであ
り、その概要は次のとおりである。 【０００３】小型化・薄型化を図るとともにリードフレ
ームを用いて製造される半導体装置としてＱＦＰ（Quad
Flat Package）と呼ばれる半導体装置が開発されてい
る。 【０００４】半導体装置に組み込まれる半導体チップで
は、表面電極であるボンディングパッド（以下、単にパ
ッドともいう）は、外周パッド配列もしくはセンタパッ
ド配列に一列で配置されている。 【０００５】さらに、ワイヤボンディングを行ってボン
ディングパッドとインナリードとを電気的に接続してお
り、特に多ピンの半導体装置では、ボンディングパッド
のパッドピッチが狭くなると、隣接するワイヤ間のクリ
アランスが特にコーナー部付近で小さくなる。 【０００６】これは、チップ上のボンディングパッドの
配列に対するワイヤリングの角度が、コーナー部になる
ほど鋭角になるためであり、このことは、インナリード
のパターンの引き回しによってある程度は回避可能であ
るが、狭ピッチ化が進むにつれてインナリードの引き回
しのみの回避では困難になってきている。 【０００７】ここでＱＦＰの構造やその多ピン化による
狭ピッチ化については、例えば、日経ＢＰ社、１９９３
年５月３１日発行、香山晋、成瀬邦彦（監修）、「実践
講座ＶＬＳＩパッケージ技術（下）」165〜172頁に記載
されている。 【０００８】 【発明が解決しようとする課題】前記した技術では、狭
ピッチ化が進むと、コーナー部におけるワイヤ間のクリ
アランスが小さくなり、これにより、ワイヤのショート
に対するマージンも少なくなる。 【０００９】この現象は、特に、多ピンになるにしたが
って発生しやすく、その対策として、コーナー部の隣接
するボンディングパッド間のピッチを中央部より広げる
というボンディング制約が生じることが問題である。 【００１０】本発明の目的は、半導体チップのコーナー
部におけるボンディング制約を緩和もしくは無くして製
造性向上を図る半導体装置を提供することにある。 【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。 【００１２】 【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。 【００１３】すなわち、本発明は、外周の４つの辺に沿
って並んで設けられた複数の表面電極を有する半導体チ
ップと、前記半導体チップを支持するタブと、前記半導
体チップの周囲に延在する複数のインナリードと、前記
半導体チップの表面電極と前記インナリードとを接続す
るワイヤとを有し、前記半導体チップの各辺における前
記複数の表面電極の配列方向が、前記複数のインナリー
ドの配列方向と４５°を成すように前記半導体チップが
前記タブに搭載されているものである。 【００１４】 【発明の実施の形態】以下の実施の形態を図面に基づい
て詳細に説明する。なお、実施の形態を説明するための
全図において、同一の機能を有する部材には同一の符号
を付し、その繰り返しの説明は省略する。 【００１５】また、以下の実施の形態において、要素の
数等（個数、数値、量、範囲等を含む）に言及する場
合、特に明示した場合および原理的に明らかに特定の数
に限定される場合などを除き、その特定の数に限定され
るものではなく、特定の数以上でも以下でも良いものと
する。 【００１６】さらに、以下の実施の形態において、その
構成要素（要素ステップなども含む）は、特に明示した
場合および原理的に明らかに必須であると考えられる場
合などを除き、必ずしも必須のものではないことは言う
までもない。 【００１７】同様に、以下の実施の形態において、構成
要素などの形状、位置関係などに言及するときは、特に
明示した場合および原理的に明らかにそうでないと考え
られる場合などを除き、実質的にその形状などに近似ま
たは類似するものなどを含むものとする。このことは前
記数値および範囲についても同様である。 【００１８】図１は本発明の実施の形態による半導体装
置の構造の一例を示す断面図、図２は図１に示す半導体
装置における半導体チップのパッドとインナリードとの
ワイヤリング状態を示す拡大部分平面図、図３は図２の
Ａ部を示す拡大部分平面図、図４は図１に示す半導体装
置の組み立て手順の一例を示す製造プロセスフロー図、
図５は本発明の実施の形態の半導体装置に用いられるリ
ードフレームの構造の一例を示す部分平面図、図６は本
発明の実施の形態の半導体装置の組み立てにおけるダイ
ボンディング状態の一例を示す部分平面図である。 【００１９】本実施の形態の半導体装置は、半導体チッ
プ２の表面電極であるパッド２ａ（ボンディングパッド
ともいう）とインナリード５とがボンディング用のワイ
ヤ７を用いてワイヤボンディングされて組み立てられた
狭ピッチタイプのものであり、本実施の形態では、前記
半導体装置の一例として、多ピン（例えば、２００ピン
以上）のＱＦＰ（Quad Flat Package）１を取り上げて
説明する。 【００２０】図１〜図３を用いて図１に示すＱＦＰ１の
構造について説明すると、外周に４つの辺が形成される
とともに、各辺２ｃに沿って並んで設けられた複数のパ
ッド２ａ（表面電極）を有する略正方形の半導体チップ
２と、この半導体チップ２をダイボンド材である銀ペー
スト６を介して支持するタブ３と、タブ３を支持するタ
ブ吊りリード４と、半導体チップ２のパッド２ａと電気
的に接続され、かつ半導体チップ２の周囲から外方に向
かって延在する複数のインナリード５と、インナリード
５と一体となって繋がって形成された外部端子である複
数のアウタリード８と、半導体チップ２のパッド２ａと
これに対応するインナリード５とを電気的に接続する複
数のボンディング用の金属細線であるワイヤ７と、半導
体チップ２とワイヤ７とインナリード５とを樹脂封止し
て形成された封止部９とから構成されている。 【００２１】さらに、ＱＦＰ１では、半導体チップ２の
各辺２ｃにおける複数のパッド２ａの配列方向が、複数
のインナリード５の配列方向と４５°を成すように半導
体チップ２がタブ３に搭載され、これにより半導体チッ
プ２のコーナー部において隣接するワイヤ間のクリアラ
ンスを広げることを可能にした構造である。 【００２２】すなわち、ＱＦＰ１はタブ３の半導体チッ
プ支持面に対して水平に半導体チップ２を４５°θ方向
に回転させて、タブ３に搭載した構造のものである。 【００２３】なお、本実施の形態の半導体装置はＱＦＰ
１であるため、半導体チップ２のパッド２ａの配列は、
図２に示すように、各辺２ｃに沿って主面２ｄの外周端
部に形成された外周パッド配列である。 【００２４】さらに、図３に示すように、各パッド２ａ
には、目的に応じた配線２ｂが接続されている。 【００２５】また、半導体チップ２のそれぞれのパッド
２ａは、図２に示すように、それぞれに対応するインナ
リード５とワイヤ７によって電気的に接続され、かつ、
このインナリード５と一体に繋がったそれぞれのアウタ
リード８が、図１に示すように封止部９のそれぞれの辺
の側面から突出しており、さらに、前記アウタリード８
はガルウィング状に形成されている。 【００２６】また、半導体チップ２は、タブ３上に、ダ
イボンド材である銀ペースト６によって固着されてい
る。 【００２７】さらに、本実施の形態のＱＦＰ１では、半
導体チップ２の各辺２ｃにおける複数のパッド２ａの配
列方向が、複数のインナリード５の配列方向と４５°を
成すように半導体チップ２をタブ３に搭載するため、複
数のインナリード５の各先端部によって形成されたチッ
プ搭載領域である開口部を、半導体チップ２より十分に
大きくすることが可能な小タブ構造を採用している。 【００２８】すなわち、少タブ構造では、各インナリー
ド５の先端部とタブ３との距離を長くすることができ、
一種類のリードフレーム１０で種々の大きさの半導体チ
ップ２を搭載できるというメリットがあるため、このメ
リットを生かして、本実施の形態のＱＦＰ１では、小タ
ブ構造を採用している。 【００２９】なお、インナリード５、タブ３、タブ吊り
リード４およびアウタリード８は、例えば、Ｆｅ（鉄）
−Ｎｉ（ニッケル）合金などによって形成された薄板上
の部材である。 【００３０】さらに、ワイヤ７は、例えば、金などの金
属細線である。 【００３１】また、封止部９は、例えば、熱硬化性のエ
ポキシ樹脂などをモールドによって硬化させたものであ
る。 【００３２】次に、本実施の形態のＱＦＰ１の製造方法
を図４に示す製造プロセスフロー図にしたがって説明す
る。 【００３３】まず、インナリード５、タブ３、タブ吊り
リード４およびアウタリード８を有した図５に示すリー
ドフレーム１０を準備する（ステップＳ１）。 【００３４】続いて、図２、図３に示すように、外周に
４つの辺が形成されるとともに、各辺２ｃに沿って並ん
で設けられた複数のパッド２ａを有する半導体チップ２
を供給する（ステップＳ２）。 【００３５】その後、リードフレーム１０のタブ３に銀
ペースト６を塗布し、さらに、銀ペースト６上に半導体
チップ２を載置し、これにより、半導体チップ２をタブ
３に搭載する（ステップＳ３）。 【００３６】その際、図６に示すように、半導体チップ
２の４つの外周辺２ｃに沿って並んで設けられた複数の
パッド２ａの配列方向が複数のインナリード５の配列方
向と４５°を成すように半導体チップ２のタブ３へ搭載
を行う。 【００３７】その後、半導体チップ２のパッド２ａとこ
れに対応する各インナリード５とをボンディング用のワ
イヤ７を用いてワイヤボンディングし、両者を電気的に
接続する（ステップＳ４）。 【００３８】その後、例えば、エポキシ系の熱硬化性の
封止用樹脂を用いて半導体チップ２とワイヤ７とインナ
リード５を樹脂封止して封止部９を形成する（ステップ
Ｓ５）。 【００３９】続いて、封止部９から突出したアウタリー
ド８を支持するリードフレーム１０の枠部１２とアウタ
リード８とを切断によって分離し、さらにアウタリード
８をガルウィング状に形成する（ステップＳ６）。 【００４０】これにより、本実施の形態による半導体装
置すなわちＱＦＰ１の組み立てが完了する（ステップＳ
７）。 【００４１】本実施の形態の半導体装置およびその製造
方法では、半導体チップ２の各辺２ｃにおける複数のパ
ッド２ａの配列方向が複数のインナリード５の配列方向
と４５°を成すように半導体チップ２を搭載したことに
より、ワイヤボンディング時、半導体チップ２のコーナ
ー部における隣合ったワイヤ間のクリアランスを大きく
することができる。 【００４２】ここで、ワイヤ間のクリアランスが大きく
なる原理について説明する。 【００４３】隣接するワイヤ間のクリアランスは、パッ
ド２ａの狭ピッチ化に伴って小さくなるが、特にワイヤ
ボンディングの角度がパッド２ａの配列に対して鋭角に
なるとこの傾向が助長される。 【００４４】そこで、図３に示すように、パッド間隔を
Ｄ、ワイヤ径をＬ、ワイヤリング角度をθとすると、ワ
イヤ間のクリアランスＰはＰ＝（Ｄ×ｓｉｎθ）−Ｌで
表される。 【００４５】すなわち、パッド２ａの配列に対するワイ
ヤリングの角度（θ）が小さい鋭角になるほど、ワイヤ
間のクリアランスＰが小さくなる。 【００４６】図６に示す本実施の形態のように、半導体
チップ２の各辺２ｃにおける複数のパッド２ａの配列方
向が複数のインナリード５の配列方向と４５°を成すよ
うに傾けてダイボンディングすることにより、半導体チ
ップ２を４５°傾けないで搭載した場合と比較して、半
導体チップ２のコーナー部付近のワイヤリングの角度を
大きくすることができる。 【００４７】したがって、半導体チップ２のコーナー部
におけるワイヤ間のクリアランスを大きくできるため、
半導体チップ２のコーナー部付近のパッド間隔のボンデ
ィング制約を緩和もしくは無くすことが可能となり、Ｑ
ＦＰ１の製造性向上を図ることができる。 【００４８】さらに、コーナー部の隣合ったワイヤ間の
クリアランスを大きくできるため、ＱＦＰ１において、
狭ピッチ化を図ったワイヤボンディングによる実装を実
現できる。 【００４９】例えば、チップサイズ3.96ｍｍ×3.85ｍ
ｍ、パッド間隔0.080ｍｍでピン数が２０８ピンの場
合、コーナー部のワイヤ間のクリアランスは0.065ｍｍ
となり、半導体チップ２を４５°傾けない場合（ワイヤ
間のクリアランスの0.061ｍｍとなる）と比較して0.004
ｍｍ広くなる。 【００５０】また、本発明の実施の形態のように小タブ
構造を採用することにより、種々の大きさの半導体チッ
プ２を搭載することが可能である。 【００５１】すなわち、一種類のリードフレーム１０で
種々のサイズの半導体チップ２を搭載することが可能と
なる。 【００５２】その結果、リードフレーム１０の種類を少
なくして、開発コストを低減できる。 【００５３】なお、以上は多ピンの場合の説明であった
が、例えば、チップサイズ4.32ｍｍ×4.32ｍｍでピン数
が４４ピン程度の少ピンの場合、コーナー部のワイヤ間
のクリアランスは0.285ｍｍとなり、半導体チップ２を
４５°傾けない場合（ワイヤ間のクリアランスの0.274
ｍｍ）と比較して0.011ｍｍ広くすることができる。 【００５４】すなわち、本実施の形態のＱＦＰ１は、少
ピンの場合であっても、半導体チップ２のコーナー部の
ワイヤ間のクリアランスを大きくすることができる。 【００５５】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記発明の実施の形態に限定されるものではなく、その
要旨を逸脱しない範囲で種々変更可能であることは言う
までもない。 【００５６】例えば、前記本実施の形態では、半導体装
置であるＱＦＰ１が小タブ構造の場合について説明した
が、ＱＦＰ１は小タブ構造に限らず、チップ搭載部が十
字形を成す十字形タブ構造であってもよい。 【００５７】さらに、小タブ構造に限らず、半導体チッ
プ２より大きいサイズのタブ３であってもよい。 【００５８】また、前記実施の形態では、半導体チップ
２が略正方形の場合を説明したが、例えば、図７に示す
ように、半導体チップ２が長方形の場合、この半導体チ
ップ２を複数のインナリード５の配列方向に対して複数
のパッド２ａの配列方向が４５°を成すように半導体チ
ップ２を搭載することにより、モールド時に、略四角形
に配列されたインナリード５のコーナー部からモールド
樹脂を充填する際、モールド樹脂の流動方向１１に示す
ように、コーナー部から注入されたモールド樹脂は半導
体チップ２の一方の短辺の中央付近に衝突し、そこから
左右に均等に分散して流れる。 【００５９】しかし、図８の比較例に示すように、長方
形の半導体チップ２の各辺２ｃにおける複数のパッド２
ａの配列方向が複数のインナリード５の配列方向に対し
て平行になるように半導体チップ２を搭載すると、モー
ルド樹脂の流動方向１３に示すように、モールド樹脂
は、半導体チップ２の一方の長辺に衝突し、長辺側と短
辺側に対して均等に流れない。 【００６０】したがって、図７に示すように、半導体チ
ップ２が長方形においても、複数のパッド２ａの配列方
向が複数のインナリード５の配列方向と４５°を成すよ
うに半導体チップ２を搭載することにより、モールド時
のモールド樹脂によるワイヤ７の流れおよびボイドの発
生を低減できる。 【００６１】また、前記実施の形態では半導体装置がＱ
ＦＰ１の場合を説明したが、前記半導体装置は、ＱＦＮ
（Quad Flat Non-leaded Package）やＱＦＪ（Quad Fla
t J-leaded Package）などの他の半導体装置であっても
適用可能である。 【００６２】 【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。 【００６３】半導体チップの複数の表面電極の配列方向
が、複数のインナリードの配列方向に対して４５°を成
すように半導体チップを搭載することにより、半導体チ
ップのボンディング制約を緩和もしくは無くすことが可
能となり、その結果、半導体装置の製造性向上を図るこ
とができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to a high density of wire bonding accompanying a narrow pitch. [0002] The technology described below is a study of the present invention.
It was examined by the inventor during development, and the outline thereof is as follows. As a semiconductor device manufactured using a lead frame while reducing the size and thickness, QFP (Quad
A semiconductor device called “Flat Package” has been developed. In a semiconductor chip incorporated in a semiconductor device, bonding pads (hereinafter also simply referred to as pads) which are surface electrodes are arranged in a line in an outer peripheral pad arrangement or a center pad arrangement. Furthermore, wire bonding is performed to electrically connect the bonding pad and the inner lead. Especially in a multi-pin semiconductor device, when the pad pitch of the bonding pad is narrowed, the clearance between adjacent wires is particularly large. It becomes smaller near the corner. This is because the angle of wiring with respect to the arrangement of bonding pads on the chip becomes sharper as the corner portion is reached. This can be avoided to some extent by routing the inner lead pattern, but is narrow. As pitching progresses, it is becoming difficult to avoid the inner lead only. Here, regarding the structure of the QFP and the narrowing of the pitch due to the increase in the number of pins, for example, Nikkei BP, 1993.
Issued May 31, 2000, Kayama Kaoru, Naruse Kunihiko (supervised), “Practical Course VLSI Package Technology (below)” pp. 165-172. In the above-described technique, as the pitch becomes narrower, the clearance between the wires at the corner portion becomes smaller, thereby reducing the margin for shorting of the wire. This phenomenon is particularly likely to occur as the number of pins increases. As a countermeasure against this phenomenon, there is a problem that a bonding restriction is generated in which the pitch between adjacent bonding pads in a corner portion is wider than that in the central portion. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that improves the manufacturability by relaxing or eliminating the bonding restrictions at the corners of the semiconductor chip. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings. To briefly explain the summary of typical inventions among the inventions disclosed in this application,
It is as follows. That is, according to the present invention, a semiconductor chip having a plurality of surface electrodes provided side by side along the four sides of the outer periphery, a tab for supporting the semiconductor chip, and extending around the semiconductor chip. A plurality of inner leads; and a wire connecting the surface electrode of the semiconductor chip and the inner lead; and an arrangement direction of the plurality of surface electrodes on each side of the semiconductor chip is an arrangement of the plurality of inner leads The semiconductor chip is mounted on the tab so as to form 45 ° with the direction. DESCRIPTION OF THE PREFERRED EMBODIMENTS The following embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), it is particularly limited to a specific number when clearly indicated and in principle. Except in some cases, the number is not limited to a specific number, and may be a specific number or more. Furthermore, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and apparently essential in principle. It goes without saying that there is nothing. Similarly, in the following embodiments, when referring to the shape and positional relationship of components and the like, it is substantially the case except when specifically stated and in principle not clearly considered otherwise. Includes the ones that are approximate or similar to the shape. The same applies to the numerical values and ranges. FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an enlarged partial plan view showing the wiring state of pads and inner leads of a semiconductor chip in the semiconductor device shown in FIG. FIG. 3, FIG. 3 is an enlarged partial plan view showing part A of FIG. 2, FIG.
FIG. 5 is a partial plan view showing an example of the structure of a lead frame used in the semiconductor device of the embodiment of the present invention, and FIG. 6 is a portion showing an example of a die bonding state in the assembly of the semiconductor device of the embodiment of the present invention. It is a top view. In the semiconductor device of this embodiment, a pad 2a (also referred to as a bonding pad) which is a surface electrode of a semiconductor chip 2 and an inner lead 5 are assembled by wire bonding using a bonding wire 7. In this embodiment, a multi-pin (for example, 200 pins or more) QFP (Quad Flat Package) 1 will be described as an example of the semiconductor device. The structure of the QFP 1 shown in FIG. 1 will be described with reference to FIGS. 1 to 3. Four sides are formed on the outer periphery, and a plurality of pads 2a (surfaces) provided side by side along each side 2c. A substantially square semiconductor chip 2 having electrodes), a tab 3 that supports the semiconductor chip 2 via a silver paste 6 that is a die-bonding material, a tab suspension lead 4 that supports the tab 3, and a pad 2a of the semiconductor chip 2. And a plurality of inner leads 5 that extend outward from the periphery of the semiconductor chip 2 and a plurality of outer leads 8 that are external terminals formed integrally with the inner leads 5. A plurality of thin metal wires for bonding that electrically connect the pads 2a of the semiconductor chip 2 and the inner leads 5 corresponding to the pads 2a; And a 7 and the inner leads 5 and the formed resin-sealing the sealing portion 9. Furthermore, in the QFP 1, the semiconductor chip 2 is mounted on the tab 3 so that the arrangement direction of the plurality of pads 2a on each side 2c of the semiconductor chip 2 forms 45 ° with the arrangement direction of the plurality of inner leads 5. As a result, the clearance between adjacent wires at the corner of the semiconductor chip 2 can be widened. That is, the QFP 1 has a structure in which the semiconductor chip 2 is rotated in the 45 ° θ direction horizontally with respect to the semiconductor chip support surface of the tab 3 and mounted on the tab 3. The semiconductor device of this embodiment is QFP.
1 so that the arrangement of the pads 2a of the semiconductor chip 2 is
As shown in FIG. 2, it is the outer periphery pad arrangement | sequence formed in the outer peripheral end part of the main surface 2d along each edge | side 2c. Further, as shown in FIG. 3, each pad 2a
Is connected to a wiring 2b according to the purpose. Each pad 2a of the semiconductor chip 2 is electrically connected by a corresponding inner lead 5 and wire 7 as shown in FIG.
Each outer lead 8 integrally connected with the inner lead 5 protrudes from the side surface of each side of the sealing portion 9 as shown in FIG.
Is formed in a gull wing shape. The semiconductor chip 2 is fixed on the tab 3 with a silver paste 6 which is a die bond material. Furthermore, in the QFP 1 of the present embodiment, the semiconductor chip 2 is tabbed so that the arrangement direction of the plurality of pads 2a on each side 2c of the semiconductor chip 2 forms 45 ° with the arrangement direction of the plurality of inner leads 5. 3, a small tab structure is employed in which an opening, which is a chip mounting area formed by the tip portions of the plurality of inner leads 5, can be made sufficiently larger than the semiconductor chip 2. That is, in the small tab structure, the distance between the tip of each inner lead 5 and the tab 3 can be increased.
Since there is a merit that the semiconductor chip 2 of various sizes can be mounted with one type of lead frame 10, the QFP 1 of the present embodiment adopts a small tab structure taking advantage of this merit. The inner lead 5, the tab 3, the tab suspension lead 4 and the outer lead 8 are, for example, Fe (iron).
-A member on a thin plate formed of Ni (nickel) alloy or the like. Further, the wire 7 is a fine metal wire such as gold. The sealing portion 9 is obtained by curing, for example, a thermosetting epoxy resin with a mold. Next, a method for manufacturing the QFP 1 of the present embodiment will be described with reference to a manufacturing process flowchart shown in FIG. First, the lead frame 10 shown in FIG. 5 having the inner lead 5, the tab 3, the tab suspension lead 4 and the outer lead 8 is prepared (step S1). Subsequently, as shown in FIGS. 2 and 3, four sides are formed on the outer periphery, and a semiconductor chip 2 having a plurality of pads 2a provided side by side along each side 2c.
Is supplied (step S2). Thereafter, the silver paste 6 is applied to the tab 3 of the lead frame 10, and the semiconductor chip 2 is further placed on the silver paste 6, thereby mounting the semiconductor chip 2 on the tab 3 (step S3). . At this time, as shown in FIG. 6, the arrangement direction of the plurality of pads 2a provided side by side along the four outer peripheries 2c of the semiconductor chip 2 is 45 ° from the arrangement direction of the plurality of inner leads 5. It is mounted on the tab 3 of the semiconductor chip 2 so as to be formed. Thereafter, the pads 2a of the semiconductor chip 2 and the corresponding inner leads 5 are wire-bonded using bonding wires 7 and are electrically connected (step S4). Thereafter, for example, the semiconductor chip 2, the wire 7, and the inner lead 5 are resin-sealed using an epoxy-based thermosetting sealing resin to form the sealing portion 9 (step S5). Subsequently, the frame portion 12 of the lead frame 10 that supports the outer lead 8 protruding from the sealing portion 9 and the outer lead 8 are separated by cutting, and the outer lead 8 is formed in a gull wing shape (step S6). Thus, the assembly of the semiconductor device according to the present embodiment, that is, QFP 1 is completed (step S
7). In the semiconductor device and the manufacturing method thereof according to the present embodiment, the semiconductor chip 2 is arranged such that the arrangement direction of the plurality of pads 2a on each side 2c of the semiconductor chip 2 forms 45 ° with the arrangement direction of the plurality of inner leads 5. By mounting, the clearance between adjacent wires in the corner portion of the semiconductor chip 2 can be increased during wire bonding. Here, the principle of increasing the clearance between the wires will be described. The clearance between adjacent wires is reduced as the pitch of the pads 2a is reduced, but this tendency is promoted particularly when the angle of wire bonding becomes an acute angle with respect to the arrangement of the pads 2a. Therefore, as shown in FIG. 3, when the pad interval is D, the wire diameter is L, and the wiring angle is θ, the clearance P between the wires is expressed by P = (D × sin θ) −L. That is, the clearance P between wires becomes smaller as the angle (θ) of the wiring with respect to the arrangement of the pads 2a becomes smaller. As in the present embodiment shown in FIG. 6, die bonding is performed so that the arrangement direction of the plurality of pads 2a on each side 2c of the semiconductor chip 2 forms 45 ° with the arrangement direction of the plurality of inner leads 5. By doing so, the angle of the wiring near the corner portion of the semiconductor chip 2 can be increased compared to the case where the semiconductor chip 2 is mounted without being inclined by 45 °. Therefore, since the clearance between the wires at the corner of the semiconductor chip 2 can be increased,
It becomes possible to alleviate or eliminate the bonding restrictions on the pad spacing near the corner of the semiconductor chip 2, and Q
The productivity of FP1 can be improved. Furthermore, since the clearance between adjacent wires in the corner portion can be increased, in QFP1,
Mounting by wire bonding with a narrow pitch can be realized. For example, chip size 3.96 mm x 3.85 m
m, when the pad spacing is 0.080 mm and the number of pins is 208 pins, the clearance between the wires at the corner is 0.065 mm
Compared to the case where the semiconductor chip 2 is not inclined 45 ° (the clearance between the wires is 0.061 mm), it is 0.004.
mm wide. Further, by adopting a small tab structure as in the embodiment of the present invention, it is possible to mount semiconductor chips 2 of various sizes. That is, it is possible to mount semiconductor chips 2 of various sizes with one type of lead frame 10. As a result, the number of types of lead frames 10 can be reduced and the development cost can be reduced. The above description is for a case of multiple pins. For example, when the chip size is 4.32 mm × 4.32 mm and the number of pins is about 44 pins, the clearance between the wires at the corner is 0.285 mm. When the semiconductor chip 2 is not inclined 45 ° (the clearance between the wires is 0.274
mm) and 0.011 mm wider. That is, the QFP 1 of the present embodiment can increase the clearance between the wires at the corners of the semiconductor chip 2 even when the number of pins is small. The invention made by the present inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment of the invention, and does not depart from the gist of the invention. Needless to say, various changes can be made. For example, in the present embodiment, the case where the semiconductor device QFP1 has a small tab structure has been described. However, the QFP1 is not limited to the small tab structure, and the chip mounting portion has a cruciform tab structure having a cruciform shape. There may be. Further, the tab 3 is not limited to the small tab structure but may be a tab 3 having a size larger than that of the semiconductor chip 2. In the above embodiment, the case where the semiconductor chip 2 is substantially square has been described. For example, as shown in FIG. 7, when the semiconductor chip 2 is rectangular, the semiconductor chip 2 is connected to a plurality of inner leads. By mounting the semiconductor chip 2 so that the arrangement direction of the plurality of pads 2a is 45 ° with respect to the arrangement direction of 5, the mold resin is filled from the corner portion of the inner leads 5 arranged in a substantially square shape at the time of molding. At this time, as shown in the flow direction 11 of the mold resin, the mold resin injected from the corner portion collides with the vicinity of the center of one short side of the semiconductor chip 2 and flows evenly distributed from side to side. However, as shown in the comparative example of FIG. 8, a plurality of pads 2 on each side 2c of the rectangular semiconductor chip 2 are used.
When the semiconductor chip 2 is mounted so that the arrangement direction of “a” is parallel to the arrangement direction of the plurality of inner leads 5, the mold resin is one length of the semiconductor chip 2 as shown in the flow direction 13 of the mold resin. Collides with the sides and does not flow evenly on the long and short sides. Therefore, as shown in FIG. 7, even when the semiconductor chip 2 is rectangular, the semiconductor chip 2 is mounted so that the arrangement direction of the plurality of pads 2a forms 45 ° with the arrangement direction of the plurality of inner leads 5. Thus, the flow of the wire 7 and the generation of voids due to the molding resin during molding can be reduced. In the above embodiment, the semiconductor device is Q.
Although the case of FP1 has been described, the semiconductor device is QFN.
(Quad Flat Non-leaded Package) and QFJ (Quad Fla
It can also be applied to other semiconductor devices such as (t-J-leaded Package). The effects obtained by typical ones of the inventions disclosed in this application will be briefly described.
It is as follows. By mounting the semiconductor chip so that the arrangement direction of the plurality of surface electrodes of the semiconductor chip forms 45 ° with respect to the arrangement direction of the plurality of inner leads, the bonding restrictions of the semiconductor chip can be alleviated or eliminated. As a result, the manufacturability of the semiconductor device can be improved.

【図面の簡単な説明】 【図１】本発明の実施の形態による半導体装置の構造の
一例を示す断面図である。 【図２】図１に示す半導体装置における半導体チップの
パッドとインナリードとのワイヤリング状態を示す拡大
部分平面図である。 【図３】図２のＡ部を示す拡大部分平面図である。 【図４】図１に示す半導体装置の組み立て手順の一例を
示す製造プロセスフロー図である。 【図５】本発明の実施の形態の半導体装置に用いられる
リードフレームの構造の一例を示す部分平面図である。 【図６】本発明の実施の形態の半導体装置の組み立てに
おけるダイボンディング状態の一例を示す部分平面図で
ある。 【図７】本発明の他の実施の形態の半導体装置における
モールド樹脂の流動方向の一例を示す拡大部分平面図で
ある。 【図８】図７に対する比較例のモールド樹脂の流動方向
を示す拡大部分平面図である。 【符号の説明】 １ ＱＦＰ（半導体装置） ２ 半導体チップ ２ａ パッド（表面電極） ２ｂ 配線 ２ｃ 辺 ２ｄ 主面 ３ タブ ４ タブ吊りリード ５ インナリード ６ 銀ペースト ７ ワイヤ ８ アウタリード ９ 封止部 １０ リードフレーム １１ モールド樹脂の流動方向 １２ 枠部 １３ モールド樹脂の流動方向BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment of the present invention. 2 is an enlarged partial plan view showing a wiring state between a pad and an inner lead of a semiconductor chip in the semiconductor device shown in FIG. 1; FIG. FIG. 3 is an enlarged partial plan view showing a part A of FIG. 2; 4 is a manufacturing process flow chart showing an example of an assembly procedure of the semiconductor device shown in FIG. 1; FIG. FIG. 5 is a partial plan view showing an example of the structure of a lead frame used in the semiconductor device according to the embodiment of the present invention. FIG. 6 is a partial plan view showing an example of a die bonding state in assembling the semiconductor device according to the embodiment of the present invention. FIG. 7 is an enlarged partial plan view showing an example of a flow direction of a mold resin in a semiconductor device according to another embodiment of the present invention. 8 is an enlarged partial plan view showing a flow direction of a mold resin of a comparative example with respect to FIG. [Description of Symbols] 1 QFP (semiconductor device) 2 Semiconductor chip 2a Pad (surface electrode) 2b Wiring 2c Side 2d Main surface 3 Tab 4 Tab suspension lead 5 Inner lead 6 Silver paste 7 Wire 8 Outer lead 9 Sealing portion 10 Lead frame 11 Flow direction of mold resin 12 Frame portion 13 Flow direction of mold resin

Claims (1)

【特許請求の範囲】 【請求項１】 外周に４つの辺が形成され、前記辺に沿
って並んで設けられた複数の表面電極を有する半導体チ
ップと、 前記半導体チップを支持するタブと、 前記半導体チップの周囲に延在する複数のインナリード
と、 前記半導体チップの表面電極とこれに対応する前記イン
ナリードとを電気的に接続するボンディング用のワイヤ
と、 前記半導体チップおよび前記ワイヤを樹脂封止して形成
された封止部とを有し、 前記半導体チップの各辺における前記複数の表面電極の
配列方向が、前記複数のインナリードの配列方向と４５
°を成すように前記半導体チップが前記タブに搭載され
ていることを特徴とする半導体装置。1. A semiconductor chip having four sides formed on an outer periphery and having a plurality of surface electrodes provided side by side along the side; a tab that supports the semiconductor chip; A plurality of inner leads extending around the semiconductor chip; a bonding wire that electrically connects the surface electrode of the semiconductor chip and the corresponding inner lead; and the semiconductor chip and the wire are sealed with resin. A plurality of surface electrodes on each side of the semiconductor chip are arranged in the same direction as the arrangement direction of the plurality of inner leads.
A semiconductor device, wherein the semiconductor chip is mounted on the tab so as to form an angle.
JP2001253431A 2001-08-23 2001-08-23 Semiconductor device Pending JP2003068781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001253431A JP2003068781A (en) 2001-08-23 2001-08-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001253431A JP2003068781A (en) 2001-08-23 2001-08-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003068781A true JP2003068781A (en) 2003-03-07

Family

ID=19081762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001253431A Pending JP2003068781A (en) 2001-08-23 2001-08-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003068781A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015220271A (en) * 2014-05-15 2015-12-07 ローム株式会社 package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015220271A (en) * 2014-05-15 2015-12-07 ローム株式会社 package

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