JP2003068568A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JP2003068568A
JP2003068568A JP2001255719A JP2001255719A JP2003068568A JP 2003068568 A JP2003068568 A JP 2003068568A JP 2001255719 A JP2001255719 A JP 2001255719A JP 2001255719 A JP2001255719 A JP 2001255719A JP 2003068568 A JP2003068568 A JP 2003068568A
Authority
JP
Japan
Prior art keywords
electrodes
external
ground
electrode
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001255719A
Other languages
Japanese (ja)
Inventor
Masayuki Watanabe
正之 渡辺
Hiroshi Ito
博史 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001255719A priority Critical patent/JP2003068568A/en
Publication of JP2003068568A publication Critical patent/JP2003068568A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a laminated ceramic capacitor for which many capacitor elements are constituted in a laminated body in high density. SOLUTION: For the laminated ceramic capacitor, internal electrodes 2, 3 and 4 and ground electrodes 5, 6 and 7 are alternately laminated through a dielectric layer 8 and turned to the laminated body, external electrodes connected to the internal electrodes and external ground electrodes connected to the ground electrodes are alternately formed respectively on both surfaces of the laminated body, the capacitor elements are constituted between the adjacent ground electrode and external electrode on both surfaces of the laminated body, and the capacitor elements are constituted between the external ground electrode and the external electrode facing each other on both surfaces of the laminated body.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は誘電体層を介して内
部電極と接地電極とを交互に積層して積層体とし、この
積層体に前記内部電極と接続した外部電極と前記接地電
極に接続した外部接地電極とを備える積層セラミックコ
ンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated body in which internal electrodes and ground electrodes are alternately laminated via dielectric layers, and the laminated body is connected to the external electrodes and the ground electrodes. The present invention relates to a laminated ceramic capacitor including the external ground electrode.

【0002】[0002]

【従来の技術】以下に一般的な積層電子部品として積層
セラミックコンデンサの構成を説明する。
2. Description of the Related Art The structure of a laminated ceramic capacitor as a general laminated electronic component will be described below.

【0003】図7は積層セラミックコンデンサの分解斜
視図、図8は同積層セラミックコンデンサの外観斜視
図、図9は同積層セラミックコンデンサの電気回路図で
ある。
FIG. 7 is an exploded perspective view of the monolithic ceramic capacitor, FIG. 8 is an external perspective view of the monolithic ceramic capacitor, and FIG. 9 is an electric circuit diagram of the monolithic ceramic capacitor.

【0004】図7、図8、図9において101は積層セ
ラミックコンデンサであり、この積層セラミックコンデ
ンサ101は誘電体で形成した誘電体層102を介して
内部電極103〜108と接地電極109〜114とを
交互に積層し、最上段と最下段に無効層115,116
を重ねて積層体117を形成し、この積層体117の表
面に前記内部電極103〜108の延長部118〜12
3と接続した外部電極124〜129と、前記接地電極
109〜114の延長部130〜135と接続した外部
接地電極136〜141とを備え、前記積層体117の
外部電極124〜129と相対向する外部接地電極13
6〜141との間にそれぞれコンデンサC101〜C1
06を構成している。
In FIGS. 7, 8 and 9, reference numeral 101 denotes a monolithic ceramic capacitor. The monolithic ceramic capacitor 101 has internal electrodes 103 to 108 and ground electrodes 109 to 114 via a dielectric layer 102 made of a dielectric material. Are alternately laminated, and ineffective layers 115 and 116 are provided at the top and bottom.
To form a laminated body 117, and the extended portions 118 to 12 of the internal electrodes 103 to 108 are formed on the surface of the laminated body 117.
3 and external ground electrodes 136-141 connected to the extension parts 130-135 of the ground electrodes 109-114, and opposed to the external electrodes 124-129 of the laminate 117. External ground electrode 13
6 to 141 and capacitors C101 to C1 respectively.
It is composed of 06.

【0005】前記のように構成された積層セラミックコ
ンデンサ101について、以下にその製造方法を説明す
る。
A method of manufacturing the monolithic ceramic capacitor 101 having the above structure will be described below.

【0006】まず、主成分がチタン酸バリウムからなる
セラミックスラリーを公知のドクターブレード法により
キャリアフィルム上に塗布後乾燥し、前記誘電体層10
2及び前記無効層115,116となるセラミックグリ
ーンシート(図示せず)とを作製する。
First, a ceramic slurry containing barium titanate as a main component is applied on a carrier film by a known doctor blade method and then dried to obtain the dielectric layer 10.
2 and a ceramic green sheet (not shown) to be the ineffective layers 115 and 116 are prepared.

【0007】次に前記セラミックグリーンシートの内、
前記無効層116となるセラミックグリーンシートを所
定枚数、加圧して圧着を繰り返し、この上段の上面にパ
ラジウムやニッケルからなる導電性ペーストをスクリー
ン印刷法などにより印刷、乾燥して内部電極103を形
成し、さらにこの上に誘電体層102となる前記セラミ
ックグリーンシートを圧着して上面にパラジウムやニッ
ケルからなる導電性ペーストを印刷、乾燥して接地電極
109を形成する。その後、順次前記誘電体層102と
なるセラミックグリーンシートを介して前記内部電極1
04と前記接地電極110、前記内部電極105と前記
接地電極111、前記内部電極106と前記接地電極1
12、前記内部電極107と前記接地電極113、前記
内部電極108と前記接地電極114とを形成して圧着
し、最上段に前記無効層115となるセラミックグリー
ンシートを所定枚数重ねて圧着して前記積層体117の
ブロックを作製し、この積層体117のブロックを所定
の寸法に切断して前記積層セラミックコンデンサ101
のグリーンチップを作製する。
Next, among the ceramic green sheets,
A predetermined number of ceramic green sheets to be the ineffective layer 116 are pressed and repeatedly pressed, and a conductive paste made of palladium or nickel is printed on the upper surface of the upper stage by a screen printing method or the like and dried to form the internal electrodes 103. Further, the ceramic green sheet to be the dielectric layer 102 is pressure-bonded thereon, a conductive paste made of palladium or nickel is printed on the upper surface, and dried to form the ground electrode 109. After that, the internal electrodes 1 are sequentially inserted through a ceramic green sheet that becomes the dielectric layer 102.
04 and the ground electrode 110, the internal electrode 105 and the ground electrode 111, the internal electrode 106 and the ground electrode 1
12, the internal electrode 107 and the ground electrode 113, the internal electrode 108 and the ground electrode 114 are formed and pressure-bonded, and a predetermined number of ceramic green sheets to be the ineffective layer 115 are stacked on the uppermost layer and pressure-bonded. A block of the laminated body 117 is produced, and the block of the laminated body 117 is cut into a predetermined size to obtain the laminated ceramic capacitor 101.
Make a green chip.

【0008】次に前記グリーンチップを脱脂、焼成して
焼結体とした後に前記積層体117の表面に露出した前
記複数の内部電極103〜108の延長部118〜12
3と、前記接地電極109〜114の延長部130〜1
35を覆うように導電性ペーストを塗布して焼き付け前
記外部電極124〜129と外部接地電極136〜14
1とを形成し、前記外部電極124〜129と外部接地
電極136〜141との対となる数だけのコンデンサ素
子C101〜C106を有する積層セラミックコンデン
サ101を完成する。
Next, after degreasing and firing the green chip to obtain a sintered body, the extension portions 118 to 12 of the plurality of internal electrodes 103 to 108 exposed on the surface of the laminated body 117.
3 and extension parts 130-1 of the ground electrodes 109-114
35 is coated with a conductive paste so as to cover 35 and baked, and the external electrodes 124 to 129 and the external ground electrodes 136 to 14
1 to form a monolithic ceramic capacitor 101 having the same number of capacitor elements C101 to C106 as the pair of the external electrodes 124 to 129 and the external ground electrodes 136 to 141.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、前記従
来の積層セラミックコンデンサ101の構成によれば、
前記内部電極103〜108と接地電極109〜114
とが前記誘電体層102を介して重なり合う数だけの前
記コンデンサ素子C101〜C106しか得られず、一
つの積層体117により多数のコンデンサ素子を構成す
るために、内部電極と接地電極の積層数を増やして積層
体の両面に更に多数の外部電極と外部接地電極とを形成
する必要があるので、生産性を損なったり、積層体の外
形が大きくなり高密度な実装が困難になるという問題点
があった。
However, according to the structure of the conventional monolithic ceramic capacitor 101,
The internal electrodes 103 to 108 and the ground electrodes 109 to 114
And only the number of capacitor elements C101 to C106 that are overlapped with each other via the dielectric layer 102 can be obtained, and in order to configure a large number of capacitor elements with one laminated body 117, the number of laminated internal electrodes and ground electrodes is Since it is necessary to increase the number of external electrodes and external ground electrodes formed on both surfaces of the laminated body, productivity may be impaired, and the outer shape of the laminated body may become large, making it difficult to perform high-density mounting. there were.

【0010】本発明は前記従来の問題を解決するもの
で、積層体の表面に形成する外部電極と外部接地電極と
の数を増やすことなく多数のコンデンサ素子の組み合わ
せを構成し、電子機器に高密度に実装できる積層セラミ
ックコンデンサを提供することを目的とする。
The present invention solves the above-mentioned problems of the prior art by constructing a combination of a large number of capacitor elements without increasing the number of external electrodes and external ground electrodes formed on the surface of the laminated body, which is suitable for electronic equipment. An object is to provide a monolithic ceramic capacitor that can be mounted at high density.

【0011】[0011]

【課題を解決するための手段】前記目的を達成するため
に、本発明の積層セラミックコンデンサは以下の構成を
有するものである。
In order to achieve the above object, the laminated ceramic capacitor of the present invention has the following constitution.

【0012】本発明の請求項1に記載の発明は、内部電
極と接地電極とを誘電体層を介して交互に積層して積層
体とし、この積層体の両面のそれぞれに前記内部電極と
接続した外部電極と前記接地電極と接続した外部接地電
極とを交互に形成し、積層体の両面において隣接する前
記外部接地電極と外部電極との間にコンデンサ素子を構
成するとともに積層体の両面に対向する前記外部接地電
極と外部電極との間にコンデンサ素子を構成した積層セ
ラミックコンデンサであり、これにより積層体の両面で
相対向した外部電極と外部接地電極との間に第一のコン
デンサ素子を構成でき、積層体の両面で並設した外部電
極と外部接地電極との間にそれぞれコンデンサ素子を構
成できるので、内部電極と接地電極との一対の重なりで
多数のコンデンサ素子を構成でき、電子機器に高密度に
実装できる付加価値の優れた積層セラミックコンデンサ
を得ることができるという作用、効果が得られる。
According to the first aspect of the present invention, the internal electrodes and the ground electrodes are alternately laminated via the dielectric layers to form a laminated body, and the internal electrodes are connected to both surfaces of the laminated body. External electrodes and external ground electrodes connected to the ground electrodes are alternately formed to form a capacitor element between the external ground electrodes and the external electrodes that are adjacent to each other on both sides of the laminated body and face both sides of the laminated body. A multilayer ceramic capacitor in which a capacitor element is formed between the external ground electrode and the external electrode, whereby a first capacitor element is formed between the external electrode and the external ground electrode facing each other on both surfaces of the multilayer body. Since a capacitor element can be formed between the external electrode and the external ground electrode, which are arranged side by side on both sides of the laminated body, a large number of capacitors can be formed by a pair of the internal electrode and the ground electrode. Can configure the child, effect that it is possible to obtain an excellent multilayer ceramic capacitor of value added which can be mounted densely on the electronic equipment, the effect can be obtained.

【0013】本発明の請求項2に記載の発明は、接地電
極に積層体の両面に露出する複数の延長部を並設し、内
部電極に積層体の両面に露出する一対の延長部を形成
し、前記内部電極と接地電極とを誘電体層を介して積層
する毎に前記内部電極の延長部を前記接地電極の並設方
向に順次ずらして積層し、前記接地電極の延長部と前記
内部電極の延長部とを交互に配置し、積層体の両面に前
記内部電極に接続した外部電極と前記接地電極に接続し
た外部接地電極とを交互に複数形成した請求項1に記載
の積層セラミックコンデンサであり、これにより外部電
極と交互に構成した外部接地電極のそれぞれが電気的に
短絡して電位が等しくなるので電気的接地効果が良好で
あり、隣接する外部電極間に外部接地電極を形成してい
るので複数の外部電極間のクロストークを防止でき、内
部電極と接地電極との一対の重なりで多数のコンデンサ
素子を構成できると共に電気特性の優れた積層セラミッ
クコンデンサを得ることができるという作用、効果が得
られる。
According to a second aspect of the present invention, a plurality of extension portions exposed on both sides of the laminated body are arranged in parallel to the ground electrode, and a pair of extension portions exposed on both sides of the laminated body are formed on the internal electrode. Then, every time the internal electrode and the ground electrode are laminated via the dielectric layer, the extension portion of the internal electrode is sequentially shifted and laminated in the juxtaposed direction of the ground electrode, and the extension portion of the ground electrode and the internal portion are laminated. The multilayer ceramic capacitor according to claim 1, wherein extension parts of the electrodes are alternately arranged, and a plurality of external electrodes connected to the internal electrodes and external ground electrodes connected to the ground electrodes are alternately formed on both surfaces of the multilayer body. As a result, each of the external ground electrodes alternately arranged with the external electrodes is electrically short-circuited and the potentials become equal, so that the electrical grounding effect is good, and the external ground electrodes are formed between the adjacent external electrodes. Since there are multiple external power Can prevent crosstalk between, effect that it is possible to obtain an excellent multilayer ceramic capacitor of the electrical properties is possible configure multiple capacitor elements in a pair of overlap between the internal electrode and the ground electrode, the effect can be obtained.

【0014】本発明の請求項3に記載の発明は、内部電
極を積層体の相対向する両面の間で分離して一対の内部
電極で構成した請求項1に記載の積層セラミックコンデ
ンサであり、これにより積層体の両面で対向する外部電
極どうしが短絡することなく独立して構成されるので一
層多数のコンデンサ素子を高密度に構成し、電気特性の
優れた積層セラミックコンデンサを得ることができると
いう作用、効果が得られる。
The invention according to claim 3 of the present invention is the monolithic ceramic capacitor according to claim 1 in which the internal electrodes are separated by a pair of internal electrodes between opposite surfaces of the laminate. As a result, since the external electrodes facing each other on both sides of the laminated body are independently configured without short-circuiting, it is possible to configure a larger number of capacitor elements at high density and obtain a laminated ceramic capacitor having excellent electrical characteristics. Action and effect can be obtained.

【0015】本発明の請求項4に記載の発明は、一対の
内部電極の面積を相異なるものとした請求項3に記載の
積層セラミックコンデンサであり、これにより、積層体
の両面で静電容量の異なるコンデンサ素子を構成できる
ので、多数、多種のコンデンサ素子を高密度に構成し、
付加価値の優れた積層セラミックコンデンサを得ること
ができるという作用、効果が得られる。
The invention according to claim 4 of the present invention is the monolithic ceramic capacitor according to claim 3, wherein the areas of the pair of internal electrodes are different from each other, whereby the capacitance on both surfaces of the laminate is increased. Since different capacitor elements can be configured, a large number of various capacitor elements can be configured at high density,
The action and effect of obtaining a monolithic ceramic capacitor having an excellent added value can be obtained.

【0016】[0016]

【発明の実施の形態】(実施の形態1)以下、実施の形
態1を用いて、本発明の特に請求項1,2に記載の発明
について説明する。
BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) In the following, the invention described in claims 1 and 2 of the present invention will be described with reference to Embodiment 1.

【0017】図1は本発明の実施の形態1における積層
セラミックコンデンサの分解斜視図、図2は同積層セラ
ミックコンデンサの外観斜視図、図3は同積層セラミッ
クコンデンサの電気回路図である。
FIG. 1 is an exploded perspective view of a monolithic ceramic capacitor according to Embodiment 1 of the present invention, FIG. 2 is an external perspective view of the monolithic ceramic capacitor, and FIG. 3 is an electric circuit diagram of the monolithic ceramic capacitor.

【0018】図1〜図3において1は積層セラミックコ
ンデンサであり、この積層セラミックコンデンサ1は内
部電極2,3,4と接地電極5,6,7とを誘電体層8
を介して交互に積層し、上段と下段に無効層9,10を
複数枚重ねて積層体11とし、この積層体11の両面の
それぞれに前記内部電極2,3,4と接続した外部電極
12〜17と前記接地電極5,6,7と接続した外部接
地電極18〜23とを交互に形成した構成としている。
1 to 3, reference numeral 1 denotes a monolithic ceramic capacitor, and the monolithic ceramic capacitor 1 has internal electrodes 2, 3, 4 and ground electrodes 5, 6, 7 as a dielectric layer 8.
And the external electrodes 12 connected to the internal electrodes 2, 3 and 4 respectively on both surfaces of the laminated body 11 by stacking a plurality of ineffective layers 9 and 10 on the upper and lower layers alternately. ˜17 and external ground electrodes 18 to 23 connected to the ground electrodes 5, 6 and 7 are alternately formed.

【0019】前記接地電極5,6,7に前記積層体11
の両面に露出する複数の延長部24〜29を並設し、前
記内部電極2,3,4に前記積層体11の両面に露出す
る一対の延長部30と31、32と33、34と35と
を形成し、前記内部電極2,3,4と接地電極5,6,
7とを前記誘電体層8を介して積層する毎に前記内部電
極2,3,4の延長部30と31、32と33、34と
35とを前記接地電極5,6,7の延長部24〜29の
並設方向に順次ずらして積層し、前記接地電極5,6,
7の延長部24〜29と前記内部電極2,3,4の延長
部30と31、32と33、34と35とを交互に配置
し、前記積層体11の両面に前記内部電極2〜4に接続
した外部電極12〜17と前記接地電極5〜7に接続し
た外部接地電極18〜23とを交互に複数形成してい
る。
The laminated body 11 is formed on the ground electrodes 5, 6 and 7.
A plurality of extension parts 24 to 29 exposed on both surfaces of the laminate 11 are arranged side by side, and a pair of extension parts 30 and 31, 32, 33, 34 and 35 exposed on both surfaces of the laminated body 11 on the internal electrodes 2, 3 and 4. And the internal electrodes 2, 3, 4 and the ground electrodes 5, 6,
7 and the extension portions 30 and 31, 32 and 33, 34 and 35 of the internal electrodes 2, 3 and 4 each time the dielectric layer 8 is laminated via the extension portions of the ground electrodes 5, 6 and 7. 24 to 29 are sequentially staggered in the juxtaposed direction to be laminated, and the ground electrodes 5, 6,
7 extending portions 24 to 29 and the extending portions 30 and 31, 32 and 33, 34 and 35 of the internal electrodes 2, 3 and 4 are alternately arranged, and the internal electrodes 2 to 4 are provided on both surfaces of the laminated body 11. A plurality of external electrodes 12 to 17 connected to and external ground electrodes 18 to 23 connected to the ground electrodes 5 to 7 are alternately formed.

【0020】前記にように構成された積層セラミックコ
ンデンサ1について、以下にその製造方法を説明する。
A method of manufacturing the monolithic ceramic capacitor 1 having the above structure will be described below.

【0021】まず、主成分がチタン酸バリウムからなる
セラミックスラリーを公知のドクターブレード法により
キャリアフィルム上に塗布後乾燥し、前記誘電体層8及
び前記無効層9,10となるセラミックグリーンシート
(図示せず)とを作製する。
First, a ceramic slurry containing barium titanate as a main component is applied on a carrier film by a known doctor blade method and then dried to form a ceramic green sheet for forming the dielectric layer 8 and the ineffective layers 9 and 10 (see FIG. And (not shown).

【0022】次に前記セラミックグリーンシートの内、
前記無効層10となるセラミックグリーンシートを所定
枚数、加圧して圧着を繰り返し、この上段にパラジウム
やニッケルからなる導電性ペーストを印刷、乾燥して内
部電極2を形成し、さらにこの上に誘電体層8となる前
記セラミックグリーンシートを圧着し、上面にパラジウ
ムやニッケルからなる導電性ペーストを印刷、乾燥して
接地電極5を形成する。このとき、前記接地電極5には
前記誘電体層8の両端に延長し対となる複数の延長部2
4と25、26と27、28と29とを形成し、前記内
部電極2には一対の延長部30と31を形成する。その
後、前記誘電体層8を介して積層する毎に前記内部電極
2,3,4の延長部30と31、32と33、34と3
5とを前記接地電極5,6,7の延長部24〜29の並
設方向に順次ずらして積層し、前記接地電極5,6,7
の延長部24〜29と前記内部電極2,3,4の延長部
30と31、32と33、34と35とを交互に配置し
て圧着し、最上段に無効層9となるセラミックグリーン
シートを所定枚数重ねて圧着して積層体11のブロック
を作製し、この積層体11のブロックを所定の寸法に切
断して積層セラミックコンデンサ1のグリーンチップを
作製する。
Next, among the ceramic green sheets,
A predetermined number of ceramic green sheets to be the ineffective layer 10 are pressed and repeatedly pressed, and a conductive paste made of palladium or nickel is printed on the upper layer and dried to form the internal electrodes 2, and a dielectric substance is further formed thereon. The ceramic green sheet to be the layer 8 is pressure-bonded, a conductive paste made of palladium or nickel is printed on the upper surface, and dried to form the ground electrode 5. At this time, the ground electrode 5 has a plurality of extension parts 2 extending to both ends of the dielectric layer 8 and forming a pair.
4 and 25, 26 and 27, 28 and 29 are formed, and a pair of extension portions 30 and 31 are formed in the internal electrode 2. Then, each time the layers are laminated with the dielectric layer 8 interposed therebetween, the extension portions 30 and 31, 32 and 33, 34 and 3 of the internal electrodes 2, 3 and 4 are laminated.
5 and 5 are sequentially shifted in the direction in which the extension portions 24 to 29 of the ground electrodes 5, 6 and 7 are arranged in parallel, and are stacked to form the ground electrodes 5, 6, 7
24 to 29 and the extension parts 30 and 31, 32 and 33, 34 and 35 of the internal electrodes 2, 3 and 4 are alternately arranged and crimped to form the ineffective layer 9 at the uppermost stage. A predetermined number of sheets are stacked and pressure-bonded to produce a block of the laminated body 11, and the block of the laminated body 11 is cut into a predetermined size to produce a green chip of the laminated ceramic capacitor 1.

【0023】次に前記グリーンチップを脱脂、焼成して
焼結体とした後に前記積層体11の表面に露出した前記
複数の内部電極2〜4の延長部30〜35と、前記接地
電極5〜7の延長部24〜29とを覆うように導電性ペ
ーストを塗布して焼き付けて前記外部電極12〜17と
外部接地電極18〜23とを形成し、積層セラミックコ
ンデンサ1を完成する。
Next, after degreasing and firing the green chip into a sintered body, the extension portions 30 to 35 of the plurality of internal electrodes 2 to 4 exposed on the surface of the laminated body 11 and the ground electrode 5 are exposed. 7. A conductive paste is applied so as to cover the extended portions 24 to 29 of 7 and baked to form the external electrodes 12 to 17 and the external ground electrodes 18 to 23, thus completing the monolithic ceramic capacitor 1.

【0024】前記の構成により積層セラミックコンデン
サ1において外部電極12,13と外部接地電極18,
19,20,21,22,23との間にそれぞれコンデ
ンサ素子C1を構成し、外部電極14,15と外部接地
電極18,19,20,21,22,23との間にそれ
ぞれコンデンサ素子C2を構成し、外部電極16,17
と外部接地電極18,19,20,21,22,23と
の間にそれぞれコンデンサ素子C3を構成し、内部電極
と接地電極との重なりが3対であるが前記C1,C2,
C3のコンデンサ素子がそれぞれ外部接地電極18〜2
3とのそれぞれの組み合わせで得られるので、内部電極
と接地電極との重なり合う数が少なくても多数のコンデ
ンサ素子を構成できている。
With the above structure, in the monolithic ceramic capacitor 1, the external electrodes 12, 13 and the external ground electrode 18,
Capacitor element C1 is respectively formed between 19, 20, 21, 22, and 23, and capacitor element C2 is respectively formed between the external electrodes 14, 15 and the external ground electrodes 18, 19, 20, 21, 22, 23. And external electrodes 16 and 17
And external ground electrodes 18, 19, 20, 21, 22, and 23, respectively, to form a capacitor element C3, and the internal electrode and the ground electrode overlap with each other in three pairs.
The capacitor elements of C3 are external ground electrodes 18-2, respectively.
Since it can be obtained by each combination with 3, a large number of capacitor elements can be configured even if the number of overlapping internal electrodes and ground electrodes is small.

【0025】(実施の形態2)以下、実施の形態2を用
いて、本発明の特に請求項3,4に記載の発明について
説明する。尚、本実施の形態2における積層セラミック
コンデンサは基本的に実施の形態1で示した積層セラミ
ックコンデンサと同じ構成なので共通となる構成部分に
は同一符号を付し詳細な説明は省略する。
(Second Embodiment) The second embodiment of the present invention will be described below. Since the monolithic ceramic capacitor according to the second embodiment has basically the same configuration as that of the monolithic ceramic capacitor according to the first embodiment, common components are designated by the same reference numerals and detailed description thereof will be omitted.

【0026】図4は本発明の実施の形態2における積層
セラミックコンデンサの分解斜視図、図5は同積層セラ
ミックコンデンサの外観斜視図、図6は同積層セラミッ
クコンデンサの電気回路図である。
FIG. 4 is an exploded perspective view of the monolithic ceramic capacitor according to the second embodiment of the present invention, FIG. 5 is an external perspective view of the monolithic ceramic capacitor, and FIG. 6 is an electric circuit diagram of the monolithic ceramic capacitor.

【0027】図4〜図6において、41は積層セラミッ
クコンデンサであり、この積層セラミックコンデンサ4
1は間隙を形成して分離した一対の内部電極42,43
と接地電極54、内部電極44,45と接地電極55、
内部電極46,47と接地電極56とを誘電体層8を介
して交互に積層し、上段と下段に無効層9,10を複数
枚重ねて積層体74とし、この積層体74の両面のそれ
ぞれに前記内部電極42〜47と接続した外部電極63
〜68と、前記接地電極57〜62と接続した外部接地
電極69〜74とを前記積層体74の相対向する両面に
向かい合うように交互に形成している。
In FIGS. 4 to 6, reference numeral 41 denotes a monolithic ceramic capacitor.
1 is a pair of internal electrodes 42, 43 separated by forming a gap
And the ground electrode 54, the internal electrodes 44, 45 and the ground electrode 55,
The internal electrodes 46, 47 and the ground electrode 56 are alternately laminated with the dielectric layer 8 interposed therebetween, and a plurality of ineffective layers 9, 10 are laminated on the upper and lower layers to form a laminated body 74. An external electrode 63 connected to the internal electrodes 42 to 47
To 68 and external ground electrodes 69 to 74 connected to the ground electrodes 57 to 62 are alternately formed so as to face opposite surfaces of the laminate 74.

【0028】前記接地電極54,55,56には誘電体
層8の一端に向かう延長部57,59,61と、誘電体
層8の他端に向かう延長部58,60,62とを並設
し、前記内部電極42,44,46に前記誘電体層8の
一端に向かう延長部48,50,52を形成し、前記内
部電極43,45,47に前記誘電体層8の他端に向か
う延長部49,51,53とを形成し、前記内部電極4
2,44,46の延長部48〜52と前記外部電極63
〜68とを接続し、前記接地電極54,55,56の延
長部57〜62と前記外部接地電極69〜74とを接続
した構成としている。このとき前記内部電極42,4
4,46の面積は前記内部電極43,45,47の面積
の1/2で形成している。
The ground electrodes 54, 55 and 56 are provided with extension portions 57, 59 and 61 extending toward one end of the dielectric layer 8 and extension portions 58, 60 and 62 extending toward the other end of the dielectric layer 8. Then, extending portions 48, 50, 52 are formed on the internal electrodes 42, 44, 46 toward one end of the dielectric layer 8, and the internal electrodes 43, 45, 47 are extended toward the other end of the dielectric layer 8. The extension parts 49, 51 and 53 are formed, and the internal electrode 4 is formed.
2, 44, 46 extended portions 48 to 52 and the external electrode 63
To 68, the extension portions 57 to 62 of the ground electrodes 54, 55, 56 and the external ground electrodes 69 to 74 are connected. At this time, the internal electrodes 42, 4
The areas of 4, 46 are formed to be half the area of the internal electrodes 43, 45, 47.

【0029】前記の構成により積層セラミックコンデン
サ41において前記外部電極63と前記外部接地電極6
9〜74との間にそれぞれコンデンサ素子C21を構成
し、前記外部電極64と前記外部接地電極69〜74と
の間にそれぞれコンデンサ素子C22を構成し、前記外
部電極65と前記外部接地電極69〜74との間にそれ
ぞれコンデンサ素子C23を構成し、前記内部電極66
と前記外部接地電極69〜74との間にそれぞれコンデ
ンサ素子C24を構成し、前記外部電極67と前記外部
接地電極69〜74との間にそれぞれコンデンサ素子C
25を構成し、前記外部電極68と前記外部接地電極6
9〜74との間にそれぞれコンデンサ素子C26を構成
している。
With the above structure, in the multilayer ceramic capacitor 41, the external electrode 63 and the external ground electrode 6 are provided.
9 to 74, a capacitor element C21 is formed between the external electrode 64 and the external ground electrodes 69 to 74, and a capacitor element C22 is formed between the external electrode 64 and the external ground electrodes 69 to 74. 74 to form a capacitor element C23 between them and the internal electrode 66.
And a capacitor element C24 between the external ground electrodes 69 to 74 and a capacitor element C between the external electrode 67 and the external ground electrodes 69 to 74, respectively.
25, and includes the external electrode 68 and the external ground electrode 6
Capacitor element C26 is formed between each of them and 9 to 74.

【0030】前記構成により、内部電極と接地電極との
重なりが3対であるが前記C21,C22,C23,C
24,C25,C26のコンデンサ素子がそれぞれ外部
接地電極69〜74とのそれぞれの組み合わせで得られ
るので、内部電極と接地電極との重なり合う数が少なく
ても多数のコンデンサ素子を構成でき、且つ、外部電極
63,65,67に接続したコンデンサ素子は外部電極
64,66,67に接続したコンデンサ素子に比べて静
電容量が1/2になるように構成し2種類の静電容量値
を構成できて付加価値の高い積層セラミックコンデンサ
が得られている。
With the above structure, although the internal electrode and the ground electrode overlap with each other in three pairs, the C21, C22, C23, C
Since 24, C25, and C26 capacitor elements are obtained by respectively combining with the external ground electrodes 69 to 74, a large number of capacitor elements can be configured even if the number of overlapping internal electrodes and ground electrodes is small, and external The capacitor element connected to the electrodes 63, 65 and 67 has a capacitance that is half that of the capacitor element connected to the external electrodes 64, 66 and 67, and can have two types of capacitance values. As a result, a monolithic ceramic capacitor with high added value has been obtained.

【0031】尚、前記内部電極42〜48の面積をそれ
ぞれ異なるように形成すると一つの積層体の中に静電容
量が相異なる多種のコンデンサ素子を構成でき、複数の
コンデンサ素子のそれぞれを構成する誘電体層の材質を
それぞれ変えて温度特性の相異なるコンデンサ素子を構
成できる。
If the areas of the internal electrodes 42 to 48 are formed to be different from each other, various capacitor elements having different electrostatic capacities can be formed in one laminated body, and each of the plurality of capacitor elements is formed. Capacitor elements having different temperature characteristics can be formed by changing the materials of the dielectric layers.

【0032】[0032]

【発明の効果】以上のように本発明は、積層体の両面で
相対向した外部電極と外部接地電極との間に第一のコン
デンサ素子を構成でき、積層体の両面で並設した外部電
極と外部接地電極との間にそれぞれコンデンサ素子を構
成できるので、内部電極と接地電極との一対の重なりで
多数のコンデンサ素子を高密度に構成し、付加価値の優
れた積層セラミックコンデンサを得ることができる。
INDUSTRIAL APPLICABILITY As described above, according to the present invention, the first capacitor element can be formed between the external electrode and the external ground electrode facing each other on both sides of the laminated body, and the external electrodes arranged side by side on both sides of the laminated body. Since a capacitor element can be formed between the external electrode and the external ground electrode, a large number of capacitor elements can be densely formed by a pair of the internal electrode and the ground electrode, and a multilayer ceramic capacitor with excellent added value can be obtained. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態1における積層セラミック
コンデンサの分解斜視図
FIG. 1 is an exploded perspective view of a monolithic ceramic capacitor according to a first embodiment of the present invention.

【図2】同実施の形態1における積層セラミックコンデ
ンサの外観斜視図
FIG. 2 is an external perspective view of the monolithic ceramic capacitor according to the first embodiment.

【図3】同実施の形態1における積層セラミックコンデ
ンサの電気回路図
FIG. 3 is an electric circuit diagram of the monolithic ceramic capacitor according to the first embodiment.

【図4】本発明の実施の形態2における積層セラミック
コンデンサの分解斜視図
FIG. 4 is an exploded perspective view of a monolithic ceramic capacitor according to a second embodiment of the present invention.

【図5】同実施の形態2における積層セラミックコンデ
ンサの外観斜視図
FIG. 5 is an external perspective view of the monolithic ceramic capacitor according to the second embodiment.

【図6】同実施の形態2における積層セラミックコンデ
ンサの電気回路図
FIG. 6 is an electric circuit diagram of the monolithic ceramic capacitor according to the second embodiment.

【図7】従来例における積層セラミックコンデンサの分
解斜視図
FIG. 7 is an exploded perspective view of a conventional monolithic ceramic capacitor.

【図8】同積層セラミックコンデンサの外観斜視図FIG. 8 is an external perspective view of the multilayer ceramic capacitor.

【図9】同積層セラミックコンデンサの電気回路図FIG. 9 is an electric circuit diagram of the multilayer ceramic capacitor.

【符号の説明】[Explanation of symbols]

1,41 積層セラミックコンデンサ 2,3,4,42〜47 内部電極 5,6,7,54,55,56 接地電極 8 誘電体層 9,10 無効層 11 積層体 12〜17 外部電極 18〜23 外部接地電極 24〜35,48〜53,57〜62 延長部 1,41 Multilayer ceramic capacitors 2, 3, 4, 42-47 Internal electrodes 5,6,7,54,55,56 Ground electrode 8 Dielectric layer 9,10 Invalid layer 11 laminate 12-17 External electrode 18-23 External ground electrode 24-35, 48-53, 57-62 Extension

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 内部電極と接地電極とを誘電体層を介し
て交互に積層して積層体とし、この積層体の両面のそれ
ぞれに前記内部電極と接続した外部電極と前記接地電極
と接続した外部接地電極とを交互に形成し、積層体の両
面において隣接する前記外部電極と前記外部接地電極と
の間にコンデンサ素子を構成するとともに、この積層体
の両面に対向する前記外部電極と前記外部接地電極との
間にコンデンサ素子を構成した積層セラミックコンデン
サ。
1. An internal electrode and a ground electrode are alternately laminated through a dielectric layer to form a laminated body, and an external electrode connected to the internal electrode and the ground electrode are connected to both surfaces of the laminated body. External ground electrodes are alternately formed to form a capacitor element between the external electrodes and the external ground electrodes that are adjacent to each other on both sides of the laminated body, and the external electrodes and the outside that are opposed to both sides of the laminated body. A monolithic ceramic capacitor that has a capacitor element between it and the ground electrode.
【請求項2】 接地電極に積層体の両面に露出する複数
の延長部を並設し、内部電極に積層体の両面に露出する
一対の延長部を形成し、前記内部電極と接地電極とを誘
電体層を介して積層する毎に前記内部電極の延長部を前
記接地電極の並設方向に順次ずらして前記接地電極の延
長部と前記内部電極の延長部とを交互に配置し、積層体
の両面に前記内部電極に接続した外部電極と前記接地電
極に接続した外部接地電極とを交互に複数形成した請求
項1に記載の積層セラミックコンデンサ。
2. A ground electrode is provided with a plurality of extension portions that are exposed on both sides of the laminate, and a pair of extension portions that are exposed on both sides of the laminate are formed on the internal electrode. The internal electrode and the ground electrode are connected to each other. Every time the layers are laminated via the dielectric layer, the extension parts of the internal electrodes are sequentially shifted in the juxtaposed direction of the ground electrodes, and the extension parts of the ground electrodes and the extension parts of the internal electrodes are alternately arranged to form a laminate. The multilayer ceramic capacitor according to claim 1, wherein a plurality of external electrodes connected to the internal electrodes and external ground electrodes connected to the ground electrodes are alternately formed on both surfaces of the multilayer ceramic capacitor.
【請求項3】 内部電極を積層体の相対向する両面の間
で分離して一対の内部電極で構成した請求項1に記載の
積層セラミックコンデンサ。
3. The monolithic ceramic capacitor according to claim 1, wherein the internal electrode is formed between a pair of internal electrodes separated from each other on opposite sides of the laminated body.
【請求項4】 一対の内部電極の面積を相異なるものと
した請求項3に記載の積層セラミックコンデンサ。
4. The monolithic ceramic capacitor according to claim 3, wherein the areas of the pair of internal electrodes are different from each other.
JP2001255719A 2001-08-27 2001-08-27 Laminated ceramic capacitor Pending JP2003068568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001255719A JP2003068568A (en) 2001-08-27 2001-08-27 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001255719A JP2003068568A (en) 2001-08-27 2001-08-27 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JP2003068568A true JP2003068568A (en) 2003-03-07

Family

ID=19083646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001255719A Pending JP2003068568A (en) 2001-08-27 2001-08-27 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2003068568A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1560235A3 (en) * 2004-01-27 2008-01-02 Epcos Ag Electrical multilayer component
US7652869B2 (en) 2005-08-19 2010-01-26 Tdk Corporation Multilayer capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1560235A3 (en) * 2004-01-27 2008-01-02 Epcos Ag Electrical multilayer component
US7652869B2 (en) 2005-08-19 2010-01-26 Tdk Corporation Multilayer capacitor

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