JP2003067323A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new processor system with a peripheral function block whose devices respectively independently operate, having high operation speed and high CPU processing efficiency without increasing electric power consumption. SOLUTION: This processor system 1 wherein a CPU 11 and the plurality of devices P1-Pn constituting the peripheral block 3 of the CPU 11 exchange a signal via a first bus (MBUS) 14 is provided with a second bus (PCBUS30) for exchanging a signal among the plurality of devices P1-Pn. The respective devices P1-Pn are provided with a connection/separation means gate circuits P1g-Png connectable/separable to/from the second bus 30. A signal changeover means (SMX) 24 having a plurality of connection means changing over the signals transmitted through a plurality of signal lines and selecting the device P1-Pn of a connection destination is provided between an output signal bus (PCBUS) 31 and an input signal bus (PCBUS) 32 constituting the second bus 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data access between peripheral devices forming peripheral function blocks of a processor system.

[0002]

2. Description of the Related Art In recent years, in computers, home electric appliances, industrial equipment, etc., higher speed and higher functionality have been promoted according to the needs of users. These devices are equipped with a microprocessor as a control device. The microprocessor has the functions of a central processing unit (CPU) integrated in one semiconductor chip. A device equipped with a microprocessor is provided with a plurality of devices that form peripheral function blocks of a CPU, a memory that stores programs and data, and the like, and a processor system is configured by these.

A conventional processor system has, for example, a configuration as shown in FIG. FIG. 7 is a block diagram showing a schematic configuration of a conventional processor system. The processor system 101 is a Main System Block (MBLOC
K) 102 (hereinafter referred to as main system block 102) and Peripheral Block (PBLOCK) 103 (hereinafter referred to as peripheral function block 103).
The main system block 102 includes a CPU 111 and a Prog
A ram memory 112 (hereinafter referred to as PROM 112) and a data memory 113 (hereinafter referred to as DRAM 113) are provided. In addition, the peripheral function block 10
3 is a Peripheral D as a peripheral device of the CPU 111.
evice1 to Peripheral Device 3 (hereinafter, peripheral device P
1 to peripheral device P3. ) Is provided. Further, the CPU 111 has a main system bus 107 (hereinafter, MBUS107) which is an internal bus of the processor system.
Called. ) Is connected with each device.

In the processor system 101, the CPU 1
11 reads out the instruction stored in the PROM 112 via the MBUS 107 and decodes it. Also, the CPU 11
1 is the peripheral devices P1 to P of the peripheral function block 102
A value is written to or read from each register in 3. Then, after calculating and processing the data, the data is output to an output device (not shown) or a storage device such as the DRAM 113. Each of the above registers is a register unique to the peripheral function block 102, and is used to monitor the operation (for example, operation stop, start, operation mode, etc.) setting and state of the peripheral function block. As described above, in the conventional processor system, the CPU operates to control the peripheral function block, and the Progra storing the control instruction is controlled.
m Memory must be read.

In the processor system, the CPU is an active device, whereas the peripheral function block is a block having a passive device, and is generally C
The PU is called a master, and the peripheral function blocks are called slaves for distinction. Further, in a conventional processor system, the slave generally operates depending on the master, and the master generally controls the entire processor system.

Therefore, in order to realize high-speed operation of the entire processor system which is a user's need, it is essential to improve the performance of the CPU. Specifically, by increasing the frequency of the operating clock, the instruction execution time is shortened, and the instruction processing efficiency is improved by pipeline processing that performs the instruction reading, decoding, operation, and execution processes in parallel.
U performance improvement is realized.

[0007]

However, there is a problem in that the speeding up of the processor system by the above method causes an increase in power consumption of the processor system.
That is, increase the operating clock frequency and program
The memory read operation increases power consumption. Further, there is a problem in that the amount of heat generated by the CPU due to this increase in power consumption is large, and a cooling fan, heat radiation fins, etc. are required.

Further, the pipeline processing is performed by Program Memo.
Instructions stored in ry are not always executed in order, but instructions are often executed in irregular order due to program jumps, subroutine calls, interrupts, and the like. Therefore, there is a limit to the performance improvement of the processor system even if the pipeline processing is performed. Further, in order to realize the pipeline processing, complicated circuits such as a data storage register and a pipeline bus in each stage are required. Therefore, there is a problem that the circuit scale is increased and eventually the cost is increased.

Further, the peripheral function block is controlled by the program execution of the CPU, but the control of the peripheral function block may be delayed due to the program interrupt processing or the like, which may cause a time lag. Therefore, such a time lag is not preferable in the processor system in which it is necessary to operate the peripheral function blocks in a precise time without variation.

A known technique for such a problem is DMA (Direct Memory Access). DMA is
This is a method of directly transferring data between each device and a memory without going through the CPU, and can improve the data transfer speed and reduce the load on the CPU.

Data transfer by DMA is called DMA transfer, and as this prior art, Japanese Patent Application Laid-Open No. 11-296472 discloses a technology relating to a display control circuit.
This technology uses C when displaying information on a liquid crystal panel.
In order to reduce the involvement of PU as much as possible, transfer means for performing DMA transfer is provided, and display data is sent to the liquid crystal display control circuit without going through the CPU, whereby power consumption can be suppressed.

However, DMA is limited to the transfer of continuous memory data. Also, DMA is
Data exchange is performed using a general-purpose bus (main bus) to which a CPU is connected. Therefore, there is a problem that the general-purpose bus cannot be used for other purposes while the DMA is being performed. Further, the display control circuit disclosed in the above publication is specialized for a liquid crystal display system and can be used only in a limited system or application.

Therefore, the present invention was created in order to solve the above problems, and an object of the present invention is to provide a processor system having a peripheral function block with a high-speed operation and a high-speed CPU processing without increasing the power consumption. It is to provide a highly efficient processor system. further,
It is to provide a new processor system in which each peripheral function block operates independently.

[0014]

The present invention has the following structure as means for solving the above problems.

(1) In a processor system in which signals are exchanged between a CPU and a plurality of devices that form a peripheral function block of the CPU via a first bus, signals of the plurality of devices are exchanged. It is characterized by having a second bus for exchanging.

In this configuration, in the processor system, signals are exchanged between the CPU and a plurality of devices forming the peripheral function block of the CPU via the first bus, and the plurality of devices are exchanged with each other. Signals are exchanged via the second bus. Therefore, since internal signals can be exchanged between a plurality of devices of the peripheral function block without going through the first bus, the load on the CPU can be reduced, the instruction processing efficiency can be improved, and the processing of the entire processor system can be speeded up. It becomes possible. Moreover, since the number of instructions can be reduced, the program memory capacity can be reduced.

(2) Each of the plurality of devices is provided with a contacting / separating means capable of contacting / separating with the second bus.

In this structure, the plurality of devices are provided with the contacting / separating means capable of contacting / separating with the second bus. Therefore, it is possible to block signal transmission / reception in a device that does not require signal exchange, and prevent signals from being erroneously output due to noise or the like.

(3) Each of the plurality of devices forming the peripheral function block includes a first storage unit that stores control data of the contacting / separating unit, and the control data is transmitted via the first bus. The CPU is rewritable.

In this structure, the plurality of devices forming the peripheral function block are connected to the C via the first bus.
A first storage unit that stores control data of the contacting / separating unit is rewritable from the PU. Therefore, it becomes possible to specify a device for exchanging data in the peripheral function block and freely set a signal for exchanging data, and it is possible to improve the degree of freedom of the processor system.

(4) The second bus includes an output signal bus having a plurality of signal lines for transmitting signals output from the plurality of devices, and a plurality of output signals for transmitting signals input to the plurality of devices. A plurality of connections comprising an input signal bus provided with a signal line, for exchanging signals for transmitting the plurality of signal lines, and selecting a connection destination device between the output signal bus and the input signal bus. And a signal switching means having means.

In this configuration, the processor system includes an output signal bus having a plurality of signal lines for transmitting signals output from a plurality of devices and a plurality of signal lines for transmitting signals input to the plurality of devices. The input signal bus and the exchange of signals that transmit multiple signal lines,
And signal switching means having a plurality of connection means for selecting a device to be connected. Therefore, it becomes possible to reliably exchange signals and exchange signals between a plurality of devices.

(5) A second storage means for storing control data of a plurality of connection means included in the signal switching means is provided, and the control data is sent to the CP via the first bus.
It is rewritable from U.

In this configuration, the control data of the plurality of connecting means included in the signal switching means stored in the second storage means included in the processor system can be rewritten from the CPU via the first bus. Therefore, it becomes possible to specify a device for exchanging data in the peripheral function block and freely set a signal for exchanging data, and it is possible to improve the degree of freedom of the processor system.

(6) The plurality of connecting means are composed of NMOS transistors.

In this structure, the processor system is provided with a plurality of connecting means composed of NMOS transistors. Therefore, the signal switching means can be easily created.

(7) The plurality of connecting means are constituted by analog switches having an NMOS transistor and a PMOS transistor.

In this configuration, the processor system includes a plurality of connecting means composed of analog switches having NMOS transistors and PMOS transistors. Therefore, when the analog switch is used as the connecting means, the ON resistance value can be made lower than that when only the NMOS transistor is used, which is suitable for high-speed signal transmission.

(8) The plurality of connecting means are fixed in an open / closed state in advance during manufacturing.

In this structure, the processor system is provided with a plurality of connecting means whose open / closed states are fixed in advance during manufacturing. Therefore, since it is not necessary to control the open / closed states of the plurality of connecting means, the second storage means becomes unnecessary,
The present invention can be applied to a case where a signal relationship is fixed and used without exchanging signals, or to a processor system having a small circuit configuration.

(9) The CPU and peripheral function blocks of the CPU are each provided with a clock supply means for supplying a clock signal, and the supply of the clock signal can be stopped.

In this structure, the clock supply means is
A clock signal can be supplied to the CPU and peripheral function blocks of the CPU, and the supply of the clock signal can be stopped. Therefore, if the operation of the CPU is not necessary,
Power supply can be reduced by stopping the clock supply to the peripheral function block only.

[0033]

1 is a block diagram showing a schematic configuration of a processor system according to an embodiment of the present invention. Processor system 1 is the Main System Block (MBLO
CK) (hereinafter referred to as the main system block) 2
, Peripheral Block (PBLOCK) (hereinafter referred to as peripheral function block) 3, and Clock Ge as a clock supply means.
neratator (hereinafter referred to as clock generation circuit) 4
And are equipped with. Main system block 2 is CP
U11, Program Memory (hereinafter referred to as PROM)
12, Data Memory (hereinafter referred to as DRAM) 13
Composed by. The peripheral function block 3 is C
N Peripheral Devic as peripheral devices of PU11
e1 to Peripheral Device n (hereinafter, peripheral device P1 to
It is called a peripheral device Pn. ), Signal switching means
Signal Switch Matrix (hereinafter referred to as SMX) 2
4 and a routing control unit (hereinafter, referred to as RCU) 25 which is a second storage unit that stores control data of the signal switching unit.

The CPU 11 uses a main system bus (hereinafter referred to as MBUS) 14, which is a first bus, to PROM 12, DRAM 13, and peripheral devices P1 to P1.
It is connected to Pn and RCU25.

In the peripheral function block 3, each of the peripheral devices P1 to Pn is a second bus which is a Peripheral Commu
A nication bus (hereinafter, referred to as PCBUS) 30 is used for connection. The PCBUS 30 is an output signal bus that transmits signals output from the peripheral devices P1 to Pn, and a peripheral device P1.
To Pn, which is an input signal bus for transmitting signals input to Pn
And CBUS 32.

An SMX 24 is installed between the PCBUS 31 and the PCBUS 32. In addition, the peripheral devices P1 to Pn respectively include gate circuits P1g to Png, which are contact / separation means for connecting / disconnecting with the PCBUS 30. Further, the SMX 24 and the RCU 25 are connected by a control signal line 33. In addition, RCU
The monitor signal PSTATE is output from 25 to the CPU 11.

From the CPU 11 to the clock generation circuit 4,
The stop signal CGCTRL is output, and the clock generation circuit 4
The main system block 2 is supplied with the clock MCK from the clock generation circuit 4 to the peripheral function block 3
Is supplied with the clock PCK.

Here, each of the peripheral devices P1 to Pn of the peripheral function block inputs and outputs an m-bit signal. Therefore, since there are n peripheral devices, P
CBUS31, PCBUS32, and control signal line 33
Each have mn (= m × n) signal lines.

In the processor system 1, similarly to the conventional processor system 101, the CPU 11 has the MBUS.
The instruction stored in the PROM 12 is read out via 14 to be decoded, and a value is written to or read from each register in the peripheral devices P1 to Pn of the peripheral function block 2. Then, after calculating and processing the data, the data is output to the output device or a storage device such as the DRAM 13.

Next, the PCBS, which is a feature of the present invention, will be described. In the present invention, the peripheral devices P1 to Pn of the peripheral function block 3 are connected to the CPU 1 via the MBUS 14
In addition to being controlled from 1, the peripheral devices in the peripheral function block 3 directly exchange data via the PCBUS 30.

For example, when transmitting data from the peripheral device P1 to the peripheral device P2, the signal output from P1 when the gate circuit P1g is turned on is PCBUS31.
To SMX25. For SMX25, RCU
The open / closed state of the internal connecting means can be switched by a control signal from 24, and a value obtained by arbitrarily replacing the order (bit order) of the input m-bit signals can be output. In addition, as a data transmission destination, the peripheral device P
2 is selected and this signal is sent from SMX25 to PCBUS
Is output to 32. In the peripheral device P2, the gate circuit P
2g is turned on, and the signal output to the PCBUS 32 is input to the peripheral device P2.

The configuration and operation of each unit in the processor system 1 having the above configuration will be described in detail. First, the configuration of the gate circuits P1g to Png for connecting and disconnecting the peripheral devices P1 to Pn and the PCBUS 30 will be described.
FIG. 2 is a block diagram showing a schematic configuration of a gate circuit of a peripheral device. Although only the configuration of the gate circuit P1g of the peripheral device P1 will be described with reference to FIG. 2, the gate circuits P2g to Pn included in the other peripheral devices P2 to Pn will be described.
g has the same configuration.

The gate circuit P1g includes an internal signal output enable register 41 and an external signal input enable register 42 which are first storage means, m transfer gates 43-0 to 43- (m-1), and m transfer gates. The gates 44-0 to 44- (m-1) are provided.

The gate circuit P1g transfers the m-bit internal signal of the peripheral device P1 to another peripheral device by the PCBUS31.
And output signals from other peripheral devices via the PCBUS 32 to the peripheral device P.
It is for inputting into 1.

First, the signal output side of the gate circuit P1g connected to the PCBUS 31 will be described. The transfer gates 43-0 to 43- (m-1) are 3-state buffers, and are connected to the internal signal line of the peripheral device P1 and the PCB.
It is for opening and closing the connection with US31. The transfer gate 43-0 has an internal signal P1 [0] out.
Is input, and this signal is output as the output signal EP1 [0] out. Transfer gates 43-1 to 43-
Similarly, in (m-1), the internal signal P1 [1] out to the internal signal P1 [m-1] out are input, and the external signal EP1 is input.
[1] out to external signal EP1 [m-1] out is output. This output signal EP1 [0] out to external signal EP
1 [m-1] out is SMX via PCB31
25 is output.

The internal signal output enable register 41 is
PC of transfer gates 43-0 to 43- (m-1)
It is for holding (storing) and outputting a control signal for controlling contact and separation with the BUS 31. That is, according to the value held by the internal signal output enable register 41, the control signal EnOUT of the transfer gate 43-0.
Outputs 1 [0]. Similarly, according to the value held by the internal signal output enable register 41, the control signal EnOUT1 of the transfer gates 43-1 to 43- (m-1) is generated.
Output [1] to EnOUT1 [m-1].

The internal signal output enable register 4
1 holds the transfer gates 43-0 to 43- (m
-1) Control signals EnOUT1 [0] to EnOUT1
The value used as [m-1] is C via MBUS14.
It can be rewritten by the signal transmitted from the PU 11.

Next, the signal input side of the gate circuit P1g connected to the PCBUS 32 will be described. The transfer gates 44-0 to 44- (m-1) are three-state buffers for connecting and disconnecting the PCBUS 32 and the internal signal line of the peripheral device P1. An external signal EP1 [0] in is input to the transfer gate 44-0, and this signal is output as an internal signal P1 [0] in. Transfer gates 44-1 to 44- (m-1)
Similarly, the external signal EP1 [1] in to the external signal EP1
[M-1] in is input, and the internal signal P1 [1] in ~
The internal signal P1 [m-1] in is output.

The external signal output enable register 42 is
It is for holding (storing) and outputting a control signal for controlling the opening and closing of the transfer gates 44-0 to 44- (m-1). That is, the external signal output enable register 42 outputs the control signal EnIN1 [0] of the transfer gate 44-0 according to the held value. Similarly, the external signal output enable register 42 transfers the transfer gates 44-1 to 44-in accordance with the held value.
(M-1) control signals EnIN1 [1] to EnIN1
Output [m-1].

The external signal output enable register 4
2 holds the transfer gates 44-0 to 44- (m
-1) Control signals EnIN1 [0] to EnIN1 [m-
The value used as [1] is CPU1 via MBUS14.
It is rewritable by the signal transmitted from 1.

Next, the SMX 24 and RCU 25 will be described. Gate circuit P1g of peripheral devices P1 to Pn
The m-bit parallel signal output from -Png to PCBUS31 is input to SMX24. SMX24
Is for switching the output destination of the signal output from any of the peripheral devices P1 to Pn and converting it into a value in which the bit order of the input signal is arbitrarily exchanged. For example, The configuration is as shown in FIG. Figure 3
It is a circuit diagram showing a schematic structure of SMX24 and RCU25.

The SMX 24 is a P consisting of mn signal lines.
External signal EP1 [0] ou input from CBUS31
mn input signal lines 51- (1,0) to 51- (n, m-1) for transmitting t to EPn [m-1] out.
Is equipped with. Also, a PCBU consisting of mn signal lines
External signal EP1 [0] in to EPn output to S32
It is provided with mn output signal lines 52- (1,0) to 52- (n, m-1) for transmitting [m-1] in. Further, input signal lines 51- (1,0) to 51-
(N, m-1) and output signal lines 52- (1,0) to 52
-(N, m-1) and are arranged in a grid pattern, and m ² n ² contacting / separating means for connecting the signal lines are provided near each intersection. In addition, it is provided with SELECTOR1 [0] to SELECTORn [m-1] for controlling m ² n ² connecting means.

The RCU 25 has SELECTOR1 [0] to SELECTOR
mn for storing the control signal to be transmitted to n [m-1]
Routing Register 1 [0] ~ Routing Register n [m
-1].

In FIG. 3, an NMOS is shown as an example of connecting means.
Transistors T1 [0] [1,0] to Tn [m-1] [n, m
-1] is used. The NMOS transistors T1 [0] [1,0] to Tn [m-1] [n, m-1] are
As shown in FIG. 3, the source is the input signal line 51- (1,
0) to 51- (n, m-1), and the drains thereof are output signal lines 52- (1,0) to 52- (n, m).
-1). The control signal line GP1 [0] [1,0] is provided to the gates of the NMOS transistors T1 [0] [1,0] to T1 [0] [n, m-1], respectively.
To GP1 [0] [n, m-1] are connected. Similarly, the NMOS transistors T1 [1] [1,0] to Tn [m
The control signal lines GP1 [1] [1,0] to GPn [m-1] [n, m-1] are respectively connected to the gates of -1] [n, m-1].
Are connected. Furthermore, the control signal line GP1 [0]
[1,0] to GP1 [0] [n, m-1] are SELECTOR1
It is connected to [0]. Similarly, the control signal line GP1 [1]
[1,0] to GPn [m-1] [n, m-1] are connected to SELECTOR1 [1] to SELECTORn [m-1], respectively.

In addition, Routing Register 1 of RCU25
[0] to Routing Register n [m-1] are SELECT
It is connected to OR1 [0] to SELECTORn [m-1]. Then, each NMOS transistor T1 included in the SMX24
A control signal is output from the RCU 25 to control the opening and closing of [0] [1,0] to Tn [m-1] [n, m-1].

FIG. 4 is a table showing an example of the output signal of the Routing Register. Routing Register 1 [0] ~ Routin
The g Register n [m-1] includes a Peripheral selection register and a connection destination Signal selection register, respectively. The Peripheral selection register is for selecting a peripheral device to be connected, and the Signal selection register is for setting which signal is connected to the selected peripheral device.

As a specific example, the external signal EP1 [0] out
Input signal line 51- (1,0) for transmitting the external signal E
A case where P1 [1] in is connected to the output signal line 52- (1,1) for transmission will be described. Routing Register 1
Peripheral selection register 1 [0] of [0] is the cell SELPeri
, 1 [0], SELPeri1 [1], ..., SELPeri1 [m-1]. As shown in FIG. 4A, the peripheral devices P1 to Pn are set to be selected according to the value of each cell.

The Signal selection register is a cell SELSig.
, [SELSig1 [1], ..., SELSig1 [m-1]. As shown in FIG. 4B, the input signal lines EP1 [0] in to EPn [m-1] in are set to be selected according to the value of each cell.

First, Pe of the setting of Routing Register 1 [0]
The ripheral selection register 1 [0] contains SELPeri1 [0], SELP
Set eri1 [1], ..., SELPeri1 [m-1] = 0,0, ..., 0. In this case, the peripheral device P1 (Peripheral1) is selected. Also, the Signal selection register
SELSig1 [0], SELSig1 [1], ..., SELSig1 [m-1] = 1,
Set 0,0, ..., 0. In this case, the output signal line 52- (1, 2, which transmits the external signal EP1 [1] in as the connection destination
1) shall be selected.

In this state, as shown in FIG. 4C, only the gate signal GP1 [0] [1,1] becomes H, so that the gate is connected to the input signal line 51- (1,0). NMOS transistors T1 [0] [1,0] to T1 [0]
Of [n, m-1], NMOS transistor T1 [0]
[1,1] turns on. Therefore, the input signal line 51- (1,
0) is connected to the output signal line 52- (1,1).

As described above, each input signal line 51-
(1,0) to 51- (n, m-1) are output signal lines 5
It can be connected to any of 2- (1,0) to 52- (n, m-1). Also, PCBUS31 and PC
Since each BUS 32 is composed of mn signal lines, data can be exchanged between a plurality of peripheral devices at the same time.

FIG. 5 is a circuit diagram showing the configuration of another embodiment of the connecting means. The connecting means (switch element) is not limited to the NMOS transistor, and for example, as shown in FIG. 5A, an analog switch having a configuration in which the NMOS transistor 61 and the PMOS transistor 62 are paired is used. good. In this case, an inverter element 63 or the like is connected to the gate of the PMOS transistor 62 to give an inverted signal of the signal given to the gate of the NMOS transistor 61.

When an analog switch is used as the connecting means, the on resistance value can be made lower than that when only an NMOS transistor is used. Therefore, the analog switch is preferable for high-speed signal transmission.

In addition, the gate P of the peripheral devices P1 to Pn
Internal signal output enable register 41, external signal input enable register 42, and RCU provided in 1g to Png.
The 25 Routing Register is connected to the MBUS 14 so that it can be set by the CPU 11 by a program. As a result, the signals exchanged between the peripheral function blocks and their connections can be freely set by the program, and the degree of freedom of the processor system is improved.

When the signal connection is fixed and used, it is not necessary to electrically turn on / off the switch element.
On / off may be connected or disconnected by a physical method. For example, in the case of a semiconductor, as shown in FIG. 5B, if a pattern is used to short-circuit the connection signal with a mask pattern, a fixed connection state can be realized in the manufacturing process. When fixed in this way, NMOS
RCU25 or SELECT to generate the gate signal in
OR1 [0] to SELECTORn [m-1] are not necessary and can be applied to a processor system having a small circuit configuration.

Next, a function and an embodiment for realizing low power consumption will be described with reference to FIGS. Figure 6
FIG. 3 is a circuit diagram showing a schematic configuration of a clock transmission circuit. By providing the PCBUS 31 as described above and providing a system configuration for exchanging signals between peripheral function blocks, the PROM or DRAM required when processing by the CPU is unnecessary or when the CPU executes the program When access to the main system block including the CPU is not necessary, the power consumption can be significantly reduced by stopping the clock supplied to the main system block including the CPU.

To this end, as shown in FIG. 6, the system clock is divided into two and one is input to the 2-input AND gate 71. Also, the other is input to the buffer 73. Further, the 2-input AND gate 71 has a CPU 11
The stop signal CGCTRL is input, and the output signal of the 2-input AND gate 71 is input to the buffer 72. The output signal of the buffer 72 is used as the supply clock MCK for the main system block 2, and the output signal of the buffer 73 is used as the supply clock PCK for the peripheral function block 3. Further, the state of the peripheral function block is monitored by the RCU, and the monitoring signal PSTATE is sent to the CPU 11.

When receiving the PSTATE signal, the CPU 11 sets the stop signal CGCTRL output to the clock generation circuit 4 to the L state to stop the supply clock MCK when the program execution is not required. Supply clock M
CK is A between the system clock and the stop signal CGCTRL
ND output. Therefore, when the stop signal CGCTRL is H, the system clock is transmitted as it is as the supply clock MCK. However, if the stop signal CGCTRL is L
In the case of, the supply clock MCK is fixed to L. Therefore, the supply clock MC to the main system block 2
K is stopped, and the power consumption of the processor system 1 can be reduced.

[0069]

According to the present invention, the following effects can be obtained.

(1) In the processor system, the CPU
And a plurality of devices that form the peripheral function block of the CPU, signals are exchanged via the first bus, and signals are exchanged between the plurality of devices via the second bus. Since internal signals can be exchanged between a plurality of devices in the peripheral function block without going through the first bus, the load on the CPU can be reduced, the instruction processing efficiency can be improved, and the processing of the entire processor system can be speeded up. You can Moreover, since the number of instructions can be reduced, the program memory capacity can be reduced.

(2) Since the plurality of devices are provided with the contacting / separating means capable of contacting / separating with the second bus, the transmission / reception of the signal in the device which does not need the signal exchange can be blocked, and the signal is transmitted by the noise. It is possible to prevent erroneous output.

(3) The plurality of devices constituting the peripheral function block are provided with the first storage means for storing the control data of the contacting / separating means, which is rewritable from the CPU via the first bus. As a result, it becomes possible to specify a device for exchanging data in the peripheral function block and freely set a signal for exchanging signals by a program, and the degree of freedom of the processor system can be improved.

(4) The processor system is provided with an output signal bus having a plurality of signal lines for transmitting signals output from a plurality of devices and a plurality of signal lines for transmitting signals input to the plurality of devices. Between the input signal bus and
Since a signal switching means having a plurality of connecting means for selecting a device to be connected and a signal for transmitting a plurality of signal lines is exchanged, it is possible to exchange signals and exchange signals between a plurality of devices. It can be implemented reliably.

(5) Since the control data stored in the second storage unit included in the processor system and included in the signal switching unit and stored in the plurality of connecting units can be rewritten from the CPU via the first bus, the peripheral function block is provided. It is possible to specify the device to exchange data with and to set the signal to exchange freely by the program, and the degree of freedom of the processor system can be improved.

(6) Since the processor system is provided with a plurality of connecting means composed of NMOS transistors, the signal switching means can be easily created.

(7) NMOS transistor and PMOS
Since the processor system is provided with a plurality of connecting means composed of analog switches having transistors, the on resistance value is lower when the analog switches are used as the connecting means than when only the NMOS transistor is used. can do.

(8) Since the processor system is provided with a plurality of connecting means whose open / closed states are fixed at the time of manufacture, it is not necessary to control the open / closed states of the plurality of connecting means. It becomes unnecessary and can be applied to the case where the relationship of signals is fixed and used without exchanging the signals, or to a processor system having a small circuit configuration.

(9) The clock supply means is a CPU and C
A clock signal can be supplied to each peripheral function block of the PU, and the supply of the clock signal can be stopped.
When the operation of U is unnecessary, the power supply can be reduced by stopping the clock supply to the CPU and supplying it to only the peripheral function block.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a processor system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a gate circuit of a peripheral device.

FIG. 3 is a circuit diagram showing a schematic configuration of SMX24 and RCU25.

FIG. 4 is a table showing an example of an output signal of a Routing Register.

FIG. 5 is a circuit diagram showing the configuration of another embodiment of the connecting means.

FIG. 6 is a circuit diagram showing a schematic configuration of a clock transmission circuit.

FIG. 7 is a block diagram showing a schematic configuration of a conventional processor system.

[Explanation of symbols]

1-processor system 2-Main system block 3-Peripheral function block 14-First Bus (MBUS) 24-Signal switching means (SMX) 30-second bus (PCBUS) 31-Output signal bus (PCBUS) 32-Input signal bus (PCBUS) P1-Pn-Peripheral devices P1g to Png-gate circuit

Claims (9)

[Claims] 1. A processor system for exchanging signals between a CPU and a plurality of devices constituting a peripheral function block of the CPU via a first bus, and exchanging signals between the plurality of devices. Second to do
A processor system having a bus of. 2. The processor system according to claim 1, wherein each of the plurality of devices includes a contact / separation unit that can connect / disconnect with the second bus. 3. A plurality of devices forming the peripheral function block each include first storage means for storing control data of the contacting / separating means, and the control data is stored in the first storage means.
The processor system according to claim 1 or 2, wherein the CPU system can be rewritten via the bus. 4. The output signal bus having a plurality of signal lines for transmitting signals output from the plurality of devices, and the plurality of signals for transmitting signals input to the plurality of devices. And an input signal bus having a line, and a plurality of connection means for interchanging signals transmitted through the plurality of signal lines and selecting a connection destination device between the output signal bus and the input signal bus. 4. The processor system according to claim 1, further comprising a signal switching unit having the. 5. A second storage unit for storing control data of a plurality of connection units included in the signal switching unit, the control data being rewritable from the CPU via the first bus. The processor system according to any one of claims 1 to 4, wherein: 6. The processor system according to claim 4, wherein the plurality of connecting units are NMOS transistors. 7. The processor system according to claim 4, wherein the plurality of connection units are analog switches each having an NMOS transistor and a PMOS transistor. 8. The processor system according to claim 4, wherein the plurality of connecting means have their open / closed states fixed in advance during manufacture. 9. The processor according to claim 1, wherein the CPU and peripheral function blocks of the CPU are provided with clock supply means for supplying a clock signal, respectively, and the supply of the clock signal can be stopped. system.