JP2003060615A - Ofdm receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale for an OFDM receiver used for a receiver for digital broadcast that adopts an OFDM modulation system. SOLUTION: One Viterbi demodulation circuit 48 is provided corresponding to three hierarchies, and at the same time a TS(transport stream) reproduction circuit 52 is provided so that transport stream reproduction processing can be made after the Viterbi demodulation processing due to the Viterbi demodulation processing 48.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to OFDM (Orthog
OFD used in a receiver for digital broadcasting adopting an onal frequency division multiplexing method
M receiver.

Unlike satellite broadcasting, terrestrial broadcasting is susceptible to reflected waves from buildings and other structures. Therefore, in Japan and Europe, an OFDM modulation method that is strong against multipath is adopted as a modulation method for terrestrial digital broadcasting. A major feature of digital terrestrial broadcasting in Japan is that the frequency band of one channel is divided into 13 segments, and the segments are further divided into 3 layers to enable layered transmission in which different transport streams can be transmitted in each layer. is there.

[0003]

2. Description of the Related Art FIG. 5 is a block circuit diagram showing an example of a transmission path coding unit of a conventionally proposed OFDM transmitter for digital terrestrial broadcasting. In FIG. 5, 1 is a TS that multiplexes three types of transport streams TSA, TSB, and TSC of the MPEG2 system in which one packet has 188 bytes into one transport stream having one byte having 204 bytes and including null bytes. The remultiplexing circuit 2 is an RS encoding circuit that performs RS (Reed Solomon) encoding processing on the transport stream output from the TS remultiplexing circuit 1.

Reference numeral 3 is a layer dividing circuit for dividing the transport stream output from the RS encoding circuit 2 into three layers, and 4A, 4B, and 4C are energies for averaging the frequency spectrums of the transport streams of the respective layers. Energy diffusion circuits 5A, 5B, 5 for performing diffusion processing
C is a byte interleave circuit that performs interleave processing on a byte-by-byte basis for the transport streams output from the energy diffusion circuits 4A, 4B, and 4C.

Reference numerals 6A, 6B and 6C are convolutional encoding circuits for performing convolutional encoding processing on the transport streams output by the byte interleaving circuits 5A, 5B and 5C, and 7A, 7B and 7C are convolutional encoding circuits 6A and 6C.
The puncture circuits 8A, 8B, and 8C that create a transport stream having a higher coding rate by erasing a part of the coded bits from the transport stream output by the B and 6C are puncture circuits 7A and 7C.
It is a bit interleave circuit that performs interleave processing on a bit-by-bit basis for the transport streams output by B and 7C.

Reference numerals 9A, 9B and 9C are mapping circuits for performing mapping processing for modulating a transport stream output from the bit interleaving circuits 8A, 8B and 8C into carriers for OFDM modulation, and 10 is a mapping circuit 9A, 9B, 9C. Is a hierarchical synthesizing circuit for hierarchically synthesizing the transport streams of the three hierarchical layers output by, and 11 is a time interleaving circuit for performing interleaving processing in the time direction on the transport streams output by the hierarchical synthesizing circuit 10.

Reference numeral 12 is a frequency interleave circuit for performing interleave processing in the frequency direction on the transport stream output from the time interleave circuit 11.
3 is an OFDM frame configuration circuit for converting the transport stream output from the frequency interleave circuit 12 into an OFDM frame configuration bit stream, and 14 is O
An IFFT (Inverse Fast Fouri) is used to inverse fast Fourier transform the bit stream of the OFDM frame structure output from the FDM frame structure circuit 13 to form a transmission signal on the time axis.
er Transform) circuit.

[0008] Table 1 shows the transmission parameters, OFD
The transmission band of an M frame is divided into 13 segments, and each segment has 108 in MODE1 and MO in MO.
It is composed of 216 carriers in DE2 and 432 carriers in MODE3. Further, 13 segments are 1 OFDM symbol, and 204 symbols are 1 OFDM frame.

[0009]

[Table 1]

FIG. 6 is a block circuit diagram showing an example of a transmission line decoding unit of a conventionally proposed OFDM receiver for digital terrestrial broadcasting. In FIG. 6, reference numeral 15 is an FFT (Fast Fourier Transform) circuit that demodulates a received signal on the time axis, which has been channel-selected and frequency-converted and digitally converted, into a signal on the frequency axis, and 16 is an FFT.
For the output signal of the circuit 15, differential demodulation is performed for the DQPSK modulated signal, and the QPSK modulated signal, 16QAM
This is a differential demodulation / synchronous demodulation circuit that performs synchronous demodulation for the modulated signal and the 64QAM modulated signal.

Reference numeral 17 is a frequency deinterleave circuit for performing deinterleaving processing in the frequency direction on the bit stream output from the differential demodulation / synchronization demodulation circuit 16. Reference numeral 18 is deinterleaving in the time direction for the bit stream output from the frequency deinterleave circuit 17. A time deinterleave circuit that performs processing, 19 is a layer division circuit that divides the bitstream output by the time deinterleave circuit 18 into three layers, and 20A, 20B, and 20C are demapping processing that performs demapping processing on the bitstream of each layer. It is a mapping circuit.

Reference numerals 21A, 21B and 21C denote bit deinterleave circuits for performing deinterleave processing on a bit-by-bit basis for the bitstreams output by the demapping circuits 20A, 20B and 20C, and 22A, 22B and 22C are bit deinterleave circuits 21A, 21B and 21C. Depuncture circuits 23A, 23B, and 23C that perform depuncture processing on the bit stream output by 21C are hierarchical buffers that store the data of the bit streams output by the depuncture circuits 22A, 22B, and 22C.

Reference numeral 24 is a hierarchical buffer 23A, 23B, 23.
Selectors for selecting and outputting bit stream data accumulated in C, 25 and 26 TS buffers for accumulating data for one transport packet, 27 and 28
Is a null TSP circuit for generating a null packet, 29 is a TS
A selector for selecting and outputting either the transport packet accumulated in the buffer 25 or the null packet generated by the null TSP circuit 27, and 30 is the TS buffer 26
Is a selector for selecting and outputting either the transport packet accumulated in 1) or the null packet generated by the null TSP circuit 28, and 31 is a selector for selecting and outputting either of the outputs of the selectors 29 and 30.

Here, the selector 24 is the hierarchical buffer 2
When one transport packet worth of data is stored in any of 3A, 23B, and 23C, the data is selected and transferred to the TS buffer of the TS buffers 25 and 26 in which no data is stored. TS buffer 25,
At 26, the data from the TS buffer accumulating the preceding data is read. Therefore, when the data is read from the TS buffer 25, the selector 29 selects and outputs the data read from the TS buffer 25, and when there is no more data in the TS buffer 25, the null TSP circuit 27 The null packet to be output is selected and output, and the null packet is added to the data output from the TS buffer 25.

The selector 30 has a TS buffer 26.
When data is read from the TS buffer 26
When the TS buffer 26 has no data, the null packet output by the null TSP circuit 28 is selected and output, and the TS
A null packet is added to the data output from the buffer 26. Further, the selector 31 selects the selectors 29 and 30 and outputs the transport packet to which the null packet is added. In this way, the transport stream is reproduced from the bit stream having the OFDM frame structure.

Reference numeral 32 is a layer dividing circuit for dividing the transport stream output from the selector 31 into three layers, and 33.
A, 33B, and 33C are Viterbi decoding circuits that perform Viterbi decoding processing on transport streams of respective layers, and 34.
A, 34B and 34C are Viterbi decoding circuits 33A and 33B,
It is a byte deinterleave circuit that performs deinterleave processing in byte units on the transport stream output by the 33C.

35A, 35B and 35C are energy despreading circuits for carrying out energy despreading processing on the transport streams output from the byte deinterleave circuits 34A, 34B and 34C, and 36 is output from the energy despreading circuits 35A, 35B and 35C. A hierarchical synthesizing circuit for hierarchically synthesizing the transport stream, 37 performs RS decoding processing on the hierarchically synthesized transport stream output from the hierarchical synthesizing circuit, and reproduces the transport stream re-multiplexed by the transmitting device. It is an RS decoding circuit for outputting.

[0018]

In the conventional receiving apparatus having the channel decoding unit shown in FIG. 6, it is supposed that the transport stream is reproduced from the bit stream having the OFDM frame structure before the Viterbi decoding process. Buffers 23A, 23B, 23C and TS buffer 25,
However, since the data before the Viterbi decoding processing includes redundant information necessary for error correction by Viterbi decoding, the hierarchical buffers 23A, 23B, and 23C are required.
And TS buffers 25 and 26 require buffers having a large memory capacity and three Viterbi decoding circuits 3
Since 3A, 33B and 33C are provided, there is a problem that the circuit scale becomes large.

In view of the above points, the present invention has as its object the provision of an OFDM receiver capable of reducing the circuit scale.

[0020]

The OFDM receiver of the present invention is provided with one Viterbi decoding circuit corresponding to each layer, and is capable of performing a transport stream reproduction process after the Viterbi decoding process by this Viterbi decoding circuit. A transport stream reproduction circuit is provided so that it can be performed.

According to the present invention, since the transport stream reproduction processing is performed after the Viterbi decoding processing, the transport stream is reproduced from the bit stream of the OFDM structure that does not include the redundant information necessary for error correction by Viterbi decoding. can do. Therefore, a buffer having a large memory capacity is not required as a buffer for reproducing the transport stream.

[0022]

FIG. 1 is a block circuit diagram showing a configuration of a transmission line decoding unit included in an embodiment of the present invention.
An embodiment of the present invention includes the transmission path decoding unit shown in FIG. 1, and the other parts are configured in a conventionally known manner.

In FIG. 1, reference numeral 38 denotes an FFT circuit for demodulating a received signal on the time axis, which has been selected, frequency-converted and digitally converted, into a signal on the frequency axis by fast Fourier transform, 3
Reference numeral 9 denotes the output signal of the FFT circuit 38, and the DQPSK modulated signal is subjected to differential demodulation to obtain a QPSK modulated signal,
This is a differential demodulation / synchronous demodulation circuit that performs synchronous demodulation for 16QAM modulated signals and 64QAM modulated signals.

Reference numeral 40 denotes a frequency deinterleave circuit for performing deinterleaving processing in the frequency direction on the bit stream output by the differential demodulation / synchronization demodulation circuit 39, and 41 deinterleaving in the time direction for the bit stream output by the frequency deinterleave circuit 40. A time deinterleave circuit that performs processing, and 42 is a layer division circuit that divides the bit stream output by the time deinterleave circuit 41 into three layers.

Reference numerals 43A, 43B and 43C denote demapping circuits for performing demapping processing on bit streams of respective layers, and 44A, 44B and 44C demapping circuit 4.
3A, 43B, and 43C perform deinterleaving processing on a bit-stream basis for the bitstreams, and 45A, 45B, and 45C perform depuncture processing on the bitstreams output by the bit deinterleaving circuits 44A, 44B, and 44C. Circuit.

Reference numeral 46 indicates a TMCC (Transmission and Transmission) from the bit stream output by the differential demodulation / synchronization demodulation circuit 39.
Multiplexing Configuration Control) A modulation method, a convolutional coding rate, a TMCC decoding circuit that extracts the number of used segments, 47 is a modulation method, a convolutional coding rate, and the number of used segments that are extracted by the TMCC decoding circuit 46. Then, it is an intra-symbol packet number calculation circuit for calculating the number of packets of each layer generated in the received symbol.

The arithmetic expression of the number of packets T _n of each layer generated in the received symbol is as shown in Expression 1. However,
S is the number of segments used by the layer (0 to 13), M
Is a value determined by the modulation method (“6” for 64QAM, “4” for 16QAM, QPSK and DQ).
In the case of PSK, “2”), R is the convolutional coding rate (1 /
2, 2/3, 3/4, 5/6, 7/8), T _n-1 is the remainder in the previous symbol.

[0028]

[Equation 1]

Reference numeral 48 is a depuncture circuit 45A, 45.
Viterbi decoding circuits for performing Viterbi decoding processing on the bit streams of the respective layers output by B and 45C, 49A and 49A
B and 49C are byte deinterleave circuits for performing deinterleave processing in byte units on the bit streams of the respective layers output from the Viterbi decoding circuit 48, and 50A and 50.
B and 50C are byte deinterleave circuits 49A and 49
This is an energy despreading circuit that performs energy despreading processing on the bit streams output by B and 49C.

Reference numeral 51 is an energy despreading circuit 50A, 50.
B and 50C are hierarchical synthesis circuits for hierarchically synthesizing three hierarchical bitstreams, and 52 is a TS for reproducing a transport stream in transport packet units from the OFDM-configured bitstream output by the hierarchical synthesis circuit 51. A reproduction circuit 53 is an RS decoding circuit that performs RS decoding processing on the transport stream output from the TS reproduction circuit 52 and reproduces and outputs the transport stream re-multiplexed by the transmission device.

FIG. 2 is a block circuit diagram showing the configuration of the Viterbi decoding circuit 48. In FIG. 2, reference numeral 54 is a control circuit, 55 is a selector which is controlled by the control circuit 54 to select and output either input data (data output by any of the depuncture circuits 45A, 45B, 45C) or dummy data. 56 is a branch metric circuit that calculates a branch metric; 57 is an ACS (Add Compare Select) circuit that calculates a path metric that is a cumulative value of branch metrics to each state and selects a surviving path; and 58 is a Viterbi decoding candidate. Path memory that stores only the required number of stages,
Reference numeral 59 is a traceback circuit that searches for the longest surviving path based on the contents of the path memory 58.

Numerals 60A, 60B and 60C are ACS circuits 57.
Is provided for the register, 61 is the control circuit 5
The selectors 62A, 62B, and 62C controlled by 4 select one of the registers 60A, 60B, and 60C, and 62A, 62B, and 62C are provided corresponding to the path memory 58.
3 is controlled by the control circuit 54 and registers 62A, 62
Selector for selecting either B or 62C, 64A,
64B and 64C are registers provided corresponding to the traceback circuit 59, and 65 is a selector controlled by the control circuit 54 to select one of the registers 64A, 64B, and 64C.

The registers 60A, 62A and 64A are provided for saving the data remaining in the ACS circuit 57, the path memory 58 and the traceback circuit 59 when the Viterbi decoding of the bit stream output by the depuncture circuit 45A is completed. Register 60A, 6
The data saved in the 2A and 64A are again subjected to the Viterbi decoding for the bit stream output by the depuncture circuit 45A, when the ACS circuit 57 and the path memory 5 are used.
8, set in the traceback circuit 59.

The registers 60B, 62B and 64B are used to save the data remaining in the ACS circuit 57, the path memory 58 and the traceback circuit 59 when the Viterbi decoding of the bit stream output by the depuncture circuit 45B is completed. Register 60B, 6
The data saved in 2B and 64B are again subjected to the Viterbi decoding for the bit stream output by the depuncture circuit 45B, the ACS circuit 57, the path memory 5
8, set in the traceback circuit 59.

The registers 60C, 62C and 64C are for saving the data remaining in the ACS circuit 57, the path memory 58 and the traceback circuit 59 when the Viterbi decoding of the bit stream output by the depuncture circuit 45C is completed. Register 60C, 6
The data saved in the 2C and 64C are again subjected to Viterbi decoding with respect to the bit stream output by the depuncture circuit 45C, and the ACS circuit 57 and the path memory 5
8, set in the traceback circuit 59.

The control circuit 54 inputs the information on the number of packets calculated by the intra-symbol packet number calculation circuit 47, counts the number of input packets of the layer under the Viterbi decoding process,
Until the last packet of the layer under the Viterbi decoding process is input, the selector 55 is made to input the data of the layer under the Viterbi decoding process.

Then, the control circuit 54, when the last packet of the layer under the Viterbi decoding process is input, the frequency deinterleave circuit 40 and the time deinterleave circuit 4.
1, hierarchy division circuit 42, demapping circuits 43A, 43
B, 43C, bit deinterleave circuits 44A, 44
B, 44C and depuncture circuits 45A, 45B, 4
5C, an operation stop instruction signal is output to temporarily stop the decoding operation before the Viterbi decoding process, and the selector 5
5 causes the dummy data to be selected.

After that, when the Viterbi decoding of the layer under the Viterbi decoding process is completed, the control circuit 54 transfers the data remaining in the ACS circuit 57, the path memory 58, and the traceback circuit 59 to the registers 60A to 60A. 60C, 62A
To 62C and 64A to 64C, the data is saved in a corresponding register, and when the Viterbi decoding process is performed again for the bit stream of the same layer, these data are stored in the ACS.
The circuit 57, the path memory 58, and the traceback circuit 59 are restored.

FIG. 3 is a block circuit diagram showing the structure of the TS reproducing circuit 52. In FIG. 3, 66 is a memory control circuit, 6
7 is a TS reproduction memory, 68 is a null packet generation circuit, 6
A selector 9 selects and outputs either the transport packet output from the TS reproduction memory 67 or the null packet output from the null packet generation circuit 68,
70 is a write pointer register, 71 is a read pointer register, 72 is a hierarchy information register, and 73 is a model receiver.

FIG. 4 is a diagram showing the structure of the TS reproduction memory 67, the write pointer register 70, the read pointer register 71, and the hierarchy information register 72. The TS reproduction memory 67 manages the transport stream in 204 bytes (1 packet unit), and is divided into a plurality of blocks in packet units.

The write pointer register 70 is currently
It indicates which block is being written. The read pointer register 71 indicates a readable block. The layer information register 72 is linked to the read pointer register 71 and indicates which layer the transport packets stored in the readable block belong to.

The model receiver 73 simulates the operation of the model receiver by an arithmetic circuit, and determines which layer of the transport packet or the null packet is output to the memory control circuit 66. It is an instruction.

Here, when writing the data of the transport packet in the TS reproduction memory 67, the flag of the write pointer register 70 is referred to search for a writable block. Once the writable block is decided,
The writable flag is inverted and writing to the TS reproduction memory 67 is started. When the writing for one packet is completed, the block number and the layer information for which the writing for one packet is completed are written as a readable block and its layer information in the portion indicated by the write pointer of the read pointer register 71, and the write pointer Is incremented.

When reading the data of the transport packet from the TS reproduction memory 67, the reading is started from the block stored in the register indicated by the read pointer of the read pointer register 71. When the reading of one packet is completed, the writable flag of the block is inverted and the read pointer is incremented. Reading from the TS reproduction memory 67 is performed while simulating the operation of the model receiver 73.
If there is no transport stream to be read from the reproduction memory 67, a null packet is inserted.

As described above, according to the present embodiment, since the TS reproduction processing is performed after the Viterbi decoding processing, the TS reproduction circuit 52 does not include the redundant information necessary for error correction by Viterbi decoding. A transport stream can be played back from the constituent bitstreams. As a result, since a large capacity memory is not required as the TS reproduction memory 67, it is possible to significantly reduce the memory amount. Further, as the Viterbi decoding circuit, one Viterbi decoding circuit 48 is provided so as to correspond to all layers. Therefore, the circuit scale can be reduced.

[0046]

As described above, according to the present invention, since the transport stream reproduction processing is performed after the Viterbi decoding processing, redundant information necessary for error correction by Viterbi decoding is not included. Since the transport stream can be reproduced from the bit stream having the OFDM structure, it is possible to significantly reduce the memory amount, and as a Viterbi decoding circuit, one Viterbi decoding circuit is provided for all layers. Because
The circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of a transmission line decoding unit included in an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a configuration of a Viterbi decoding circuit included in an embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a configuration of a TS (transport stream) reproducing circuit included in an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a TS (transport stream) reproduction memory, a write pointer register, a read pointer register, and a hierarchical register included in an embodiment of the present invention.

FIG. 5 is a block circuit diagram showing an example of a transmission path coding unit of a conventionally proposed OFDM transmitter for digital terrestrial broadcasting.

FIG. 6 is a block circuit diagram showing an example of a channel decoding unit of a conventionally proposed OFDM receiver for digital terrestrial broadcasting.

[Explanation of symbols]

TSA, TSB, TSC ... Transport stream

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideo Owada             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F term (reference) 5J065 AA01 AB01 AC02 AD10 AE06                       AF03 AG06 AH06 AH23                 5K014 AA01 BA11 HA10                 5K022 DD01 DD33                 5K028 AA07 BB04 CC05 DD01 DD02                       KK32 RR04

Claims (3)

[Claims] 1. A single Viterbi decoding circuit is provided corresponding to each layer, and a transport stream reproducing circuit is provided so that the transport stream reproducing process can be performed after the Viterbi decoding process by the Viterbi decoding circuit. A characteristic OFDM receiver. 2. The Viterbi decoding circuit is provided with a function of saving the data of the layer remaining in the Viterbi decoding circuit when the Viterbi decoding of the layer under the Viterbi decoding process is completed. The OFDM receiver according to claim 1. 3. A function of temporarily stopping the decoding operation before the Viterbi decoding process and inputting dummy data to the Viterbi decoding circuit when the last packet of the layer under the Viterbi decoding process is input to the Viterbi decoding circuit. The OFDM receiver according to claim 2, further comprising: