JP2009147682A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reception performance by effectively utilizing a holding means for deinterleaving in a receiver for receiving broadcasting using a hierarchical transmission system. <P>SOLUTION: The receiver 10 comprises: a modulation demapping circuit 30 for generating determination value data by determining the amplitude or phase of a received signal; a time deinterleaving circuit including a holding means for holding determination value data to rearrange the determination value data; and a data distribution circuit for holding determination value data of a first bit number representing a determination value in a deinterleaving holding means in accordance with each bit of symbol data when broadcasting by a first modulation system is received, and holding determination value data of a second bit number (>first bit number) representing a determination value in the deinterleaving holding means in accordance with each bit of the symbol data when broadcasting using a second modulation system in which the number of bits of the symbol data is small is received. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a receiving apparatus for receiving broadcasts using a hierarchical transmission system that is allowed to use different modulation systems depending on layers, such as terrestrial digital audio broadcasting.

  In recent years, terrestrial digital audio broadcasting using a hierarchical transmission system has been developed. The hierarchical transmission scheme is a transmission scheme that simultaneously transmits a plurality of layers having different transmission formats such as a modulation scheme. In digital terrestrial audio broadcasting, QPSK or DQPSK, which has excellent error rate characteristics, is used as a modulation method when the state of the transmission line is poor, and 16QAM or 64QAM with high transmission efficiency when the state of the transmission line is good. Is used.

  In consideration of transmitting not only audio data but also simple moving image data, two transmission formats called a 1-segment format and a 3-segment format are defined. A segment is a basic band of a transmission signal, and is defined as (6/14) MHz (about 430 kHz) in terrestrial digital audio broadcasting. The 3-segment format is a transmission format having a data transmission capacity three times that of the 1-segment format, and is for providing a higher-quality broadcasting service.

  For example, in the three-segment format, data in the A layer can be transmitted using one segment, and data in the B layer can be transmitted using two segments. At that time, it is also possible to use the QPSK modulation method in the A layer and use the 16QAM modulation method in the B layer. Further, in order to change the transmission capacity and change the quality of service, it is possible to dynamically change the 16QAM modulation scheme to the QPSK modulation scheme in the B layer.

  In the receiving apparatus, since a deinterleaving holding unit having a scale corresponding to a modulation scheme (for example, 16QAM modulation scheme) having a large transmission rate and a large number of symbol data bits is mounted, the bit of symbol data is reduced in transmission rate. When a broadcast based on a small number of modulation schemes (for example, QPSK modulation scheme) is received, a part of the deinterleaving holding means is not used.

  In many cases, the scale of the deinterleaving holding means is very large. For example, in terrestrial digital audio broadcasting of transmission mode 3 and time interleaving length 4, when symbol data by the QPSK modulation method is interleaved, its hard decision In order to perform the deinterleave processing on the value (2 bits), deinterleaving holding means for 145,920 bits per segment is required. Further, when the interleave processing is performed on the symbol data by the 16QAM modulation method, deinterleaving holding for 291 and 840 bits per segment is performed in order to perform the deinterleaving processing on the hard decision value (4 bits). Means are needed. However, when such a receiving apparatus receives a broadcast by the QPSK modulation method, deinterleaving holding means for 291, 840-145, 920 = 145, 920 bits is wasted.

As a related technique, Patent Document 1 discloses a hierarchical transmission method and its transmission / reception apparatus. In the conventional hierarchical transmission system, when interleaving hierarchical transmission signals, interleaving is performed for each symbol using a common interleaving circuit for each hierarchy, so that only a constant interleave distance can be obtained regardless of the hierarchy. There wasn't. According to Patent Document 1, in a hierarchical transmission method using a plurality of hierarchies having different multilevel levels, an interleave distance of a hierarchy having a lower multilevel level is set to a hierarchy having a higher multilevel level. The feature is that the interleaving process is commonly performed for each layer. As a result, it is possible to reduce the influence of noise in the transmission path or reduce the memory scale while using a common interleave circuit. However, in order to change the interleave distance, it is necessary to deal with both the transmission side and the reception side, and it is not possible to deal with only the reception side.
Japanese Patent Laid-Open No. 10-107865 (second page, page 4, FIG. 1)

  Therefore, in view of the above points, the present invention provides a deinterleaving apparatus for receiving a broadcast by a hierarchical transmission scheme that is allowed to use a modulation scheme that differs depending on the hierarchy, such as terrestrial digital audio broadcasting. It is an object to improve the reception performance by effectively using the holding means.

  In order to solve the above problem, a receiving apparatus according to one aspect of the present invention includes a first modulation scheme and a second modulation scheme in which symbol data having a smaller number of bits than in the first modulation scheme is used. A modulation demapping circuit for receiving a broadcast in which a plurality of types of modulation schemes are selectively used, and generating decision value data by determining amplitude and / or phase represented by a received signal And a time deinterleave circuit for rearranging the judgment value data, and corresponding to each bit of the symbol data when a broadcast by the first modulation method is received. Then, the decision value data of the first number of bits representing the hard decision value or the soft decision value generated by the modulation demapping circuit is supplied to the time deinterleave circuit. A second that represents a hard decision value or a soft decision value generated by the modulation demapping circuit in correspondence with each bit of the symbol data when the second modulation method broadcast is received. And a data distribution circuit for supplying determination value data of the number of bits (second bit number> first bit number) to the time deinterleave circuit and holding the data in the holding means.

  Here, the receiving device receives a broadcast that selectively uses a plurality of types of modulation schemes and generates a reception signal, and a frequency signal is generated as necessary for the reception signal generated by the reception circuit. A frequency deinterleaving circuit that performs interleaving processing and supplies time-series received signals to the modulation demapping circuit may be further included.

  In addition, the receiving device, based on the determination value data output from the time deinterleave circuit, each generates a parallel data corresponding to the modulation scheme, and each parallel data generated by the data multiplexing circuit A parallel / serial converter that outputs determination value data of a predetermined number of bits for the symbol, and a decoder that performs error correction on the determination value data output from the parallel / serial converter by maximum likelihood sequence estimation You may make it comprise.

  In the above, the holding means may include a number of buffer columns corresponding to the number of determination value data for one segment for each of a predetermined number of segments.

  In addition, when the data distribution circuit is receiving a broadcast by the 16QAM modulation method, the decision value data representing the 1-bit hard decision value is supplied to the time deinterleave circuit and held in the holding means, and the broadcast by the QPSK modulation method is performed. , The decision value data representing the 2-bit soft decision value may be supplied to the time deinterleave circuit and held in the holding means.

  According to the present invention, when the broadcast by the first modulation method is received, the determination value data of the first number of bits corresponding to each bit of the symbol data is supplied to the time deinterleave circuit and is held. The second number of bits corresponding to each bit of the symbol data when a broadcast by the second modulation method in which symbol data having a smaller number of bits than in the first modulation method is used is received By supplying the determination value data of (> first number of bits) to the time deinterleave circuit and holding it in the holding means, it is possible to improve the reception performance by effectively utilizing the holding means for deinterleaving.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a receiving apparatus according to an embodiment of the present invention. This receiving apparatus includes a receiving circuit 10, a frequency deinterleave circuit 20, a modulation demapping circuit 30, a data distribution circuit 40, time deinterleave circuits 51 to 53, a data multiplexing circuit 60, and a P / S (parallel). / Serial) converter 70 and a 2-bit Viterbi decoder 80.

  The receiving circuit 10 uses an antenna 10a to receive a broadcast in which a plurality of types of modulation methods are selectively used, such as terrestrial digital audio broadcasting, and extracts a modulated wave to perform an FFT (Fast Fourier Transform) process. As a result, a frequency-sequence received signal is generated and output to the frequency deinterleave circuit 20. The frequency deinterleave circuit 20 performs frequency deinterleave processing on the frequency sequence reception signal generated by the reception circuit 10 as necessary, and outputs a reception signal (I + jQ). For example, the bit widths of the data I and Q are each 10 bits.

  FIG. 2 is a diagram showing the relationship between hierarchical data and transmission spectrum used in terrestrial digital audio broadcasting. In terrestrial digital audio broadcasting, two transmission formats called a 1-segment format and a 3-segment format are defined. A segment is a basic band of a transmission signal, and is defined as (6/14) MHz (about 430 kHz) in terrestrial digital audio broadcasting.

  As shown in FIG. 2A, only the A layer data is transmitted in the one segment format. On the other hand, as shown in FIG. 2 (b), the 3-segment format is a transmission format having a data transmission capacity three times that of the 1-segment format, and two-layer data transmission of A-layer data and B-layer data is possible. It has become. In the 3-segment format, frequency interleaving processing is applied to the A layer data and the B layer data.

  FIG. 3 is a diagram showing an example of frequency band allocation to broadcasters in terrestrial digital audio broadcasting. In FIG. 3, a frequency band for one segment is assigned to each of broadcasters A to E, and a frequency band for three segments is assigned to broadcaster F. The broadcaster F to which the frequency band for 3 segments is assigned can dynamically switch between the 1-segment format and the 3-segment format. For example, in the case of broadcasting of only audio, the 1-segment format is selected. In the case of broadcasting of audio and simple video, the 3-segment format is selected. Therefore, in a receiving apparatus that receives terrestrial digital audio broadcasting, it is necessary to switch the receiving operation between the 1-segment format and the 3-segment format.

  In terrestrial digital audio broadcasting, processing of convolutional coding and bit interleaving, modulation mapping, time interleaving, and frequency interleaving is included as part of the prescribed transmission method.

  FIG. 4 is a diagram illustrating an example of a convolutional encoding circuit that performs a convolutional encoding process defined in terrestrial digital audio broadcasting. This convolutional coding circuit is composed of a 1-bit storage element 1 such as a D flip-flop, and an EOR gate 2 for obtaining an exclusive OR of two input data. Input data is input bit by bit to the input terminal, and one set of output data is output from the X output terminal and the Y output terminal.

  FIG. 5 is a diagram showing an example of input data and output data in the convolutional encoding circuit shown in FIG. When the initial data in all the memory elements 1 is set to zero, as shown in FIG. 4, the bit sequence of the input data IN is input to the convolutional encoding circuit, the convolutional encoding is performed, and the bit sequence of the output data X And a bit sequence of the output data Y is output. Here, 1-bit output data X and 1-bit output data Y form 2-bit output data OUT (XY).

  As described above, in convolutional coding, redundancy is added by dispersing input bits and superimposing them on neighboring bits separated by a constraint length. As a result, even when an error occurs in a certain output bit, since the information of the bit is included in the neighboring bits of the bit, the error can be corrected in the receiving apparatus. However, since the information of a certain output bit is included only in the neighboring bits of the bit, the error correction capability is reduced when a burst-like error occurs in the transmission path. In order to prevent this, a bit interleave circuit that replaces the order of bits in the data output from the convolutional coding circuit in accordance with a predetermined rule is provided at the subsequent stage of the convolutional coding circuit.

  Data output from the bit interleave circuit is subjected to modulation mapping processing by the modulation circuit. QPSK, DQPSK, 16QAM, and 64QAM are used as modulation schemes in terrestrial digital audio broadcasting. Here, QPSK modulation mapping and 16QAM modulation mapping will be described as an example.

  FIG. 6 is a diagram illustrating amplitude and phase information in QPSK modulation mapping. In FIG. 6, the I axis represents a real number and the Q axis represents an imaginary number. In QPSK modulation mapping, data output from the bit interleave circuit is parallelized into 2 bits, and four types of phases are obtained according to the values of parallel data (B0, B1). FIG. 7 is a diagram illustrating an example of input data and output data in QPSK modulation mapping. The modulation circuit generates output data (symbol data) OUT (I + jQ) representing a complex number in accordance with the value of parallel data (B0, B1) obtained by parallelizing 2-bit input data IN.

  FIG. 8 is a diagram illustrating amplitude and phase information in 16QAM modulation mapping. In FIG. 8, the I axis represents a real number, and the Q axis represents an imaginary number. In 16QAM modulation mapping, data output from the bit interleave circuit is parallelized to 4 bits, and 16 types of amplitudes and phases are obtained according to the values of parallel data (B0, B1, B2, B3). FIG. 9 is a diagram illustrating an example of input data and output data in QPSK modulation mapping. The modulation circuit generates output data (symbol data) OUT (I + jQ) representing a complex number according to the value of parallel data (B0, B1, B2, B3) obtained by parallelizing the 4-bit input data IN.

  The symbol data output from the modulation circuit is input to the time interleave circuit. Here, a convolutional interleaving scheme used in time interleaving for terrestrial digital audio broadcasting will be described.

  FIG. 10 is a diagram conceptually showing time interleaving processing used in terrestrial digital audio broadcasting. The symbol data subjected to the modulation mapping process is input to the time interleave circuit with one segment of data as one unit. In terrestrial digital audio broadcasting, 384 symbol data constitute one segment.

  The time interleave circuit includes 384 symbol buffer columns (holding means such as a FIFO memory and shift register for holding symbol data) having different numbers of stages, and the symbol data input to the time interleave circuit is a clock signal. Synchronously with this, the data is sequentially written to the first stage of the symbol buffer columns of the first column to the 384th column. In each symbol buffer column, the symbol data input to the first stage is shifted by one stage toward the last stage in synchronization with the clock signal. Then, the symbol data is sequentially read from the last stage of the first to 384th symbol buffer columns in synchronization with the clock signal.

  That is, on the writing side, the symbol buffer string is switched every time one symbol is written, and on the reading side, the symbol buffer string is switched every time one symbol is read. At this time, since the number of stages is different in the 384 symbol buffer columns, the symbol data is rearranged.

  Specifically, 4 × m (i) stage symbol buffers are included in the (i + 1) th symbol buffer column (i = 0, 1, 2,..., 383). Here, m (i) = (i × 5) mod 96, that is, m (i) is a remainder obtained by dividing (i × 5) by 96. For example, since m (0) = 0 mod 96 = 0, the first symbol buffer string includes a 0-stage symbol buffer (direct input / output connection), and m (1) = 5 mod 96 = 5. The second symbol buffer column includes 20 symbol buffers.

  The symbol data output from the time interleave circuit is input to the frequency interleave circuit, subjected to frequency interleave processing, and then transmitted on a carrier wave by the transmission circuit.

  As described above, the convolutional coding and bit interleaving, modulation mapping, time interleaving, and frequency interleaving are performed in this order on the transmission side. The received signal can be decoded by performing a process of deinterleaving, time deinterleaving, modulation demapping, and Viterbi decoding.

  However, if the modulation demapping process is performed before the time deinterleaving process, the number of bits of data per symbol is reduced, and the scale of the holding means used for the time deinterleaving process can be reduced. it can. Therefore, a decoding method in which the order of the time deinterleaving process and the modulation demapping process is switched is more general. The present invention is applied to such a decoding scheme.

  Referring to FIG. 1 again, the modulation demapping circuit 30 performs modulation demapping processing on the received signal (I + jQ) input from the frequency deinterleave circuit 20. FIG. 11 is a diagram for explaining the demapping process of the QPSK modulation signal in the receiving apparatus shown in FIG. The modulation demapping process is an operation for generating a bit set of decision value data corresponding to symbol data based on a reception signal representing a complex number. In the QPSK modulation signal demapping process, as shown in FIG. The determination value data of 2 bits (1 bit for each of B0 and B1) representing the identification point closest to the input received signal is generated. For example, the received signal located in the first quadrant of FIG. 11 is quantized to 2-bit decision value data (B0, B1) = (0, 0), and the received signal located in the second quadrant of FIG. It is quantized to 2-bit decision value data (B0, B1) = (1, 0). Such a determination value is called a hard determination value.

  On the other hand, as shown in FIG. 12, a soft decision value representing one or a plurality of identification points close to the input received signal may be used. In FIG. 12, for example, “00” representing the data B1 represents a high likelihood that the value of the data B1 is “0”, and “01” representing the data B1 represents that the value of the data B1 is “ The likelihood that “0” is the first largest and the likelihood that the value of the data B1 is “1” is the second largest. Such a determination value is called a soft determination value.

  By using the soft decision value, error correction capability is improved in the subsequent Viterbi decoding process. As the 2-bit soft decision value, decision value data of 4 bits (2 bits for each of B0 and B1) representing one or a plurality of identification points close to the input reception signal is generated as shown in FIG. The As the 3-bit soft decision value, decision value data of 6 bits (3 bits for each of B0 and B1) is generated. The hard decision value is equivalent to a soft decision value having a 1-bit width.

  FIG. 13 is a diagram for explaining demapping processing of a 16QAM modulated signal in the receiving apparatus shown in FIG. The modulation demapping process is an operation for generating a bit set of decision value data corresponding to symbol data based on a reception signal representing a complex number. In the demapping process of a 16QAM modulated signal, as shown in FIG. The determination value data of 4 bits (1 bit for each of B0 to B3) representing the identification point closest to the input reception signal is generated. For example, the received signal located at the upper right in FIG. 13 is quantized into 4-bit decision value data (B0, B1, B2, B3) = (0, 0, 0, 0) and located at the upper left in FIG. The received signal is quantized into 4-bit decision value data (B0, B1, B2, B3) = (1, 0, 0, 0). Such a determination value is called a hard determination value.

  On the other hand, you may make it use the soft decision value showing the 1 or several identification point close | similar to the input received signal. By using the soft decision value, error correction capability is improved in the subsequent Viterbi decoding process. As the 2-bit soft decision value, decision value data of 8 bits (2 bits for each of B0 to B3) representing one or a plurality of identification points close to the input reception signal is generated. As the 3-bit soft decision value, decision value data of 12 bits (3 bits for each of B0 to B3) is generated.

  In the demapping process of the 64QAM modulated signal, 6-bit (1 bit for each of B0 to B5) determination value data is generated as the hard decision value, and 12 bits (B0 to B5 each) as the 2-bit soft decision value. Judgment value data of 2 bits) is generated, and 18-bit (3 bits for each of B0 to B5) judgment value data is generated as a 3-bit soft decision value.

  In this embodiment, when receiving a broadcast by the QPSK modulation method, the modulation demapping circuit 30 generates a hard decision value or a 2-bit soft decision value, and when receiving a broadcast by the 16QAM modulation method, the modulation is performed. The demapping circuit 30 generates a 2-bit soft decision value.

  FIG. 14 is a diagram illustrating a format of output data of the modulation demapping circuit. Here, it is assumed that a 2-bit soft decision value is used in the demapping process of the QPSK modulation signal or the 16QAM modulation signal. The modulation demapping circuit 30 outputs determination value data for one symbol as 8-bit data D [7: 0]. Here, [n: m] means data of bit numbers n to m. In this embodiment, in general, the bit number of the least significant bit is set to “0”, and the bit number is incremented toward the upper bit.

  As shown in FIG. 14, in the QPSK modulation signal demapping process, the modulation demapping circuit 30 performs determination value data B0 to B1 (the hard decision value is 2 bits, the 2-bit soft decision value is 2 × 2 = 4 bits). ) And the remaining data is zero, and 8-bit data D [7: 0] is output. On the other hand, in the demapping process of the 16QAM modulated signal, the modulation demapping circuit 30 generates determination value data B0 to B3 (the hard decision value is 4 bits, the 2-bit soft decision value is 4 × 2 = 8 bits), Output as 8-bit data D [7: 0].

  FIG. 15 is a timing chart showing input data and output data of the data distribution circuit. Here, a case where a three-segment broadcast is received will be described. The data D [7: 0] of the three segments S0 to S2 are sequentially input from the modulation demapping circuit 30 to the data distribution circuit 40. Each segment contains 384 symbols. Of the three segments S0 to S2, the segment S0 is an A-layer QPSK modulated signal, and the segments S1 and S2 are B-layer 16QAM modulated signals.

  When the demodulating process of the QPSK modulation signal is performed, the data distribution circuit 40 distributes the data D [5, 4, 1, 0] of the segment S0 to the time deinterleave circuit 51 and performs the demodulating process of the 16QAM modulation signal. In this case, the data D [3: 0] of the segment S1 is distributed to the time deinterleave circuit 52, and the data D [3: 0] of the segment S2 is distributed to the time deinterleave circuit 53. As a result, the time deinterleave circuit 51 is used to perform the deinterleave processing of the 2-bit soft decision value of the A-layer QPSK modulation signal, and the time deinterleave circuits 52 and 53 perform the hard-decoding of the B-layer 16QAM modulation signal. It is used to perform deinterleaving processing of the judgment value.

  FIG. 16 is a diagram conceptually showing time deinterleaving processing in the receiving apparatus shown in FIG. Each of the time deinterleave circuits 51 to 53 includes 384 decision value buffer strings (a FIFO memory, a shift register, etc. that hold decision values) having different numbers of stages, and is inputted to the time deinterleave circuit. The value data is sequentially written in the first stage of the determination value buffer columns of the first column to the 384th column in synchronization with the clock signal. In each decision value buffer train, the soft decision value input to the first stage is shifted by one stage toward the last stage in synchronization with the clock signal. Then, determination value data is sequentially read from the final stage of the determination value buffer columns of the first column to the 384th column in synchronization with the clock signal.

  That is, on the writing side, the judgment value buffer string is switched every time one judgment value data is written, and on the reading side, the judgment value buffer string is switched every time one judgment value data is read. At this time, since the number of stages in the 384 determination value buffer columns is different from each other, the determination value data is rearranged.

  Specifically, the determination value buffer column of the (i + 1) th column includes 4 × (95−m (i)) determination value buffers (i = 0, 1, 2,..., 383). Here, m (i) = (i × 5) mod 96, that is, m (i) is a remainder obtained by dividing (i × 5) by 96. For example, since m (0) = 0 mod 96 = 0, the determination value buffer string of the first column includes a determination value buffer of 380 stages, and m (1) = 5 mod 96 = 5. The determination value buffer column of the column includes 360 determination value buffers. In addition, since m (383) = 1915 mod 96 = 91, the determination value buffer string of the 384th column includes 16 levels of determination value buffers.

  Thus, in each of the time deinterleave circuits 51 to 53, when the delay amount in the 384 determination value buffer sequences is added to the delay amount added by the time interleaving process, the end of each determination value buffer sequence. The decision value data is delayed so as to be equal to each other at the stage output points. Since the maximum value of the delay amount added by the time interleaving process described above is 4 × 95 = 380 symbols, a delay amount of 4 × (95−m (i)) stages is given in the time deinterleaving process. .

  In the present embodiment, the time deinterleave circuits 51 to 53 shown in FIG. 1 determine the determination value of the 16QAM modulated signal of a predetermined number of segments in order to support both QPSK modulation and 16QAM modulation. A holding means for holding data is included. The holding means includes, for each of a predetermined number of segments, a number of determination value buffer sequences corresponding to the number of determination value data for one segment.

  FIG. 17 is a diagram illustrating a usage pattern of the deinterleaving holding unit in the receiving apparatus according to the embodiment of the present invention. Here, a case where a three-segment broadcast is received will be described. (A) of FIG. 17 shows a usage pattern of the deinterleaving holding means when receiving a broadcast including a 16QAM modulated signal of A layer and a 16QAM modulated signal of B layer (B layer 1 and B layer 2). In order to make a hard decision of the 16QAM modulation signal in the A layer and the B layer, the holding capacity of the decision value buffer string in the holding area for one segment is 291 and 840 bits. On the other hand, (b) of FIG. 17 shows a usage form of the de-interleaving holding means when receiving a broadcast including a QPSK modulated signal of A layer and a 16QAM modulated signal of B layer (B layer 1 and B layer 2). As shown, since the 2-bit soft decision of the QPSK modulation signal is performed in the A layer, all the holding capacities of 291 and 840 bits of the decision value buffer string in the holding area for one segment are used effectively.

  In the case of receiving a QPSK modulation signal of the A layer in a receiving apparatus that supports both 16QAM modulation system broadcasting and QPSK modulation system broadcasting, conventionally, only half of the time deinterleave circuit 51 is used. The other half of the time deinterleave circuit 51 was unused. On the other hand, according to the present invention, the error correction capability in the 2-bit Viterbi decoder 80 is improved by effectively utilizing the time deinterleave circuit 51 and holding the decision value data used for soft decision of the QPSK modulation signal. be able to. In general, in soft decision, it is effective to use a soft decision value of 2 to 6 bits.

  The data multiplexing circuit 60 shown in FIG. 1 generates parallel data corresponding to the modulation method based on the determination value data output from the time deinterleave circuits 51 to 53. FIG. 18 is a diagram showing a format of parallel data output from the data multiplexing circuit shown in FIG. The data multiplexing circuit 60 generates parallel data D [7: 0] including decision value data B0 to B1 (soft decision, 2 bits each) in the demodulation process of the QPSK modulation signal, and in the demodulation process of the 16QAM modulation signal. Parallel data D [7: 0] including determination value data B0 to B3 (hard determination, 1 bit each) is generated. Here, by generating parallel data D [3: 0] and D [7: 4] based on the input 1-bit hard decision value, the hard decision value “0” is formally set to the soft decision value “ The hard decision value “1” is formally converted into the soft decision value “11”.

  FIG. 19 is a timing chart showing input data and output data of the P / S converter shown in FIG. The P / S converter 70 (FIG. 1) uses the decision value data B0 to B1 (in the demodulation process of the QPSK modulation signal based on the 8-bit parallel data D [7: 0] output from the data multiplexing circuit 60. 2 bits), and in the demodulation process of the 16QAM modulated signal, determination value data B0 to B3 (each 2 bits) are generated and output to the 2-bit Viterbi decoder 80.

  The 2-bit Viterbi decoder 80 (FIG. 1) can always make soft decisions formally. The 2-bit Viterbi decoder 80 performs error correction by soft decision on the decision value data output from the P / S converter 70, thereby regenerating bit data before convolutional coding on the transmission side. The Viterbi decoder applies the Viterbi algorithm to the maximum likelihood sequence estimator that performs error correction by maximum likelihood sequence estimation, enabling a significant reduction in the amount of computation, and is generally used for decoding convolutional codes. ing.

  In the embodiment of the present invention, the reception apparatus that supports both the broadcasting by the 16QAM modulation system and the broadcasting by the QPSK modulation system has been described. However, the present invention is not limited to this, and there are a plurality of types of modulation systems. The present invention can be applied to a receiving device that receives a broadcast to be used. In general, in a hierarchical transmission system (i> j) using both a first modulation system with a high transmission rate and symbol data of i bits and a second modulation system with a low transmission rate and symbol data of j bits (i> j), When receiving a broadcast according to the first modulation method, the receiving device according to the above stores hard decision value data or m-bit soft decision value data in the deinterleaving holding means, and receives the broadcast according to the second modulation method. At this time, the n-bit soft decision value data is stored in the deinterleave holding means (m <n).

  In the present invention, as a modulation method, a general multi-level modulation method such as an 8PSK modulation method or a 256QAM modulation method can be used in addition to the 16QAM modulation method and the QPSK modulation method. In addition to the convolutional deinterleaving method, a block deinterleaving method or the like can be used as the time deinterleaving method.

The block diagram which shows the structure of the receiver which concerns on one Embodiment of this invention. The figure showing the relationship between the hierarchical data and transmission spectrum of terrestrial digital audio broadcasting. The figure which shows the example of the allocation of the frequency band in terrestrial digital audio broadcasting. The figure which shows the example of the convolutional encoding circuit in terrestrial digital audio broadcasting. FIG. 5 is a diagram showing an example of input data and output data of the convolutional encoding circuit shown in FIG. 4. The figure showing the amplitude and phase information in QPSK modulation mapping. The figure which shows the example of the input data in QPSK modulation mapping, and output data. The figure showing the amplitude and phase information in 16QAM modulation mapping. The figure which shows the example of the input data in QPSK modulation mapping, and output data. The figure which shows the time interleave process in terrestrial digital audio broadcasting. The figure explaining the demapping process of the QPSK modulation signal in a receiver. The figure explaining the demapping process of the QPSK modulation signal in a receiver. The figure explaining the demapping process of 16QAM modulation signal in a receiver. The figure which shows the format of the output data of a modulation demapping circuit. The timing chart which shows the input data and output data of a data distribution circuit. The figure which shows notionally the time deinterleaving process in the receiver shown in FIG. The figure which shows the usage condition of the time deinterleave circuit in one Embodiment. The figure which shows the format of the judgment value data output from a data multiplexing circuit. The timing chart which shows the input data and output data of a P / S converter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Receiving circuit, 10a Antenna, 20 Frequency deinterleaving circuit, 30 Modulation demapping circuit, 40 Data distribution circuit, 51-53 Time deinterleaving circuit, 60 Data multiplexing circuit, 70 P / S converter, 80 2-bit Viterbi decoder

Claims (5)

Reception for receiving a broadcast in which a plurality of types of modulation schemes are selectively used, including a first modulation scheme and a second modulation scheme in which symbol data having a smaller number of bits than in the first modulation scheme is used. A device,
A modulation demapping circuit that generates decision value data by determining the amplitude and / or phase represented by the received signal;
A time deinterleave circuit that includes a holding unit that holds the determination value data, and in which the determination value data is rearranged;
Determination of a first number of bits representing a hard decision value or a soft decision value generated by the modulation demapping circuit corresponding to each bit of symbol data when a broadcast by the first modulation method is received The value data is supplied to the time deinterleave circuit and held in the holding means, and when the broadcast by the second modulation method is received, the modulation demapping circuit corresponds to each bit of the symbol data. Determination value data of a second bit number (second bit number> first bit number) representing the generated hard decision value or soft decision value is supplied to the time deinterleave circuit and held in the holding unit. A data distribution circuit;
A receiving apparatus comprising: A receiving circuit that receives a broadcast in which a plurality of types of modulation methods are selectively used and generates a received signal;
A frequency deinterleave circuit that performs frequency deinterleave processing on the reception signal generated by the reception circuit as necessary, and supplies a time-series reception signal to the modulation demapping circuit;
The receiving device according to claim 1, further comprising: A data multiplexing circuit that generates parallel data according to a modulation method based on determination value data output from the time deinterleave circuit;
A parallel / serial converter that outputs determination value data of a predetermined number of bits for each symbol based on parallel data generated by the data multiplexing circuit;
A decoder that performs error correction by maximum likelihood sequence estimation on the decision value data output from the parallel / serial converter;
The receiving device according to claim 1, further comprising:   The receiving apparatus according to claim 1, wherein the holding unit includes a number of buffer strings corresponding to the number of determination value data for one segment for each of the predetermined number of segments.   When the data distribution circuit receives a broadcast by a 16QAM modulation method, the data distribution circuit supplies decision value data representing a 1-bit hard decision value to the time deinterleave circuit and holds the decision value data in the holding unit. 5. The receiving device according to claim 1, wherein determination value data representing a 2-bit soft decision value is supplied to the time deinterleave circuit and held by the holding unit when receiving a broadcast. .

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