JP2002077095A - Ofdm demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an OFDM demodulator that reduces a required capacity of a memory so as to be able to decrease the circuit scale. SOLUTION: Storage means 2, 3 respectively store I, Q data obtained by applying orthogonal demodulation to a received signal by an orthogonal demodulation section 1. A 1st supply means 4 reads prescribed data stored in the storage means 2, 3 and gives the data to an FFT circuit 6. A 2nd supply means 5 reads prescribed data stored in the storage means 2, 3 and gives the data to a synchronous demodulation circuit 7. The synchronous demodulation circuit 7 specifies start timing of FFT by synchronous demodulation. The FFT circuit 6 applies an FFT arithmetic operation to the data supplied from the 1st supply means 4 on the basis of the timing specified by the synchronous demodulation circuit 7 and outputs the obtained result as output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an OFDM demodulator, and more particularly to an OFDM demodulator which receives and demodulates an OFDM-modulated signal.

[0002]

2. Description of the Related Art OFDM (Orthogonal Digital Television Broadcasting)
ISDB-T using the Frequency Division Multiplex (orthogonal multiplexing) technique is ARIB (Association
ation of Radio Industries and Businesses).

[0003] This OFDM system is a type of multi-carrier modulation system, in which coded data (information symbols) subjected to serial / parallel conversion is allocated to a number of subcarriers orthogonal to each other between adjacent cells, and an inverse fast Fourier transform IFFT (Invert) is used.
After the signals are collectively converted into a time-domain signal by Fast Fourier Transform, an OFDM signal is generated by quadrature modulation and transmitted.

Since the OFDM system is a multi-carrier system, it is possible to set a modulation system for each carrier. For example, according to the bit rate of data to be transmitted, DQPSK, QPSK, 16QAM,
64QAM or the like can be set.

[0005] ISDB-T employs a system (segment structure) in which a 6 MHz frequency band of the UHF band is divided into bands called 13 segments. With this method, it is possible to set the modulation method for each segment,
The feature is that hierarchical modulation of up to three layers can be performed.

FIG. 11 is a diagram showing a configuration example of a conventional ISDB-T model receiving apparatus. As shown in this figure,
The model receiving device includes a synchronous demodulation unit 20 and an FEC unit 2
1 and 22.

The synchronous demodulation unit 20 includes a quadrature demodulation unit 20a, a frequency / clock synchronization unit 20b, an FFT 20c, and a detection unit 2.
0d, the OFDM frame decoding unit 20e, and T
It is constituted by an MCC signal section 20f.

[0008] The FEC unit 21 includes a frequency deinterleave unit 21a, a time deinterleave unit 21b, and a modulation division unit 21.
c, a QPSK demapping unit 21d, a 16QAM demapping unit 21e, a 64QAM demapping unit 21f, and a modulation and synthesis unit 21g.

The FEC unit 22 includes a hierarchy division unit 22a, bit deinterleaving units 22b to 22d, depuncturing units 22e to 22g, a hierarchy synthesis unit 22h, and a Viterbi decoding unit 2.
2i, hierarchical division unit 22j, byte deinterleave unit 22
k to 22m, energy spreading units 22n to 22p, null packet unit 22q, TS reproducing unit 22r, and outer coding unit 22s.

FIG. 12 is a diagram showing a detailed configuration example of the synchronous demodulation unit 20 shown in FIG. As shown in this figure, the synchronous demodulation unit 20 includes a quadrature demodulation unit 20a, a complex multiplier 30,
It is composed of an FFT circuit 31 and a synchronous demodulation circuit 32.

The FFT circuit 31 has an input buffer 31a,
31b, operation memory 31c, butterfly operation circuit 31
d, output buffers 31e and 31f. Further, the synchronous demodulation circuit 32 includes delay units 32a, 32
b, correlation sections 32c and 32d, FFT start detection section 32
e, a frequency error detection circuit 32f.

The orthogonal demodulation unit 20a orthogonally demodulates the received OFDM signal and outputs an I signal and a Q signal. The complex multiplier 30 removes a frequency error due to a tuner, a frequency error at the time of quadrature demodulation, and a clock sampling error, which are included in the I signal and the Q signal, according to a detection result of the frequency error detection circuit 32f.

The FFT circuit 31 performs a fast Fourier transform on the I signal and the Q signal from which the error has been removed, and performs a conversion into code information. The input buffers 31a and 31b constituting the FFT circuit 31 temporarily store the data input from the complex multiplier 30, read out the data in a predetermined order, and supply it to the butterfly operation circuit 31d.

The operation memory 31c temporarily stores data during the operation when the butterfly operation circuit 31d performs the operation. The butterfly operation circuit 31d performs a Fourier transform by performing a butterfly operation on the data supplied from the input buffers 31a and 31b, and outputs the data.

The output buffers 31e and 31f temporarily store the data output from the butterfly operation circuit 31d, rearrange the data in the original order, and output the data. Further, delay units 32a and 32b constituting the synchronous demodulation circuit 32
Outputs the data output from the complex multiplier 30 with a delay.

The correlation units 32c and 32d are provided with delay units 32a and 32d.
A correlation value between the data delayed by 32b and the data output from the complex multiplier 30 is calculated and output. F
The FT start detection unit 32e refers to the outputs from the correlation units 32c and 32d, and sets the time point having the highest correlation value as the start timing of the FFT and sets the input buffers 31a and 31d.
Notify b.

The frequency error detection circuit 32f includes a correlation unit 32
The frequency error is detected by referring to the correlation values output from c and 32d, and is notified to the complex multiplier 30. FIG. 13 (A)
Shows an example of the OFDM I signal. As shown in this figure, the OFDM signal is configured by copying the end portion of the effective symbol to the head portion, the portion copied at the head portion is called a guard interval, and the guard interval is defined as The included effective symbol is called one symbol period. Therefore, the guard interval is detected by calculating the correlation value (see FIG. 13C) with the delay signal (the signal delayed by the delay unit 32a) shown in FIG. 13B, and the head of the effective symbol is detected. can do. The head of the guard interval detected in this manner is located at the start position of the FFT circuit (FIG. 13).
(See (D)). As described above, the guard interval is inserted in the OFDM system, so that the OFDM system is strong against multipath peculiar to terrestrial waves.

FIG. 14 is a diagram showing a detailed configuration example of a part of the detection and FEC section 21 of the synchronous demodulation section 20 shown in FIG. As shown in the figure, the detection of the synchronous demodulation unit 20 and a part of the FEC unit 21 are performed by an FFT output buffer 50,
A complex division circuit 51, a one-symbol previous memory buffer 52,
Differential demodulation memory buffer 53, frequency deinterleaving section 54, time deinterleaving section 55, QPSK demapping section 56, 16QAM demapping section 57, and 64QAM
It is constituted by a demapping section 58.

The FFT output buffer 50 is provided for the FFT circuit 3
1 represents the same as the output buffers 31e and 31f. The complex division circuit 51 performs complex division on the data supplied from the FFT output buffer 50 by the data of one symbol before supplied from the one symbol previous memory buffer 52, and outputs the result.

The one-symbol previous memory buffer 52 includes an FF
The data output from the T output buffer 50 is output after being delayed by one symbol. The differential demodulation memory buffer 53 temporarily stores the data subjected to the differential demodulation,
The signal is supplied to the frequency deinterleave unit 54.

The frequency deinterleaving unit 54 restores (deinterleaves) the carrier arrangement on the transmitting side in order to prevent a specific frequency carrier from disappearing when a multipath occurs. Execute the process.

The time deinterleaving section 55 executes processing for restoring the interleaving performed on the time axis. The QPSK demapping unit 56 performs a QPSK demapping process. The 16QAM demapping section 57
Execute the demapping process. 64QAM demapping section 58
Performs a 64QAM demapping process.

[0023]

By the way, the delay unit 32
a, 32b, to generate a delayed signal,
A buffer for storing data for the symbol period is required.

In the FFT circuit 31, the complex multiplier 3
Input buffers 31a and 31 for storing input signals from 0
b, an operation memory 31c for storing data during the operation of the butterfly operation circuit 31d and output buffers 31e and 31f for storing the results of the butterfly operation are required.

Further, in the FEC unit 21 shown in FIG.
There is no particular problem in synchronous modulation such as PSK or QAM. However, in the case of differential modulation such as DQPSK, the difference between the previous symbol and the current symbol is used as a modulation element. Must be held for the effective carriers (1405 in the case of mode 1). In addition, wide-band frequency synchronization is performed using differentially demodulated data. Even in the case of a segment configuration including synchronous modulation, it is necessary to hold differential data of an effective carrier (13 segments).

As described above, the synchronous demodulation circuit 32 and the FF
In each of the T circuits 31, it is necessary to provide a buffer memory for one symbol, and it is necessary to provide an output buffer and a memory for differential demodulation of the FFT circuit 31 for effective carriers. Thus, there is a problem that the circuit scale is increased, and it is difficult to implement an LSI.

The present invention has been made in view of the above points, and has as its object to provide an OFDM demodulator capable of reducing the circuit size by reducing the required memory capacity. .

[0028]

According to the present invention, in order to solve the above-mentioned problems, in an OFDM demodulator shown in FIG. 1 for receiving and demodulating a signal subjected to OFDM modulation, a received signal is demodulated by a quadrature demodulator 1. Storage means 2 and 3 for respectively storing I and Q data obtained as a result of quadrature demodulation by
First supply means 4 for reading predetermined data stored in storage means 2 and 3 and supplying the same to FFT circuit 6, and reading predetermined data stored in storage means 2 and 3;
An OFDM demodulator having second supply means 5 for supplying to the synchronous demodulation circuit 7 is provided.

Here, the storage means 2 and 3 respectively store I and Q data obtained as a result of orthogonal demodulation of the received signal by the orthogonal demodulation unit 1. The first supply unit 4 reads out predetermined data stored in the storage units 2 and 3, and
It is supplied to the FT circuit 6. The second supply unit 5 reads out predetermined data stored in the storage units 2 and 3 and supplies the data to the synchronous demodulation circuit 7.

Also, in an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a first storage means for storing output data from an FFT circuit and a second storage means for storing output data from an FFT circuit. Storage means and FF
Writing means for alternately writing output data from the T circuit into the first or second storage means, and predetermined data stored in the first or second storage means, which are alternately read out to the subsequent circuit And a reading means for supplying the OFDM demodulator.

Here, the first storage means stores output data from the FFT circuit. The second storage means is FFT
Stores output data from the circuit. The writing means is F
Output data from the FT circuit is alternately written to the first or second storage means. The reading means comprises a first or a second
Is alternately read out and supplied to a subsequent circuit.

Further, in an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a DQPSK demapping process is performed on the data subjected to differential demodulation.
QPSK demapping processing means, storage means for storing data subjected to DQPSK processing, and supply means for reading data stored in the storage means and supplying the data to a subsequent frequency deinterleave circuit. OFD
An M demodulator is provided.

Here, the DQPSK demapping processing means
DQPSK demapping is performed on the data that has been subjected to differential demodulation. The storage unit stores the data on which the DQPSK processing has been performed. The supply means reads out the data stored in the storage means and supplies the data to a subsequent frequency deinterleave circuit.

Further, in an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a demapping unit for demapping data subjected to frequency deinterleaving, and a demapping process performed by the demapping unit. And a time deinterleaving means for performing time deinterleaving on the decoded data.

Here, the demapping means demaps the frequency-deinterleaved data. The time deinterleaving means performs time deinterleaving on the data demapped by the demapping processing means.

Also, in an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, FFT processing means for performing FFT processing on the received data;
If an overflow or underflow occurs during the operation of the processing, a counting means for counting the number of occurrences of the overflow or underflow, and if the count result of the counting means exceeds a predetermined value, the input data of the FFT processing means is An OFDM demodulator, comprising: level adjusting means for adjusting a level.

Here, the FFT processing means performs FFT processing on the received data. The counting means is FFT
If an overflow or an underflow occurs in the operation of the processing, the number of occurrences is counted. The level adjusting means adjusts the level of the input data of the FFT processing means when the count result of the counting means exceeds a predetermined value.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the OFDM demodulator according to the present invention. As shown in the figure, an OFDM demodulator according to the present invention includes a quadrature demodulator 1, storage units 2, 3, a first supply unit 4, a second supply unit 5, an FFT circuit 6, and a synchronous demodulation circuit. 7.

Here, the quadrature demodulation section 1 outputs an I signal and a Q signal by performing quadrature demodulation on the received signal. The storage means 2 and 3 store the I and Q data obtained as a result of the quadrature demodulation, respectively.

The first supply means 4 reads out predetermined data stored in the storage means 2, 3 and supplies it to the FFT circuit 6. The second supply unit 5 reads out predetermined data stored in the storage units 2 and 3 and supplies the data to the synchronous demodulation circuit 7.

The FFT circuit 6 performs FFT processing on the data supplied from the first supply means 4, and outputs the obtained result as code information. The synchronous demodulation circuit 7
By calculating the correlation value between the data supplied from the supply means 5 and the data one symbol before, the timing of the FFT operation is specified and the FFT circuit 6 is notified.

Next, the operation of the above principle diagram will be described. When receiving data is input, the quadrature demodulation unit 1 performs quadrature demodulation processing and outputs I data and Q data.

The storage units 2 and 3 store the I data and Q data output from the quadrature demodulation unit 1, respectively. The first supply unit 4 reads out predetermined data stored in the storage units 2 and 3 and supplies the data to the FFT circuit 6. At this time, for example, assuming that one I signal and one Q signal are respectively stored in the storage units 2 and 3 from the quadrature demodulation unit 1, the first supply unit 4 transmits the six signals from the storage units 2 and 3 respectively. The data is read and supplied to the FFT circuit 6.

The second supply means 5 includes storage means 2,
3 is read and supplied to the synchronous demodulation circuit 7. At this time, for example, each of the I signal and the Q signal from the
3, the second supply means 5 reads out one data each from the storage means 2 and 3 and supplies the data to the synchronous demodulation circuit 7.

That is, the first supply means 4 and the second supply means 5 multiplex read operations from the storage means 2 and 3, so that the FFT circuit 6 and the synchronous demodulation circuit 7 have The storage means to be possessed can be shared, and as a result, the capacity of the storage means (buffer memory) can be reduced.

As described above, the OFD according to the present invention
According to the M demodulator, the reading of data from the buffer memory is multiplexed, and the required buffer memory is shared by the FFT circuit 6 and the synchronous demodulation circuit 7, so that the required buffer memory capacity can be reduced. It becomes possible. As a result, the OFDM demodulator can be easily formed into an LSI.

Next, according to the first embodiment of the present invention, O
The FDM demodulation circuit will be described. FIG. 2 is a diagram illustrating a configuration example of the first embodiment of the present invention. In this figure, the parts corresponding to those in FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

In the example of this figure, as compared with the case of FIG. 12, the input buffers 31a, 31b and the delay units 32a,
32b is omitted, and instead, buffer memories 35 and 36 integrating these are newly added. Also,
Memory control circuit 3 for controlling buffer memories 35 and 36
7 is newly added. Otherwise, it is the same as the case of FIG.

Here, the buffer memories 35 and 36 store the I data and Q data output from the complex multiplier 30, respectively. Further, under the control of the memory control circuit 37, predetermined data is read and supplied to the FFT circuit 31 and the synchronous demodulation circuit 32.

The memory control circuit 37 includes a buffer memory 3
Read the data stored in 5, 36 and FFT
The signals are supplied to a circuit 31 and a synchronous demodulation circuit 32, respectively.
Next, the operation of the above embodiment will be described.

The quadrature demodulation unit 20a outputs I data and Q data by inputting the received signal and performing quadrature demodulation. The complex multiplier 30 includes a frequency error detection circuit 32f
I data and Q according to the frequency error detected by
Eliminates frequency errors and clock sampling errors at the time of tuner and quadrature demodulation that data has.

The I data and Q data output from the complex multiplier 30 are supplied to buffer memories 35 and 36, where they are sequentially stored. Buffer memories 35, 36
Is read out in a predetermined order,
It is sequentially supplied to a T circuit 31 and a synchronous demodulation circuit 32.
FIG. 3 is a diagram showing how data is read from and written to the buffer memories 35 and 36. FIG. 3A is a diagram illustrating a state of input I data input from the complex multiplier 30 to the buffer memory 35. As shown in FIG.
Data is read at a period of 8 MHz.

FIG. 3B is a diagram showing a state of conventional memory control. As shown in this figure, conventionally, data is read from the input buffer 31a at a half cycle of the input data, that is, at a cycle of 16 MHz, and then written to the delay unit 32a.

As shown in FIG. 3C, in this embodiment, data is read or written at a cycle of 1/8 of the input data, that is, at a cycle of 64 MHz. First, in the first one cycle, the data of one symbol before is read from the buffer memory 35 as in the conventional memory control.
2c. Then, in the second cycle, data newly output from the complex multiplier 30 is written to a predetermined area of the buffer memory 35. Reading and writing to and from the buffer memory 35 is performed as shown in FIG.
The current data is written over the data before the symbol. In this example, the current data is D
However, since the data D0 is one symbol before in the area to be written, the data D0 is read and then the current data D2048 is written.

In the synchronous demodulation circuit 32, the correlation sections 32c, 3
By 2d, a correlation value between the current data output from the complex multiplier 30 and the data one symbol before output from the buffer memories 35 and 36 is calculated, and the frequency error detection circuit 32f, the memory control circuit 37 Supplied to

The frequency error detection circuit 32f includes a correlation unit 32
With reference to the correlation values supplied from c and 32d, a frequency error is calculated and supplied to the complex multiplier 30. Further, the memory control circuit 37 starts the FFT operation on the data stored in the buffer memories 35 and 36 at the timing when the correlation value reaches a peak. That is, the third to
In the eighth cycle, the data stored in the buffer memory 35 is sequentially read out and the butterfly operation circuit 31 is read.
d.

The butterfly operation circuit 31d generates code information by performing a butterfly operation on the data supplied from the buffer memories 35 and 36, and supplies the code information to the output buffers 31e and 31f.

The output buffers 31e and 31f rearrange and output the data output from the butterfly operation circuit 31d. As described above, according to the present embodiment, the input buffers 31a and 31b of the FFT circuit,
By integrating the delay units 32a and 32b, the buffer memory 3
5 and 36, and access to the buffer memories 35 and 36 is made possible by time sharing without causing bus congestion, so that the amount of memory required by the device can be reduced.

Next, a detection circuit according to a second embodiment of the present invention will be described. FIG. 4 is a diagram illustrating a configuration example of the second embodiment of the present invention. In the embodiment of FIG. 4, the FFT output buffer 50 is different from that of FIG.
And the one-symbol previous memory buffer 52 are integrated, and F
FT output buffers 60 and 61 are provided. Also, DQ
A PSK demapping unit 64 is newly provided after the complex division circuit 62. Furthermore, the demapping units 68 to 70
It is moved between the frequency deinterleaving section 67 and the time deinterleaving section 71 from the subsequent stage of the time deinterleaving section 71.

Here, the FFT output buffers 60 and 61
Is divided into two, and when data is written to one, data can be read from the other.

Next, the operation of the conventional detection circuit will be described with reference to FIG. 5, and then the operation of the detection circuit of the present invention will be described. FIG. 5A is a diagram illustrating the operation of a conventional detection circuit. As shown in this figure, in the conventional detection circuit, one symbol period is divided into eight, each of which is called a slot, and processing is executed in slot units.

That is, in the first slot, the result of the FFT is written to the FFT output buffer 50. In the second slot, differential detection is performed by acquiring FFT output data and data one symbol before, and performing complex division between them. The differentially detected data is written to the differential demodulation memory buffer 53.

In the third slot, the wideband frequency synchronization processing is performed using the differentially detected data, and the SP information is extracted from the FFT output buffer 50.
The transmission characteristic of the synchronous modulation data is estimated. In the fourth slot, synchronous detection is performed using the estimated SP information.

In the fifth to seventh slots, time deinterleaving and demapping are performed on the results of differential detection and synchronous detection while performing frequency deinterleaving. In the eighth slot, the data one symbol before is FFT
Overwritten by output data.

The above operation is repeated, and detection is performed. Next, the operation of the embodiment of the present invention shown in FIG. 4 will be described with reference to FIG.

In the embodiment shown in FIG.
Since the output buffers 60 and 61 are provided, access to the buffers is complicated, but FFT is performed within one slot.
Reading and writing of output data can be performed alternately. Specifically, when the current data is written to the FFT output buffer 60, the data one symbol before is read from the FFT output buffer 61,
When the current data is being written to the FT output buffer 61, data one symbol before can be read from the FFT output buffer 60.

As a result, in the previous symbol period, FFT
The data (one-symbol previous data) written to the output buffers 60 and 61 is read, and complex division (differential detection) can be performed with the FFT output data of the current symbol. Can be removed.

Also, in the embodiment shown in FIG.
, The QPSK demapping unit 68, 16QA
M demapping section 69 and 64QAM demapping section 70
Are arranged between the frequency deinterleaving section 67 and the time deinterleaving section 71, and the DQPSK demapping section 64
Are arranged at the subsequent stage of the complex division circuit 62.

Here, since the frequency deinterleaving, the time deinterleaving, and the demapping process are executed for each carrier, even if the order of the processes is changed, there is substantially no difference in the operation result. Therefore, by changing the order of time deinterleaving and demapping processing, DQ
The bit length of the output data from the PSK demapping unit 64 is 1
/ 4. As a result, it is possible to reduce the memory capacity of the differential demodulation memory buffer 65, the frequency deinterleaving unit 67, and the time deinterleaving unit 71.

According to the above embodiment, only the FFT output buffers 60 and 61 and the differential demodulation memory buffer 65 have 21 Kbits, which is 58 Kb in the case of the conventional circuit.
It is possible to reduce the capacity of the memory to half or less as compared with it.

Similarly, by moving the demapping circuit to a stage preceding the time deinterleaving section 71, the memory capacity of the deinterleaving can be reduced by about half from about 48 Mbit to about 18 Mbit.

Further, by adopting the FFT output buffers 60 and 61, the processing time is shortened, and the shortened processing time is allocated to the detection output. Therefore, the time allocated to the detection output is set to 4.5 slots. It becomes possible. Therefore, it is possible to allocate a time 1.5 times longer than that of the conventional three slots, so that it is possible to allow a margin for the subsequent processing.

Next, a method of removing a wideband frequency error in the embodiment shown in FIG. 4 will be described with reference to FIG. The received OFDM signal includes a frequency error under the influence of the transmission path, and it is necessary to remove the frequency error. In general, in order to remove such a frequency error, a coarse frequency error (narrowband frequency error) is removed in a synchronization unit, and then a wideband frequency error, which is a shift in a carrier unit, is obtained using an FFT result. Is removed.

In the embodiment shown in FIG. 4, DQPSK demapping is performed on the output of the complex division circuit 62, and the number of expression bits is reduced as compared with the conventional case. Conventionally, as described above, the result of the FFT is used as it is to remove the wideband frequency error. Therefore, in the present embodiment, it is necessary to remove the wideband frequency error with a small number of expression bits.

FIG. 6 shows the demap data held in the differential demodulation memory buffer 65. In order to remove a wideband frequency error, a transmission and multiplexing configuration (TMCC) inserted in a certain carrier is used.
A transmission parameter signal such as uration control) or AC (auxiliary channel) is used as a reference. They are,
Tens or more are inserted into all effective carriers, and have a feature that the phase is always constant as compared with other data. When these signals are subjected to the demapping processing, the shaded area ((I, Q) = (0, 3) shown in FIG.
(or 4) or (I, Q) = (7, 3 or 4)), and is written to the differential demodulation memory buffer 65. When performing synchronization detection, these data are read from the differential demodulation memory buffer 65 and mapping is performed as shown in FIG.

As a specific detection method, for example, a case where the detection range is plus / minus ten-odd carriers from the center carrier f0, when each carrier itself is regarded as a center carrier, it corresponds to TMCC. Only the carrier to be extracted is extracted (read from the differential demodulation memory buffer 65) and mapped, and the value of the carrier corresponding to TMCC is squared and cumulatively added. As a result, since a certain carrier has a peak as shown in FIG. 8, that carrier becomes the center carrier. The reason for squaring the carrier corresponding to TMCC is to convert the value of the carrier after mapping, plus or minus 3, into plus 3, thereby fixing the phase to one side.

In this way, even when the data after demapping is used, compared with the conventional method,
The inventor has already verified by simulation that the accuracy is not inferior.

According to the above embodiment, the wideband frequency error is removed after the remapping of the demap data. Therefore, even if the data representation length is reduced, the wideband frequency error is reliably removed. can do.

In the above embodiment, the wideband frequency error is removed by the re-mapping. However, as shown in FIG. 9, the weighting of the demap data can be performed in the same manner as described above. The effect of can be expected.

In this example, a larger weight value (for example, “5” or “2”) is assigned to a portion having a higher probability that the TMCC is demapped. Therefore, in this case, a peak appears at the center of the band by performing cumulative addition of the weight values where the TMCC is demapped without performing mapping, and this is used as a clue to remove the wideband frequency error. Becomes possible.

According to the above-described embodiment, it is possible to remove a wideband frequency error by a simple method without performing a square calculation having a high calculation cost as in the above-described method.

Finally, another embodiment of the FFT circuit will be described. FIG. 10 is a diagram showing an example of another embodiment of the FFT circuit. The FFT circuit shown in FIG.
It comprises an FT input gain control section 90, an FFT input buffer memory 91, a butterfly operation circuit 92, a limit processing section 93, a work memory 94, and an FFT output buffer memory 95.

The FFT input gain control section 90
The size of the input data to be subjected to the FFT is controlled by multiplying the input data under the control of the limit processing unit 93 by a predetermined constant.

The FFT input buffer memory 91 has an FFT
The input data output from the input gain control unit 90 is temporarily stored. The butterfly operation circuit 92 calculates F
The data stored in the FT input buffer memory 91 is sequentially read out, subjected to a butterfly operation, and then output.

The work memory 94 temporarily stores data in the middle of the calculation via the limit processing unit 93 when the butterfly calculation circuit 92 executes the butterfly calculation.
The limit processing unit 93 counts the number of occurrences of overflow or underflow in the butterfly operation circuit 92 when the overflow or underflow occurs, and sends the FFT input gain control unit 90 to the FFT input gain control unit 90 when the count value exceeds a predetermined value. Notify and butterfly operation circuit 9
2 is subjected to clip processing (processing for fixing data to a maximum value or a minimum value) to the work memory 9.
4 is stored.

Next, the operation of the above embodiment will be described. The FFT input gain control section 90 multiplies the input data by a predetermined constant under the control of the limit processing section 93 and outputs the result. For example, if no overflow or underflow has occurred, the input data is multiplied by “1” and output.

The FFT input buffer memory 91 has an FFT
The data output from the input gain control unit 90 is temporarily stored. The butterfly operation circuit 92 uses the FFT
The data stored in the input buffer memory 91 is read out in a predetermined order, and a butterfly operation is performed. At this time, the data in the middle of the calculation is stored in the work memory 94 via the limit processing unit 93.

The limit processing section 93 counts the number of occurrences of overflow or underflow in the butterfly operation circuit 92 when the overflow or underflow has occurred. After performing a clip process on the calculation result of the butterfly calculation circuit 92,
It is stored in the work memory 94.

The FFT input gain control section 90
If an overflow occurs, for example, a constant X
(0 <X <1) is multiplied by the input data. When an underflow occurs, the constant X
Is multiplied by the input data.

The FFT output buffer memory 95 temporarily stores the data output from the limit processing unit 93,
After sorting the data, output. According to the above embodiment, it is possible to prevent overflow or underflow from occurring continuously in the butterfly operation circuit 92.

(Supplementary Note 1) In an OFDM demodulator that receives and demodulates a signal that has been subjected to OFDM modulation, I and Q data obtained as a result of quadrature demodulation of a received signal are
A storage unit for storing the data, a first supply unit for reading predetermined data stored in the storage unit and supplying the data to an FFT circuit; a read unit for reading predetermined data stored in the storage unit; And a second supply unit for supplying to the OFDM demodulator.

(Supplementary Note 2) In an OFDM demodulator that receives and demodulates a signal subjected to OFDM modulation, an FFT
First storage means for storing output data from the circuit;
Second storage means for storing output data from the FT circuit, writing means for alternately writing output data from the FFT circuit to the first or second storage means, and first or second storage means Reading means for alternately reading predetermined data stored in the means and supplying the read data to a subsequent circuit.

(Supplementary Note 3) In an OFDM demodulator that receives and demodulates a signal subjected to OFDM modulation, DQPSK demapping processing means for performing DQPSK demapping processing on differentially demodulated data, and the DQPSK processing An OFDM demodulator comprising: storage means for storing the data on which the data has been subjected; and supply means for reading the data stored in the storage means and supplying the read data to a subsequent frequency deinterleave circuit.

(Supplementary Note 4) Remapping means for remapping the data demapped by the DQPSK demapping means, and wideband frequency synchronization processing for performing wideband frequency synchronization processing according to the mapping result of the remapping means 3. The OFDM demodulator according to claim 3, further comprising:

(Supplementary Note 5) Weighting means for weighting the data demapped by the DQPSK demapping processing means, and wideband frequency synchronization for performing wideband frequency synchronization processing according to the weighting result of the weighting means 4. The OFDM demodulator according to claim 3, further comprising a processing unit.

(Supplementary Note 6) In an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a demapping unit for demapping data subjected to frequency deinterleaving, and a demapping process performed by the demapping unit And a time deinterleaving unit for performing time deinterleaving on the data subjected to (1).

(Supplementary Note 7) In an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, FFT processing means for performing FFT processing on the received data;
When overflow or underflow occurs in the calculation process of the FFT processing, counting means for counting the number of occurrences thereof, and when the count result of the counting means exceeds a predetermined value, the FFT processing means And a level adjusting means for adjusting the level of the input data.

(Supplementary Note 8) If the count result of the counting means exceeds a predetermined value, clip processing means for performing clip processing on data stored in the work memory of the FFT processing means is further provided. 8. The OFDM demodulator according to claim 7, further comprising:

[0099]

As described above, according to the present invention, OFD
In an OFDM demodulator for receiving and demodulating a signal subjected to M modulation, a storage means for storing I and Q data obtained as a result of quadrature demodulation of a received signal, and a predetermined data stored in the storage means. Read the data of FF
A first supply unit that supplies the data to the T circuit; and a second supply unit that reads out predetermined data stored in the storage unit and supplies the read data to the synchronous demodulation circuit. By integrating the delay unit of the synchronous demodulation circuit, the required memory capacity can be reduced.

In an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, first storage means for storing output data from an FFT circuit and second storage means for storing output data from an FFT circuit. Storage means and FF
Writing means for alternately writing output data from the T circuit into the first or second storage means, and predetermined data stored in the first or second storage means, which are alternately read out and sent to a subsequent circuit. And a reading means for supplying the FFT output buffer and the one-symbol previous memory buffer, so that the required memory capacity can be reduced and the time for reading and writing to the memory can be reduced. Therefore, the processing of the subsequent circuit can be performed with a margin.

In an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a DQPSK demapping process is performed on data subjected to differential demodulation.
Since QPSK demapping processing means, storage means for storing data subjected to DQPSK processing, and supply means for reading data stored in the storage means and supplying the data to a subsequent frequency deinterleave circuit are provided, DQP
By arranging the SK processing at the beginning of the processing, it is possible to reduce the bit length of data representation, and as a result, it is possible to reduce the memory capacity of the subsequent processing circuit.

Further, in an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a demapping means for demapping data subjected to frequency deinterleaving and a demapping process by a demapping means are performed. Time deinterleaving means for performing time deinterleaving on the data thus obtained,
It is possible to reduce the data representation bit length, and as a result, to reduce the memory capacity of the time deinterleaving means.

Also, in an OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, FFT processing means for performing FFT processing on the received data;
If an overflow or underflow occurs during the operation of the processing, a counting means for counting the number of occurrences of the overflow or underflow, and if the count result of the counting means exceeds a predetermined value, the input data of the FFT processing means is Since the level adjusting means for adjusting the level is provided, it is possible to prevent a calculation error from occurring in the FFT processing means.

[Brief description of the drawings]

FIG. 1 is a principle diagram for explaining the operation principle of the present invention.

FIG. 2 is a diagram illustrating a configuration example of an embodiment of the present invention.

FIG. 3 is a diagram explaining the operation of the buffer memory shown in FIG. 2;

FIG. 4 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of the embodiment shown in FIG. 4;

6 is an example of demap data stored in a differential demodulation memory buffer shown in FIG.

FIG. 7 is an example of a case where the demap data shown in FIG. 6 is mapped again;

FIG. 8 is a conceptual diagram of wideband frequency synchronization.

FIG. 9 is a diagram showing an example of weighted demap data.

FIG. 10 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration example of an ISDB-T model receiving circuit.

FIG. 12 is a diagram illustrating a configuration example of a conventional OFDM synchronous demodulation unit.

FIG. 13 is a diagram illustrating an example of a guard interval.

FIG. 14 is a diagram illustrating a configuration example of a conventional detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Quadrature demodulation part 2 Storage means 3 Storage means 4 First supply means 5 Second supply means 6 FFT circuit 7 Synchronous demodulation circuit

Claims (5)

[Claims] 1. An OFDM demodulator for receiving and demodulating a signal that has been subjected to OFDM modulation, storing means for respectively storing I and Q data obtained as a result of quadrature demodulation of a received signal; First supply means for reading predetermined data stored in the storage means and supplying the data to the FFT circuit; second supply means for reading predetermined data stored in the storage means and supplying the data to the synchronous demodulation circuit; An OFDM demodulator characterized by having: 2. An OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, wherein: first storage means for storing output data from an FFT circuit; and second storage means for storing output data from an FFT circuit. A writing means for alternately writing output data from the FFT circuit to the first or second storage means; and a predetermined data stored in the first or second storage means, Reading means for alternately reading and supplying the read data to a subsequent circuit. 3. An OFDM demodulator that receives and demodulates a signal that has been subjected to OFDM modulation, comprising: a DQPSK demapping unit that performs a DQPSK demapping process on data that has been subjected to differential demodulation; An OFDM demodulator, comprising: storage means for storing the stored data; and supply means for reading the data stored in the storage means and supplying the read data to a subsequent frequency deinterleave circuit. 4. An OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, a demapping unit for demapping data subjected to frequency deinterleaving, and a demapping process performed by the demapping unit. Time deinterleaving means for performing time deinterleaving on the obtained data. An OFDM demodulation device comprising: 5. An OFDM demodulator for receiving and demodulating a signal subjected to OFDM modulation, comprising: an FFT processing unit for performing FFT processing on received data; and an overflow or underflow during a calculation process of the FFT processing. Counting means for counting the number of occurrences when the occurrence occurs, and level adjusting means for adjusting the level of input data of the FFT processing means when the count result of the counting means exceeds a predetermined value. An OFDM demodulator, comprising: