JP2003059287A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which incorporated plural function circuits are timing-controlled accurately. SOLUTION: This semiconductor integrated circuit is provided with a plurality of function circuits, a plurality of signal lines arranged over these function circuits and transferring a plurality of control signal in which timing to be supplied to each function circuit is different, and a control circuit generating a plurality of control signals. The control circuit has a plurality stage of control signal generating circuits for generating a plurality of control signals respectively, the plurality stage of control signal generating circuits are linked so that the next stage is activated by a control signal outputted from the prescribed stage and transferred via a corresponding signal line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a plurality of functional circuits controlled by a plurality of control signals.

[0002]

2. Description of the Related Art In various semiconductor memories such as DRAM, a redundant circuit system is adopted for relieving defects. In the redundancy circuit type memory, a redundant row cell array and a redundant column cell array are prepared in addition to the normal cell array.
Then, when a defective address is input, control is performed to replace the defective row and the defective column with a redundant row and a redundant column. In order to perform such replacement control,
A defective address storage circuit such as a fuse circuit is mounted in the memory chip. A defective address is programmed in the defective address storage circuit based on the result of the test of the memory chip.

FIG. 16 shows a structure of a portion related to the fuse information latch in such a conventional semiconductor memory. The plurality of fuse latch circuits 11 automatically read and latch programmed fuse data after power-on. After that, control of address replacement is performed based on the latch data. A power-on circuit 10 and a fuse-latch initialization circuit (initialization circuit) that is activated by its output and initializes the fuse-latch circuit 11 in order to automatically initialize the fuse-latch circuit 11 upon detection of power-on And 13 are provided.

A power-on signal PWRON output from the power-on circuit 10 is input to the fuse-latch initialization circuit 13, and based on this, a pre-charge signal bFP for uniformly pre-charging the fuse-latch circuit 11.
The RCH and the fuse set signal FSET for setting the fuse information in the fuse latch are generated. The precharge signal bFPRCH and the fuse set signal FSET are input to each fuse latch circuit 11, and the fuse information initialized by these is output to the output terminal FBLWN.
Output to.

FIG. 17 shows the fuse latch circuit 11, FIG. 18 shows the fuse latch initialization circuit 13, and FIG. 19 shows the power-on circuit 10. Figure 1
As shown in FIG. 9, in the power-on circuit 10, when the power supply voltage Vcc reaches a certain level after the power is turned on, the resistance R1,
The inverter INV31 to which the intermediate voltage generated by the voltage division of R2 is input is inverted. Receiving the output of the inverter INV31, each inverter INV further connected in series
32, INV33, INV34 are sequentially inverted, and finally the output PWRON changes from "L" to "H".

As shown in FIG. 18, in the fuse latch initialization circuit 13, inverters INV11 to INV are provided.
The level transition detection circuit 61 composed of V13 and the NAND gate G1 detects the level transition of the power-on signal PWRON from "L" to "H", and outputs the precharge signal bFPRCH which is a negative logic pulse. In addition, the delay circuit 62 and the level transition detection circuit 63 that detects the level transition of the output from “L” to “H” are delayed by the fuse set signal FS after the precharge signal bFPRCH.
ET is issued. The level transition detection circuit 63, like the level transition detection circuit 61, has inverters INV21 to INV.
23 and a NAND gate G2, and an inverter INV24 is provided at the output thereof, and the fuse set signal FSET becomes a positive logic pulse. Precharge signal b
The timing of the FPRCH and the fuse set signal FSET is adjusted by the delay circuit 62.

As shown in FIG. 17, the fuse latch circuit 11 comprises a fuse F programmed by laser irradiation and a latch 111. Fuse F
Is programmed such that the portion corresponding to the defective address is cut based on the wafer test result.
After turning on the power, PM is generated by the precharge signal bFPRCH.
The OS transistor QP is turned on, and the node A is precharged with the “H” level of the power supply potential Vcc. afterwards,
When the fuse set signal FSET is supplied, the node A is discharged through the turned-on NMOS transistor QN and the fuse F when the fuse F is not cut, and "H" when the fuse F is cut. Hold the level. Eventually, the fuse 111 reads and holds the fuse information (cut or non-cut), and finally outputs the output signal F.
BLWN is "L" when the fuse is not blown and "H" when the fuse is blown.

In order for the fuse latch circuit 11 to perform such an operation, the negative pulse width of the precharge signal bFPRCH, which is the output of the fuse latch initialization circuit 13, is set to a time sufficient for the node A to be precharged.
The positive pulse width of the fuse set signal FSET is set to a time sufficient for discharging the node A.

FIG. 20 shows an operation timing chart from power-on to setting of fuse information. From the timing when the precharge signal bFPRCH in the figure transitions to the "L" level, the fuse set signal FSE
The delay time τ until the timing when T changes to “H” is
It is the delay time set by the delay circuit 62 in the fuse latch initialization circuit 13 described above. In order for the fuse latch circuit 11 to correctly read and latch the information of the fuse contained therein, it is necessary to avoid the situation where the PMOS transistor QP and the NMOS transistor QN are simultaneously turned on. Therefore, the delay time τ is
The pulse width of the precharge signal bFPRCH must be set to be equal to or larger than the pulse width of the precharge signal bFPRCH.

If the delay time τ is the precharge signal bFP
It is assumed that the pulse width is less than the RCH pulse width. In this case, in the fuse latch circuit 11 in which the fuse is not cut,
Since the discharge of the node A by the NMOS transistor QN is started during the precharge by the PMOS transistor QP, the discharge and the precharge collide. Therefore, during the time when the fuse set signal FSET is at the “H” level, that is, NMO
It is uncertain whether the potential of the node A is lowered to the Vss level within the time when the S transistor QN is turned on and is surely latched. Therefore, it is necessary to set the delay time τ by adding a sufficient margin to the pulse width of the negative pulse of the precharge signal bFPRCH.

[0011]

However, even if the delay time τ is sufficiently secured in the fuse latch initialization circuit 13 which is the source of the precharge signal bFPRCH and the fuse set signal FSET, the precharge signal bFPRCH and the fuse are not generated. When the set signal FSET is transmitted through a long signal line, there is no guarantee that the delay time τ will be secured. The reason will be specifically described.

Normally, the fuse latch circuit 11 is shown in FIG.
Since a large number are provided as shown in FIG. 5, the gate capacitance which becomes a load on the signal line 12 for the precharge signal bFPRCH and the fuse set signal FSET becomes large accordingly. Further, the fuse latch circuits 11 are not always arranged collectively in a limited area in the memory chip, but are often arranged in a dispersed manner. Then, due to the wiring, the parasitic capacitance and the parasitic resistance of the signal line 12 cannot be ignored. In particular, the precharge signal bFP
Regarding the RCH and the fuse set signal FSET, when the parasitic capacitance and the parasitic resistance of the signal line 12 are different, the signal line 1
In the fuse latch circuit 11 at a position far from the initialization circuit 13 of No. 2, the delay time τ becomes insufficient and the fuse information may be erroneously latched.

Therefore, in order to prevent the malfunction of the fuse latch circuit 11, it is necessary to accurately estimate the resistance and capacitance to be added to the respective signal lines 12 of the precharge signal bFPRCH and the fuse set signal FSET, and then, at the time of signal transmission. It is also necessary to lay out the fuse set signal FSET with a larger delay than the precharge signal bFPRCH. However, this is a real difficult task. After all, in order to surely prevent the malfunction, it is effective to set the delay time τ in the fuse latch initialization circuit 13 to be sufficiently large at the circuit design stage, but this is also not sure.

Not only the fuse latch circuit but also a plurality of programmable control data storage circuits having the same function as the fuse latch circuit are built in, and when these are initialized to control the operation of the integrated circuit chip, the same problem occurs. Occurs. From a broader point of view, the same problem occurs in an integrated circuit having a plurality of functional circuits controlled by a plurality of control signals each having a constant timing difference.

An object of the present invention is to provide a semiconductor integrated circuit in which a plurality of built-in functional circuits are precisely controlled in timing.

[0016]

A semiconductor integrated circuit according to the present invention includes a plurality of functional circuits and a plurality of control circuits which are arranged over the plurality of functional circuits and which are supplied to the respective functional circuits at different timings. A plurality of signal lines for transferring signals and a control circuit for generating the plurality of control signals are provided, and the control circuit includes a plurality of stages of control signal generation circuits for respectively generating the plurality of control signals. The control signal generation circuits of the plurality of stages are linked so that the next stage is activated by a control signal output from a predetermined stage and transferred through a corresponding signal line.

According to the present invention, a plurality of stages of control signal generation circuits for generating a plurality of control signals supplied to a plurality of functional circuits are linked via signal lines to which the plurality of control signals are transferred. As a result, it is possible to reliably hold the timing difference between the plurality of control signals supplied to each functional circuit.

In the present invention, for example, the functional circuit is a control data storage circuit configured to hold the programmed control data so as to be output. In this case, the control circuit is an initialization circuit that causes the control data storage circuit to read and hold the programmed control data, and the control signal generation circuits in the plurality of stages respectively store the control data via signal lines. It is an initialization signal generation circuit that generates an initialization signal supplied to the circuit. A waveform shaping circuit can be inserted in at least one place of the signal line.

The control data storage circuit is, for example, a defective address storage circuit for storing the defective address of the memory cell array and controlling replacement of the defective cell array corresponding to the defective address with a redundant cell array when the defective address is accessed. The defective address storage circuit is configured to include, for example, a laser blown fuse and a fuse latch circuit having a latch for reading and holding data of the fuse. In this case, the initialization signal generation circuit of a plurality of stages includes a precharge signal generation circuit that generates a precharge signal for initializing the latch node of each fuse latch circuit, and each fuse latch circuit via a corresponding signal line. And a fuse set signal generation circuit that generates a fuse set signal that is activated by the precharge signal transferred to the fuse latch circuit to read and hold the fuse data of each fuse latch circuit.

The defective address storage circuit also turns on or off according to the data of the capacitor type electric fuse, the first latch for reading and holding the data of the electric fuse through the transfer gate, and the data of the first latch. The fuse latch circuit includes a sense transistor that is turned off and a second latch that reads and holds the state of the sense transistor. In this case, the initialization signal generation circuit of a plurality of stages includes a read signal generation circuit that generates a read signal for driving the transfer gate, and each fuse output from the read signal generation circuit via the first signal line. An activation signal generation circuit that generates an activation signal that is activated by the read signal transferred to the latch circuit and activates the first latch, and a second signal line that is output from the activation signal generation circuit. A precharge signal generation circuit that generates a precharge signal that is activated by the activation signal transferred to each fuse latch circuit to initialize the latch node of the second latch, and this precharge signal generation circuit Of the sense transistor, which is activated by the precharge signal output from the fuse latch circuit and transferred to each fuse latch circuit through the third signal line. The formed and a fuse set signal generation circuit for generating a fuse set signal for holding is transferred to the second latch.

In the present invention, another example of the functional circuit is
This is a counter circuit that is cascaded so that the output of a predetermined stage becomes the input of the next stage and that operates with the first and second clock signals having different timings. In this case, the plurality of stages of control signal generation circuits detect the level transition of the second clock signal and generate a first clock signal, and a level transition of the first clock signal. A second clock signal generation unit for detecting and generating a second clock signal, wherein the first and second clock signals transferred to the respective counter circuits via the corresponding signal lines are the second and the second clock signals, respectively. It is input to the first clock signal generator.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a semiconductor memory adopting a redundant circuit system according to an embodiment of the present invention. In addition to the normal cell array, the memory cell array 1 has a redundant row cell array including a plurality of spare word lines and a redundant column cell array including a plurality of spare column selection lines.

The word line WL of the memory cell array 1 is selected by the row decoder 5, and the bit line is selected by the column decoder 6 and the column gate 3. The sense amplifier 2 is connected to the bit line BL. The read data of the bit line BL selected by the column gate 3 is output to the I / O terminal via the data buffer 4. The write data supplied from the I / O terminal is transferred to the bit line via the data buffer 4. The address signal Add is fetched via the address buffer 7, and the row address and the column address are decoded by the row decoder 5 and the column decoder 6, respectively.

In order to perform replacement control of defective cells in the memory cell array 1 by the redundant row cell array and the redundant column cell array, a defective address memory circuit 8 in which a defective address is programmed based on a test result, and an address supplied from the outside are provided. A replacement control circuit 9 for detecting a match with a defective address held in the defective address storage circuit 8 and outputting a replacement signal is provided. The replacement signal inactivates the corresponding decoder section in the row decoder 5 or the column decoder 6 and activates the spare decoder section for selecting the redundant row cell array or the redundant column cell array.

The defective address storage circuit 8 is provided with a fuse latch circuit as will be described later, and automatically after power-on.
An initialization operation is required to read the programmed data. Therefore, the power-on circuit 10 and the initialization circuit 13
And are provided. Power-on circuit 10 when power is turned on
In response to the power-on signal PWRON output by the initialization circuit 13, the initialization circuit 13 outputs a plurality of initialization signals FIN with different timings.
Generate ITi. The initialization operation (reading and holding of programmed data) of the address storage circuit 8 is performed by the initialization signal FINITi.

FIG. 2 shows a specific configuration of the defective address storage circuit 8. The defective address storage circuit 8 is composed of a plurality of fuse latch circuits 11. In order to initialize each fuse latch circuit 11, a plurality of initialization signals FINITi (FI
NIT1, FINIT2, ...) are required, and the initialization circuit 13 has a plurality of stages of initialization signal generation circuits 13a, 13b, for sequentially outputting these initialization signals FINITi.
13c, ...

The initializing signal generating circuit 13a receives the activation signal FINIT0 and outputs the first initializing signal FINIT1 based on the activation signal FINIT0. Start signal FINIT0
Here, the output PWRON of the power-on circuit 10
Is used. The initialization signal FINIT1 is the signal line bundle 1
One of the signal lines 12a is transferred to the plurality of fuse latch circuits 11. As a result, the initializing operation is performed in each fuse latch circuit 11. Signal line 1
The end of 2a is connected to the activation input terminal of the second stage initialization signal generation circuit 13b. Therefore, the second-stage initialization signal generation circuit 13b has the first
The second initialization signal FINIT2 is activated by the initialization signal FINIT1 of FIG.

Like the first initialization signal FINIT1, the second initialization signal FINIT2 is transferred through the signal line 12b in the signal line bundle 12 to each fuse latch circuit 11.
Is supplied to. As a result, each fuse latch circuit 11
Then, the following initialization operation is performed. Second initialization signal FI
NIT2 is input as an activation signal from the end of the signal line 12b to the third stage initialization signal generation circuit 13c. Similarly, a plurality of stages of initialization signal generation circuits 13a, 13b, ...
After the output signal of the n-th circuit is supplied to each fuse latch circuit 11, from the end of the transfer path to n +
It is linked so that it is inputted to the first circuit as an activation signal.

As described above, each fuse latch circuit 11
In order to read and hold the fuse data, the initialization operation by a plurality of initialization signals having a constant timing difference is required. According to this embodiment, after the first initialization signal FINIT1 is supplied to all fuse latch circuits 11, the second initialization signal FINIT2 is generated, and after this is supplied to all fuse latch circuits 11. , A third initialization signal FINIT3 is generated. Therefore, in any fuse latch circuit 11, the initialization operation order is not changed, and the initialization signals are supplied in a fixed order, so that the fuse information can always be set correctly.

FIG. 3 shows an example in which a waveform shaping circuit 14 for waveform shaping is inserted in the middle of the signal line 12 of each initialization signal based on the configuration of FIG. The waveform shaping circuit 14 is provided at, for example, a plurality of locations according to the length of the signal line 12. By arranging the waveform shaping circuit 14 on the signal lines in this manner, it is possible to suppress the waveform blunting or attenuation due to the parasitic capacitance or parasitic resistance added to each signal line, and to make the operation of the fuse latch circuit 11 more reliable. it can.

2 and 3, the fuse latch circuit 11 includes a fuse F and a latch 1 as shown in FIG.
In the case of the normal configuration using 11, the precharge signal bFPRCH is used as the first initialization signal FINIT1.
However, the fuse set signal FSET is used as the second initialization signal FINIT2. Therefore, in this case, the initialization circuit 13 has two stages of initialization signal generation circuits 13a and 13a.
It suffices if there is only b, and the first stage initialization signal generation circuit 13a serves as a precharge signal generation circuit and the second stage initialization signal generation circuit 13b serves as a fuse set signal generation circuit.

FIG. 4 specifically shows a configuration example of the precharge signal generation circuit (first stage initialization signal generation circuit) 13a and the fuse set signal generation circuit (second stage initialization signal generation circuit) 13b. Precharge signal generation circuit 13a
Is an odd-stage inverter INV41 to INV43 and N for detecting the rising edge of the power-on signal PWRON.
It is a level transition detection circuit (rising edge detection circuit) including an AND gate G41. As a result, as shown in FIG. 5, the precharge signal bFPRCH of the negative logic pulse determined by the delay of the inverters INV41 to INV43 is obtained.

The fuse set signal generation circuit 13b has N
The flip-flop 41 is composed of AND gates G42 and G43, and a level transition detection circuit 42 for detecting the level transition of its set output. The flip-flop 41 has a power-on signal PWRO.
It is reset by the PMOS transistor QP0 and set by the precharge signal bFPRCH until N becomes "H". As a result, as shown in FIG. 5, the fuse set signal FSET of the positive logic pulse is output with a delay of τ from the rising edge of the precharge signal bFPRCH. The delay time τ depends on the precharge signal generation circuit 13
It is determined by the transfer delay in the signal line 12 between the precharge signal bFPRCH output from a and the precharge signal bFPRCH input to the fuse set signal generation circuit 13b.

FIG. 6 shows another precharge signal generation circuit 1
3a and a configuration example of the fuse set signal generation circuit 13b. The precharge signal generation circuit 13a includes even-stage inverters INV51 to INV54 that delay the rising of the power-on signal PWRON. As a result, as shown in FIG. 7, the power-on signal P
A precharge signal bFP which becomes "L" from the "L" period of WRON until a certain time elapses after it becomes "H"
Output RCH.

The fuse set signal generation circuit 13b is a level transition detection circuit having an odd number of stages of inverters INV55 to INV57, a NAND gate G51, and an inverter INV58 for inverting the output of the NAND gate G51. As a result, as shown in FIG. 7, a positive pulse fuse set signal FSET determined by the delay of the inverters INV55 to INV57 is obtained. The delay τ from the rising edge of the precharge signal bFPRCH to the rising edge of the fuse set signal FSET is the same as in the examples of FIG. 4 and FIG.
It is determined by the delay of the H signal line 12.

FIG. 8 shows a configuration example of the fuse latch circuit 11. This is different from FIG. 17 in that the fuse F is arranged on the power supply terminal Vcc side. The PMOS transistor QP arranged between the fuse F and the latch node A is a fuse set transistor, and the NMOS transistor QN arranged between the latch node A and the ground Vss is a precharge transistor. In this fuse latch circuit, a positive logic precharge signal FPRCH and a negative logic fuse set signal bFSET are used.

In the case of the fuse latch circuit configuration as shown in FIG. 8, the precharge signal generation circuit 13a and the fuse set signal generation circuit 13b are configured as shown in FIG. 9, for example. The precharge signal generation circuit 13a detects the rising edge of the power-on signal PWRON and, as shown in FIG. 10, the precharge signal FPRCH of the positive logic pulse.
Is a level transition detection circuit for generating The fuse set signal generation circuit 13b is configured to include a flip-flop 41 and a level transition detection circuit 42 that detects the transition of the output thereof, almost similarly to FIG. As shown in FIG. 10, the fuse set signal generation circuit 13b receives the precharge signal FPRCH and outputs the negative logic pulse fuse set signal bFSET. Precharge signal FPR
The delay τ from the fall of CH to the fall of the fuse set signal FSET is determined by the delay of the precharge signal FPRCH by the signal line 12 as in the previous two examples.

FIG. 11 shows another configuration example of the precharge signal generation circuit 13a and the fuse set signal generation circuit 13b in the case of the fuse latch circuit configuration of FIG. The precharge signal generation circuit 13a uses the power-on signal PWRO.
It is an odd-numbered inverter chain that delays the rising of N, and as shown in FIG. 12, a power-on signal PWRON
A precharge signal FPRCH which is a positive logic pulse having a constant time width is generated from the rising edge of The fuse set signal generation circuit 13b is a level transition detection circuit that detects the falling edge of the precharge signal FPRCH,
As shown in FIG. 12, the fuse set signal bFSET of a negative logic pulse is output. Precharge signal FPRCH
The delay τ from the falling edge of the fuse set signal FSET to the falling edge of the fuse set signal FSET is
It depends on the delay of the PRCH signal line 12.

In the above-described embodiments, the laser-blown fuse is used for the defective address storage circuit 8, but the present invention is also applicable to the case where an electric fuse (capacitor type) is used. FIG. 13 shows the configuration of the fuse latch circuit 11 using the electric fuse EF. Initialization of the fuse latch circuit 11 requires a larger number of initialization signals than in the case where a laser fuse is used. That is, as the initialization signals that need to be sequentially activated, in addition to the precharge signal bFPRCH and the fuse set signal FSET similar to those in the previous embodiment, the electric fuse EF that needs to be generated prior to them Read signal E for reading data to the latch 131 via the transfer gate
FOPEN and a signal bEFPRCH for controlling activation of the latch 131 are required. Initialization signal generation circuit 1 for sequentially generating these initialization signals
FIG. 14 shows the configuration of the initialization circuit 13 including 3a, 13b, 13c, 13d.

In the fuse latch circuit 11 of FIG. 13, the boosted power supply voltage Vpp is applied to the electric fuse EF through the NMOS transistor QN3 which is turned on by the program signal EFPROG, so that the electric fuse EF is supplied.
Is programmed and becomes conductive. At this time, the NMOS transistor QN4 which is the transfer gate is kept off so that the high voltage Vpp is not applied to the node B and thereafter.

Whether or not the electric fuse EF is in the conductive state is held as "L" and "H" of the node C. The data of the node C is transferred to the node B via the NMOS transistor QN4 driven by the read signal EFOPEN and temporarily held in the latch 131. The state of this node B is the sense NMOS transistor QN.
2. Turn on or off. When the node B is "H", the NMOS transistor QN2 is turned on, which corresponds to the case where the fuse is not blown in the laser fuse latch circuit. When the node B is "L", N
Since the MOS transistor QN2 is turned off, this corresponds to the case where the fuse is blown. The state of the sense NMOS transistor QN2 is read and held in the latch 111 by the precharge signal bFPRCH and the fuse set signal FSET, as in the case of using the laser fuse. The final output FBLWN becomes "L" and "H" depending on whether the electric fuse EF is short-circuited or non-short-circuited.

FIG. 15 shows a read signal EFOPEN, an activation signal bEFPRCH, a precharge signal bFPRCH and a fuse set signal FSET which are initialization signals to be sequentially generated in response to the power-on signal PWRON.
Is generated. The initializing signal generation circuit 13a in the first stage supplies the power-on signal P under the condition that the fuse program is completed (EFPROG = “L”).
WRON is an inverter INV71, NOR gate G7
1, a read signal generation circuit for generating a read signal EFOPEN delayed by a predetermined time by a chain of inverters INV72, INV73. Read signal EFO
When PEN = “H”, the NMOS transistor QN4 of FIG. 13 is turned on, and the fuse data of the node C is transferred to the node B.

That is, when the fuse is not programmed, the nodes B and C become "H". In this state, even if the signal bEFPRCH becomes "H", the inverter IN
It is held in the latch 131 composed of V61 and NAND gate G61. On the other hand, when the electric fuse EF is programmed, both electrodes of the electric fuse EF become conductive, and
When OPEN = “H”, the charging of the NAND gate G61 and the discharging of the electric fuse EF collide with each other, and both the nodes B and C become indefinite.

The second-stage initialization signal generation circuit 13b formed by the even-numbered stages of inverter chains INV74 to INV77 receiving the read signal EFOPEN is an activation signal generation circuit which activates the latch 131. When the activation signal bEFPRCH = “H” is generated, the charge from the NAND gate G61 is stopped and the nodes B and C are held as “L” due to the discharge of the electric fuse EF. By the operation up to this point, the sense NMOS transistor QN2 is turned on or off according to the state of the electric fuse EF.

The subsequent operation is similar to that of the previous embodiment using the laser fuse. That is, the precharge signal bFPRCH is generated by the third stage initialization signal generation circuit 13c having the same configuration as the initialization signal generation circuit 13a in FIG. After the precharge signal bFPRCH is delayed, as shown in FIG.
The fuse set signal FSET is generated by the fourth-stage initialization signal generation circuit 13d similar to the initialization signal generation circuit 13b of FIG. The fuse information read output FBLWN is determined by the precharge signal bFPRCH and the fuse set signal FSET.

Also in the case of this embodiment, after the output of the initial stage initialization signal generation circuit 13a is supplied to all the fuse latch circuits, the signal at the end of the transfer path is the second stage initialization signal generation circuit 13b. To the fuse latch circuits in series in the same manner by serially linking the initialization signal generation circuits of the respective stages. That is,
In the timing chart shown in FIG. 15, delay times τ1, τ
2 and τ3 are guaranteed in all fuse latch circuits, and malfunctions are prevented.

In the above embodiments, the case where the control data storage circuit is the defective address storage circuit used in the redundant circuit system of the semiconductor memory has been described, but the present invention is not limited to this. For example, it is effective to store various chip information such as chip ID information and circuit trimming information as control data together with the defective address or separately from the defective address. Although the fuse latch is used as the control data storage circuit, the present invention can be similarly applied to the case where a storage circuit using a non-volatile memory cell known as an EEPROM or the like is used.

Even more generally, the same invention can be applied to an integrated circuit having a plurality of functional circuits which are controlled by a plurality of control signals having different timings. Specifically, another example of such a functional circuit is a binary counter.

FIG. 21 shows an embodiment in which the present invention is applied to a binary counter. The binary counter has a master clock signal MSCLK and a slave clock signal SLCLK.
A plurality of counter circuits 22 controlled by are connected in series. Clock signals MSCLK, SLCLK
Is generated by the control clock generation circuit 21 based on the output OSCOUT of the ring oscillator 20. These clock signals MSCLK and SLCLK are applied to the signal line 2
3 (master clock signal line 23a and slave clock signal line 23b) to all counter circuits 22.

As shown in FIG. 23, the ring oscillator 20 is formed by connecting inverters in odd stages in a ring. As shown in FIG. 24, the control clock generating circuit 21 is composed of a master clock generating section 21a and a slave clock generating section 21b. These clock generators 21a and 21b are connected to the NAND gates G101 and G10.
It is mainly composed of 2. In the conventional method, the inputs and outputs of these clock generators 21a and 21b are directly linked. That is, the clock MSCLK output from the master clock generation unit 21a becomes the input of the slave clock generation unit 21b, and the slave clock generation unit 21b
The clock SLCLK output from b is input to the master clock generating unit 21a. On the other hand, in this embodiment, the master clock generator 21a and the slave clock generator 21b are linked via the signal line 23. That is, the master clock generator 21
The clock MSCLK output from a is the signal line 23a.
Signal MSCLKend which is transferred to the end of the signal
Becomes an input of the slave clock generator 21b. Similarly, the clock MSCLK output from the slave clock generation unit 21b is transferred through the signal line 23b, and the signal SLCLKend obtained at the end of the clock MSCLK is input to the master clock generation unit 21a.

As shown in FIG. 25, the counter circuit 22 comprises a master latch 221 and a slave latch 222. NMOs connected in series between the nodes A and B of the master latch 221 and the ground terminal
The portions of the S transistors (Q1, Q2) and (Q3, Q4) form a logic gate 223 that determines the states of the nodes A and B according to the output state of the slave latch 222 and the master clock MSCLK. Further, NMOS transistors (Q5, Q6) and (Q) connected in series between the nodes C and D of the slave latch 222 and the ground terminal, respectively.
7, Q8) constitutes a logic gate 224 which determines the states of the nodes C and D by the output state of the master latch 221 and the slave clock SLCLK.

The operation of the counter circuit 22 is as follows. When the ring oscillator 20 becomes active and its output OSCOUT changes from "L" to "H", the control clock generating circuit 21 changes the slave clock SLCLK from "H" to "L" as shown in FIG. Become. In response to this, the master clock MSCLK changes from "L" to "H". Thereafter, similarly, the master clock MSCLK and the slave clock SLCLK are alternately generated.

In the counter circuit 22, the nodes A and C are "H" in the initial state, the nodes B and D are "L", and the output C is
It is assumed that NOUT is "L". Input CNIN is "L"
As long as the NAND gate G103 is inactive,
The counter circuit 22 maintains the initial state. Input CNIN is "
H ”, and master clock MSCLK becomes“ L ”→”
When transitioning from H ”to“ L ”, node A is“ H ”to“ L ”
In response to this, the node B goes from “L” to “H”. Next, the slave clock SLCLK becomes "L" → "
When it becomes “H”, the node C becomes “H” → “L”, and accordingly, the node D becomes “L” → “H”, and further, in response, the output CNOUT becomes “L” → “H”. .

"L" of the next master clock MSCLK
→ "H" → "L" makes node B "H"
→ "L", and node A receives "L" → "
H ". Subsequent slave clock SLCLK
When "L" → "H" → "L", the node D is "H"
→ "L", and node C receives "L" → "
It becomes H ”, and the output CNOUT becomes“ H ”→“ L ”.
In this way, the count output CNOU is output in two cycles of the master clock MSCLK and the slave clock SLCLK.
T operates in one cycle.

As shown in FIG. 22, such a counter circuit 22 is cascade-connected so that the output CNOUT of the preceding stage circuit becomes the input CNIN of the circuit of the next stage.
As shown in FIG. 3, the second counter circuit operates at a cycle twice that of the first counter circuit, and the third counter circuit operates at a cycle twice that of the second counter circuit. Therefore, by extracting the outputs CNT1, CNT2, CNT3, ... Of each counter circuit as the output of each digit of the count signal, it functions as a binary counter.

As in the conventional system, the control clock MSCL
When K and SLCLK are directly linked in the control clock generation circuit 21, the master clock MSCLJK and the slave clock SLCLK are “H” due to wiring delay while being supplied to the many counter circuits 22 via the signal line 23.
Periods may overlap. Master clock MSC
If the "H" periods of LJK and slave clock SLCLK overlap, the state of the counter circuit 22 becomes indefinite, which causes a malfunction.

On the other hand, in this embodiment, since the clock generators 21a and 21b for generating the clocks MSCLK and SLCLK are linked through the signal line 23, the two clocks MSCLK and SLCLK are "H".
It is possible to avoid situations where the periods overlap. That is, the slave clock SLCLK is generated only after the master clock MSCLK is supplied to all the counter circuits 22, and similarly, the master clock M is supplied only after the slave clock SLCLK is supplied to all the counter circuits 22.
SCLK is generated.

In FIG. 26, the internal delay of the control clock generation circuit 21 is ignored, and the slave clock SLCLK undergoes level transition in response to the level transition of the terminal signal MSCLKend after the master clock MSCLK has been transferred through the signal line 23a. Similarly, the end signal SLCLKend after the slave clock SLCLK has been transferred through the signal line 23b.
A state in which the master clock MSCLK makes a level transition in response to the level transition of is shown by a broken line. Delay times τ11 and τ12 in the figure respectively indicate maximum delays in the signal lines 23a and 23b.

As described above, according to this embodiment, the overlapping of the two kinds of clocks is prevented, and the malfunction of the binary counter is prevented.

FIG. 22 is based on the configuration of FIG. 21 and has a clock signal line 23 for shaping the waveform of each clock signal.
An example is shown in which the waveform shaping circuit 24 is inserted in various places.
By arranging the waveform shaping circuits here and there,
The operation of the clock circuit can be made more reliable by suppressing the blunting or attenuation of the waveform due to the parasitic capacitance or the parasitic resistance added to each signal line 23.

[0061]

As described above, according to the present invention, a plurality of control signal generating circuits for generating a plurality of control signals supplied to a plurality of functional circuits are transferred to the plurality of control signals. By linking via a signal line corresponding to each of the functional circuits, it is possible to reliably hold the timing difference between the plurality of control signals supplied to each functional circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a defective address storage circuit and an initialization circuit of the same embodiment.

FIG. 3 is a diagram showing configurations of a defective address storage circuit and an initialization circuit according to another embodiment.

FIG. 4 is a diagram showing a configuration example of an initialization circuit.

FIG. 5 is an operation timing chart of the initialization circuit.

FIG. 6 is a diagram illustrating another configuration example of an initialization circuit.

FIG. 7 is an operation timing chart of the initialization circuit.

FIG. 8 is a diagram showing a configuration of a fuse latch circuit.

FIG. 9 is a diagram showing a configuration example of an initialization circuit when the fuse latch circuit is used.

FIG. 10 is an operation timing chart of the initialization circuit.

FIG. 11 is a diagram showing another configuration example of the initialization circuit.

FIG. 12 is an operation timing chart of the initialization circuit.

FIG. 13 is a diagram showing a configuration of a fuse latch circuit using an electric fuse.

FIG. 14 is a diagram showing a configuration of an initialization circuit for initializing the fuse latch circuit.

FIG. 15 is a diagram showing an operation timing of the fuse latch circuit.

FIG. 16 is a diagram showing a configuration of a defective address storage circuit section in a conventional semiconductor memory.

FIG. 17 is a diagram showing a configuration of a fuse latch circuit of the defective address storage circuit unit.

FIG. 18 is a diagram showing a configuration of an initialization circuit of the fuse latch circuit.

FIG. 19 is a diagram showing a configuration of a power-on circuit.

20 is a diagram showing an operation timing of the fuse latch circuit of FIG.

FIG. 21 is a diagram showing a configuration of a binary counter according to another embodiment.

FIG. 22 is a diagram showing a configuration of a binary counter according to another embodiment.

23 is a diagram showing a configuration of the ring oscillator 20 of FIGS. 21 and 22. FIG.

FIG. 24 is a control clock generation circuit 2 of FIGS. 21 and 22;
It is a figure which shows the structure of 1.

FIG. 25 is a diagram showing a configuration of the counter circuit 22 of FIGS. 21 and 22.

FIG. 26 is an operation timing chart of the binary counter of FIGS. 21 and 22.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Sense amplifier, 3 ... Column gate, 4 ... Data buffer, 5 ... Row decoder, 6 ...
Column decoder, 7 ... Address buffer, 8 ... Bad address storage circuit, 9 ... Replacement control circuit, 10 ... Power-on circuit, 13 ... Initialization circuit, 13a, 13b, 13c ... Initialization signal generation circuit, 12 ... Signal line, 14 ... Waveform shaping circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Daisuke Kato             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5L106 CC03 CC04 CC05 CC12 CC13                       CC17 FF08 GG03 GG07

Claims (13)

[Claims] 1. A plurality of functional circuits, a plurality of signal lines that are arranged over the plurality of functional circuits, and that transfer a plurality of control signals with different timings to be supplied to the respective functional circuits, A control circuit that generates a plurality of control signals, wherein the control circuit has a plurality of control signal generation circuits for generating the plurality of control signals, and the plurality of control signal generation circuits are , A semiconductor integrated circuit which is linked so that the next stage is activated by a control signal output from a predetermined stage and transferred to a corresponding signal line. 2. The functional circuit is a control data storage circuit configured to outputably hold programmed control data, and the control circuit stores programmed control data of the control data storage circuit. An initialization circuit for performing read and hold operations, wherein the plurality of stages of control signal generation circuits each generate an initialization signal supplied to each control data storage circuit via the signal line. The semiconductor integrated circuit according to claim 1, wherein 3. The semiconductor integrated circuit according to claim 2, wherein a waveform shaping circuit is inserted in at least one location of the signal line. 4. The control data storage circuit is a defective address storage circuit for storing a defective address of a memory cell array and controlling replacement of a corresponding defective cell array with a redundant cell array when the defective address is accessed. The semiconductor integrated circuit according to claim 2, wherein 5. The defective address memory circuit includes a fuse latch circuit having a laser-blown fuse and a latch for reading and holding the data of the fuse, and the initialization signal generation circuits in each of the plurality of stages have respective fuses. A precharge signal generation circuit for generating a precharge signal for initializing a latch node of the fuse latch circuit, and each precharge signal activated by the precharge signal transferred to each fuse latch circuit via a corresponding signal line. 5. The semiconductor integrated circuit according to claim 4, further comprising: a fuse set signal generation circuit that generates a fuse set signal for reading and holding the fuse data of the fuse latch circuit. 6. The defective address storage circuit includes a capacitor-type electric fuse, and a first latch for reading and holding data of the electric fuse through a transfer gate.
A fuse latch circuit having a sense transistor that turns on or off according to the data of the first latch and a second latch that reads and holds the state of the sense transistor is provided, and the initialization signals of the plurality of stages are provided. The generation circuit generates a read signal for driving the transfer gate, and the read signal generation circuit outputs the read signal and transfers the read signal to each fuse latch circuit via a first signal line. An activation signal generation circuit that generates an activation signal that is activated by a read signal to activate the first latch, and each of the fuses that is output from the activation signal generation circuit and that is output from a second signal line. A precharge signal that is activated by the activation signal transferred to the latch circuit to initialize the latch node of the second latch. And a sense transistor that is activated by the precharge signal that is generated from the precharge signal generation circuit and is transferred from the precharge signal generation circuit to the fuse latch circuits via a third signal line. 5. The semiconductor integrated circuit according to claim 4, further comprising: a fuse set signal generation circuit that generates a fuse set signal for transferring and holding the data of 1. in the second latch. 7. The plurality of functional circuits are counter circuits which are cascaded so that an output of a predetermined stage becomes an input of a next stage and operate by first and second clock signals having different timings. The control signal generation circuit of the stage detects a level transition of the second clock signal and generates a first clock signal, and a level transition of the first clock signal. And a second clock signal generation unit that generates the second clock signal, and the first and second clock signals transferred to the respective counter circuits via corresponding signal lines are respectively the first and second clock signals. 2 and 1
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is input to the clock signal generating unit. 8. A plurality of control data storage circuits configured to outputably hold programmed control data, and an initial stage for reading and holding programmed control data of these control data storage circuits. An initialization circuit, the initialization circuit includes a plurality of stages of initialization signal generation circuits for supplying a plurality of initialization signals having different timings to the control data storage circuits, and the plurality of stages. 2. The semiconductor integrated circuit according to claim 1, wherein the initialization signal generating circuit is linked so that the next stage is activated by an initialization signal output from a predetermined stage. 9. In the initialization signal generation circuit of the plurality of stages, an initialization signal output from a predetermined stage is transferred to a signal line, supplied to each control data storage circuit, and obtained at the end of the signal line. 9. The semiconductor integrated circuit according to claim 8, wherein the initialization signal is linked via a signal line so that the initialization signal is input to the next stage as an activation signal. 10. The semiconductor integrated circuit according to claim 8, wherein a waveform shaping circuit is inserted in at least one location of the signal line. 11. The control data storage circuit is a defective address storage circuit for storing a defective address of a memory cell array and controlling replacement of a corresponding defective cell array with a redundant cell array when the defective address is accessed. 9. The semiconductor integrated circuit according to claim 8, wherein 12. The defective address storage circuit includes a fuse latch circuit having a laser-blown fuse and a latch for reading and holding data of the fuse, and the plurality of stages of initialization signal generation circuits each include A precharge signal generation circuit that generates a precharge signal for initializing the latch node of the fuse latch circuit, and is activated by the precharge signal supplied to each fuse latch circuit via a corresponding signal line. 12. The semiconductor integrated circuit according to claim 11, further comprising: a fuse set signal generation circuit that generates a fuse set signal for reading and holding the fuse data of each fuse latch circuit. 13. The defective address storage circuit, according to a capacitor type electric fuse, a first latch for reading and holding data of the electric fuse through a transfer gate, and data of the first latch. A fuse latch circuit having a sense transistor that turns on or off and a second latch that reads and holds the state of the sense transistor is provided, and the initialization signal generation circuits of the plurality of stages drive the transfer gate. And a read signal generation circuit for generating a read signal for use, and the read signal output from the read signal generation circuit and supplied to each fuse latch circuit via a first signal line to activate the read signal. And an activation signal generation circuit that generates an activation signal that activates the latch of A precharge signal generation circuit that generates a precharge signal that is activated by the activation signal supplied to each fuse latch circuit via the second signal line to initialize the latch node of the second latch. And is activated by the precharge signal output from the precharge signal generation circuit and supplied to each of the fuse latch circuits via the third signal line to transfer the data of the sensing transistor to the second latch. The semiconductor integrated circuit according to claim 11, further comprising: a fuse set signal generation circuit that generates a fuse set signal to be transferred and held.