JP2002133898A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect defective multi-selection at the time of access simply and in a short time. SOLUTION: Row decoders 12-0, 12-1, 12-2,... are provided corresponding to blocks No.0, No.1, No.2,... in a cell area 11. At the time of normal access operation, one row decoder is selected by row address signals (block address signals) A0, A1, A2. When defective multi-selection exist, two or more row decoders are selected by row address signals A0, A1, A2. The selected row decoders discharge electric charges of a RSEN node. The potential of a common node A is varied in accordance with the number of selected row decoders. A sdefect detecting circuit 21 detects variation of the potential of a common node A, and detects whether defective multi-selection exists or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a failure detection circuit for detecting a failure in which a row (or a block) of a memory cell array is multi-selected at the time of access.

[0002]

2. Description of the Related Art In semiconductor memories, wirings are short-circuited due to the influence of dust or the like generated during manufacturing, and a defect (multi-selection defect) in which rows (or blocks) of a memory cell array are simultaneously selected at the time of access occurs. There are cases. If such a defect is detected and the defect can be remedied, the defect must be remedied. If the defect cannot be remedied, it must be removed as a defective product. Must.

Hereinafter, a conventional method for detecting such a defect will be described using a NAND flash memory as an example.

First, as shown in FIG. 20, all memory cells (memory cell arrays) in a chip are brought into an erased state ("1" -state). Thereafter, a diagonal pattern is written in the memory cell array.

That is, the block No. Of the memory cells existing in 0, “0” − is assigned to the memory cell of the first bit from the left end (the memory cell existing in the leftmost column).
Write data. Subsequently, the block No. “0” -data is written to the memory cell of the second bit from the left end among the memory cells existing in 1. Similarly, block No. n of the memory cells existing in n
“0” -data is written into the memory cell of the +1 bit.

In this way, all block Nos.
0, No. 1,... "0" -data is written to a predetermined memory cell in n, and a diagonal pattern is completed.

Thereafter, the block No. 0, No. 1,
・ ・ No. By sequentially reading the data of the memory cells in n, it is possible to detect whether or not the block of the memory cell array is multi-selected.

For example, in the example of FIG. 1, No. 2 shows a case where multi-selection is performed. In this case, the block No. 1, No. When the data of the memory cells in the memory cell 2 are read out, both of them become “1001”.
.., 111111...
(In the case of block No. 1) or the expected value "11011111111 ..." (in the case of block No. 2), that is, two adjacent block Nos. It is detected that 2 is multi-selected.

In the example shown in FIG. 21, two block Nos. 1, No. 4 shows a case where multi-selection is performed. In this case, the block No. 1, No. 4
When the data of the memory cells in the memory cell are read out,
.., And the expected value “101111”
1111... (In the case of block No. 1) or the expected value “1111011111.
At the time). In other words, two block Nos. 1, No. 4 is detected to be multi-selected.

Further, the example of FIG. 22 shows a case where there are a plurality of portions (defective portions) to be multi-selected. In this case, the block No. 1, No. 3, No. 5
When the data of the memory cells in the memory cell are read out,
01011111... "And the expected value" 101111
.. (At the time of block No. 1) or the expected value “1110111111.
) Or expected value “1111101111...”
(In the case of block No. 5). That is, the block No. 1, No. 3, No. 5 is detected to be multi-selected.

However, in the above-described test sequence, a multi-selection failure may not be detected depending on the mode of the multi-selection.

For example, as shown in FIG.
o. 0, No. 1 is multi-selected and block N
o. 0, No. 2 is multi-selected (block N
o. 1, No. 2 is not multi-selected).

In the semiconductor memory, first, a die sort test is performed.

At the time of the die sort test, for example, FIG.
As described above, by using a diagonal pattern as described above, it is possible to detect whether or not a block of a memory cell array is multi-selected (a method using a so-called checker pattern is also known as another test method). ing).

As a result of the die sort test, block no.
0, No. 1 is multi-selected and block No. 1 is selected.
0, No. It turns out that 2 is multi-selected.

Accordingly, these defective block Nos. 1, N
o. 2, No. 3 can be replaced with a spare block, the defective block No. 1, No.
2, No. 3 is replaced with a spare block. 1, No. 2, No. Relief 3

In the case of a NAND flash memory, usually, one or more spare blocks are provided in one semiconductor memory (chip) in consideration of an increase in chip area and an increase in cost. However, as in this example, when only one spare block is provided in one semiconductor memory, for example, all the defective block Nos. 1, No. 2, No. 3 cannot be rescued.

Therefore, as shown in this example, the number of defective blocks is three.
If there is one, only one defective block is replaced with a spare block, and the remaining two defective blocks are not used as bad blocks. That is, in the NAND flash memory, a chip having a block that cannot be remedied by the spare block is not discarded as a defective product but is adopted as a good product having a bad block.

By the way, after various product tests after assembling, a bad block mark is written on a bad block having a bad block so that the bad block is not used.

However, after the above-mentioned die sort test,
Complete non-defective products (products having no defective blocks and products in which all of the defective blocks are replaced with spare blocks) and non-defective products having bad blocks are combined into one, and assembly is performed on these non-defective products at once. That is, it is not possible to determine whether or not a product after assembly has a bad block.

Therefore, after various product tests after assembly, a bad block mark is written to the bad block, so that a test for detecting a multi-selection defect must be performed again for all products. No.

In this test, conventionally, depending on the mode of multi-selection, a multi-selection failure may not be detected.

Hereinafter, a specific description will be given.

As a precondition, in the above-mentioned die sort test, the defective block No. 0 is replaced with a spare block. 1, No. Let us consider the case where 2 is a bad block.

First, as shown in FIG. 24, all the memory cells (memory cell arrays) in the chip are brought into the erased state ("1" -state). Thereafter, a diagonal pattern is written in the memory cell array.

That is, as shown in FIG. 24, of the memory cells existing in the spare block (corresponding to block No. 0), the memory cell of the first bit from the left end (memory cell existing in the leftmost column) To "0" -data.

Subsequently, the block No. “0” -data is written to the memory cell of the second bit from the left end among the memory cells existing in 1. Here, block N
o. 0, No. Since block 1 is multi-selected, block No. 1 is selected. 0 and the block No. 1 are the same as each other (“10111111111”).
···")become.

Subsequently, as shown in FIG.
o. "0" -data is written into the memory cell of the third bit from the left end among the memory cells existing in 2.
Here, the block No. 0, No. Since block 2 is multi-selected, block No. 2 is selected. “0” -data is also written to the memory cell of the third bit from the left end among the memory cells in 0.

Therefore, the block No. The data pattern in block No. 2 is “11011111111. The data pattern in 0 is “1001111”.
111 ... ".

Similarly, block No. “0” -data is written to the memory cell of the (n + 1) th bit from the left end among the memory cells existing in n.

In this manner, all the block Nos.
0, No. 1,... "0" -data is written to a predetermined memory cell in n, and a diagonal pattern is completed.

Thereafter, the block No. 0, No. 1,
・ ・ No. The data of the memory cells in n are sequentially read, and it is detected whether or not the block of the memory cell array is multi-selected.

However, in the example of FIG.
0, No. 1 is multi-selected and block No. 1 is selected.
0, No. Despite the fact that 2 is multi-selected,
Block No. 1, No. The two read data both match the expected value. That is, the block No. The read data of “1” is “10111111111. 2 is “1101”.
111111... ", The block No. 0,
No. No. 1 cannot be detected even though it is a bad block.

The defective block No. 0 has been replaced with a spare block, so that block no.
0 and block No. 1 is multi-selected and block No. 1 is selected. 0 and block No. Even if 2 is multi-selected, it seems that there is no problem for normal operation.

However, overlooking such a multi-selection,
During normal operation, the bad block No. 1, No. The use of 2 causes a very serious problem.

For example, as shown in FIG. 26, each block (spare block and block N
o. 1 to No. n. Block No. 0 is not used. )
It is assumed that predetermined data (diagonal pattern) has been written.

In such a state, the block No.
Consider a case where data of all memory cells in 2 is erased. In this case, the block No. All the data of the memory cells in 2 are in the “1” -state (the state where the threshold value is low).
At this time, the block No. 0 and block No. Block No. 2 is multi-selected, so block No. 2 All the data of the memory cells in 0 are also “1” -state (the state where the threshold value is low).
Becomes

Thereafter, for example, as shown in FIG. It is assumed that the data of the memory cell in 1 is read. In this case, the block No. 1, the data read from the memory cell in “1” is “10111111111.
•, but “0” in the second bit from the left end changes to “1”.

The reason is as follows. 0 and block No. Since block 1 is multi-selected, block No. 1 is selected.
When data is read from the memory cell of block No. 1,
This is because the 0 memory cell is also electrically connected to the bit line. That is, since the bit line is common to all blocks, the block No. Although the bit line corresponding to the second bit from the left end in block 1 must maintain “H” (= “0”), block No. The memory cell of the second bit from the left end in 0 (the threshold value is “1” −
State), it changes to “L” (= “1”).

Therefore, as a conclusion, regardless of the multi-selection mode, a multi-selection defect is always detected for a product after assembly, and a bad block mark is written for a defective block (bad block). It is important not to use blocks.

Therefore, a method of always detecting a multi-selection defect regardless of the mode of multi-selection will be described with reference to FIGS. 27 to 29.

First, "0" -data is written to all memory cells in the chip (initial state).

Next, the spare block (block No. 0)
The data of the memory cell in () is read. At this time,
All data read from the spare block
Since it is “0” and matches the expected value, it is confirmed that the spare block has not been multi-selected (step ST1).

Thereafter, the data of all the memory cells in the spare block is erased ("1" -state), and subsequently, "0" -data is written to the memory cell of the first bit from the left end in the spare block. (Steps ST2 to ST
3).

Next, the block is shifted by one, and the block No. The data of the memory cell in 1 is read. At this time, the block No. Since the data read from 1 are all "0" and coincide with the expected values,
o. 1 cannot be detected (step ST
1).

Thereafter, the block No. 1 is erased ("1" -state), and then the data of the block No. 1 is erased. "0" -data is written to the memory cell of the second bit from the left end in 1 (steps ST2 to ST2).
3).

At this time, the block No. 0 and block N
o. Block No. 1 has been multi-selected, so block no.
0 are also erased, and the data of the block No. 0 is also erased. “0” -data is also written to the memory cell of the second bit from the left end in “0”.

Next, the block is shifted by one and the block N
o. The data of the memory cell in 2 is read. Here, the block No. The data of the memory cells in 2 are all
Although it is “0”, the block No. Block N at the same time as 2
o. Since block 0 is also selected (multi-selection), block N
o. 2 is “10111111”
11... ", Which is different from the expected value (ALL“ 0 ”).

Therefore, the block No. 2 are detected (step ST1).

Thereafter, the block No. 2 is erased (“1” -state), and then the data of the block No. 2 is erased. 2, "0" -data is written in the third bit memory cell from the left end (steps ST2 to ST2).
3).

At this time, the block No. 0 and block N
o. Block No. 2 is multi-selected, so block No. 2
0 are also erased, and the data of the block No. 0 is also erased. “0” -data is also written to the memory cell of the third bit from the left end in “0”.

Similarly, block No. The data of the memory cell in n is read (step ST1).
Block No. n, the data of all the memory cells in the block No. n are erased (step ST2). "0" -data is written into the memory cell of the (n + 1) th bit from the left end of n (step ST3).

When the above operation is completed for all the blocks, the data of all the blocks is sequentially read out.
Read (steps ST4 to ST5).

Then, by comparing data read from each block with an expected value (diagonal pattern), it is determined whether each block is good or bad.

For example, a spare block (block No.
The read data of 0) is “0111111111”, which matches the expected value, so that it is confirmed that the spare block is not multi-selected. Block N
o. The read data of No. 1 is “1111111111”
And does not match the expected value. 1 defect is detected. Block No. The read data of No. 2 is “11011111111”, which matches the expected value, but has already been read as described above (step ST1).
Since a defect is detected at block No. 2 is determined to be a bad block.

As described above, for example, as a result of the die sort test, the block No. 0 and block No. 1 is multi-selected and block No. 1 is selected. 0 and block No. 2 is multi-selected (block No. 1 and block N
o. 2 is not multi-selected), and after that, block No. When only the spare block is replaced with the spare block and the assembly is executed, the above-described test method is employed to obtain the block No. 1 and block no. 2 can be reliably detected.

[0057]

Conventionally, in order to detect a defective block and not use it as a bad block in a product after assembly,
Since a complicated test sequence as described above is required, there is a problem that a test time is increased and a manufacturing cost is increased.

The present invention has been made in order to solve the above-mentioned problem, and an object of the present invention is to provide a novel test method for detecting a defect in which a row (or a block) of a memory cell array is multi-selected at the time of access, and a new test method. An object of the present invention is to propose a test circuit to be executed and detect a multi-selection failure in a short time regardless of the type of test (die sort test, test after assembly, etc.).

[0059]

A semiconductor memory according to the present invention is provided in correspondence with a cell area in which a plurality of memory blocks are arranged and the plurality of memory blocks, and determines whether or not the plurality of memory blocks are selected. A plurality of row decoders to be determined, a common node commonly connected to the plurality of row decoders, and a multi-selection method in which two or more memory blocks are selected by one row address signal based on the potential of the common node. A failure detection circuit for detecting a failure, wherein the potential of the common node is changed according to the number of memory blocks selected by the one row address signal, and the multi-select failure is performed based on the potential of the common node. Is determined.

When the number of memory blocks selected by the one row address signal is one, the common node has the first potential, and the number of memory blocks selected by the one row address signal is two. In the case of more than one, the common node is at the second potential, and when the common node is at the second potential, it is determined that the multi-selection failure has occurred.

A row decoder corresponding to the memory block selected by the one row address signal discharges the common node, and the defect detection circuit charges the common node and selects the common node by the one row address signal. The potential of the common node is determined by the difference between the discharge capability of the common node by the row decoder corresponding to the memory block to be performed and the charging capability of the common node by the defect detection circuit.

Each row decoder has an internal node whose potential changes depending on whether or not a corresponding memory block is selected. Each row decoder determines whether or not to discharge the common node based on the potential of the internal node. To decide.

The internal node is input to the gate of an N-channel MOS transistor, the source of the N-channel MOS transistor is connected to a ground point, and the drain is connected to the common node.

A row decoder corresponding to a memory block selected by the one row address signal charges the common node, and the defect detection circuit discharges the common node and selects the common node by the one row address signal. The potential of the common node is determined by the difference between the charging capability of the common node by the row decoder corresponding to the memory block to be performed and the discharging capability of the common node by the defect detection circuit.

Each row decoder has an internal node whose potential changes depending on whether a corresponding memory block is selected, and each row decoder determines whether to charge the common node based on the potential of the internal node. To decide.

The internal node is input to the gate of a P-channel MOS transistor, the source of the P-channel MOS transistor is connected to a power supply node, and the drain is connected to the common node.

Each row decoder has an address decoder, and the internal node is an output node of the address decoder.

Each row decoder has a level shifter.
The internal node is an output node of the level shifter.

Each row decoder has an address latch circuit, and the internal node is an output node of the address latch circuit.

A semiconductor memory according to the present invention includes a cell area in which a plurality of word lines are arranged, and a plurality of row decoders provided corresponding to the plurality of word lines and determining whether to select the plurality of word lines. And a common node commonly connected to the plurality of row decoders, and a failure detection for detecting a multi-select failure in which two or more word lines are selected by one row address signal based on the potential of the common node. A potential of the common node is changed according to the number of word lines selected by the one row address signal, and the presence or absence of the multi-selection failure is determined based on the potential of the common node.

When the number of word lines selected by the one row address signal is one, the common node has the first potential, and the number of word lines selected by the one row address signal is two. In the case of more than one, the common node is at the second potential, and when the common node is at the second potential, it is determined that the multi-selection failure has occurred.

A row decoder corresponding to a word line selected by the one row address signal discharges the common node, and the failure detection circuit charges the common node and selects the common node by the one row address signal. The potential of the common node is determined by the difference between the discharge capability of the common node by the row decoder corresponding to the word line to be performed and the charging capability of the common node by the defect detection circuit.

Each row decoder has an internal node whose potential changes depending on whether or not a corresponding word line is selected. Each row decoder determines whether or not to discharge the common node based on the potential of the internal node. To decide.

The internal node is input to the gate of an N-channel MOS transistor, the source of the N-channel MOS transistor is connected to a ground point, and the drain is connected to the common node.

A row decoder corresponding to a word line selected by the one row address signal charges the common node, and the failure detection circuit discharges the common node and selects the common node by the one row address signal. The potential of the common node is determined by the difference between the charge capability of the common node by the row decoder corresponding to the word line to be performed and the discharge capability of the common node by the defect detection circuit.

Each row decoder has an internal node whose potential changes depending on whether or not the corresponding word line is selected. Each row decoder determines whether to charge the common node based on the potential of the internal node. To decide.

The internal node is input to the gate of a P-channel MOS transistor, the source of the P-channel MOS transistor is connected to a power supply node, and the drain is connected to the common node.

Each row decoder has an address decoder, and the internal node is an output node of the address decoder.

Each row decoder has a level shifter.
The internal node is an output node of the level shifter.

Each row decoder has an address latch circuit, and the internal node is an output node of the address latch circuit.

The test method of the present invention detects a multi-selection failure in which two or more memory blocks are selected by one row address signal in a cell area having a plurality of memory blocks. When one row address signal is input and the number of the memory blocks selected by the one row address signal is one, a common row address is provided to all of a plurality of row decoders provided corresponding to the plurality of memory blocks. When the number of the memory blocks selected by the one row address signal is two or more, the common node is set to the second potential, and the common node is set to the second potential. At the time of the second potential, it is determined that the multi-selection failure has occurred.

For example, in a die sort test, a memory block determined to have the multi-selection failure among the plurality of memory blocks is replaced with a spare block.

Further, for example, in a test after assembly, a memory block determined to have the multi-selection failure among the plurality of memory blocks is prohibited from being used, and the multi-memory block among the plurality of memory blocks is not used. Only the memory blocks determined not to have a selection failure can be used.

The test method of the present invention detects a multi-selection failure in which two or more word lines are selected by one row address signal for a cell area having a plurality of word lines. When one row address signal is input and the number of the word lines selected by the one row address signal is one, the row decoder is commonly used for all of a plurality of row decoders provided corresponding to the plurality of word lines. The connected common node is set to the first potential, and the number of the word lines selected by the one row address signal is two.
In the case of more than one, the common node is set to the second potential, and when the potential of the common node is the second potential, it is determined that the multi-selection failure has occurred.

Then, of the plurality of word lines, the word line determined to have the multi-selection failure is replaced with a spare word line.

[0086]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory according to the present invention will be described in detail with reference to the drawings.

The test method of the present invention can be applied to all semiconductor memories irrespective of the type of semiconductor memory (DRAM, SRAM, non-volatile memory, etc.). Etc.), which is a breakthrough that can be applied to all tests. However, in the following, a test of the NAND flash memory will be described for easy understanding.

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.
1 shows a main part of a NAND flash memory according to an embodiment.

In the cell area 11, a memory cell array is arranged. In this example, since the NAND type flash memory is assumed, the cell area 11 includes, for example, 16 memory cells connected in series and two select gate transistors connected one at each of both ends thereof. N
AND cell units are arranged in an array.

The NAND cell units in the row direction constitute one block. The NAND cell units in one block share word lines (control gate lines) WL0, WL1,... WL15 and select gate lines SG1, SG2.

One row decoder (block decoder) is provided corresponding to one block. For example,
Block No. 0 corresponds to the row decoder 12-0. 1, the row decoder 12-1 corresponds to the block No. 1; 2 corresponds to the row decoder 12-2. Row decoder 12-i (i = 0, 1,
,...) Are the block numbers. Word line WL in i
0, WL1,... WL15 and select gate line SG
1, SG2.

In this example, to simplify the description, the row address signals (block address signals) A0, A1, A2
Is 3 bits. The selection / non-selection of eight or less row decoders can be controlled by the 3-bit row address signals A0, A1, and A2. For example, "A
0, “A1” and “A2” are “0”, “0”,
When "0", the row decoder 12-0 is selected and "A"
0, “A1” and “A2” are “1”, “0”,
When "0", the row decoder 12-1 is selected and "A"
0 "," A1 ", and" A2 "are" 0 "," 1 ",
When "0", the row decoder 12-2 is selected.

Note that "/ A0", "/ A1", "/ A
"2" is an inverted signal of "A0", "A1", and "A2", respectively.

Each row decoder is provided with an RSEN node. This RSEN node is unique to the present invention. The RSEN node, as shown in FIG.
Channel MOS transistor Tr. It is connected to the ground point Vss via two current paths (source, drain). The N-channel MOS transistor Tr. The second gate is connected to an internal node of the row circuit.

This internal node is connected to the row decoder selection /
The node must be able to determine the non-selection. For example, when a row decoder is selected, the internal node of the selected row decoder is set to "H" level, and N-channel MOS transistor Tr. 2 is turned on. When a row decoder is not selected, the internal node of the unselected row decoder is set to the “L” level, and the N-channel MOS
Transistor Tr. 2 is turned off.

The internal node may be any node as long as it can determine whether the row decoder is selected or not. Specific examples of the internal node will be described in detail in the second to sixth embodiments.

The RSEN node of each row decoder is connected to the common node A, and the common node A is connected to the failure detection circuit 21. This failure detection circuit 21 is also unique to the present invention. Control signals SENn, LATCHn, and RESET are input to the failure detection circuit 21. The failure detection circuit 21 detects whether the row decoder is multi-selected by detecting the level of the common node A.

For example, when the row decoder is multi-selected, the output signal MFAIL of the failure detection circuit 21 becomes "H", and the row decoder selected by the row address signal at this time is determined to be defective. You. When the row decoder is not multi-selected, the output signal MFAIL of the failure detection circuit 21 becomes "L", and the row decoder selected by the row address signal at this time is determined to be good.

FIG. 3 shows an example of the defect detection circuit of FIG.

The control signal SENn is input to the inverter I1 and the NOR circuit NR1. The output node of inverter I1 is connected to common node A via resistor R (or N-channel MOS transistor Tr.1). The common node A is connected to the NOR circuit NR1.

The output signal MOUT of the NOR circuit NR1 and the control signal LATCHn are input to the NOR circuit NR2. Output signal of NOR circuit NR2 and control signal RESE
T is input to the latch circuit LATCH. The latch circuit LATCH has two flip-flop connected NOs.
It is composed of R circuits NR3 and NR4. Latch circuit LA
When the output signal of the TCH passes through the inverter I2, it becomes an output signal MFAIL indicating the presence or absence of a defect.

The feature of this failure detection circuit is that the level of the common node A changes according to the presence or absence of a multi-select failure.

For example, when the pass / fail is detected, the control signal S
Since ENn becomes “L”, the common node A is charged by the inverter I1. On the other hand, when detecting good / bad,
The MOS transistor Tr. In the selected row decoder.
2 (see FIG. 2) is turned on, so that the common node A
Is the MOS transistor Tr. 2 discharges.

That is, in a normal case (when multi-selection is not performed), only one row decoder is selected by one row address signal. In this case, the charging capacity of the inverter I1 is reduced by one. MOS transistor Tr. 2 so that it is stronger than the discharge capacity,
The level of the common node A becomes "H", and it can be recognized that the row decoder is good.

When a multi-select failure occurs, two or more row decoders are selected by one row address signal. In this case, two or more MOS transistors Tr. If the discharge capability of the common node A is made higher than the charging capability of the inverter I1, the level of the common node A becomes "L", and it can be recognized that the row decoder is defective.

As described above, in the present invention, the level of the internal node indicating whether or not a row decoder is selected is detected, and the potential level of the common node is changed according to the number of selected row decoders. Based on the potential level of the common node, it is determined whether there is a multi-selection failure of the row decoder.

Therefore, according to the test method of the present invention, unlike the related art, there is no need to write data (test pattern) to the memory cells and no need to read data from the memory cell array. This can contribute to a reduction in manufacturing cost.

Further, in the present invention, instead of writing data (test pattern) to the memory cells, the potential level of the common node is changed according to the number of selected row decoders, and the multi-selection failure of the row decoders is prevented. Since detection is performed, a multi-select failure can be accurately detected in all tests regardless of the type of test (die sort test, post-assembly test, etc.).

Next, the test method (circuit operation) of the present invention will be described with reference to the circuit diagrams of FIGS. 1 to 3 and the waveform diagrams of FIG.

First, the row address signals A0, A1, A2
, One row decoder (one block) is selected. In this example, the row decoder 12-0 is selected by the row address signals A0, A1, A2.

In the case where no multi-select failure has occurred In this case, the N-channel MOS in row decoder 12-0
Transistor Tr. 2 is turned on, the common node A is connected to one MOS transistor Tr. 2, and is connected to the ground point Vss.

Thereafter, the control signal (reset pulse) RE
When SET is input, the output signal of the latch circuit LATCH is reset to “L”. That is, the output signal MFAIL of the failure detection circuit becomes “H” (reset state).

When the control signal SENn is changed from "H" to "L", the output signal of the inverter I1 becomes
It changes from “L” to “H”. That is, the common node A is
It is connected to the power supply potential Vdd via the resistor R and the P-channel MOS transistor in the inverter I1.

As a result, the inverter I1 charges the common node A and raises the potential of the common node A, while the MOS transistor Tr. In the row decoder 12-0. 2 discharges the common node A to lower the potential of the common node A.

Therefore, the potential of the common node A depends on the charging capability of the common node A by the inverter I1 and the resistor R and the MOS transistor Tr. In the row decoder 12-0. 2 is determined by the magnitude relationship between the discharge capacities of the common node A and the common node A.

In the present invention, when the row decoder is not multi-selected, that is, when the common node A is a single MOS transistor Tr. 2, the charging capability of the common node A by the inverter I1 and the resistor R is higher than that of the MO in the row decoder 12-0.
S transistor Tr. 2 is set to be larger than the discharge capacity of the common node A by the second node.

For this reason, the potential of the common node A (RSEN)
The potential of the node) gradually increases, for example, the control signal S
After a certain period has elapsed since ENn became “L”,
It changes from “L (ground potential Vss)” to “H”.

Since the common node A is "H",
The output signal MOUT of the NOR circuit NR1 becomes "L". Thereafter, when the control signal LATCHn is set to “L”,
The output signal of the NOR circuit NR2 changes according to the level of the output signal MOUT of the NOR circuit NR1.

Needless to say, the time when the control signal LATCHn is set to "L" (the time when the latch pulse is input) is set after the potential of the common node A is sufficiently charged and becomes "H". .

In this example, the output signal M of the NOR circuit NR1 is
Since OUT is at "L", when the control signal LATCHn is set to "L", the output signal of the NOR circuit NR2 becomes
It becomes "H". When the output signal of the NOR circuit NR2 becomes “H”, the output signal of the latch circuit LATCH becomes
It becomes "H".

That is, the output signal MFAI of the defect detection circuit
L becomes “L”, and it is confirmed that the multi-selection failure of the row decoder has not occurred.

In the case where a multi-select failure has occurred When two or more row decoders have been multi-selected,
In this example, the case where the row decoder 12-1 is selected at the same time by the row address signal for selecting the row decoder 12-0 (multi-selection) is considered.

In this case, the row decoders 12-0, 12-
1 in the N-channel MOS transistor Tr. 2 are turned on, the common node A is connected to two MOS
Transistor Tr. 2 is connected to the ground point Vss.

Thereafter, the control signal (reset pulse) RE
When SET is input, the output signal of the latch circuit LATCH is reset to “L”. That is, the output signal MFAIL of the failure detection circuit becomes “H” (reset state).

When the control signal SENn is changed from "H" to "L", the output signal of the inverter I1 becomes
It changes from “L” to “H”. That is, the common node A is
It is connected to the power supply potential Vdd via the resistor R and the P-channel MOS transistor in the inverter I1.

As a result, the inverter I1 charges the common node A and raises the potential of the common node A.
MOS transistors Tr. In the row decoders 12-0 and 12-1. 2 discharges the common node A to lower the potential of the common node A.

Therefore, the potential of the common node A depends on the charging capability of the common node A by the inverter I1 and the resistor R and the MOS transistor Tr. In the row decoders 12-0 and 12-1. 2 is determined by the magnitude relationship between the discharge capacities of the common node A and the common node A.

In the present invention, when the common node A has two or more M
OS transistor Tr. 2 and two or more MOS transistors T
r. 2, the discharge capability of the common node A is
It is set so as to be larger than the charging capability of the common node A by 1 and the resistor R.

For this reason, the potential of the common node A (RSEN)
The node potential) is “L (for example, ground potential Vss)”.
To maintain.

Since the common node A is at "L",
The output signal MOUT of the NOR circuit NR1 becomes "H". Thereafter, when the control signal LATCHn is set to “L”,
The output signal of the NOR circuit NR2 changes according to the level of the output signal MOUT of the NOR circuit NR1.

In this example, the output signal M of the NOR circuit NR1 is
Since OUT is “H”, even if the control signal LATCHn is set to “L”, the output signal of the NOR circuit NR2 becomes
It remains at "L", and the output signal of the latch circuit LATCH remains at "L".

That is, the output signal MFAI of the defect detection circuit
L maintains “H”, and it is confirmed that a multi-selection failure of the row decoder has occurred.

Thereafter, the output signal MFAI of the defect detection circuit is output.
L is taken out of the chip. The above operation (test sequence) is performed for all the row decoders (blocks) by sequentially changing the row address signals A0, A1, and A2, thereby detecting a row decoder having a multi-selection failure.

As described above, according to the test method of the present invention, when the common node A is connected to the ground point Vss via one MOS transistor (when only one row decoder is selected), the inverter When the common node A is charged to the “H” level by the I1 and the resistor R2 and the common node A is connected to the ground point Vss via two or more MOS transistors (two or more row decoders are selected). Case), these MOS transistors
The common node A is discharged to the “L” level.

Therefore, in the test for multi-selection failure, it is not necessary to write data (test pattern) to the memory cells and it is not necessary to read data from the memory cell array, so that the test time can be greatly reduced and the manufacturing cost can be reduced. It can contribute to reduction. Also, regardless of the type of test (die sort test, post-assembly test, etc.), a multi-select failure can be accurately detected in all tests.

[Second Embodiment] A semiconductor memory according to a second embodiment of the present invention is a specific example of the semiconductor memory according to the above-described first embodiment.

FIG. 5 shows a main part of a NAND flash memory according to a second embodiment of the present invention.

In cell area 11, a memory cell array is arranged. In this example, since the NAND type flash memory is assumed, the cell area 11 includes, for example, 16 memory cells connected in series and two select gate transistors connected one at each of both ends thereof. N
AND cell units are arranged in an array.

The NAND cell units in the row direction constitute one block. The NAND cell units in one block share word lines (control gate lines) WL0, WL1,... WL15 and select gate lines SG1, SG2.

One row decoder is provided corresponding to one block. For example, the block No. 0 corresponds to the row decoder 12-0. 1
Corresponds to the row decoder 12-1.
2 corresponds to the row decoder 12-2. The row decoder 12-i (i = 0, 1, 2,...) Word lines WL0, WL1,... WL1 in i
5 and select gate lines SG1 and SG2.

In this example, the row address signals A0, A1 and A2 have three bits for the sake of simplicity. The selection / non-selection of eight or less row decoders can be controlled by the 3-bit row address signals A0, A1, and A2. For example, “A0”, “A1”, “A2”
Are "0", "0", and "0", respectively, the row decoder 12-0 is selected, and "A0", "A1", and "A2" are selected.
Are "1", "0", and "0", respectively, the row decoder 12-1 is selected, and "A0", "A1", "A2"
Are "0", "1", and "0", respectively, the row decoder 12-2 is selected.

Note that "/ A0", "/ A1", "/ A
"2" is an inverted signal of "A0", "A1", and "A2", respectively.

Each row decoder is provided with an RSEN node. This RSEN node is unique to the present invention. The RSEN node, as shown in FIG.
Channel MOS transistor Tr. It is connected to the ground point Vss via two current paths (source, drain). The N-channel MOS transistor Tr. The second gate is connected to the output node of the level shifter 14.

In the example shown in FIG. 6, the row decoder has an address decoder 13, a level shifter 14, and a transfer gate (driver) 15. Address decoder 1
3 decodes the row address signals A0, A1, A2. Address decoder 13 in the selected row decoder
Is at the "H" level. Level shifter 14
Converts the level of the output signal of the address decoder 13 and supplies it to the transfer gate 15.

The transfer gate 15 connects the first control gate lines CG0, CG1,... CG15 to the second control gate lines (word lines) WL0, WL1,. And the first select gate lines SGD, SGS
Are electrically connected to the second select gate lines SG1 and SG2.

Note that the potential is changed from the first control gate lines CG0, CG1,... CG15 and the first select gate lines SGD, SGS to the second control gate lines (word lines) WL0, WL1,. 2 are transferred to the select gate lines SG1 and SG2.

The output node of the level shifter 14 is a node that can determine the selection / non-selection of the row decoder. For example, when a row decoder is selected, the output node of level shifter 14 in the selected row decoder is set at "H" level, and N-channel MOS transistor Tr. 2 is turned on. When a row decoder is not selected, the output node of the level shifter 14 in the unselected row decoder is
"L" level, and N-channel MOS transistor Tr. 2 is turned off.

The RSEN node of each row decoder is connected to a common node A, and the common node A is connected to the failure detection circuit 21. This failure detection circuit 21 is also unique to the present invention. Control signals SENn, LATCHn, and RESET are input to the failure detection circuit 21. The failure detection circuit 21 detects whether the row decoder is multi-selected by detecting the level of the common node A.

For example, when the row decoder is multi-selected, the output signal MFAIL of the failure detection circuit 21 becomes "H", so that the row decoder selected by the row address signal at this time is determined to be defective. You. When the row decoder is not multi-selected, the output signal MFAIL of the failure detection circuit 21 becomes "L", and the row decoder selected by the row address signal at this time is determined to be good.

FIG. 7 shows an example of the defect detection circuit of FIG.

The control signal SENn is input to the inverter I1 and the NOR circuit NR1. The output node of inverter I1 is connected to common node A via resistor R (or N-channel MOS transistor Tr.1). The common node A is connected to the NOR circuit NR1.

The output signal MOUT of the NOR circuit NR1 and the control signal LATCHn are input to the NOR circuit NR2. Output signal of NOR circuit NR2 and control signal RESE
T is input to the latch circuit LATCH. The latch circuit LATCH has two flip-flop connected NOs.
It is composed of R circuits NR3 and NR4. Latch circuit LA
When the output signal of the TCH passes through the inverter I2, it becomes an output signal MFAIL indicating the presence or absence of a defect.

The feature of this failure detection circuit is that the level of the common node A changes according to the presence or absence of a multi-select failure.

For example, when the pass / fail is detected, the control signal S
Since ENn becomes “L”, the common node A is charged by the inverter I1. On the other hand, when detecting good / bad,
The MOS transistor Tr. In the selected row decoder.
2 (see FIG. 6) is turned on, so that the common node A
Is the MOS transistor Tr. 2 discharges.

That is, in a normal case (when multi-selection is not performed), only one row decoder is selected by one row address signal. In this case, the charging capability of the inverter I1 is reduced by one. MOS transistor Tr. 2 so that it is stronger than the discharge capacity,
The level of the common node A becomes "H", and it can be recognized that the row decoder is good.

If a multi-select failure occurs, two or more row decoders are selected by one row address signal. In this case, two or more MOS transistors Tr. If the discharge capability of the common node A is made higher than the charging capability of the inverter I1, the level of the common node A becomes "L", and it can be recognized that the row decoder is defective.

As described above, in the present invention, the level of the internal node indicating whether or not a row decoder is selected is detected, and the potential level of the common node is changed according to the number of selected row decoders. Based on the potential level of the common node, it is determined whether there is a multi-selection failure of the row decoder.

Therefore, according to the test method of the present invention, unlike the related art, there is no need to write data (test pattern) to the memory cells and no need to read data from the memory cell array, so that the test time is greatly reduced. This can contribute to a reduction in manufacturing cost.

Further, according to the present invention, instead of writing data (test pattern) to the memory cells, the potential level of the common node is changed according to the number of selected row decoders, and the multi-selection failure of the row decoders is prevented. Since detection is performed, a multi-select failure can be accurately detected in all tests regardless of the type of test (die sort test, post-assembly test, etc.).

Next, the test method (circuit operation) of the present invention will be described with reference to the circuit diagrams of FIGS. 5 to 7 and the waveform diagrams of FIG.

First, the row address signals A0, A1, A2
, One row decoder (one block) is selected. In this example, the row decoder 12-0 is selected by the row address signals A0, A1, A2.

In the case where no multi-select failure has occurred In this case, the level shifter 14 in the row decoder 12-0
Output signal attains the "H" level. Therefore, the N-channel MOS transistor T in the row decoder 12-0
r. 2 is turned on, and the common node A is connected to one MOS transistor Tr. 2 only, the ground point V
Connected to ss.

Thereafter, the control signal (reset pulse) RE
When SET is input, the output signal of the latch circuit LATCH is reset to “L”. That is, the output signal MFAIL of the failure detection circuit becomes “H” (reset state).

When the control signal SENn is changed from "H" to "L", the output signal of the inverter I1 becomes
It changes from “L” to “H”. That is, the common node A is
It is connected to the power supply potential Vdd via the resistor R and the P-channel MOS transistor in the inverter I1.

As a result, the inverter I1 charges the common node A and raises the potential of the common node A, while the MOS transistor Tr. In the row decoder 12-0. 2 discharges the common node A to lower the potential of the common node A.

Therefore, the potential of the common node A depends on the charging capability of the common node A by the inverter I1 and the resistor R and the MOS transistor Tr. In the row decoder 12-0. 2 is determined by the magnitude relationship between the discharge capacities of the common node A and the common node A.

In the present invention, when the row decoder is not multi-selected, that is, when the common node A is a single MOS transistor Tr. 2, the charging capability of the common node A by the inverter I1 and the resistor R is higher than that of the MO in the row decoder 12-0.
S transistor Tr. 2 is set to be larger than the discharge capacity of the common node A by the second node.

Therefore, the potential of the common node A (RSEN)
The potential of the node) gradually increases, for example, the control signal S
After a certain period has elapsed since ENn became “L”,
It changes from “L (ground potential Vss)” to “H”.

Further, since the common node A is at “H”,
The output signal MOUT of the NOR circuit NR1 becomes "L". Thereafter, when the control signal LATCHn is set to “L”,
The output signal of the NOR circuit NR2 changes according to the level of the output signal MOUT of the NOR circuit NR1.

Needless to say, the timing when the control signal LATCHn is set to "L" (the timing for inputting the latch pulse) is set after the potential of the common node A is sufficiently charged and turned to "H". .

In this example, the output signal M of the NOR circuit NR1 is
Since OUT is at "L", when the control signal LATCHn is set to "L", the output signal of the NOR circuit NR2 becomes
It becomes "H". When the output signal of the NOR circuit NR2 becomes “H”, the output signal of the latch circuit LATCH becomes
It becomes "H".

That is, the output signal MFAI of the failure detection circuit
L becomes “L”, and it is confirmed that the multi-selection failure of the row decoder has not occurred.

In the case where a multi-select failure has occurred When two or more row decoders have been multi-selected,
In this example, the case where the row decoder 12-1 is selected at the same time by the row address signal for selecting the row decoder 12-0 (multi-selection) is considered.

In this case, row decoders 12-0 and 12-
The output signals of the level shifters 14 in each 1 become "H" level. Therefore, the row decoders 12-0, 12-1
N-channel MOS transistor Tr. 2 are turned on, and the common node A is connected to the two MOS transistors Tr. 2 is connected to the ground point Vss.

Thereafter, the control signal (reset pulse) RE
When SET is input, the output signal of the latch circuit LATCH is reset to “L”. That is, the output signal MFAIL of the failure detection circuit becomes “H” (reset state).

When the control signal SENn is changed from "H" to "L", the output signal of the inverter I1 becomes
It changes from “L” to “H”. That is, the common node A is
It is connected to the power supply potential Vdd via the resistor R and the P-channel MOS transistor in the inverter I1.

As a result, the inverter I1 attempts to charge the common node A and raise the potential of the common node A,
MOS transistors Tr. In the row decoders 12-0 and 12-1. 2 discharges the common node A to lower the potential of the common node A.

Therefore, the potential of the common node A depends on the charging capability of the common node A by the inverter I1 and the resistor R and the MOS transistor Tr. In the row decoders 12-0 and 12-1. 2 is determined by the magnitude relationship between the discharge capacities of the common node A and the common node A.

In the present invention, when the common node A has two or more M
OS transistor Tr. 2 and two or more MOS transistors T
r. 2, the discharge capability of the common node A is
It is set so as to be larger than the charging capability of the common node A by 1 and the resistor R.

Therefore, the potential of the common node A (RSEN)
The node potential) is “L (for example, ground potential Vss)”.
To maintain.

Since the common node A is at "L",
The output signal MOUT of the NOR circuit NR1 becomes "H". Thereafter, when the control signal LATCHn is set to “L”,
The output signal of the NOR circuit NR2 changes according to the level of the output signal MOUT of the NOR circuit NR1.

In this example, the output signal M of the NOR circuit NR1
Since OUT is “H”, even if the control signal LATCHn is set to “L”, the output signal of the NOR circuit NR2 becomes
It remains at "L", and the output signal of the latch circuit LATCH remains at "L".

That is, the output signal MFAI of the failure detection circuit
L maintains “H”, and it is confirmed that a multi-selection failure of the row decoder has occurred.

Thereafter, the output signal MFAI of the defect detection circuit is output.
L is taken out of the chip. The above operation (test sequence) is performed for all the row decoders (blocks) by sequentially changing the row address signals A0, A1, and A2, thereby detecting a row decoder having a multi-selection failure.

As described above, according to the test method of the present invention, when the common node A is connected to the ground point Vss via one MOS transistor (when only one row decoder is selected), the inverter When the common node A is charged to the “H” level by the I1 and the resistor R2 and the common node A is connected to the ground point Vss via two or more MOS transistors (two or more row decoders are selected). Case), these MOS transistors
The common node A is discharged to the “L” level.

Therefore, in a test for a multi-selection failure, there is no need to write data (test pattern) to the memory cells and no need to read data from the memory cell array, so that the test time can be greatly reduced and the manufacturing cost can be reduced. It can contribute to reduction. Also, regardless of the type of test (die sort test, post-assembly test, etc.), a multi-select failure can be accurately detected in all tests.

[Third Embodiment] A semiconductor memory according to a third embodiment of the present invention is a modification of the semiconductor memory according to the above-described second embodiment.

The circuit configuration of the semiconductor memory of this embodiment is exactly the same as the circuit configuration of the semiconductor memory according to the second embodiment (FIGS. 5 and 7). However, the semiconductor memory according to the present embodiment is different from the semiconductor memory according to the above-described second embodiment in that an N-channel MOS transistor T is used to detect selection / non-selection of a row decoder.
r. 2 are different from each other.

FIG. 9 shows a main part of a row decoder of a NAND flash memory according to a third embodiment of the present invention.

The row decoder is provided with an RSEN node. This RSEN node is an N-channel MOS
Transistor Tr. 2 current paths (source, drain)
And is connected to the ground point Vss. N channel M
OS transistor Tr. 2 is connected to the output node of the address decoder 13.

The row decoder includes an address decoder 13,
Level shifter 14 and transfer gate (driver)
15. The address decoder 13 decodes the row address signals A0, A1, A2. The output signal of the address decoder 13 in the selected row decoder is
It becomes "H" level. The level shifter 14 converts the level of the output signal of the address decoder 13 and supplies the level to the transfer gate 15.

The transfer gate 15 connects the first control gate lines CG0, CG1,... CG15 to the second control gate lines (word lines) WL0, WL1,. And the first select gate lines SGD, SGS
Are electrically connected to the second select gate lines SG1 and SG2.

Note that the potential is changed from the first control gate lines CG0, CG1,... CG15 and the first select gate lines SGD, SGS to the second control gate lines (word lines) WL0, WL1,. 2 are transferred to the select gate lines SG1 and SG2.

The output node of the address decoder 13 is a node that can determine selection / non-selection of a row decoder.
For example, when a row decoder is selected, the address decoder 13 in the selected row decoder is selected.
Is set at "H" level, and N-channel MOS transistor Tr. 2 is turned on. Also,
When the row decoder is not selected, the output node of the address decoder 13 in the unselected row decoder is set to the “L” level, and the N-channel MO is set.
S transistor Tr. 2 is turned off.

With such a configuration, the same effect as that of the semiconductor memory according to the second embodiment can be obtained.

[Fourth Embodiment] The semiconductor memory according to the fourth embodiment of the present invention is a modified example of the semiconductor memory according to the above-described second embodiment.

The circuit configuration of the semiconductor memory according to the present embodiment (FIGS. 10 and 12) is exactly the same as the circuit configuration of the semiconductor memory according to the second embodiment (FIGS. 5 and 7). However, the semiconductor memory according to the present embodiment is different from the semiconductor memory according to the above-described second embodiment in the circuit configuration of the row decoder (FIGS. 6 and 11).

Note that the circuit configurations in FIGS. 10 and 12 are the same as the circuit configurations in FIGS. 5 and 7, and therefore description thereof is omitted. Hereinafter, only the configuration of the row decoder will be described.

FIG. 11 shows a main part of a row decoder of a NAND flash memory according to a fourth embodiment of the present invention.

The row decoder has an RSEN node. This RSEN node is an N-channel MOS
Transistor Tr. 2 current paths (source, drain)
And is connected to the ground point Vss. N channel M
OS transistor Tr. 2 is a level shifter 1
4 output nodes.

The row decoder comprises an address decoder 13,
Level shifter 14, transfer gate (driver) 1
5 and an address latch circuit 16. The address decoder 13 decodes the row address signals A0, A1, A2. The output signal of the address decoder 13 in the selected row decoder becomes "H" level. The address latch circuit 16 latches the decoded address signal (decode signal). The level shifter 14 converts a level of an output signal of the address latch circuit 16 and supplies the converted signal to the transfer gate 15.

The transfer gate 15 connects the first control gate lines CG0, CG1,... CG15 to the second control gate lines (word lines) WL0, WL1,. And the first select gate lines SGD, SGS
Are electrically connected to the second select gate lines SG1 and SG2.

Note that the potential is changed from the first control gate lines CG0, CG1,... CG15 and the first select gate lines SGD, SGS to the second control gate lines (word lines) WL0, WL1,. 2 are transferred to the select gate lines SG1 and SG2.

The output node of the level shifter 14 is a node that can determine selection / non-selection of a row decoder. For example, when a row decoder is selected, the output node of level shifter 14 in the selected row decoder is set at "H" level, and N-channel MOS transistor Tr. 2 is turned on. When a row decoder is not selected, the output node of the level shifter 14 in the unselected row decoder is
"L" level, and N-channel MOS transistor Tr. 2 is turned off.

With such a configuration, the same effect as that of the semiconductor memory according to the second embodiment can be obtained.

The operation (test method) of the semiconductor memory according to the present embodiment is as shown in a waveform diagram of FIG. The detailed description is the same as that of the above-described second embodiment, and thus will not be repeated.

[Fifth Embodiment] The semiconductor memory according to the fifth embodiment of the present invention is a modified example of the semiconductor memory according to the above-described fourth embodiment.

The circuit configuration of the semiconductor memory according to the present embodiment is exactly the same as the circuit configuration of the semiconductor memory according to the above-described fourth embodiment (FIGS. 10 and 12). However, the semiconductor memory according to the present embodiment is different from the semiconductor memory according to the above-described fourth embodiment in that the selection / selection of the row decoder is performed.
In order to detect non-selection, an N-channel MOS transistor Tr. 2 are different from each other.

FIG. 14 shows a main part of a row decoder of a NAND flash memory according to the fifth embodiment of the present invention.

[0210] The row decoder is provided with an RSEN node. This RSEN node is an N-channel MOS
Transistor Tr. 2 current paths (source, drain)
And is connected to the ground point Vss. N channel M
OS transistor Tr. 2 is connected to the output node of the address latch circuit 16.

The row decoder includes an address decoder 13,
Level shifter 14, transfer gate (driver) 1
5 and an address latch circuit 16. The address decoder 13 decodes the row address signals A0, A1, A2. The output signal of the address decoder 13 in the selected row decoder becomes "H" level. The address latch circuit 16 latches the decoded address signal (decode signal). The level shifter 14 converts a level of an output signal of the address latch circuit 16 and supplies the converted signal to the transfer gate 15.

The transfer gate 15 connects the first control gate lines CG0, CG1,... CG15 to the second control gate lines (word lines) WL0, WL1,. And the first select gate lines SGD, SGS
Are electrically connected to the second select gate lines SG1 and SG2.

Note that the potential is changed from the first control gate lines CG0, CG1,... CG15 and the first select gate lines SGD, SGS to the second control gate lines (word lines) WL0, WL1,. 2 are transferred to the select gate lines SG1 and SG2.

The output node of the address latch circuit 16 is
This node can determine whether the row decoder is selected or not. For example, if a row decoder is selected,
The output node of address latch circuit 16 in the selected row decoder is set at "H" level, and N-channel MOS transistor Tr. 2 is turned on.
When a row decoder is not selected, the output node of the address latch circuit 16 in the unselected row decoder is set to the “L” level, and the N-channel MOS transistor Tr. 2 is turned off.

In such a configuration, the same effect as that of the semiconductor memory according to the fourth embodiment can be obtained.

[Sixth Embodiment] The semiconductor memory according to the sixth embodiment of the present invention is a modification of the semiconductor memory according to the above-described fourth embodiment.

The circuit configuration of the semiconductor memory according to the present embodiment is exactly the same as the circuit configuration of the semiconductor memory according to the above-described fourth embodiment (FIGS. 10 and 12). However, the semiconductor memory according to the present embodiment is different from the semiconductor memory according to the above-described fourth embodiment in that the selection / selection of the row decoder is performed.
In order to detect non-selection, an N-channel MOS transistor Tr. 2 are different from each other.

FIG. 15 shows a main part of a row decoder of a NAND flash memory according to the sixth embodiment of the present invention.

[0219] The row decoder is provided with an RSEN node. This RSEN node is an N-channel MOS
Transistor Tr. 2 current paths (source, drain)
And is connected to the ground point Vss. N channel M
OS transistor Tr. 2 is connected to the output node of the address decoder 13.

The row decoder comprises an address decoder 13,
Level shifter 14, transfer gate (driver) 1
5 and an address latch circuit 16. The address decoder 13 decodes the row address signals A0, A1, A2. The output signal of the address decoder 13 in the selected row decoder becomes "H" level. The address latch circuit 16 latches the decoded address signal (decode signal). The level shifter 14 converts a level of an output signal of the address latch circuit 16 and supplies the converted signal to the transfer gate 15.

The transfer gate 15 electrically connects the first control gate lines CG0, CG1,... CG15 to the second control gate lines (word lines) WL0, WL1,. And the first select gate lines SGD, SGS
Are electrically connected to the second select gate lines SG1 and SG2.

It should be noted that the potential is changed from the first control gate lines CG0, CG1,... CG15 and the first select gate lines SGD, SGS to the second control gate lines (word lines) WL0, WL1,. 2 are transferred to the select gate lines SG1 and SG2.

The output node of the address decoder 13 is a node that can determine the selection / non-selection of the row decoder.
For example, when a row decoder is selected, the address decoder 13 in the selected row decoder is selected.
Is set at "H" level, and N-channel MOS transistor Tr. 2 is turned on. Also,
When the row decoder is not selected, the output node of the address decoder 13 in the unselected row decoder is set to the “L” level, and the N-channel MO is set.
S transistor Tr. 2 is turned off.

In such a configuration, the same effect as that of the semiconductor memory according to the fourth embodiment can be obtained.

[Seventh Embodiment] In the semiconductor memories according to the first to sixth embodiments described above, in order to detect whether or not a row decoder (block) is selected, a row decoder is provided in the row decoder. An N-channel MOS transistor for detecting the potential of the internal node of the decoder (selection = “H”, non-selection = “L”) is provided. In this case, the N-channel MOS transistor is connected between the common node and the ground point, and is set so that the potential level of the common node becomes "L" when a multi-selection failure occurs.

However, the transistor for detecting the internal node of the row decoder is, of course, an N-channel MOS.
It is not limited to transistors.

Therefore, in this embodiment, in order to detect whether or not the row decoder (block) is selected, the potential of the internal node of the row decoder (selection = “L”, unselected = "H") will be described. In this case, the P-channel MOS transistor
It is connected between a common node and a power supply node (for example, Vdd), and is set so that the potential level of the common node becomes “H” when a multi-select failure occurs.

Hereinafter, the semiconductor memory according to the present embodiment will be described in detail.

FIG. 16 shows a main part of a NAND flash memory according to the seventh embodiment of the present invention.

In the cell area 11, a memory cell array is arranged. In this example, since the NAND type flash memory is assumed, the cell area 11 includes, for example, 16 memory cells connected in series and two select gate transistors connected one at each of both ends thereof. N
AND cell units are arranged in an array.

The NAND cell units in the row direction constitute one block. The NAND cell units in one block share word lines (control gate lines) WL0, WL1,... WL15 and select gate lines SG1, SG2.

One row decoder is provided for one block. For example, the block No. 0 corresponds to the row decoder 12-0. 1
Corresponds to the row decoder 12-1.
2 corresponds to the row decoder 12-2. The row decoder 12-i (i = 0, 1, 2,...) Word lines WL0, WL1,... WL1 in i
5 and select gate lines SG1 and SG2.

In this example, the row address signals A0, A1 and A2 have three bits for the sake of simplicity. The selection / non-selection of eight or less row decoders can be controlled by the 3-bit row address signals A0, A1, and A2. For example, “A0”, “A1”, “A2”
Are "0", "0", and "0", respectively, the row decoder 12-0 is selected, and "A0", "A1", and "A2" are selected.
Are "1", "0", and "0", respectively, the row decoder 12-1 is selected, and "A0", "A1", "A2"
Are "0", "1", and "0", respectively, the row decoder 12-2 is selected.

Note that "/ A0", "/ A1", "/ A
"2" is an inverted signal of "A0", "A1", and "A2", respectively.

Each row decoder is provided with an RSE node. This RSE node is unique to the present invention. The RSE node is, as shown in FIG. 17, a P-channel MOS transistor Tr. 3 current paths (source,
(Drain) via the power supply node Vdd. Further, a P-channel MOS transistor Tr. The gate of No. 3 is connected to an internal node of the row circuit.

Vdd is the internal power supply potential. P
Channel MOS transistor Tr. Even if the “H” level of the internal node to which the gate of the third node is connected is Vdd,
Or Vpp, for example, the P-channel MOS transistor Tr. The source of 3 is connected to the Vdd node.

The internal node must be a node that can determine the selection / non-selection of the row decoder. For example, when a row decoder is selected, the internal node of the selected row decoder is set to "L" level, and P-channel MOS transistor Tr. 3 is turned on. When a row decoder is not selected, the internal node of the unselected row decoder is set to "H" level, and P-channel MOS transistor Tr. 3 is turned off.

The internal node may be any node as long as it can determine whether the row decoder is selected or not. Since the specific example of the internal node is the same as in the above-described second to sixth embodiments,
A detailed description thereof will be omitted.

An RSE node of each row decoder is connected to a common node A, and the common node A is connected to a failure detection circuit 21. This failure detection circuit 21 is also unique to the present invention. Control signals SEN, LATCH, and RESET are input to the failure detection circuit 21. The failure detection circuit 21 detects whether the row decoder is multi-selected by detecting the level of the common node A.

For example, when the row decoder is multi-selected, the output signal MFAIL of the failure detection circuit 21 becomes "H", and the row decoder selected by the row address signal at this time is determined to be defective. You. When the row decoder is not multi-selected, the output signal MFAIL of the failure detection circuit 21 becomes "L", and the row decoder selected by the row address signal at this time is determined to be good.

FIG. 18 shows an example of the defect detection circuit of FIG.

Control signal SEN is output from inverters I1 and N
The signal is input to the AND circuit ND1. The output node of inverter I1 is connected to common node A via resistor R (or N-channel MOS transistor Tr.1). The common node A is connected to the NAND circuit ND1.

The output signal MOUT of the NAND circuit ND1 and the control signal LATCH are input to the NAND circuit ND2. Output signal of NAND circuit ND2 and control signal RE
SET is input to the latch circuit LATCH. The latch circuit LATCH includes two NAND circuits ND3 and ND4 connected by flip-flops. The output signal MFAIL of the latch circuit LATCH is an output signal indicating whether or not the row decoder has a defect.

The feature of this failure detection circuit is that the level of the common node A changes according to the presence or absence of a multi-select failure.

For example, when the pass / fail is detected, the control signal S
Since EN becomes “H”, the common node A is discharged by the inverter I1. On the other hand, when the pass / fail is detected, the P-channel MOS transistor Tr. 3 (see FIG. 17) is turned on, so that the common node A is connected to the P-channel MOS transistor Tr.
3 is charged.

That is, in a normal case (when multi-selection is not performed), only one row decoder is selected by one row address signal. In this case, the discharge capability of inverter I1 is reduced by one. MOS transistor Tr. If it is made to be stronger than the charging ability by 3,
The level of the common node A becomes "L", and it can be recognized that the row decoder is good.

When a multi-select failure occurs, two or more row decoders are selected by one row address signal. In this case, two or more MOS transistors Tr. If the charging capability by 3 is made stronger than the discharging capability by the inverter I1, the level of the common node A becomes "H", and it can be recognized that the row decoder is defective.

As described above, in the present invention, the level of the internal node indicating whether or not a row decoder is selected is detected, and the potential level of the common node is changed according to the number of selected row decoders. Based on the potential level of the common node, it is determined whether there is a multi-selection failure of the row decoder.

Therefore, according to the test method of the present invention, unlike the related art, there is no need to write data (test pattern) to the memory cells and no need to read data from the memory cell array, so that the test time is greatly reduced. This can contribute to a reduction in manufacturing cost.

According to the present invention, the data (test pattern) is not written in the memory cell, but the potential level of the common node is changed in accordance with the number of selected row decoders to prevent multi-selection failure of the row decoder. Since detection is performed, a multi-select failure can be accurately detected in all tests regardless of the type of test (die sort test, post-assembly test, etc.).

Next, the circuit diagrams of FIGS.
The test method (circuit operation) of the present invention will be described with reference to the waveform chart of FIG.

First, the row address signals A0, A1, A2
, One row decoder (one block) is selected. In this example, the row decoder 12-0 is selected by the row address signals A0, A1, A2.

When Multi-selection Failure Does Not Occur In this case, the P-channel MOS in row decoder 12-0
Transistor Tr. 3 is turned on, the common node A is connected to one MOS transistor Tr. 3, and is connected to the power supply node Vdd.

Thereafter, the control signal (reset pulse) RE
When SET is input, the output signal of the latch circuit LATCH is reset to “H”. That is, the output signal MFAIL of the failure detection circuit becomes “H” (reset state).

When the control signal SEN is changed from "L" to "H", the output signal of the inverter I1 becomes
It changes from “H” to “L”. That is, the common node A is
It is connected to the ground GND via the resistor R and the N-channel MOS transistor in the inverter I1.

As a result, the inverter I1 discharges the common node A and tries to lower the potential of the common node A, while the MOS transistor T in the row decoder 12-0.
r. 3 charges the common node A and tries to raise the potential of the common node A.

Therefore, the potential of the common node A depends on the discharge capability of the common node A by the inverter I1 and the resistor R and the MOS transistor Tr. In the row decoder 12-0. 3 is determined by the magnitude relation of the charging capacity of the common node A.

In the present invention, when the row decoder is not multi-selected, that is, when the common node A is a single MOS transistor Tr. 3, the discharge capability of the common node A by the inverter I1 and the resistor R indicates that the MOS transistor Tr. 3 is set to be larger than the charging capability of the common node A by the third node.

For this reason, the potential of the common node A (the potential of the RSE node) gradually decreases, for example, the control signal SE.
After a certain period of time has elapsed since N became “H”,
It changes from “H” to “L”.

Since the common node A is at "L",
The output signal MOUT of the NAND circuit ND1 becomes “H”. Thereafter, when the control signal LATCH is set to “H”, N
The output signal of the AND circuit ND2 changes according to the level of the output signal MOUT of the NAND circuit ND1.

The time when the control signal LATCH is set to "H" (the time when the latch pulse is input) is determined by the common node A
It is needless to say that the potential is set after the potential is sufficiently discharged and becomes "L".

In this example, since the output signal MOUT of the NAND circuit ND1 is "H", when the control signal LATCH is set to "H", the output signal of the NAND circuit ND2 becomes
It becomes “L”. When the output signal of the NAND circuit ND2 becomes “L”, the output signal of the latch circuit LATCH becomes “L”.
It becomes “L”.

That is, the output signal MFAI of the failure detection circuit
L becomes “L”, and it is confirmed that the multi-selection failure of the row decoder has not occurred.

When Multi-selection Failure Occurs When two or more row decoders are multi-selected,
In this example, the case where the row decoder 12-1 is selected at the same time by the row address signal for selecting the row decoder 12-0 (multi-selection) is considered.

In this case, row decoders 12-0 and 12-
1 P-channel MOS transistor Tr. 3 are turned on, the common node A is connected to two MOS
Transistor Tr. 3 is connected to the power supply node Vdd.

Thereafter, control signal (reset pulse) RE
When SET is input, the output signal of the latch circuit LATCH is reset to “H”. That is, the output signal MFAIL of the failure detection circuit becomes “H” (reset state).

When the control signal SEN is changed from "L" to "H", the output signal of the inverter I1 becomes
It changes from “H” to “L”. That is, the common node A is
It is connected to the ground GND via the resistor R and the N-channel MOS transistor in the inverter I1.

As a result, the inverter I1 discharges the common node A to lower the potential of the common node A, and the MOS transistors T in the row decoders 12-0 and 12-1.
r. 3 charges the common node A and tries to raise the potential of the common node A.

Therefore, the potential of the common node A depends on the discharge capability of the common node A by the inverter I1 and the resistor R and the MOS transistors Tr. 3 is determined by the magnitude relation of the charging capacity of the common node A.

In the present invention, when the common node A has two or more M
OS transistor Tr. 3 and the power supply node Vdd
Is connected to two or more MOS transistors Tr. 3 is set to be greater than the discharging capability of the common node A by the inverter I1 and the resistor R.

For this reason, the potential of the common node A (the potential of the RSE node) maintains the “H” level.

Since the common node A is at “H”,
The output signal MOUT of the NAND circuit ND1 becomes "L". Thereafter, when the control signal LATCH is set to “H”, N
The output signal of the AND circuit ND2 changes according to the level of the output signal MOUT of the NAND circuit ND1.

In this example, since the output signal MOUT of the NAND circuit ND1 is "L", even if the control signal LATCH is set to "H", the output signal of the NAND circuit ND2 is
It remains at "H", and the output signal of the latch circuit LATCH remains at "H".

That is, the output signal MFAI of the defect detection circuit
L maintains “H”, and it is confirmed that a multi-selection failure of the row decoder has occurred.

Thereafter, the output signal MFAI of the defect detection circuit is output.
L is taken out of the chip. The above operation (test sequence) is performed for all the row decoders (blocks) by sequentially changing the row address signals A0, A1, and A2, thereby detecting a row decoder having a multi-selection failure.

As described above, in the test method of the present invention, when the common node A is connected to the power supply node (for example, Vdd) via one MOS transistor (when only one row decoder is selected) Has an inverter I1
When the common node A is discharged to “L” level by the resistor R2 and the common node A is connected to a power supply node (for example, Vdd) via two or more MOS transistors (two or more row decoders are used). If selected)
By these MOS transistors, the common node A is charged to "H" level.

Therefore, in the test for multi-selection failure, it is not necessary to write data (test pattern) to the memory cells and it is not necessary to read data from the memory cell array. It can contribute to reduction. Also, regardless of the type of test (die sort test, post-assembly test, etc.), a multi-select failure can be accurately detected in all tests.

[Others] In each of the above embodiments, the NA
Although the description has been made on the assumption that the ND type flash memory is used, as described above, the present invention is not limited to this.
Non-volatile semiconductor memory such as R-type flash memory, D
It is also applicable to RAM, SRAM, and the like. Here, in the above-described embodiment, multi-selection of a plurality of blocks is premised, but in the case of a DRAM or SRAM, this can be replaced with multi-selection of a plurality of word lines.

For example, in a row circuit of a semiconductor memory such as a DRAM or an SRAM, a predecode section and a main decode section may be provided, but a plurality of word lines selected by the predecode section are divided into one block. Therefore, the present invention may be applied.

[0280]

As described above, according to the semiconductor memory of the present invention, the level of an internal node indicating whether a row decoder (row or block) is selected is detected, and the number of selected row decoders is determined. The potential level of the common node is changed accordingly, and the presence or absence of the multi-selection failure of the row decoder is determined based on the potential level of the common node. Therefore, according to the test method of the present invention, there is no need to write data (test pattern) to the memory cells and no need to read data from the memory cell array, so that the test time can be greatly reduced and the manufacturing cost can be reduced. can do.

Further, in the semiconductor memory of the present invention, instead of writing data (test pattern) to the memory cells, the potential level of the common node is changed in accordance with the number of selected row decoders, and the Since a selection failure is detected, a multi-select failure can be accurately detected in all tests regardless of the type of test (die sort test, test after assembly, etc.).

[Brief description of the drawings]

FIG. 1 is a diagram showing a main part of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a row decoder of FIG. 1;

FIG. 3 is a circuit diagram showing an example of the defect detection circuit of FIG. 1;

FIG. 4 is a waveform chart showing an operation of the defect detection circuit of FIG. 3;

FIG. 5 is a diagram showing a main part of a semiconductor memory according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a row decoder of FIG. 5;

FIG. 7 is a circuit diagram showing an example of the defect detection circuit of FIG. 5;

FIG. 8 is a waveform chart showing the operation of the defect detection circuit of FIG. 7;

FIG. 9 is a diagram showing a row decoder of a semiconductor memory according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a main part of a semiconductor memory according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing an example of the row decoder of FIG. 10;

FIG. 12 is a circuit diagram illustrating an example of the failure detection circuit of FIG. 10;

FIG. 13 is a waveform chart showing the operation of the failure detection circuit of FIG.

FIG. 14 is a diagram showing a row decoder of a semiconductor memory according to a fifth embodiment of the present invention.

FIG. 15 is a diagram showing a row decoder of a semiconductor memory according to a sixth embodiment of the present invention.

FIG. 16 is a diagram showing a main part of a semiconductor memory according to a seventh embodiment of the present invention.

FIG. 17 is a diagram showing an example of the row decoder of FIG. 16;

FIG. 18 is a circuit diagram showing an example of the defect detection circuit of FIG.

FIG. 19 is a waveform chart showing the operation of the failure detection circuit of FIG. 18;

FIG. 20 is a diagram showing an example of a test method for detecting a multi-selection failure.

FIG. 21 is a diagram showing an example of a test method for detecting a multi-selection failure.

FIG. 22 is a diagram showing an example of a test method for detecting a multi-selection failure.

FIG. 23 is a diagram showing a problem of a conventional test method.

FIG. 24 is a diagram showing a problem of a conventional test method.

FIG. 25 is a diagram showing a problem of a conventional test method.

FIG. 26 is a diagram showing a problem of a conventional test method.

FIG. 27 is a diagram showing another example of a test method for detecting a multi-selection failure.

FIG. 28 is a diagram showing another example of a test method for detecting a multi-selection failure.

FIG. 29 is a flowchart showing another example of a test method for detecting a multi-selection failure.

[Description of Signs] 11: cell area, 12-0, 12-1, 12-2: row decoder, 13: address decoder, 14: level shifter, 15: transfer gate, 16: address latch circuit, 21: defect detection circuit , I1, I2: inverter, R: resistor, NR1, NR2, NR3, NR4: NOR circuit, ND1, ND2, ND3, ND4: NAND circuit, LATCH: latch circuit, Tr. 1, Tr. 2: N-channel MOS
Transistor, Tr. 3: P-channel MOS
Transistor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 11/401 G11C 11/34 302A 16/02 341C 16/04 341D 16/06 371A 371D 17/00 601Z 622E 622A 633A 639A F term (reference) 2G032 AA07 AB01 AB19 AK11 AK19 AL14 5B015 HH00 JJ00 KB44 NN09 RR06 5B024 AA15 BA18 CA07 CA17 EA01 EA02 5B025 AA01 AC01 AC03 AD02 AD13 AD16 CC10 CCA DDA CCA DDCC

Claims (27)

[Claims] 1. A cell area in which a plurality of memory blocks are arranged, a plurality of row decoders provided corresponding to the plurality of memory blocks, and determining whether or not the plurality of memory blocks are selected; A common node commonly connected to a row decoder; and a failure detection circuit for detecting a multi-select failure in which two or more memory blocks are selected by one row address signal based on the potential of the common node. And changing the potential of the common node according to the number of memory blocks selected by the one row address signal, and determining the presence or absence of the multi-selection failure based on the potential of the common node. Semiconductor memory. 2. When the number of memory blocks selected by the one row address signal is one, the common node is at the first potential, and the number of memory blocks selected by the one row address signal is two. 2. When there are two or more, the common node is at the second potential, and when the common node is at the second potential, it is determined that the multi-selection failure has occurred. The semiconductor memory according to any one of the preceding claims. 3. A row decoder corresponding to a memory block selected by the one row address signal discharges the common node, the failure detection circuit charges the common node, and outputs the one row address signal. The potential of the common node is determined by a difference between a discharge capability of the common node by a row decoder corresponding to the memory block selected by the above and a charging capability of the common node by the defect detection circuit. 2. The semiconductor memory according to 1. 4. Each row decoder has an internal node whose potential changes depending on whether or not a corresponding memory block is selected, and each row decoder discharges the common node based on the potential of the internal node. 4. The semiconductor memory according to claim 3, wherein it is determined whether or not the condition is satisfied. 5. The internal node is input to the gate of an N-channel MOS transistor, and is connected to the N-channel MOS transistor.
5. The semiconductor memory according to claim 4, wherein a source of the transistor is connected to a ground point, and a drain of the transistor is connected to the common node. 6. A row decoder corresponding to a memory block selected by said one row address signal charges said common node, said failure detection circuit discharges said common node, and said one row address signal. Wherein the potential of the common node is determined by a difference between a charging capability of the common node by a row decoder corresponding to the memory block selected by the method and a discharging capability of the common node by the defect detection circuit. 2. The semiconductor memory according to 1. 7. Each row decoder has an internal node whose potential changes depending on whether or not a corresponding memory block is selected, and each row decoder charges the common node based on the potential of the internal node. 7. The semiconductor memory according to claim 6, wherein it is determined whether or not the condition is satisfied. 8. The P-channel MOS transistor according to claim 8, wherein said internal node is input to a gate of a P-channel MOS transistor.
8. The semiconductor memory according to claim 7, wherein a source of the transistor is connected to a power supply node, and a drain of the transistor is connected to the common node. 9. The semiconductor memory according to claim 4, wherein each row decoder has an address decoder, and said internal node is an output node of said address decoder. 10. The semiconductor memory according to claim 4, wherein each row decoder has a level shifter, and said internal node is an output node of said level shifter. 11. The semiconductor memory according to claim 4, wherein each row decoder has an address latch circuit, and said internal node is an output node of said address latch circuit. 12. A cell area in which a plurality of word lines are arranged, a plurality of row decoders provided corresponding to the plurality of word lines, and determining whether or not the plurality of word lines are selected; A common node commonly connected to a row decoder; and a failure detection circuit for detecting a multi-select failure in which two or more word lines are selected by one row address signal based on the potential of the common node. And changing the potential of the common node according to the number of word lines selected by the one row address signal, and determining the presence or absence of the multi-selection failure based on the potential of the common node. Semiconductor memory. 13. When the number of word lines selected by the one row address signal is one, the common node is at the first potential and the number of word lines selected by the one row address signal is 13. When there are two or more, the common node is at the second potential, and when the common node is at the second potential, it is determined that the multi-selection failure has occurred. The semiconductor memory according to any one of the preceding claims. 14. A row decoder corresponding to a word line selected by said one row address signal discharges said common node, said failure detection circuit charges said common node, and said one row address signal The potential of the common node is determined by a difference between a discharge capability of the common node by a row decoder corresponding to a word line selected by the above and a charging capability of the common node by the defect detection circuit. 2. The semiconductor memory according to 1. 15. Each row decoder has an internal node whose potential changes depending on whether or not a corresponding word line is selected, and each row decoder discharges the common node based on the potential of the internal node. 15. The semiconductor memory according to claim 14, wherein it is determined whether or not the condition is satisfied. 16. The internal node includes an N-channel MOS.
Input to the gate of the transistor,
The semiconductor memory according to claim 15, wherein a source of the S transistor is connected to a ground point, and a drain of the S transistor is connected to the common node. 17. A row decoder corresponding to a word line selected by said one row address signal charges said common node, said failure detection circuit discharges said common node, and said one row address signal The potential of the common node is determined by a difference between a charging capability of the common node by a row decoder corresponding to the word line selected by the above and a discharging capability of the common node by the defect detection circuit. 13. The semiconductor memory according to item 12. 18. Each row decoder has an internal node whose potential changes depending on whether or not a corresponding word line is selected, and each row decoder charges the common node based on the potential of the internal node. 18. The semiconductor memory according to claim 17, wherein it is determined whether or not the current state is satisfied. 19. The internal node is a P-channel MOS
Input to the gate of the transistor, the P-channel MO
19. The semiconductor memory according to claim 18, wherein a source of the S transistor is connected to a power supply node, and a drain of the S transistor is connected to the common node. 20. The semiconductor memory according to claim 15, wherein each row decoder has an address decoder, and said internal node is an output node of said address decoder. 21. The semiconductor memory according to claim 15, wherein each row decoder has a level shifter, and said internal node is an output node of said level shifter. 22. Each of the row decoders has an address latch circuit, and the internal node is an output node of the address latch circuit.
9. The semiconductor memory according to 8. 23. A test method for detecting a multi-select failure in which two or more memory blocks are selected by one row address signal for a cell area having a plurality of memory blocks, wherein the one row address When a signal is input and the number of the memory blocks selected by the one row address signal is one, it is commonly connected to all of a plurality of row decoders provided corresponding to the plurality of memory blocks. When the number of the memory blocks selected by the one row address signal is two or more, the common node is set to the second potential, and the common node is set to the second potential. A test method, wherein it is determined that the multi-selection failure has occurred at the time of a potential. 24. The test method according to claim 23, wherein a memory block determined to have the multi-selection failure among the plurality of memory blocks is replaced with a spare block. 25. A memory block determined as having the multi-selection failure among the plurality of memory blocks is prohibited from being used, and it is determined that the multi-selection failure has not occurred among the plurality of memory blocks. A test method characterized in that only a used memory block can be used. 26. A test method for detecting a multi-select failure in which two or more word lines are selected by one row address signal for a cell area having a plurality of word lines, wherein the one row address When a signal is input and the number of the word lines selected by the one row address signal is one, the word line is commonly connected to all of a plurality of row decoders provided corresponding to the plurality of word lines. When the number of the word lines selected by the one row address signal is two or more, the common node is set to the second potential, and the common node is set to the second potential. A test method, wherein it is determined that the multi-selection failure has occurred at the time of a potential. 27. The test method according to claim 26, wherein a word line determined to have the multi-selection failure among the plurality of word lines is replaced with a spare word line.