KR19990079136A - Semiconductor memory device having redundant decoder circuit - Google Patents

Abstract

The redundant decoder circuit of the semiconductor memory device disclosed herein provides a redundancy enable circuit. The redundancy enable circuit enables the redundant decoder circuit in response to a redundancy enable signal, and the redundancy enable signal is activated in advance of the output control signal in synchronization with an external clock signal when a defective cell is replaced. Such a device can reduce the speed delay of the redundant decoder circuit.

Description

Semiconductor Memory Device with Redundant Decoder Circuit (SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANT DECODER CIRCUIT)

The present invention relates to a redundant decoder circuit, and more particularly to a redundant decoder circuit that can reduce the speed delay.

The memory device includes a main memory cell array for storage of binary data, as well as an array of redundant memory cells for replacing defective cells on each of its rows and columns. redundant memory cells are provided. Each redundant cell is connected to each redundant word and bit lines. During the inspection of the main memory cell array, if several to thousands of defective cells are found, they are replaced by redundant memory cells. This keeps the entire chip as a non-defective article.

In Fig. 1, in the semiconductor memory integrated circuit device 1, a redundant decoder circuit and its peripheral circuits for storing repair addresses and distinguishing whether row or column addresses correspond to the repair addresses are shown. have. Although not shown in the figure, the redundant row / column predecoder circuit 4 and the redundant row / column decoder circuit 6 are each composed of a plurality of redundant predecoders and a plurality of redundant decoders. In order to replace defective memory cells with redundant cells, a circuit for storing the location information of the defective cells, that is, repair addresses, and a circuit input for identifying whether the addresses input from the outside correspond with the repair addresses. I need a circuit. This is done by the redundant decoder circuit.

The redundant row / column decoder circuitry, although not shown, accepts the row / column address signals and is activated by the redundancy enable signal. As is well known, the row redundant decoder circuit drives redundant word lines, and the column redundant decoder circuit drives column select lines for selecting redundant bit line pairs. In the redundant decoder circuit, the fuse Fm is cut when relief of defective cells is necessary, but the fuse is not blown when relief of defective cells is unnecessary.

Accordingly, it is an object of the present invention to provide a redundant decoder circuit that can accelerate the activation time of the redundant decoder circuit and reduce the standby current in the stop clock mode.

1 is a schematic block diagram of a semiconductor memory device:

2 is a circuit diagram of a redundant decoder circuit:

3 is a circuit diagram of a redundant decoder circuit according to the present invention:

4 is an output timing diagram of a redundant decoder enable signal and a redundancy control signal according to a clock signal of the present invention.

* Explanation of symbols on main parts of the drawings

10: redundancy enable circuit 20: address storage circuit

30: output circuit

(Configuration)

According to one aspect of the present invention, a redundant decoder circuit includes: a redundant enable circuit for enabling the redundant decoder circuit in response to a redundant enable signal; An address storage circuit for storing an address corresponding to the defective cell; And an output circuit for outputting a redundant word line / redundant bit line selection signal corresponding to a defective cell in response to an output control signal, wherein the redundant enable signal is synchronized with an external clock signal when the defective cell is replaced. It is activated earlier.

In a preferred embodiment, the redundant enable circuit is disabled by the redundant enable signal in the stop clock mode.

In a preferred embodiment, the output control signal is activated later than the redundancy enable signal and deactivated earlier than the redundancy enable signal.

Such a device can reduce the speed delay of the redundant decoder circuit according to the chip select signal in the chip select mode.

(First embodiment)

Next, a preferred embodiment of a redundant decoder circuit according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2, the redundant decoder circuit includes a redundant enable circuit 10 for enabling a redundancy decoder circuit in the presence of a defective cell, an address storage circuit 20 for storing an address corresponding to the defective cell, and a redundant word. And an output circuit 30 for outputting a signal R_DECOUT for selecting a line or a redundant bit line.

However, it is activated by CSDESEL, which is generated by the chip select signal CS, which is caused by at least two flip-flops in the synchronous SRAM when CS is activated. This can cause a delay in speed. Therefore, CSDESEL may be activated later than RED_2ND.

(Second embodiment)

Referring to FIG. 3, since the redundant enable circuit RED_CLK is 'H' synchronized with the clock signal, the redundant enable circuit is disabled, thereby reducing the standby current in the stop clock mode.

3 is a circuit diagram illustrating a configuration of a redundant decoder circuit of the semiconductor memory device of FIG. 1.

The redundant decoder circuit includes a redundancy enable circuit 10 for enabling in the presence of a defective cell, an address storage circuit 20 for storing an address corresponding to the defective cell, and a signal for selecting a redundant word line or a redundant bit line. And an output circuit 30 for outputting (R_DECOUT).

The redundancy enable circuit 10 includes a latch circuit I1 and NM2 for initializing a master fuse Fm, which is cut in the presence of a defective cell, and a first node N1 connected to an end of the master fuse Fm, And precharge transistors PM1 and PM2 for precharging the second node N2.

The address storage circuit 20 includes inverters that accept fuse pairs {(F0, F0 ') to (Fn, Fn') and external addresses AD_0A to AD_An, all of which are connected to the first node N1. (RI1 to RIn + 1) and transistor pairs {(RN0, RN0 ') to (RNn, RNn') for discharging the voltage charged in the second node N2. The output circuit 30 includes transfer gates and latch circuits I4 and I5 which are turned on and off in response to the output control signal RED_2ND synchronized with the clock signal XCLK.

Referring back to FIG. 2, the CSDESEL output from the chip select buffer is applied as a redundant enable signal to precharge the second node N2 to a high level. However, since the CSDESEL is a signal generated from the chip select address buffer through the first clock and the second clock, the speed is delayed. At this time, the CSDESEL is activated later than RED_2ND, and thus the REDMUX is not transmitted. However, the transfer gate is already turned on and the speed of the selection signal R_DECOUT becomes slow.

Referring to FIG. 4, in the redundant decoder circuit, the master fuse Fm is cut in the non-selected mode, and the power supplied to the chip is raised to VDD to output a signal PORSET having a constant pulse width. This is applied to the gate of NM1 connected in series with the master fuse Fm to initialize the first node N1 to which the latch circuits I1 and NM2 are commonly connected to the low level. Accordingly, the PM2 is turned on together with the PM1 receiving the low level redundancy enable signal RED_CLK, which is synchronized with the external clock signal XCLK, to precharge the second node N2 to the power supply voltage level. An NMOS transistor NM2 receiving the RED_CLK is connected to the gate between the second node N2 and ground, which is a DC current in a deselect mode in which a defective cell repair is not performed. It blocks the path. In addition, in the stop clock mode (stop clcok mode), the redundant enable signal is disabled to block the DC current path.

Subsequently, the second node N2 is discharged at a low level when the address stored in the fuses {(F0, F0 ') to (Fn, Fn') and the address AD_A0 to AD_An applied from the outside match. It is charged. This is because the signal RED_2ND, which is activated later than the redundant enable signal RED_CLK, passes through the transfer gate and the latch circuit, and a high level selection signal R_DECOUT is output. The select signal R_DECOUT selects either the redundant word lines or the redundant bit lines.

As described above, the second node N2 can be precharged faster by controlling the on / off of the PM1, PM2, and NM2 with the RED_CLK synchronized with the external clock signal XCLK regardless of the chip select signal. In addition, since it is always activated before RED_2ND, the output delay of R_DECOUT can be reduced as CSDESEL is activated later than the conventional RED_2ND. This is because RED_CLK is immediately output in synchronization with the external clock signal XCLK. In the present invention, since the RED_CLK remains inactive at a high level in the stop clock mode in which the clock signal XCLK no longer occurs, PM1 may be turned off to prevent the flow of DC current.

In general, in the CS non-select mode, the current flows in the redundant decoder during the low level of RED_CLK, which is about 300 mA, which is a small amount of current that has little effect on the CS select mode.

3 and 4, the redundant decoder circuit performs address coding according to the redundancy decoder enable signal RED_CLK synchronized with the external clock signal XCLK and the control signal RED_2ND, so that a redundant word corresponding to a defective cell is provided. The line or redundant bit line is selected. However, it should be noted that the redundancy decoder enable signal RED_CLK must be activated before the output control signal RED_2ND.

As a result, the present invention can prevent the speed delay of the redundant decoder circuit and reduce the standby current consumption by blocking the DC current path in the stop clock mode.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

Therefore, the present invention can reduce the delay of the operation speed of the redundant decoder by advancing the activation time of the redundant decoder circuit, and also reduce the standby current consumption.

Claims (4)

A semiconductor memory device comprising a redundant decoder circuit for selecting a redundant word line or a redundant bit line when replacing defective cells with redundant cells. The redundant decoder circuit is A redundancy enable circuit for enabling the redundant decoder circuit in response to a redundancy enable signal; An address storage circuit for storing an address corresponding to the defective cell; An output circuit for outputting a redundant word line / redundant bit line selection signal corresponding to the defective cell in response to the output control signal, The redundancy enable signal is activated prior to the output control signal in synchronization with an external clock signal when a defective cell is replaced. The method of claim 1, And the redundancy enable circuit is disabled by the redundancy enable signal in a stop clock mode. The method of claim 1, And the output control signal is activated later than the redundancy enable signal in synchronization with an external clock. The method of claim 1, And the output control signal is activated later than the redundancy enable signal and deactivated prior to the redundancy enable signal.