JP2003058367A - Arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic unit without necessity of time management of a pipeline by a program. SOLUTION: The arithmetic unit inputs output data taken out from a register file 18 to be outputted after storing input data in operation means 26, 28 and feeds back arithmetic data obtained by performing a pipeline arithmetic processing according to a prescribed arithmetic program by the arithmetic means to the input side of the register file. There is provided a control means 13 to block transmission of the output data so that the output data from the register file is not inputted to the input side of the arithmetic means until the arithmetic data obtained by previously performing the arithmetic processing by the arithmetic means is reflected on the output data of the register file.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device, and more particularly, to an arithmetic device which does not require a program to perform time management of an arithmetic device which operates by pipeline processing.

[0002]

2. Description of the Related Art There is an arithmetic unit that controls an arithmetic procedure by listing instructions in a program and pipelines arithmetic circuits to perform arithmetic operations. In this device, instructions (instructions) are divided into fine processing units, and these are overlapped and processed to speed up the processing. The instruction processing is divided into steps such as instruction reading, instruction decoding, data reading, and instruction execution,
Multiple instructions (instructions) are shifted little by little and operated in parallel to improve processing time efficiency. In the case of an arithmetic device that controls an arithmetic procedure by enumerating instructions (instructions) in a program in this way, the address of the register file in which the data to be input to the arithmetic circuit is stored (stored) and the output of the arithmetic circuit are stored. The register file address and the type of operation are described for each instruction.

[0003]

When the operation circuit is pipelined, the operation input data of the next instruction is acquired before the result of the operation performed by the previous instruction (instruction) is stored in the register file. The register file for is read. Therefore, when the operation result performed by the previous instruction of the program is stored in the register file and the operation result stored in the register file by the next instruction is used as the operation input data, when It becomes necessary for the program to perform time management of the pipeline so that the instruction file is read after the operation result of the previous instruction is stored in the register file by inserting another instruction. However, there has been a problem that a time management program that uses such a procedure is complicated and it takes time to create the program.

When the arithmetic circuit is pipelined and the number of pipeline stages differs depending on the type of operation, the address (storage location) of the register file that stores the operation result of the previous instruction and the operation to be performed by the next instruction. The address (storage location) of the register file that stores the result is the same, and the time (timing) for storing the result of the operation to be performed in the register file is the same as the time (timing) for storing the result of the operation that was performed previously. In the former case, there is a problem that either one of the operation result data cannot be stored, or the order of the stored data does not match the program. As a countermeasure for this, it is necessary to create a program while considering the time (timing) at which the calculation result is stored in the register file, which complicates the creation of the program and takes a long time to create the program. .

Therefore, the present invention has been made in view of the above problems, and in particular, when the time management of the pipeline of the arithmetic circuit is influenced by the data of the arithmetic result previously performed, the arithmetic means is provided. Transmission of the output data so that the output data from the register file is not input to the input side of the calculation means until the calculation data obtained by the previous calculation processing is reflected in the output data of the register. An object of the present invention is to provide an arithmetic unit that does not need to consider the timing of storing the operation result in the register file when creating the program and has no need to manage the pipeline time by the program, by having the control means for preventing the operation. To do.

Further, the present invention particularly relates to the storage location of the register file for storing the operation data obtained by the operation processing to be performed as the input data and the register for storing the operation data obtained by the previous operation processing. It is the same as the storage location of the file, and the storage time of the operation data obtained by the operation processing to be performed in the register file is the same as the storage time of the operation data obtained by the previous operation processing in the register file. If it is the same as or earlier than the time, the input of the arithmetic means is continued until the arithmetic data obtained by the arithmetic processing previously performed by the arithmetic means is reflected in the input data of the register file. Up to now, by providing the side with control means for preventing the transmission of the output data so that the output data from the register file is not inputted, And to provide a unnecessary computing device consider the operation result the time stored in the register file when creating program as.

[0007]

As means for achieving the above-mentioned object, the invention as set forth in claim 1 is such that the output data taken out from the register file 18 which stores the input data and then outputs the data is calculated by the calculating means 26, In the arithmetic unit for inputting to 28, the arithmetic data obtained by pipeline arithmetic processing according to a predetermined arithmetic program by the arithmetic means, to the input side of the register file 18, the arithmetic means 26, 28 previously The output data so that the output data from the register file 18 is not input to the input side of the calculation means 26, 28 until the calculation data obtained by the calculation processing is reflected in the output data of the register file 18. An arithmetic unit is provided which has a control means 13 for blocking the transmission of The output data fetched from the register file 18 which is output after storing the data is input to the arithmetic means 26 and 28, and the arithmetic data obtained by pipeline arithmetic processing according to a predetermined arithmetic program by the arithmetic means is stored in the register file. In the arithmetic unit that feeds back to the input side, when the arithmetic data obtained by the arithmetic processing to be performed from now and the arithmetic data before that including immediately before this arithmetic data are stored in the same storage location of the register file, In addition, when the storage order is reversed from the processing order of the arithmetic processing, the arithmetic data obtained by the arithmetic processing previously performed by the arithmetic means is reflected until the input data of the register file is reflected. Transmission of the output data is blocked so that the output data from the register file is not input to the input side of the arithmetic means. There is provided a computing apparatus characterized by comprising a control unit 13.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The preferred embodiments of the arithmetic unit of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the arithmetic unit of the present invention.
Shown in. Further, timing charts of one embodiment of the arithmetic unit of the present invention are shown in FIGS. 2 and 3, respectively.

An embodiment of the arithmetic unit of the present invention shown in FIG. 1 is a program counter (PC, 10), an instruction memory 11, an instruction FIFO (12), a wait circuit 13, an instruction register-0 (INS).
T0, 14), decoder-0 (15), source register A
(SRCA, 16), source register B (SRCB, 17), register file 18, selector-0 (19), instruction register 1 (INST1, 20), decoder-1
(21), Instruction register-2 (INST2, 2
2), decoder-2 (23), instruction register-3 (INST3, 24), decoder-3 (25), first stage arithmetic circuit 26, pipeline register (PIP, 27), second stage arithmetic circuit 28, and destination. It is composed of a nation register (DST, 30).

Although the clock signal is not shown in the block diagram of FIG. 1, a program counter (PC, 10),
Instruction register-0 to 3 (14, 20, 2
2, 24), register file 18, source register 1
6, 17, the pipeline register 27, and the destination register 30 store the input data in synchronization with the clock signal.

In FIG. 1, a predetermined arithmetic program is stored in the instruction memory 11 in advance. The instruction (instruction) is read from the instruction memory 11 using the output of the program counter (PC, 10) as a read address, and stored (stored) in the instruction register-0 (14) via the instruction FIFO (12). It

This instruction register-0 (1
The instruction (instruction) stored in 4) is decoded by the next decoder-0 (15), the read address of the register file 18, the source register A (16),
The store signal of the source register B (17) is generated.

At this time, the wait circuit 13 outputs the storage address of the operation result to the decoders 1 to 3 (21, 23, 25) when there is an operation which has been performed in the past and is not yet stored in the register file 18. And read address input from the decoder-0 (15).
By comparison, it is determined whether any of the storage addresses in the decoders 1-3 (21, 23, 25) and the read address input from the decoder-0 (15) match.

First, the decoders 1-3 (21, 23, 2
5) any of the storage addresses and decoder-0 (1
The case where the read address input from 5) matches (that is, a wait signal is generated) will be described (see FIG. 2). If the addresses match, the wait circuit 13 causes the program counter (PC, 10), instruction register-0 (14), source register A (SRCA, 16), and source register B (SRCB, 1).
A wait signal is applied to these circuits to suppress (block) the updating of 7) (Fig. 2 (b),
(G), (k), (l)).

Then, an instruction (instruction) (nop: no operation) that does not store the operation result in the register file 18 is output to the instruction register-1 (INST1, 20) via the selector-0 (19) (FIG. 2). (H)).

In the next period, the output of the instruction register-1 (20) is stored in the instruction register-2 (INST2, 22), and the instruction (instruction) (no) in which the operation result is not stored in the register file 18 is stored.
p) is output (FIG. 2 (i)). In the next period, the output of the instruction register-2 (22) is transferred to the instruction register-3 (INST3, 24).
Then, the operation result is output as an instruction (instruction) (nop) which is not stored in the register file 18 (FIG. 2 (j)).

Next, the decoders 1-3 (21, 23, 2
Decoder-0 (1
A case where the read address input from 5) does not match (that is, a wait signal is not generated) will be described (see FIG. 3).

If the addresses do not match, the program counter (PC, 10), instruction register-0 (INST0, 14), source register A (SRCA, 1).
6), update of source register B (SRCB, 17) is not suppressed (blocked), and instruction register-0 (INS
The output of T0, 14) is output from the selector 19 (FIG. 3).
(B), (g), (k), (l)).

Instruction register-1 (INST1,
20) The instructions stored in
The control signal of the first stage arithmetic circuit 26, the store signal of the pipeline register 27, and the storage address of the arithmetic result are decoded in 1 (21), respectively (FIGS. 3 (h) and 3 (m)).

Instruction register-2 (INST2,
22) The instructions stored in
2 (23), the control signal of the second stage arithmetic circuit 28, the destination register (DST,
The store signal of 30) and the storage address of the calculation result are respectively generated (FIGS. 3 (i) and (n)).

Instruction register-3 (INST3,
The instruction stored in (24) is decoded by the decoder-3 (25), and the store signal of the register file 18 and the storage address of the operation result are generated (FIGS. 3 (j), (o), and (p)). )).

The data stored in the register file 18 is source register 16, 17, the first stage arithmetic circuit 26, the pipeline register (PIP, 27), the second stage arithmetic circuit 28, the destination register (DST, DST, The calculation is performed via 30) and the calculation result is stored in the register file 18 (FIGS. 3 (o) and 3 (p)).

A case where a wait signal is generated will be described below together with the timing chart of one embodiment of the arithmetic unit of the present invention shown in FIG. In the timing chart shown in Fig. 2, R is stored in the instruction register-0 (14).
1 = R0 + R7 Instruction register-1 (2
The instruction for performing R0 = R4 + R5 is stored in 0).

In this case, R obtained by decoding the instruction for performing R1 = R0 + R7 by the decoder-0 (15)
Decode the read address of the register file 18 indicating 0 and R7 and the instruction to perform R0 = R4 + R5.
Since the storage addresses of the register file 18 indicating R0 obtained by decoding in 1 (21) match, a wait signal is generated.

Instruction register-2, 3 (2
If the instructions for performing R0 = R4 + R5 are stored in 2, 24), the wait signal is generated in the same manner.

The calculation result of R4 + R5 is the register file 18
Since the nop instruction is stored in the instruction registers-1 to 3 (20, 22, 24) at the timing stored in R0 of the decoder 0 (1
5) The read address of the register file 18 indicating R0 and R7 obtained in 5) and the storage address of the register file 18 obtained by the decoders-1 to 3 (21, 23, 25) do not match, and the wait signal supply weight is It will be canceled.

Although the storage address generated by the decoder-2 (23) is not supplied to the register file 18 at this stage, it is generated by the decoder-3 (25),
At that stage, the correspondence relationship with the storage address supplied to the register file 18 is clear, and there is no problem in handling the same storage address.

Next, a block configuration of another embodiment of the arithmetic unit of the present invention will be described with reference to the drawings. FIG. 4 shows a block configuration of another embodiment of the arithmetic unit of the present invention. Timing charts of another embodiment of the arithmetic unit of the present invention are shown in FIGS. 5 and 6, respectively.

Another embodiment of the arithmetic unit of the present invention shown in FIG.
Program counter (PC, 10), instruction memory 11, instruction FIFO (12),
Wait circuit 13, instruction register-0 (I
NST0, 14), decoder-0 (15), source register A
(SRCA, 16), source register B (SRCB, 17), register file 18, selector-1 (19), instruction register-1 (INST1, 20), decoder-1
(21), Instruction register-2 (INST2, 2
2), decoder-2 (23), instruction register-3 (INST3, 24), decoder-3 (25), first stage arithmetic circuit 26, pipeline register (PIP, 27), second stage arithmetic circuit 28, said first A selector to which the output of the stage arithmetic circuit 26 and the output of the second stage arithmetic circuit 28 are supplied.
1 (29) and destination register (DST, 3
0).

Although the clock signal is not shown in the block diagram of FIG. 4, the program counter (PC, 1
0), instruction register-0 to 3 (14, 2)
0, 22, 24), register file 18, source register A (16), source register B (17), pipeline register 27, destination register (DS
Input data is stored in T, 30) in synchronization with the clock signal.

In FIG. 4, a predetermined arithmetic program is stored in the instruction memory 11. The instruction (instruction) is read from the instruction memory 11 by using the output of the program counter (PC, 10) as a read address, and is stored in the instruction register-0 (14) via the instruction FIFO (12).

Instruction register-0 (14)
The instruction (instruction) stored in is decoded by the decoder-0 (15). This decoder-0 (1
In 5), the read address of the register file 18, the storage address, the number of operation pipeline stages, the source register A
(16), the store signal of the source register B (17) is generated.

At this time, the wait circuit 13 determines the storage address (storage location) of the operation result and the number of operation pipeline stages when the operation performed in the past has not been stored in the register file 18 yet. (21)
And the storage address (storage location) input from the decoder-0 (15) and the number of operation pipeline stages.

By comparison, the storage addresses (storage locations) match, the number of operation pipeline stages acquired from the decoder-0 (15) is one, and the number of operation pipeline stages acquired from the decoder-1 (21) is In the case of two stages, the wait circuit 13 includes a program counter (PC, 10), instruction register-0 (14), source register A (1
6) Suppress (block) update of source register B (17)
A weight signal is applied to these circuits to control the weights (Figs. 5 (b), (g), (k),
(L)).

Then, through the selector-0 (19), an instruction (instruction) (nop: no operation) that does not store the operation result in the register file 18 is output to the instruction register-1 (INST1, 20) (FIG. 5).
(H)).

When the storage address and the number of operation pipeline stages do not satisfy the above conditions or when the address comparison unnecessary signal is output from the decoder-1 (21), the program counter 10 and the instruction register-0.
(14), updating of the source register A (16) and the source register B (17) are not suppressed (blocked), and the output of the instruction register-0 (14) is the selector-0 (1
9) (Figs. 6 (b), (g), (k),
(L)).

Instruction register-1 (20)
The instruction (instruction) stored in (1) is decoded by the decoder-1 (21) (FIG. 6 (h)).

In the case of the operation with one pipeline stage, the decoder-1 (21) controls the first stage arithmetic circuit 26, the selector-1 (29) selects the output of the first stage arithmetic circuit 26, and the destination register. The store signal of 30 and the storage address comparison unnecessary signal of the calculation result are generated.

In the case of the operation of the pipeline stage number 2, the decoder-1 (21) generates the control signal of the first stage operation circuit 26, the store signal of the pipeline register 27, and the storage address of the operation result.

Instruction register-2 (22)
Instructions stored in
It is decoded in 3) (Fig. 5 (i)). In the case of the operation of the pipeline stage number 1, the decoder-2 (23) generates the store signal of the register file 18 and the storage address of the operation result (FIG. 6 (i)).

In the case of the operation with two pipeline stages, the decoder-2 (23) has a control signal for the second stage arithmetic circuit 28, a signal for causing the selector-1 (29) to select the output of the second stage arithmetic circuit 28, and a destination. The store signal of the register 30 is generated.

Instruction register-3 (24)
The instructions stored in the decoder are decoder-3 (2
5) is decoded (Fig. 6 (j)). In the case of the operation of the pipeline stage number 2, the store signal of the register file 18,
Generate the storage address of the operation result.

The data stored in the register file 18 by the above control is the source register A (16),
An operation is performed via the source register B (17), the first stage operation circuit 26, the pipeline register 27, the second stage operation circuit 28, and the destination register 30, and the operation result is the register file 18
Stored in.

A case where a wait signal is generated will be described below together with the timing chart of another embodiment of the arithmetic unit of the present invention shown in FIG. The timing chart shown in FIG. 5 is the instruction register-0 (14).
At the timing at which the instruction (instruction) for performing R0 = R6 + R7 is stored (stored), the instruction for performing R0 = R4 × R5 is stored in the instruction register-1 (20) (FIG. 5 (g), (H)). Here, it is assumed that the number of pipeline stages in which R0 = R6 + R7 of the addition operation (+) is one, and the number of pipeline stages in which R0 = R4 × R5 of the multiplication operation (×) is two.

In this case, in the wait circuit 13, R0
= Decoder-0 (1
The storage address of the storage location of the register file 18 indicating R0 obtained by decoding in 5) and the register file 18 indicating R0 obtained by decoding the instruction for performing R0 = R4 × R5 in the decoder-1 (21). The address of the storage location matches, the number of operation pipeline stages obtained by decoding with the decoder-0 (15) is one, and the number of operation pipeline stages obtained by decoding with the decoder-1 (21) is two. Since it is a stage, the wait circuit 13 outputs a wait signal.

When the wait circuit 13 outputs the wait signal, the nop instruction is stored in the instruction register-1 (20) at the next timing (FIG. 5 (h)). Then, decoder-1 (21)
Since the address comparison unnecessary signal is output from, the wait state is released.

The storage address generated by the decoder-1 (21) is not supplied to the register file 18 at this stage, but the decoder-2 (23) and the decoder-3
(25), the register file 18
The correspondence with the storage address supplied to is clear,
There is no problem in treating them as the same storage address.

[0048]

As described above, according to the invention described in claim 1, the time management of the pipeline of the arithmetic means (arithmetic circuit) is performed by the arithmetic data previously obtained by the arithmetic means. Until it is reflected in the output data of the register, a control means for blocking the transmission of the output data is provided on the input side of the arithmetic means so as not to input the output data from the register file. It becomes unnecessary to manage the pipeline time by the program.

Further, the invention described in claim 2 is the operation data obtained by performing the time processing of the pipeline of the arithmetic means (arithmetic circuit) in which the number of pipeline stages differs depending on the type of arithmetic operation. Is the same as the storage location of the register file that stores the same as the storage location of the register file that stores the arithmetic data obtained by the arithmetic processing
And the storage time of the operation data obtained by the operation processing to be performed in the register file is the same as the storage time of the operation data obtained by the operation processing performed previously in the register file, or In the case before, the output data from the register file is input to the input side of the arithmetic means until the arithmetic data previously obtained by the arithmetic means is reflected in the input data of the register. Since the control means for preventing the transmission of the output data is provided so as not to be performed, it is not necessary to consider the time for storing the operation result in the register file when creating the program as in the past.

[Brief description of drawings]

FIG. 1 shows a block configuration of an embodiment of an arithmetic unit according to the present invention.

FIG. 2 shows a timing chart when a weight is generated in an embodiment of the arithmetic unit of the present invention.

FIG. 3 shows a timing chart in the case where no weight is generated in the embodiment of the arithmetic unit of the present invention.

FIG. 4 shows a block configuration of another embodiment of the arithmetic unit of the present invention.

FIG. 5 shows a timing chart when a weight is generated in another embodiment of the arithmetic unit of the present invention.

FIG. 6 shows a timing chart when a weight is not generated in another embodiment of the arithmetic unit of the present invention.

[Explanation of symbols]

10 program counter 11 instruction memory 12 Instruction FIFO 13 Weight circuit (control means) 14 Instruction register-0 15 Decoder-0 16 Source register A 17 Source Register B 18 register file 19 Selector-0 20 Instruction register-1 21 Decoder-1 22 Instruction Register-2 23 Decoder-2 24 Instruction Register-3 25 Decoder-3 26 First Stage Arithmetic Circuit (Arithmetic Means) 27 pipeline registers 28 Second stage arithmetic circuit (arithmetic means) 29 Selector-1 30 destination register CLK clock PC program counter IMRA instruction memory read address IMDO instruction memory data out IFDI Instruction FIFO Data In IFDO Instruction FIFO Data Out INST0 Instruction register-0 INST1 Instruction register-1 INST2 Instruction register-2 INST3 Instruction register-3 SRCA source register A SRCB Source register B PIP pipeline register DST destination register Register 0 of R0 register file 18 Register-1 of R1 register file 18 Register-2 of R2 register file 18 Register-3 of R3 register file 18

Claims (2)

[Claims] 1. An arithmetic data obtained by inputting output data fetched from a register file which is output after storing input data to an arithmetic means, and pipeline arithmetic processing by the arithmetic means according to a predetermined arithmetic program, to the register. In the arithmetic unit for returning to the input side of the file, the register is provided on the input side of the arithmetic means until the arithmetic data obtained by the arithmetic processing previously performed by the arithmetic means is reflected in the output data of the register file. An arithmetic unit comprising: control means for preventing transmission of the output data so that output data from a file is not input. 2. The arithmetic data obtained by inputting output data taken out from a register file which is output after storing input data to the arithmetic means and pipeline-processed the arithmetic data according to a predetermined arithmetic program by the arithmetic means. In the arithmetic unit that returns to the input side of the file, the arithmetic data obtained by the arithmetic processing to be performed and the arithmetic data before that including immediately before this arithmetic data are stored in the same storage location of the register file. hand,
Further, when the storage order is reversed from the processing order of the arithmetic processing, the arithmetic data obtained by the arithmetic processing previously performed by the arithmetic means is maintained until the arithmetic operation data is reflected in the input data of the register file. An arithmetic unit comprising: control means for preventing transmission of the output data so that output data from the register file is not inputted to an input side of the arithmetic means.