JP2003058128A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce switching noise of a planar display device which uses a data inversion transmission method. SOLUTION: When data are transmitted to a source driver 24 from an S/P controller 46 that is one of liquid crystal controllers employing a data inversion transmission method, data inversion signals are controlled so that the polarities of image data to be inputted to a two port source driver are mutually inverted in a blanking interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an active matrix type liquid crystal using a thin film transistor (hereinafter referred to as TFT) as a switch element for each pixel, an organic EL.
Etc. relating to a flat display device.

[0002]

2. Description of the Related Art Flat panel display devices represented by liquid crystal display devices have come to be used in various fields by taking advantage of their thinness, light weight and low power consumption. And, in recent years, especially for such a flat display device, a large screen,
The demand for higher definition is increasing.

In order to meet such a demand, it is possible to transfer a large amount of image data, and to process a large amount of image data within each horizontal scanning period, in addition to the high definition of the display panel itself. There is a need.

In order to enable processing of a large amount of image data, for example, when digital image data is transmitted from a liquid crystal controller, which is a control portion of a liquid crystal display device, to a source driver, the following method has been conventionally used (hereinafter, In this specification, a data inversion transmission method) has been proposed (JP-A-8-248924).

This data inversion transmission method is a method of reducing EMI by reducing switching noise when data is switched when transmitting digital data between ICs. Hereinafter, a specific example will be described.

As an example of this, data transmission between a liquid crystal controller IC and a source driver IC (2 port input / 24 bits) will be described.

The image data output from the liquid crystal controller IC on the transmitting side is the nth image data, and the image data to be output next is the (n + 1) th image data. Compare the nth and (n + 1) th image data,
When more than half of the bits change from 0 to 1 or from 1 to 0, the logic of the (n + 1) th image data is inverted and output. When the image data is inverted and output in this way, the data inversion signal indicating that the image data is the inverted data outputs the H level. vice versa,
Comparing the nth and (n + 1) th image data, and when the majority of bits do not change from 0 to 1 or from 1 to 0, the (n + 1) th image data is output without performing logical inversion. . A data inversion signal indicating that the image data is non-inversion data outputs L level.

On the other hand, on the side of the source driver IC which is the receiving side, the image data taken in when the data inversion signal is at the H level is inverted again before being taken into the shift register inside the source driver IC and the original image is reproduced. It is demodulated into data and then processed.

In the above-described data inversion transmission method, in order to realize this, it is necessary to provide a data inversion circuit in a circuit on the transmission side (for example, a liquid crystal controller IC). In this case, since the data inversion circuit only operates by comparing the adjacent image data before and after, it is not controlled by other circuits.

[0010]

When the liquid crystal controller IC having a plurality of data inversion circuits as described above is turned on, the output (image data or data inversion signal) of each data inversion circuit is the display content at that time. Initially set to a different state each time. This initialized state is 2 in a system having p data inversion circuits.
There are ^p combinations.

Depending on this combination, switching noise generated when the output of the liquid crystal controller IC on the transmitting side changes from 1 to 0 or from 0 to 1 propagates through the drive circuit board and EMI (radio wave unnecessary). radiation)
There was the problem of making the level significantly worse.

In view of the above problems, the present invention provides a flat panel display device using the data inversion transmission method, which can reduce switching noise.

[0013]

According to the present invention, a plurality of signal lines and scanning lines arranged orthogonally to each other, and a pixel arranged via a switch element in the vicinity of an intersection of the signal line and the scanning line. A signal line drive circuit that is connected to the signal line and supplies an image signal, and is connected to the scan line, and turns the switching element to an ON state to output the image signal to the pixel electrode. To the scanning line driving circuit for supplying a gate signal to be written to the signal line driving circuit.
A circuit that outputs at least two bit image data in parallel, and if each bit of the (n + 1) th image data changes by more than half of each bit of the nth image data, then (n + 1) The (n + 1) th image data is logically inverted and output, and a data inversion signal indicating that the (n + 1) th image data is inverted data is output. Also, for each bit of the nth image data ( If each bit of the (n + 1) th image data does not change by more than a majority, the (n + 1) th image data is output without being logically inverted, and it is confirmed that the (n + 1) th image data is non-inverted data. And a control circuit that outputs a data inversion signal shown in the above. It is a flat display device for the control means controls the data inversion signal to fix it to invert on timing.

In the flat panel display device of the present invention, the polarities of the image data output by the two lines are reversed at a predetermined timing (during a non-display period such as a vertical blanking period or a horizontal blanking period). Since the data inversion signal is controlled, the currents for driving the load in the control circuit on the transmission side do not complement each other in the circuit and a large noise is not generated in the power supply line supplied from the outside.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A liquid crystal display device 10 according to an embodiment of the present invention will be described below with reference to FIGS.

[1] Outline Description of Liquid Crystal Display Device FIG. 1 shows a schematic configuration of a liquid crystal display device 10 of this embodiment.

This liquid crystal display device 10 has a QUXGA (3200 × 2400) whose effective display area has a diagonal size of 20.8 inches.
A liquid crystal panel 12 having color display pixels of the specification is provided. That is, the effective display area of the liquid crystal display device 10 is
24 horizontal pixel lines consisting of 3200 × 3 (R, G, B) display pixels
It is composed of 00 pieces.

Since the liquid crystal display device 10 includes such a large number of horizontal pixel lines L1, ..., L2400, the following characteristic drive is adopted.

That is, as shown in FIGS. 6 and 7, the effective display area is vertically divided into two, and in one horizontal scanning period (1H), the horizontal pixel lines (L1 to L1200) of the upper display area and the horizontal of the lower display area are horizontal. In this method, writing is performed in parallel on each of the pixel lines (L1201 to L2400), and this is repeated sequentially. For example, in this embodiment, the first horizontal scanning period (1
H) are sequentially written in the horizontal pixel lines L1 and L2400, and L2399, L2, ... In the second horizontal scanning period (1H).

Here, the horizontal scanning period (1H) is a period in which digital image data DATA for one horizontal pixel line is transmitted from the processing device 32, and in this embodiment, 13 μse.
c.

Further, the effective display area of the liquid crystal panel 12 is assumed to be composed of four UXGA (1600 × 1200) areas which are vertically and horizontally divided as shown in FIG. On the A screen, the upper right screen on the B screen,
The lower left screen is the C screen, and the lower right screen is the D screen. In addition, when described as "upper screen", A screen, or
The B screen means the C screen or the D screen when described as "lower screen". Furthermore, A screen, B screen, C
It is assumed that the screen and the D screen are composed of an A1 screen and an A2 screen, a B1 screen and a B2 screen, a C1 screen and a C2 screen, and a D1 screen and a D2 screen, which are divided into left and right, respectively.

[2] Structure of Liquid Crystal Panel In order to realize the above-mentioned driving, this liquid crystal display device 10 is used.
Is configured as follows.

That is, as shown in FIG. 1, the liquid crystal panel 12 includes (3200 × 3 (R, G, B)) signal lines 16 and 2400 signal lines 16 arranged orthogonally to the signal lines 16. The array substrate 14 including the scanning lines 18 and the pixel electrodes 22 arranged via the TFTs 20 arranged near the intersections of the signal lines 16 and the scanning lines 18, and a predetermined number above the facing surface of the array substrate 14. A counter electrode substrate (not shown) provided with a color filter disposed with a gap of 2 and a liquid crystal (not shown) as a light modulation layer disposed between the array substrate 14 and the counter electrode substrate. There is.

If an organic EL panel is used instead of the liquid crystal panel, it is necessary to dispose an organic EL layer or the like instead of the liquid crystal.

Each of the scanning lines 18 is a gate of the TFT 20, each of the signal lines 16 is a drain of the TFT 20, and each of the pixel electrodes 22 is a source of the TFT 20.
They are electrically connected to each other, so that the scan line 1
The analog image signal Vs from the signal line 16 is written to the pixel electrode 22 in response to the scanning pulse Vg supplied to the pixel electrode 8, and display is performed based on the potential difference between the pixel electrode 22 and the counter electrode.

By the way, the signal line 1 of the liquid crystal panel 12
As shown in FIG. 1, reference numeral 6 denotes an upper lead-out signal line 16 a electrically led out from the upper side of the array substrate 14 and a lower lead-out signal line 16 electrically led out from the lower side of the array substrate 14.
b, and these signal lines 16a and 16b are alternately arranged as shown in FIG. In other words, the odd-numbered signal lines 16 are the upper lead-out signal lines 16a, and the even-numbered signal lines 16 are the lower lead-out signal lines 16b.

Among the odd-numbered signal lines 16a arranged on the AC screen, the upper lead-out signal lines 16a of R1, B1, ..., G800 are for the first AC screen arranged on the upper side of the liquid crystal panel 12. R8 to the upper source driver 24-ACU1
The upper extraction signal line 16a of 01, B801, ..., G1600 is electrically connected to the upper source driver 24-ACU2 for the second AC screen through the connection pads 17a.
In addition, among the even-numbered signal lines 16b arranged on the AC screen, G1, R2, ...
b is a lower source driver 26-ACD1 for the second AC screen arranged on the lower side of the liquid crystal panel 12, G801, R802 ,.
.., the lower lead-out signal line 16b of B1600 is connected to the lower source driver 26-ACD2 for the second AC screen by connecting pad 1 respectively.
It is electrically connected via 7b.

Similarly, among the odd-numbered signal lines 16a arranged on the BD screen, R1601, B1601, ..., G3200
The upper pull-out signal line 16a is the upper source driver 25-BDU1 for the first BD screen arranged on the upper side of the liquid crystal panel 12.
, R2401, B2401, ..., G3200 top lead signal line 1
6a is the upper source driver 25-BDU2 for the second BD screen
Are electrically connected to each other via connection pads 17a. Of the even-numbered signal lines 16b arranged on the BD screen, the lower lead-out signal line 16b of G1601, R1602, ..., B2400 is the lower source for the second BD screen arranged on the lower side of the liquid crystal panel 12. G2 to the driver 27-BDD1
The lower lead-out signal line 16b of 401, R2402, ..., B3200 is electrically connected to the lower source driver 27-BDD2 for the second BD screen through the connection pad 17b.

The scanning line 18 is led out to one end of the array substrate 14 and electrically connected to the upper screen gate driver 28 and the lower screen gate driver 30 via the connection pad 19, and these gate drivers 28, 30 are connected. The scan pulse Vg is supplied to each scan line 18 from.

With the structure of the liquid crystal panel 12 as described above,
Since the connection pads 17a and 17b of each signal line 16 are arranged with at least the signal line 16 interposed therebetween, the distance between the connection pads 17a and 17b can be set sufficiently wider than the distance between the signal lines 16. As a result, even for high definition, the upper source drivers 24 and 25 and the lower source driver 2
It is possible to easily electrically connect external circuits such as 6, 27.

If the signal lines 16 are, for example, pulled out to the upper side, the connection pads can be easily connected to the external circuit by arranging the corresponding connection pad positions of the even-numbered lines and the odd-numbered lines in a zigzag pattern. . Further, in addition to dividing into two groups of even-numbered and odd-numbered, it is also possible to divide into three or more groups and arrange the connection pads in a zigzag pattern of multiple stages in accordance with this.

[3] Circuit Configuration of Liquid Crystal Display Device The liquid crystal display device 10 supplies the analog image signal Vs to the liquid crystal panel 12 and the signal line 16 of the liquid crystal panel 12 as described above (see FIG. 1). Upper source drivers 24 and 25, lower source drivers 26 and 27 as signal line drive circuits, and each scanning line 1 of the liquid crystal panel 12.
8, an upper screen gate driver 28 and a lower screen gate driver 30 serving as a scanning line driving circuit for supplying a scanning pulse Vg to 8, and these source drivers 24, 25, 26, 2
7 and a liquid crystal controller 34 that controls the gate drivers 28 and 30.

The circuit configuration of the liquid crystal display device 10 will be described in more detail with reference to FIG.

The processing device 32 corresponds to each of the A screen, B screen, C screen and D screen of the liquid crystal panel 12, and further for each color of red (R), blue (B) and green (G). 24 lines of digital image data R: DATA-A (o), R: D corresponding to odd and even numbers in the horizontal pixel line direction
ATA-A (e), ..., R: DATA-B (o),
R: DATA-B (e), ..., R: DATA-C
(O), R: DATA-C (e), ..., R: DAT
A-D (o), R: DATA-D (e), ..., B:
DATA-D (e) (see FIGS. 11 to 13) are output in parallel to the liquid crystal controller 34, respectively.

Each digital image data DATA
Is composed of 8 bits in this embodiment, whereby the liquid crystal display device 10 can realize 256 gradation display.

Here, the processing device 32 and the liquid crystal display device 10
The data transfer between and is performed in parallel for each of the divided display screens and further for each color by dividing into odd numbers (o) and even numbers (e), thereby realizing data transfer at 60 MHz. As a result, an increase in the data transfer rate can be suppressed, and thus reliable data transfer and the influence of EMI can be reduced.

Further, the processing device 32 is shown in FIGS.
As shown in FIG. 3, the liquid crystal display device 10 displays the digital image data DATA together with the horizontal synchronizing signals HSYNC,
Vertical sync signal VSYNC, data enable signal ENA
B, the system clock signal NCLK is transmitted.

The I / F connector 36 constituting the liquid crystal controller 34 is used for inputting 24 systems of digital image data R: DATA-A (o), ..., B: DATA-.
Of D (e), 12 systems of digital image data R: DATA-A (o), R: D for forming an AC screen
ATA-A (e), ..., B: DATA-A (e),
R: DATA-C (o), R: DATA-C (e),
.., B: DATA-C (e) in the liquid crystal controller 38 for AC screen, and the other 12 systems of digital image data R: DATA-B (o), R: DAT constituting the BD screen.
AB (e), ..., B: DATA-B (e), R:
DATA-D (o), R: DATA-D (e), ...
, B: DATA-D (e) is distributed to the BD screen liquid crystal controller 40.

Each of the liquid crystal controllers 38 and 40 is an IC chip of the same configuration which is configured to control the source drivers 24, 25, 26 and 27 and the gate drivers 28 and 30.

Then, the AC screen liquid crystal controller 38
Is the first and second upper source drivers 24-A for the AC screen.
CU1, 24-ACU2 and the AC screen first and second lower source drivers 26-ACD1, 26-ACD2 are controlled, and the upper screen gate driver 28 is also controlled. The BD screen liquid crystal controller 40 includes the BD screen first and second upper source drivers 25-BDU1, 25-BDU2 and the BD screen first and second lower source drivers 27-BDD1,
It is wired so as to control 27-BDD2 and also to control the lower screen gate driver 30.

The AC screen liquid crystal controller 38 receives the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC, the data enable signal ENAB, which is input from the processing device 32.
Based on the system clock signal NCLK, control signals such as the vertical start signal STV-U, the vertical clock signal CPV-U, and the gate output enable signal OE-U are generated and transmitted to the upper screen gate driver 28. Similarly, the BD screen liquid crystal controller 40 also receives the vertical start signal STV.
-D, the vertical clock signal CPV-D, and the gate output enable signal OE-D are transmitted to the lower screen gate driver 30.

In addition, the AC screen liquid crystal controller 38
Is the input 12-system digital image data R: D
ATA-A (o), R: DATA-A (e), ...
B: DATA-A (e), R: DATA-C (o),
R: DATA-C (e), ..., B: DATA-C
The rearrangement of (e) and the timing control are performed, and the rearranged digital image data of 12 systems R: UD
ATA-A1C1, G: UDATA-A1C1, B: U
DATA-A1C1, R: DDATA-A1C1, G:
DDATA-A1C1, B: DDATA-A1C1,
R: UDATA-A2C2, G: UDATA-A2C
2, B: UDATA-A2C2, R: DDATA-A2
C2, G: DDATA-A2C2, B: DDATA-A
2C2 is a horizontal clock signal CPH and a horizontal start signal H
Through the low voltage differential signal transmission circuit 42, the low voltage differential signal reception circuit 44, and the serial / parallel controller (hereinafter, referred to as “S / P controller”) 46 together with START, the first and second upper source drivers 24. -ACU1,
24-ACU2 and first and second lower source drivers 26-AC
Output to D1 and 26-ACD2 in parallel.

Since the BD screen liquid crystal controller 40 also performs substantially the same processing, its description is omitted.

In FIG. 3, a range surrounded by a dotted line shows a wiring board used in the liquid crystal display device 10, and each circuit is mounted on the wiring board shown by the dotted line. Is shown.

[4] Configuration of AC Screen Circuit FIG. 4 shows a circuit of the liquid crystal display device 10 shown in FIG.
It shows a block diagram of a circuit for an AC screen, which will be described in more detail. It should be noted that the BD screen circuit has a similar circuit, and a description thereof will be omitted.

As shown in FIG. 4, the AC screen liquid crystal controller 38, which constitutes the liquid crystal controller 34 of the liquid crystal display device 10, is connected to the A from the processing device 32 as described above.
12-system digital image data R for each color corresponding to the screen and the C screen, and corresponding to the odd and even numbers:
DATA-A (o), R: DATA-A (e), ...
., B: DATA-C (o), and B: DATA-C
(E) is input in parallel.

The AC screen liquid crystal controller 38 includes an upper screen line memory 48 corresponding to red (R), blue (B), and green (G), and a lower screen line memory 50. 48 and 50 are connected to one selector circuit 52.

Then, timing control and data rearrangement are achieved by writing and reading to and from the line memories 48 and 50, and by setting the output destination by the selector circuit 52.

[5] Method of driving liquid crystal display device Hereinafter, it will be described in more detail with reference to the drawings.

FIG. 12 shows the data input / output timing of the liquid crystal controller 34. The system clock signal NCLK, the horizontal synchronizing signal HSYNC, the data enable signal ENAB, and the digital image data R: DATA input from the processor 32 from above. -A (o), R: DAT
A-A (e), ..., R: DATA-C (o), R:
DATA-C (e), ..., And a clock signal CL generated by the AC screen liquid crystal controller 38.
K, horizontal start signal HSTART, and output image data U output from the AC screen liquid crystal controller 38.
DATA-A1C1, DDATA-A1C1, UDATA-A2C2,
It shows UDATA-A2C2. Note that FIG. 13 and FIG.
4 output image data UDATA-A1C1, DDATA-A1C1
An enlarged view of is shown.

[5-1] The 8-bit digital image data DATA input from the processing device 32 to the liquid crystal display device 10 in parallel in 24 lines is used by the I / F connector 36 for the AC screen liquid crystal controller 38 and the BD screen. They are assigned to the liquid crystal controller 40, respectively. The digital image data DATA distributed in parallel to the AC screen liquid crystal controller 38 is for each color of red (R), blue (B), and green (G) as described above, and is for A screen and C screen. , A total of 12 systems of 8-bit digital image data R: DATA-A (o), R: DATA-A (e),
..., B: DATA-A (e), R: DATA-C
(O), R: DATA-C (e), ..., B: DAT
AC (e), and the operation of the AC screen liquid crystal controller 38 will be described below as an example.

[5-2] AC screen liquid crystal controller 3
A-screen digital image data R: DATA-A corresponding to the horizontal pixel line L1 distributed in parallel
(O), R: DATA-A (e), G: DATA-A
(O), G: DATA-A (e), B: DATA-A
(O) and B: DATA-A (e) are line memories 48
C screen digital image data R: DATA-C (o), R: DATA- corresponding to the horizontal pixel line L2400.
C (e), G: DATA-C (o), G: DATA-C
(E), B: DATA-C (o), B: DATA-C
(E) is sequentially stored in the line memory 50 based on the system clock signal NCLK.

[5-3] In this way, the line memory 4
Digital image data DATA corresponding to the horizontal pixel lines L1 and L2400 stored in 8, 50 are clock signals CL having the same frequency as the system clock signal NCLK.
The data is sequentially read based on K, and the selector circuit 52 rearranges the image data.

More specifically, digital image data R for screen A corresponding to the horizontal pixel line L1 R: DATA-A
(O), G: DATA-A (o), B: DATA-A
(O) R1 to R799, R: DATA-A (e), G:
DATA-A (e), B: R2 of DATA-A (e)
When R800 is stored in the line memory 48, sequential reading is started based on the clock signal CLK,
The selector circuit 52 rearranges the image data.

For example, in the AC screen first upper source driver 24-ACU1, the three parallel image data UDATA-A1C1 rearranged as shown in FIG. 13 are transferred to the AC screen first lower source driver 24- In the ACU1, image data UDAT of three parallel inputs rearranged as shown in FIG.
A-A1C1 is output respectively.

C corresponding to the horizontal pixel line L2400
Digital image data for screen R: DATA-C
(O), G: DATA-C (o), B: DATA-C
(O) R1 to R799, R: DATA-C (e), G:
DATA-C (e) and B: DATA-C (e) are stored in the line memory 50 as shown in FIG. 12, and after the output of the image data corresponding to the A screen is completed,
Reading is sequentially started based on the clock signal CLK, and the selector circuit 52 rearranges the image data.

[5-4] First and second upper source drivers 24-ACU1, 24-ACU2, 25-BDU1, 25-BDU2, and first and second lower source drivers 26-ACD1, 26-ACD
2, 27-BDD1 and 27-BDD2 are 2-port inputs respectively.

Therefore, the S / P controller 46 is
Control is performed to extend the time axis of the digital image data of 12 systems rearranged by the selector circuit 52 of the C-screen liquid crystal controller 38 and guide the lines in parallel to each driver by two lines.

Then, the converted image data is converted into A by using the data inversion transmission method described in [6] below.
C screen first and second upper source drivers 24-ACU1, 2
4-ACU2 and the first and second lower source drivers 24-ACD1 and 24-ACD2 for the AC screen are transmitted.

[5-5] AC screen first and second upper source drivers 24-ACU1, 24-ACU2 and AC screen first and second lower source drivers 24-ACD1, 24-ACD2
Image data UDATA-A for the A screen corresponding to the horizontal pixel line L1 input from the P controller 46
1C1, DDATA-A1C1, UDATA-A2C2, DDATA-
Serial-parallel conversion of A2C2. Then, the image data U for A screen corresponding to the horizontal pixel line L1 which has been subjected to the serial / parallel conversion
DATA-A1C1, DDATA-A1C1, UDATA-A2C2,
Converts DDATA-A2C2 to digital / analog and halves
The desired analog image signal Vs is output to the corresponding signal line 16 during the horizontal scanning period (H / 2).

Subsequently, image data UDATA for the C screen corresponding to the respective input horizontal pixel lines L2400
-A1C1, DDATA-A1C1, UDATA-A2C2, DDAT
A-A2C2 is serial-parallel converted, and further digital-analog converted, and a desired analog image signal Vs is output to the corresponding signal line 16 over the 1/2 horizontal scanning period (H / 2).

In this way, one horizontal scanning period (1H)
Then, writing to two horizontal pixel lines (L1, L2400) is performed.

[5-6] In the next horizontal scanning period, C screen digital image data R: DATA-C (o), R corresponding to the horizontal pixel line L2399 distributed in parallel to the AC screen liquid crystal controller 38. : DATA-C
(E), G: DATA-C (o), G: DATA-C
(E), B: DATA-C (o), B: DATA-C
(E) shows in the line memory 48 the A screen digital image data R: DATA-A corresponding to the horizontal pixel line L2.
(O), R: DATA-A (e), G: DATA-A
(O), G: DATA-A (e), B: DATA-A
(O) and B: DATA-A (e) are the line memories 50.
Are sequentially stored based on the system clock signal NCLK.

[5-7] In this way, the line memory 4
The digital image data DATA corresponding to the horizontal pixel lines L2399 and L2 stored in Nos. 8 and 50 are clock signals CL having the same frequency as the system clock signal NCLK.
The data is sequentially read based on K, and the selector circuit 52 rearranges the image data.

Specifically, digital image data R for the C screen corresponding to the horizontal pixel line L2399 R: DATA-C
(O), G: DATA-C (o), B: DATA-C
(O) R1 to R799, R: DATA-C (e), G:
DATA-C (e), B: R2 of DATA-C (e)
When R800 is stored in the line memory 48, sequential reading is started based on the clock signal CLK,
The selector circuit 52 rearranges the image data.

Further, digital image data R for screen A corresponding to the horizontal pixel line L2: DATA-A (o),
G: DATA-A (o), B: R of DATA-A (o)
1 to R799, R: DATA-A (e), G: DATA-
For A (e) and B: DATA-A (e), FIG.
As shown in FIG. 5, after the output of the image data corresponding to the C screen is completed and stored in the line memory 50, the sequential reading is started based on the clock signal CLK, and the selector circuit 52 rearranges the image data. .

[5-8] The first and second upper source drivers 24-ACU1 and 24-ACU2 for AC screen and the first and second lower source drivers 24-ACD1 and 24-ACD2 for AC screen are respectively input. Image data UDATA-A1C1, DDATA-A1C1, U for C screen corresponding to the horizontal pixel line L2399
DATA-A2C2 and DDATA-A2C2 are serial-parallel converted, and digital-analog conversion is performed to output a desired analog image signal Vs to the corresponding signal line 16 over the 1/2 horizontal scanning period (H / 2).

Subsequently, image data UDATA-A for the A screen corresponding to the respective input horizontal pixel lines L2.
1C1, DDATA-A1C1, UDATA-A2C2, DDATA-
A2C2 is subjected to serial / parallel conversion and further subjected to digital / analog conversion, and a desired analog image signal Vs is output to the corresponding signal line 16 over the 1/2 horizontal scanning period (H / 2).

In this way, one horizontal scanning period (1H)
Then, writing to two horizontal pixel lines (L2399, L2) is performed.

Thereafter, this operation is sequentially repeated.

[6] Data Inversion Transmission Method Next, image data is sent from the S / P controller 46 to the AC screen first and second upper source drivers 24 and the AC screen first and second lower source drivers 24. A transmission method (that is, the data inversion transmission method of this embodiment) will be described with reference to FIGS. 17 to 21.

For simplicity of explanation, the source drivers will be generically referred to as the source driver 24.

Each of the source drivers 24 is of a two-port input type capable of simultaneously capturing image data of two horizontal pixel lines at the same time. Each input port has an input terminal for a data inversion signal as well as a data input. I have it.

[6-1] Conventional Data Inversion Transmission Method First, the conventional data inversion transmission method will be described with reference to FIGS. 17 and 18, and its problems will be clarified.

FIG. 17 is a block diagram for realizing the conventional data inversion transmission method. The S / P controller 4 is shown in FIG.
6, a first inverting circuit 50 and a second inverting circuit 52 are provided. The image data input to the first data inversion circuit 50 and the second data inversion circuit 52 is assumed to have, for example, all 24 bits changed in the order of 0, 1, 0, 1.

In this conventional method, the first data inverting circuit 5
0 and the second data inversion circuit 52 start operating in different states each time depending on the state of the image data (1 or 0) at the stage when the power is turned on. Therefore, the output to the first port and the second port of the source driver 24 is performed. The signal takes four patterns of (a) to (d) of FIG.

FIG. 18A shows a case where both data inversion circuits 50,
The case 52 is the case 1 initialized to the same state when the power is turned on. In case 1
Since all the bits of the data input to both the data inversion circuits 50 and 52 are changed every time, the data output to the first port and the second port retains all the bits 0 and only the data inversion signal. The output is repeated in the order of 0, 1, 0, 1.

FIG. 18B shows both data inversion circuits 50 and 5.
2 shows the case 2 which is initialized to the opposite state when the power is turned on. In the case 2, the data output to the first port repeats 0, 1, 0, 1 only with the data inversion signal while holding all bits 0. On the other hand, conversely, the data output to the second port retains all bits 1 and only the data inversion signal is 1, 0, 1,
Repeat 0.

FIG. 18C shows both data inversion circuits 50,
The case 52 is the case 3 which is initialized to the opposite state when the power is turned on. In case 3, the data output to the first port repeats 0, 1, 0, 1 only with the data inversion signal, while holding all bits 1 in the data output to the first port, contrary to case 2. On the contrary, the data output to the second port repeats 1, 0, 1, 0 only with the data inversion signal while holding all bits 0.

FIG. 18 (d) shows both data inversion circuits 50,
The case 52 is the case 4 which is initialized to the same state when the power is turned on. In the case of Case 4, contrary to Case 1, all the bits of the data input to the data inversion circuits 50 and 52 are changed every time, so that the data output to the first port and the second port are all changed. Only the data inversion signal repeats 0, 1, 0, 1 while holding bit 1.

In Case 1 and Case 4, the first
Since the data inverting circuit 50 and the second data inverting circuit 52 operate in the same phase, relatively large switching noise occurs in the power supply line. On the other hand, in case 2 and case 3, the first data inverting circuit 50 and the second data inverting circuit 52 operate in opposite phases, so that the flow of electrification is canceled inside the IC on the transmission side, and the power supply line is canceled. The switching noise generated in 1) is much smaller than in case 1 and case 4.

However, as described above, which state of cases 1 to 4 when the power is turned on is determined by the state of the image data, so it is completely unknown whether switching noise is large or extremely small. There is a problem that is.

Therefore, the present embodiment has been invented to improve this problem.

[6-2] Data Inversion Transmission Method of This Embodiment A data inversion transmission method of this embodiment will be described with reference to FIGS. 19 to 21.

FIG. 19 shows the S / P controller 4 of this embodiment.
6 is a block diagram showing the relationship between 6 and the source driver 24. FIG.

Also in this embodiment, the S / P controller 4
6, a first data inverting circuit 54 and a second data inverting circuit 56 are provided. Also, the source driver 24
It is a 2-port input type capable of simultaneously capturing image data of 2 pixels (2 × RGB), and each port is provided with a data inversion signal input terminal in addition to the data input.

The first data inversion circuit 54 and the second data inversion circuit 56 have 24 bits (8 bits × RG).
In addition to the image data input in B), the first control signal, the second control signal, and the vertical synchronization signal VSYNC are input.

In the data inversion transmission method of the present embodiment, a control signal is input to periodically initialize each data inversion signal, and the output state (inversion / non-inversion) of each data inversion circuit 54, 56 is received by this control signal. Inversion) is controlled.

As described above, in the conventional data inversion transmission method, the states of case 2 and case 3 cannot always be realized. Therefore, in the present embodiment, the states of case 2 and case 3 are controlled by the control signal. This is realized by the above, and it is intended to suppress switching noise to a low level.

FIG. 20 shows the data inversion signal of this embodiment.

In this embodiment, the data setting period is provided in the vertical blanking period which is not the display period of the liquid crystal panel 12, and the data (24 bits) of the first port and the first data inversion signal are all set to 0. Further, the data (24 bits) of the second port and the second data inversion signal are all set to 1 so that their outputs are reversed. Non-inversion /
Although there is a difference in the inverted display format, the data of both ports represent the same data. The vertical blanking period of both the first data inversion circuit 54 and the second data inversion circuit 56 is determined based on the vertical synchronization signal VSYNC.

When the vertical blanking period shifts to the display period, image data in which all bits are changed to 0, 1, 0, 1 is input to the data inversion circuits 54 and 56 in both the first port and the second port. In response to this input, the output of the first port repeats 0, 1, 0, 1 only for the first data inversion signal while fixing all the image data to 0. On the contrary, in the second port, only the second data inversion signal repeats 1, 0, 1, 0 while the image data is fixed to all 1s.

As described above, when the data inverting circuits 54 and 56 operate in opposite phases, switching noise is less likely to occur in the power supply line. Therefore, the EMI level can be reduced.

In the above description, the relationship between the S / P controller 46 and one source driver 24 is shown, but the upper source driver 2 used in the liquid crystal display device 10 is described.
The data inversion transmission method of this embodiment is applied to all of the lower side source drivers 26 and 27. FIG. 21 is a schematic view showing that state.

In this figure, the polarity of the upper source driver is set to the opposite polarity of 1010, and the other source driver 2
Similarly, 5, 26 and 27 are set to have opposite polarities.

As a result, all source drivers 24
S / P controller 4 for controlling this from 27 to 27
In 6, the occurrence of switching noise can be suppressed to a low level, and EMI can be reduced.

[6-3] Modifications In the above description, the data setting period is provided in the vertical blanking period, but it may be replaced with a horizontal blanking period. In this case, the horizontal synchronization signal HSYN
C is input to the data inversion circuits 54 and 56, and the horizontal blanking period is determined based on this.

The data setting period may be provided in the display period instead of the blanking period.

Furthermore, when the liquid crystal display device 10 of the present embodiment is powered on, the liquid crystal panel is irrespective of the image signal input to the liquid crystal display device 10 for a predetermined time until each circuit becomes stable. A black image signal is output to 12 so that black display is performed. Therefore, the power-on initial period during displaying the black color may be the data setting period described above.

Even if the power-on initial period is not set as the data setting period as described above, the data is set in the vertical blanking period or the horizontal blanking period immediately before the normal image is displayed after the end of the power-on initial period. The EMI level can be reduced only by providing the period.

[7] Writing Method Next, a method of writing the analog image signal Vs to each pixel electrode in this embodiment will be described with reference to FIG.

As described above, in the present embodiment, the effective display area is divided into upper and lower areas (AB screen and CD screen), and writing is performed in the horizontal pixel line of each area within each horizontal scanning period (1H). It is adopted.

For this reason, it is necessary to consider driving so that the boundary between upper and lower divisions is not visually recognized.

Further, when a direct current component is applied to the liquid crystal for a long time, the liquid crystal is deteriorated. Therefore, it is necessary to invert the voltage applied to the liquid crystal every predetermined period.

Therefore, for example, the method of inverting the polarity of the voltage applied to the pixel electrode for each field (F) with respect to the reference voltage and the method of inverting the polarity for each horizontal pixel line (H line inversion drive) Further, a method of inverting the polarity for each display pixel (HV inversion drive) is known,
HV inversion drive is effective for reducing flicker.

Therefore, it is considered that the HV inversion drive is adopted also in this embodiment, but for convenience of controlling the upper lead-out signal line 16a and the lower lead-out signal line 16b which are alternately arranged by different source drivers, As shown in FIGS. 6 and 7, H2V inversion drive (every horizontal pixel line, every two vertical pixel lines) is adopted.

In this embodiment, the polarity of the analog image signal Vs is inverted for each horizontal pixel line, but the polarity inversion cycle of the analog image signal Vs itself is reduced,
It employs a method that secures sufficient write time and achieves low power consumption.

That is, within one horizontal scanning period (H), the analog image signal Vs including the signals for the upper screen (AB screen) and the lower screen (CD screen) is output to each signal line 16, and each horizontal scanning is performed. Writing is performed on the corresponding horizontal pixel line in the first half and the second half of the period (H), and the polarity inversion cycle is the horizontal scanning period (H).

More specifically, as shown in FIG. 6, in the first half of one horizontal scanning period (H), a positive polarity analog image signal Vs is generated.
To the pixel electrode connected to the signal line R1 of the horizontal pixel line L1 and the positive polarity analog image signal Vs is written to the pixel electrode connected to the signal line R1 of the horizontal pixel line L2400 in the latter half. In the first half of the next horizontal scanning period (H), the negative polarity analog image signal Vs is applied to the pixel electrode connected to the signal line R1 of the horizontal pixel line L2399, and in the second half, the negative polarity analog image signal Vs is applied to the horizontal pixel line L2 signal. Writing is performed on the pixel electrode connected to the line R1.

By such an operation, the polarity is inverted for each horizontal pixel line, but the inversion period can be set as the horizontal scanning period.

[8] Writing state In the above driving, as shown in FIG.
There are different kinds of states.

First, the four types of states will be described.

[8-1] Positive polarity pre-write state (P1) Regarding the analog image signal Vs on the positive side with respect to the reference voltage, the analog image signal Vs supplied in the first half is based on the corresponding scanning pulse Vg. A state of writing in the pixel electrode during the period of K1.

[8-2] Positive Post Writing State (P2) Regarding the analog image signal Vs on the positive side with respect to the reference voltage, the analog image signal Vs supplied in the latter half is based on the corresponding scanning pulse Vg. A state of writing to the pixel electrode during the period of K2.

[8-3] Negative prewriting state (N1) Regarding the analog image signal Vs on the negative side with respect to the reference voltage, the analog image signal Vs supplied in the first half is based on the corresponding scanning pulse Vg. A state of writing in the pixel electrode during the period of K3.

[8-4] Negative polarity post-write state (N2) Regarding the analog image signal Vs on the negative side with respect to the reference voltage, the analog image signal Vs supplied in the latter half is based on the corresponding scanning pulse Vg. A state of writing in the pixel electrode during the period of K4.

These four states are different from each other in writing state, and thus cause display defects. More specifically, even when the same image is displayed, writing is more disadvantageous in the positive polarity pre-write state (P1) than in the positive polarity post-write state (P2). Similarly, the negative polarity pre-write state (N
Writing is more disadvantageous in 1) than in the negative post-writing state (N2). In particular, such a thing becomes remarkable under a severe writing condition, for example, a low temperature condition.

Further, for example, the positive polarity pre-write state (P1) and the negative polarity pre-write state (N1), or the positive polarity post-write state (P2) and the negative polarity post-write state (N2), It is not possible to achieve completely the same display quality due to the difference in polarity.

Thus, the liquid crystal display device 1 of this embodiment
At 0, it is desired to prevent the boundary between upper and lower divisions from being visually recognized at the time of driving, further suppress occurrence of flicker and display unevenness, and secure good display quality.

[9] Scanning Method Therefore, in this embodiment, the operation shown in FIGS. 6 and 7 is performed. Note that FIG. 6 shows a screen of n fields, and FIG.
Indicates a screen of n + 1 field.

In the scanning method, the upper screen (AB screen) is scanned from the top to the bottom, that is, the horizontal pixel line L1 to the horizontal pixel line L1200 is sequentially scanned, and the lower screen (CD screen) is scanned from the bottom to the top. Scanning, that is, sequential scanning in the reverse direction from the horizontal pixel line L2400 to the horizontal pixel line L1201.

The method of writing to the pixel electrode is the signal line R1.
For example, in the nth field, the corresponding pixel electrode of the horizontal pixel line L1 is set to the positive polarity pre-write state (P1) in the first half of one horizontal scanning period (H), and the horizontal pixel line L2400 is set in the second half. Pixel electrode for positive polarity is in the post-write state (P
2). In the first half of the next horizontal scanning period, the corresponding pixel electrode of the horizontal pixel line L2399 is set to the negative pre-write state (N
In the latter half, the corresponding pixel electrode of the horizontal pixel line L2 is set to the negative post-writing state (N2) in the latter half. After that, it is sequentially repeated. In the (n + 1) th field, the corresponding pixel electrode of the horizontal pixel line L1 is set to the negative polarity pre-write state (N1) in the first half of one horizontal scanning period, and the corresponding pixel electrode of the horizontal pixel line L2400 is set to the negative polarity in the second half. Write state (N2)
And In the first half of the next horizontal scanning period, the horizontal pixel line L23
The corresponding pixel electrode of 99 is set to the positive polarity pre-writing state (P1), and the corresponding pixel electrode of the horizontal pixel line L2 is set to the positive polarity post-writing state (P2) in the latter half. After that, it is sequentially repeated.

By controlling the scanning method and the polarity of the analog image signal Vs as described above, the problems pointed out above can be solved.

That is, by scanning the upper screen (AB screen) from the top to the bottom and scanning the lower screen (CD screen) from the bottom to the top, the horizontal pixel line L near the division boundary is scanned.
The writing timings to 1200 and L1201 become close in time, and the pixel potential drops during the holding period become substantially the same between adjacent horizontal pixel lines, so that the boundary is prevented from being visually recognized. As another method of reducing the visibility of the division boundary, for example, by scanning the upper screen (AB screen) from the bottom to the top and scanning the lower screen (CD screen) from the top to the bottom, Horizontal pixel line L near the boundary
It is possible to make the write timings to the 1200 and L1201 close in time.

Also, the upper screen (AB screen) and the lower screen (CD
Since the four states related to writing are dispersed in the screen and the screen, it is possible to prevent the display state from being different between the upper screen (AB screen) and the lower screen (CD screen).

The polarity control of the analog image signal Vs described above is based on the polarity inversion signal POL transmitted from the liquid crystal controllers 38 and 40 to the source drivers 24, 25, 26 and 27. The driver digital-analog converts the image data input based on the polarity inversion signal POL into a positive polarity or negative polarity analog image signal Vs.

[10] Modification 1 The above-mentioned embodiment shows an optimum example of the present invention. Instead of the scanning shown in FIGS. 6 and 7, scanning is performed as shown in FIGS. 8 and 9, for example. It doesn't matter.

[11] Modification 2 The scanning method shown in FIGS. 15 and 16 can also be adopted. This is because the pre-writing state (P1, N1) and the post-writing state (P2, N2) are fixed in the scanning method in FIGS. 6 and 7, but in the scanning method shown in FIGS.
Pre-write state (P1, N1) and post-write state (P2, N2)
And are not fixed in each horizontal pixel line. This effectively reduces the occurrence of display unevenness in a specific display pattern such as a horizontal stripe screen.

[12] Modification 3 Besides the above, it is also possible to sequentially scan the upper screen (AB screen) and then the lower screen (CD screen).

[13] Modification 4 Further, in the above embodiment, four screens of A, B, C, and D are realized, but the present invention is not limited to this, and 6 or 8 divided screens are arranged. The present embodiment can be applied to division. Further, the present embodiment can be applied to the upper and lower split screens.

[14] Modification 5 Although this embodiment is realized in a liquid crystal display device, it can be suitably used in another flat display device such as an organic EL display device instead.

[15] Modification 6 By the way, referring to FIG. 5, there are four states for writing,
The positive polarity pre-write state (P1) is more positive polarity post-write state (P1).
Writing is disadvantageous as compared with 2), and similarly, the negative polarity pre-write state (N1) is the negative polarity post-write state (N2).
I explained that writing is disadvantageous compared to.

Therefore, in addition to the method of distributing each state to each screen area as described above, the disadvantageous state is reduced, for example, the positive polarity prewriting state (P1) and / or the negative polarity prewriting state. The amplitude of the scan pulse of (N1) is changed to the positive post-writing state (P2) and / or the negative post-writing state (N2).
It may be larger than that, or the width of the scanning pulse may be longer, and it may be used in combination with the above method.

Further, the writing may be relaxed by performing preliminary scanning prior to the positive polarity prewriting state (P1) and / or the negative polarity prewriting state (N1).

[0135]

As described above, in the flat panel display device of the present invention, when the data inversion transmission method is used, the data inversion is performed so that the polarities of the image data output by the two lines are inverted at a predetermined timing. Since the signal is controlled, generation of switching noise can be prevented and EMI can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a liquid crystal display device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a divided state of an effective display area.

FIG. 3 is a block diagram showing a circuit configuration of a liquid crystal display device.

FIG. 4 is a block diagram for an AC screen.

FIG. 5 is a waveform diagram of an analog image signal and a scan pulse showing a writing state to a pixel electrode.

FIG. 6 is a diagram showing a writing state of an n-th field in the present embodiment.

FIG. 7 is a diagram showing a written state of an (n + 1) th field.

FIG. 8 is a diagram showing a writing state of an n-th field in the first modification.

FIG. 9 is a drawing of a screen showing the writing state of the (n + 1) th field of the first modification.

FIG. 10 is a timing diagram of the data interface at horizontal timing.

FIG. 11 is a timing diagram of a data interface at vertical timing.

FIG. 12 is a data input / output timing chart of the liquid crystal controller.

FIG. 13 is an enlarged view of an upper screen data output period.

FIG. 14 is an enlarged view of a lower screen data output period.

FIG. 15 is a diagram showing a writing state of the n-th field in the second modification.

FIG. 16 is a drawing of a screen showing the writing state of the (n + 1) th field in the second modification.

FIG. 17 is a block diagram of an S / P controller and a source driver using a conventional data inversion transmission method.

FIG. 18 is a diagram showing a state of a signal using the conventional data inversion transmission method.

FIG. 19 shows S / using the data inversion transmission method of the present embodiment.
It is a block diagram of a P controller and a source driver.

FIG. 20 is a diagram of data transmission in the data inversion transmission method of the present embodiment.

FIG. 21 is a conceptual diagram showing a polarity state of a data inversion transmission method in the liquid crystal display device of the present embodiment.

[Explanation of symbols]

10 Liquid crystal display device 12 LCD panel 14 Array substrate 16 signal lines 18 scan lines 20 TFT 22 Pixel electrode 24 Upper Source Driver for AC Screen Upper Source Driver for 25 BD Screen 26 Lower Source Driver for AC Screen 27 Lower source driver for BD screen 28 Gate driver for upper screen 30 Gate driver for lower screen 34 LCD controller 46 S / P controller 51 First Data Inversion Circuit 56 second data inversion circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 612Z 633 633H F term (reference) 2H093 NA34 NA36 NB07 NB11 NC16 NC22 NC34 ND02 ND40 5C006 AF45 AF51 AF53 AF61 AF71 AF73 BB14 BB16 BC12 BC16 BC20 BF03 BF05 BF24 FA32 5C080 AA06 AA10 BB05 CC06 DD12 FF11 JJ02 JJ04

Claims (6)

[Claims] 1. An array substrate comprising a plurality of signal lines and scanning lines arranged orthogonally to each other, and a pixel electrode arranged via a switch element in the vicinity of an intersection of the signal lines and the scanning lines. A signal line driving circuit which is connected to the signal line and supplies an image signal; and a scanning which is connected to the scanning line and supplies a gate signal for writing the image signal in the pixel electrode by turning on the switching element. A line driving circuit, and a circuit for outputting at least two m-bit image data in parallel to the signal line driving circuit, each bit of the (n + 1) th image data for each bit of the nth image data If is changed by more than half, then (n +
1) The image data is logically inverted and output, and
A data inversion signal indicating that the (n + 1) th image data is inverted data is output, and each bit of the (n + 1) th image data changes by more than half for each bit of the nth image data. If not, the (n +
1) The image data is output without being logically inverted, and a control circuit that outputs a data inversion signal indicating that the (n + 1) th image data is non-inversion data, The flat panel display device, wherein the control circuit controls a data inversion signal so that the polarities of the image data output in parallel in two are fixed so as to be inverted at a predetermined timing. 2. The flat panel display device according to claim 1, wherein the control circuit is incorporated in one chip. 3. A control circuit for outputting image data from a first wiring of the two parallels is incorporated in a first chip, and a control circuit for outputting image data from a second wiring of the two parallels is a first. The flat display device according to claim 1, wherein the flat display device is incorporated in a second chip, and the first chip and the second chip are arranged close to each other. 4. The flat panel display device according to claim 1, wherein the data inversion signal is controlled so that the polarities of the image data output in parallel in two are inverted in the horizontal blanking period. 5. The flat panel display device according to claim 1, wherein the data inversion signal is controlled so that the polarities of the image data output in two parallels are mutually inverted in the vertical blanking period. 6. The signal line drive circuit is a two-port input, and the control circuit extends the time axis of the image data and guides two lines in parallel to each port of the signal line drive circuit. The flat panel display device according to claim 1, which is characterized in that: