JP2003057308A - Electronic device, and method of inspecting quality of electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contactlessly inspect quality of a circuit in an electronic device without making a probe needle contact with an electrode pad, when the quality is inspected. SOLUTION: In this inspection method for inspecting the quality of the circuit in the electronic device mounted with one or plural electronic device(s) on a wiring board, an own inspection circuit and the in-electronic-device circuit are driven using electric power by a high-frequency electromagnetic wave from an external high-frequency generating means to transmit a test pattern from the own inspection circuit to the in-electronic-device circuit, a response signal of the test pattern transmitted to the in-electronic-device circuit is received, the quality of the circuit in the electronic device is judged based on the received response signal, and a judged result therein is displayed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for inspecting the quality of an electronic device, and more particularly to a technique effective when applied to a quality inspection step in manufacturing a semiconductor device (hereinafter, simply referred to as a chip). It is a thing. For example, it is effective when applied to a probe test and burn-in of a chip having external electrodes (pads) with a narrowed pitch.

[0002]

2. Description of the Related Art A chip manufacturing method comprises a pre-process and a post-process. A probe test process and a burn-in process are typical inspection processes of the circuit in the chip in the pre-process and the post-process. The probe test step is an inspection step in the previous step, and is performed after the wafer process is completed and the regions of the semiconductor device before being diced are formed in a matrix on the wafer.

In the probe test, the quality of a plurality of in-chip circuits formed on a semiconductor device wafer is inspected. In this inspection, first, a probe needle or the like is applied to the external electrode (pad) of the chip to be measured, and the oxide film, foreign matter, and dirt are removed (wibbing) by sliding them together, and electrical connection is measured with low contact resistance. Next, pressure is applied to conduct a continuity test and a function test at room temperature or high temperature. The above electrical connection, continuity test, and function test are sequentially and automatically performed. This probe test determines that it is defective.

[0004]

The present inventor has found the following problems as a result of examining the above-mentioned prior art.

In the probe test, since the probe needle and the pad are brought into electrical contact by sliding on each other, after the probe test inspection is completed, a probe mark (indentation) is formed on the electrode pad which the probe needle was in contact with. . This indentation has a problem that the bonding property is deteriorated in the packaging process, and a required bonding strength cannot be secured. In this case, there is also a measure to perform bonding at a portion displaced from the portion where the probe needle comes into contact and the impression is left, but in recent years, it has become necessary to perform bonding at a narrow pitch as the chip becomes smaller and the pad becomes finer. The pad area is also limited. For example,
When the pad width is 55 μm, a predetermined area required for bonding is required. Therefore, during the probe test, it has become impossible to perform bonding at the portion displaced from the portion where the probe needle contacts and the indentation remains.

Further, when a chip in which the bonding strength is not secured is packaged and burn-in is performed, a short circuit occurs, and a current suddenly flows in the circuit,
If the chip is damaged, or if a plurality of chips are burned in at the same time, other chips will be damaged or the burn-in substrate will be damaged.

An object of the present invention is to provide a technique capable of performing a non-contact probe test without contacting the probe needle with the pad of the chip when inspecting the quality of the circuit in the semiconductor device. It is in.

Another object of the present invention is to provide a semiconductor device provided with a means for performing a probe test in a non-contact manner when inspecting the quality of a circuit in the semiconductor device.

Another object of the present invention is to provide a technique capable of contactlessly inspecting a circuit in an electronic device for quality.

Another object of the present invention is to provide an electronic device provided with means for contactlessly inspecting the circuit inside the electronic device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

A first aspect of the present invention is a method for inspecting the quality of a circuit in an electronic device in which one or a plurality of electronic devices are mounted on a wiring board. The self-inspection circuit uses electric power from high frequency electromagnetic waves from an external high frequency generating means. And driving an internal circuit of the electronic device, transmitting a test pattern from the self-inspection circuit to the internal circuit of the electronic device, receiving a response signal of the test pattern transmitted to the internal circuit of the electronic device, and receiving the received response. In this inspection method, the quality of the circuit in the electronic device is judged by a signal, and the judgment result is displayed.

According to the inspection method of the first invention, the electronic device can be inspected in a non-contact manner.

A second aspect of the present invention is a method for inspecting the quality of a circuit in an electronic device in which one or a plurality of electronic devices are mounted on a wiring board, which is different from the area where the electronic device is mounted on the wiring board. In the area, the first step of forming the LC resonance circuit, the rectification circuit, the result display means, the self-inspection circuit, the circuit in the electronic device, and the high frequency electromagnetic wave from the external high frequency generation means
A second step of performing resonance amplification in a resonance circuit and converting it into electric power by the rectifier circuit; and a third step of driving the self-inspection circuit and the electronic device circuit with the obtained electric power.
A fourth step of transmitting a test pattern from the self-inspection circuit to the internal circuit of the electronic device; and a fourth step of judging pass / fail of the internal circuit of the electronic device based on a response signal of the test pattern transmitted to the internal circuit of the electronic device. It is an inspection method having 5 steps and a 6th step of displaying a judgment result of the quality of the circuit in the electronic device on the result display means.

According to the inspection method of the second invention, the electronic device can be inspected in a non-contact manner. In particular,
A high frequency electromagnetic wave (energy) is generated by driving a high frequency generating means provided outside to radiate a high frequency electromagnetic wave and resonantly amplifying an LC resonance circuit provided in the electronic device. It is converted into electric power by the rectifier circuit. The electric power drives the self-inspection circuit and the circuit in the electronic device, the driven self-test circuit transmits a test pattern (inspection signal) to the circuit in the electronic device, and the circuit in the electronic device is generated by the response signal from the electronic device. It becomes possible to inspect the quality of. With the above inspection method, it is possible to identify a defective electronic device.

A third invention is the method for inspecting the electronic device according to the first invention, wherein the fourth step and the fifth step are performed.
The process includes a test pattern data storage unit, a test pattern generation unit, a comparison unit, an expected output value storage unit, and a central processing unit in the self-inspection circuit, and a test stored in advance in the test pattern data storage unit. A test pattern necessary for inspection is extracted from the pattern data, the extracted test pattern is transmitted to the electronic device internal circuit, and the transmitted test pattern is expected as a response signal from the electronic device internal circuit. This is an inspection method for comparing the expected value of the output response signal with the expected value of the output retrieved from the expected value storage unit to judge whether the circuit in the electronic device is good or bad.

According to the inspection method of the third aspect of the present invention, a test pattern (inspection signal) is transmitted and received from the self-inspection circuit to the internal circuit of the electronic device to determine the quality of the internal circuit of the electronic device. The electronic device can be inspected by using the necessary test pattern data and the expected output value expected as the response signal of the test pattern.
As a result, the cost can be reduced without the need to separately prepare an inspection device.

A fourth aspect of the present invention is a device mounted on a wiring board.
An electronic device including an individual or a plurality of electronic devices, and an LC resonance circuit, a rectifier circuit, a result display unit, and a self-inspection circuit, which are provided in a region other than a region where the electronic device is mounted on the wiring board. The LC resonant circuit resonantly amplifies a high frequency electromagnetic wave from the external high frequency generating means, and the rectifier circuit converts the high frequency electromagnetic wave (energy) from the LC resonant circuit into electric power, which is converted. Power to the self-inspection circuit and the circuit in the electronic device, the self-inspection circuit is driven by the power supplied by the rectifier circuit,
The test pattern is transmitted to the circuit in the electronic device, the quality of the circuit in the electronic device is determined based on the response signal of the transmitted test pattern, and the result of the quality of the circuit in the electronic device is displayed on the result display means. It is something to display.

According to the electronic device of the fourth aspect of the present invention, in an electronic device having a plurality of semiconductor devices mounted thereon, the electronic device can be inspected in a non-contact manner only by providing a high-frequency generating means outside, which results in a defect. The electronic device can be specified.

A fifth invention is the electronic device of the fourth invention, wherein the self-test circuit stores a test pattern data storage unit for storing a plurality of test patterns used for testing a circuit in the electronic device, and the test. A test pattern generation unit that extracts a test pattern necessary for inspection of an internal circuit of the electronic device from the pattern data storage unit and transmits the extracted test pattern to the internal circuit of the electronic device, and a test pattern transmitted to the internal circuit of the electronic device. An expected output value storage section for storing an expected output value signal corresponding to a response signal, a comparison section for comparing a response signal to the test pattern transmitted from the test pattern generation section with the expected output value signal, and the test pattern storage section. Section, a test pattern generation section, an expected output value storage section, and a processing control means for controlling the comparison section. .

According to the electronic device of the fifth aspect, the inspection can be performed in the electronic device without the need for an external inspection device.
As a result, the cost can be reduced without the need to separately prepare an inspection device.

A sixth aspect of the present invention is a method for collectively inspecting a plurality of semiconductor devices (hereinafter simply referred to as chips) formed on a semiconductor wafer in a wafer state, which is one of the main components of the semiconductor wafer. An LC resonance circuit, a rectifier circuit, a result display means, a self-inspection circuit, and an in-chip circuit are formed in a plurality of chip formation regions partitioned by a dicing area on the surface.
A twelfth process in which the high frequency electromagnetic wave from the external high frequency generating means is resonantly amplified by the LC resonance circuit, and the high frequency electromagnetic wave (energy) is converted into electric power by the rectifier circuit.
A step, a thirteenth step of driving the self-inspection circuit and the in-chip circuit with the obtained power, a fourteenth step of transmitting a test pattern from the self-inspection circuit to the in-chip circuit, and the in-chip circuit A fifteenth step of judging the quality of the in-chip circuit based on the response signal of the test pattern transmitted to the test pattern, and a sixteenth step of displaying the judgment result of the quality of the in-chip circuit on the result display means. It is an inspection method.

According to the inspection method of the sixth aspect of the present invention, a plurality of chips formed on a semiconductor wafer can be collectively inspected in a wafer state in a non-contact manner. Therefore, the bonding failure due to the indentation of the probe needle does not occur.

A seventh aspect of the present invention is the method of inspecting a semiconductor device (hereinafter, simply referred to as a chip) of the sixth aspect, wherein the fourteenth and fifteenth steps are performed by the self-inspection circuit.
Test pattern data storage unit, test pattern generation unit,
The test pattern is provided with a comparison unit, an expected output value storage unit, and a control / processing device, and a test pattern necessary for inspection is extracted from the test pattern data stored in advance in the test pattern data storage unit, and the extracted test pattern is The output response signal expected value, which is transmitted to the in-chip circuit and is expected as a response signal from the in-chip circuit for the transmitted test pattern, is compared with the expected output value fetched from the expected output value storage unit. However, this is an inspection method for determining the quality of the circuit in the chip.

According to the inspection method of the seventh aspect of the present invention, a test pattern is transmitted and received from the self-inspection circuit to the in-chip circuit to judge whether the circuit in the electronic device is good or bad. By using the expected output value expected as the response signal of the pattern data and the test pattern, it becomes possible to judge the quality of the circuit in the electronic device. As a result, the cost can be reduced without the need to separately prepare an inspection device.

An eighth aspect of the present invention is a device mounted on a wiring board.
An individual or a plurality of semiconductor devices (hereinafter, simply referred to as a chip), and an LC resonance circuit, a rectifier circuit, a result display unit, and a self-test provided in a region other than the region where the chip is mounted on the wiring board. A semiconductor device including a circuit, the LC resonance circuit resonantly amplifies high-frequency electromagnetic waves from an external high-frequency generation unit, and the rectifier circuit includes the L
The high-frequency electromagnetic wave (energy) from the C resonance circuit is converted into electric power, and the converted electric power is supplied to the self-inspection circuit and the in-chip circuit, and the self-inspection circuit is driven by the electric power supplied by the rectification circuit. Then, the test pattern is transmitted to the circuit in the electronic device, the response signal of the transmitted test pattern is received, the quality of the circuit in the chip is determined from the response signal, and the result of the quality of the circuit in the chip is determined. The result display unit transmits the result to the result display unit, and the result display unit receives the signal from the self-inspection circuit and displays the quality of the in-chip circuit.

According to the semiconductor device of the eighth aspect of the present invention, it is possible to inspect the quality of the in-chip circuit formed in the semiconductor device without contact from the outside, only by providing the high frequency generating means outside. As a result, defective bonding due to the indentation of the probe needle does not occur.

Further, each chip is provided with an LC resonance circuit and a rectifier circuit, and power can be supplied to each chip for inspection. As a result, at the time of burn-in, even if some defective chips are short-circuited, a high current will flow through all the chips and other chips will not be destroyed. Also,
The burn-in substrate is not damaged due to the above causes.

According to a ninth aspect of the invention, in the semiconductor device of the eighth aspect (hereinafter, simply referred to as a chip), the self-inspection circuit stores a plurality of test patterns used for inspecting the quality of an in-chip circuit. A test pattern data storage unit, a test pattern generation unit that extracts a test pattern necessary for checking the quality of the in-chip circuit from the test pattern data storage unit, and transmits the extracted test pattern to the in-chip circuit; An output expected value storage unit that stores an output expected value signal corresponding to the response signal of the test pattern transmitted to the in-chip circuit, a response signal to the test pattern transmitted from the test pattern generation unit, and the output expected value signal. The comparison unit for comparison, the test pattern storage unit, the test pattern generation unit, the expected output value storage unit, and the comparison unit. Those comprising a Gosuru control and processing means.

According to the ninth aspect, by configuring the self-inspection circuit as described above, it is possible to inspect the quality of the in-chip circuit without requiring an external inspection device. As a result, the cost can be reduced without the need to separately prepare an inspection device.

A tenth aspect of the present invention has a plurality of semiconductor device (hereinafter simply referred to as “chip”) formation regions partitioned by a dicing area on one main surface, and each of the plurality of chip formation regions has a result display means. , A self-inspection circuit and an in-chip circuit are formed, and the LC resonance circuit and the rectification circuit are semiconductor wafers formed in an outer peripheral region of one main surface of the semiconductor wafer. The high-frequency electromagnetic wave from the generating means is resonantly amplified, the rectifier circuit converts the high-frequency electromagnetic wave resonantly amplified by the LC resonant circuit into electric power, and the converted electric power is supplied to a self-inspection circuit and an in-chip circuit. Then, the self-inspection circuit is driven by the power supplied by the rectifier circuit, transmits a test pattern to the circuit in the electronic device, and outputs a response signal of the transmitted test pattern. And Shin, trillion Zui and to the received response signal to determine the quality of the chip circuit, and displays the result display means the results of the quality of the chip circuitry.

According to the tenth aspect of the invention, since the LC resonance circuit and the rectifier circuit are provided for each semiconductor wafer, the chip area can be reduced and the cost can be reduced.

An eleventh invention is the semiconductor wafer of the tenth invention, wherein the LC resonance circuit and the rectifier circuit are formed in a chip formation region or a plurality of chip formation regions.

According to the eleventh aspect, by providing the LC resonance circuit and the rectification circuit for each of the plurality of chips,
Since the chip area can be reduced, the cost can be reduced.

A twelfth invention is the semiconductor wafer according to the tenth invention, wherein the LC resonance circuit and the rectifier circuit are formed in a dicing area.

According to the twelfth aspect, by forming the LC resonance circuit and the rectification circuit in the dicing area, the LC resonance circuit and the rectification circuit can be formed without increasing the chip area, so that the cost can be reduced. it can.

Hereinafter, the present invention will be described in detail with reference to the drawings together with the embodiments (examples).

In all the drawings for explaining the embodiments (examples), components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit (semiconductor device) of a first embodiment of the present invention, and FIG. 2 is a self-inspection of a semiconductor device of the first embodiment. FIG. 3 is a block diagram showing a schematic configuration of the circuit, and FIG. 3 is a diagram for explaining a method of inspecting the quality of the circuit in the semiconductor device of the first embodiment. 1 to 3, 101 is a semiconductor integrated circuit (hereinafter simply referred to as a chip), 102 is an L circuit (power receiving antenna: power receiving unit), 103 is a rectifier circuit, 104 is a result display unit, 105 is a self-check circuit, 106 is a circuit in a semiconductor integrated circuit (hereinafter, simply referred to as a chip), 107 is a capacitor, 108 is a high frequency generation circuit (means), 201 is a test pattern generation unit, 202 is a test pattern data storage unit, 203 is a comparison unit, 204 Is an expected output value storage unit, 2
Reference numeral 05 denotes a control / processing device (for example, a CPU is used), 3
01 is a semiconductor device wafer.

As shown in FIG. 1, the chip 101 of the semiconductor integrated circuit according to the first embodiment has therein an L circuit 102, a rectifying circuit 103, a result display means 104, and a self-inspection circuit 10.
5, an on-chip circuit 106, and a capacitor 107.

The L circuit 102 constitutes an LC resonance circuit together with the capacitor 107, resonance-amplifies a high-frequency electromagnetic wave from the high-frequency generation circuit 108, and supplies the resonance-amplified high-frequency electromagnetic wave (energy) to the rectifier circuit 103.

The rectifier circuit 103 converts the high frequency electromagnetic wave (energy) supplied from the LC resonance circuit into electric power and supplies the electric power to the self-inspection circuit 105 and the on-chip circuit 106.

The self-inspection circuit 105 is driven by the power supplied from the rectifier circuit 103, transmits a test pattern to the in-chip circuit 106, receives a response signal of the transmitted test pattern, and receives the received response. The quality of the on-chip circuit 106 is determined based on the signal. Then, the result of pass / fail of the on-chip circuit 106 is transmitted to the result display means 104. For example, it may be transmitted to the result display unit 104 only when the inspection result is defective.

The result display means 104 is a self-inspection circuit 105.
The inspection result signal is received from and the quality of the in-chip circuit is displayed. For example, a fuse may be formed, and in the case of a chip determined to be defective, the fuse may be blown to display. For example, it is made of polysilicon, and a laser beam is squeezed to irradiate the laser beam so that the laser beam is fused.

Further, the high-frequency generating means 108 is provided outside the apparatus and has a resonance circuit (not shown) for generating a high-frequency electromagnetic wave therein, which generates a high-frequency electromagnetic wave.
The L circuit 102 provided in the electric device is supplied with electric power in the form of a high frequency electromagnetic wave, and is resonantly amplified by the LC resonance circuit including the L circuit and the capacitor 107, and the high frequency electromagnetic wave resonantly amplified by the rectifier circuit 103. Supply (energy).

The self-inspection circuit, as shown in FIG.
Test pattern generation unit 201, test pattern storage unit 2
02, comparison unit 203, expected output value storage unit 204, control /
A processing unit (CPU) 205 is provided, and BIST (B
The uilt In Self Test method enables the inspection of the circuit inside the chip.

The test pattern generation unit 201 takes out a test pattern (test pattern) from the test pattern data storage unit and transmits the taken-out test pattern to the in-chip circuit 106.

The test pattern data storage unit 202
Various test pattern data are stored in advance.

The expected output value storage section 204 stores in advance an expected signal expected as a response signal to the test pattern transmitted to the on-chip circuit 106.

The comparing unit 203 is the test pattern generating unit 2
A response signal to the test pattern transmitted from 01 to the in-chip circuit 106 is received, and the received response signal is compared with the expected output value signal obtained in advance from the expected output value storage unit 204, and the in-chip circuit 106 is compared. The quality display of the in-chip circuit 106 is inspected for the result display means 10
Send to 4. The control / processing device (CPU) 205
Controls and processes the test pattern generation unit 201 and the comparison unit 203.

The inspection of the quality of the in-chip circuit 106 is performed by
As shown in FIGS. 1 to 3, first, the high frequency generating means 108 provided outside is activated to generate a high frequency electromagnetic wave. The L circuit 1 formed on the chip 101 by this electromagnetic wave
02, and the received electromagnetic wave is the L circuit 10
2 is resonantly amplified by an LC resonant circuit configured by 2 and the capacitor 107, and an amplified high frequency electromagnetic wave (energy) is generated. This high frequency electromagnetic wave (energy) is supplied to the rectifier circuit 103.

Next, the rectifier circuit 103 converts the supplied high frequency electromagnetic wave (energy) into electric power and supplies the electric power to the self-inspection circuit 105 and the on-chip circuit 106. The self-inspection circuit 105 and the in-chip circuit 106 are driven by the supplied power, and the test pattern is transmitted from the pattern generation unit 201 of the self-inspection circuit 105 to the in-chip circuit 106.

Next, the in-chip circuit 106 transmits a response signal to the test pattern to the comparison section 203 of the self-inspection circuit 105, and the comparison section 203 outputs the response signal to the in-chip circuit 106 based on the transmitted response signal. Make a pass / fail judgment. The judgment result is transmitted to the result display means 104. Next, the result display means 104 displays the quality of the chip 101 based on the transmitted signal.

By the inspection method of the quality of the in-chip circuit 106, a probe test of a plurality of chips 101 formed on a semiconductor wafer without contact can be performed. Therefore, no probe mark (indentation) is formed on the pad of the chip 101 in the probe test, so that the entire surface of the pad can be used as a bonding portion. Therefore, even in the narrow pitch bonding, a predetermined bonding strength can be stably ensured.

Further, the L circuit 102, the capacitor 107, and the rectifying circuit 103 are provided in each chip, and power can be supplied in chip units to inspect the quality of the in-chip circuit 106. Therefore, at the time of burn-in, even if some of the defective chips are short-circuited, a high current flows through all the chips and other chips are not destroyed.

Further, the burn-in substrate is not damaged due to the same reason as described above. Since the burn-in can be performed in the packaging wafer state, only good products can be packaged and the cost can be reduced.

Further, since the burn-in up to now has been performed after packaging, it was not possible to specify the area where defective products are manufactured at the wafer level in the manufacturing process, but since the burn-in can be performed in the wafer state, the area can be specified. I can do it now. Therefore, the burn-in result can be fed back to the manufacturing process.

Further, before the wiring is carried out in the later process, the functional inspection of the chip can be performed at any time.

Further, not only the expensive probe needle kid applied on a narrow pad is not required, but also the maintenance work of the probe needle kid is not required, so that the cost of the jig and tool can be reduced.

(Embodiment 2) FIG. 4 is a diagram for explaining a method for inspecting the quality of a circuit in a semiconductor integrated circuit (semiconductor device) according to Embodiment 2 of the present invention.

Chip 30 of the semiconductor integrated circuit of the second embodiment
As shown in FIG. 4, an L circuit 102, a capacitor 107, and a rectifier circuit 103 are provided on the outer periphery of a semiconductor wafer, and the power generated by the rectifier circuit 103 is supplied to each chip 10 as shown in FIG.
1 is characterized in that a wiring (not shown) for supplying to No. 1 is provided.

By doing this, L
Since it is not necessary to provide the circuit 102, the capacitor 107, and the rectifier circuit 103, the chip area can be reduced. As a result, the number of chips per one semiconductor wafer can be increased, and the cost can be reduced.

(Embodiment 3) FIG. 5 is a diagram showing a schematic structure of a semiconductor wafer according to Embodiment 3 of the present invention. FIG. 5A is a wafer image diagram, and FIG. 5B is a circle mark in FIG. It is a figure which shows the detailed structure of the area | region shown by. In FIG. 5, 501 is a power supply area and 502 is a dicing area. Figure 5
Is an example in which an L circuit 102, a capacitor 107 (not shown), and a rectifying circuit 103 are provided for each of the six chips 101.

The semiconductor device (chip) of the third embodiment is provided with an L circuit 102, a capacitor 107, and a rectifying circuit 103 for each of a plurality of chips, and the power generated by the rectifying circuit 103 is supplied to each of the plurality of semiconductor integrated circuits. (Chip) 101
It is characterized in that a wiring (not shown) for supplying the power to the circuit is provided, and the L circuit 102, the capacitor 107, and the rectifying circuit 103 are provided in the dicing area.

By doing so, without increasing the chip area, reducing the effective element area of the wafer, and without contacting the probe needle with the electrode pad, it is possible to determine whether the circuit inside the chip is good or bad. An inspection can be done.

(Embodiment 4) FIG. 6 is a diagram showing a schematic structure of a semiconductor wafer according to Embodiment 4 of the present invention. FIG. 6A is a wafer image diagram, and FIG. 6B is a circle mark in FIG. It is a detailed view of a power supply area 501 portion shown by. In FIG. 6, 6
Reference numeral 01 is a probe inspection area.

As shown in FIG. 6, the semiconductor integrated circuit (chip) 101 of the fourth embodiment has an L circuit 1 on each chip 101.
02, the capacitor 107, and the rectifying circuit 103 are provided, which is the same as the first embodiment, but is characterized in that it is provided in the dicing area.

By doing so, it is possible to determine whether the circuit inside the chip is good or bad without contacting the electrode pad with the probe needle without reducing the effective element area of the semiconductor wafer and without increasing the chip area. Can be inspected.

Since it is possible to individually inspect the quality of the in-chip circuits of a plurality of chips, semiconductor integrated circuit chips other than the semiconductor integrated circuit chips determined to be defective will not be destroyed, and burn-in will not occur. The board is not damaged.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention.

For example, although the semiconductor device has been described as an example in the above embodiment, the above-mentioned L circuit 10 is provided on the wiring board.
2. By forming a semiconductor device having the same functions as the rectifier circuit 103, the result display means 104, and the self-inspection circuit, the same is true in the method of inspecting the quality of the circuit in the electronic device in which a plurality of semiconductor devices are mounted. The effect is obtained.

[0073]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.

According to the present invention, the quality of the circuit in the electronic device can be inspected without contact.

Further, in a plurality of semiconductor devices (chips) formed on a semiconductor wafer, the quality of the circuits in the chip can be inspected from the outside without contact by only providing the high-frequency generating means to the outside. No defective bonding due to the indentation is caused.

Further, since it is possible to supply power on a chip-by-chip basis and inspect the quality of the circuits in the chip, even if some defective chips are short-circuited during burn-in, a high current flows through all the chips, and The semiconductor device (chip) is not destroyed. Also, due to the same cause as above,
It does not damage the burn-in board.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit (semiconductor device) according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a self-inspection circuit of a semiconductor integrated circuit (semiconductor device) according to the first embodiment.

FIG. 3 is a diagram for explaining a method of checking the quality of the semiconductor integrated circuit according to the first embodiment.

FIG. 4 is a diagram for explaining a method of inspecting the quality of the semiconductor integrated circuit according to the second embodiment.

FIG. 5 is a diagram showing a schematic configuration of a semiconductor wafer according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a schematic configuration of a semiconductor wafer of Example 4 of the present invention.

[Explanation of symbols]

101 ... Semiconductor integrated circuit (chip) 102 ... L circuit (power receiving antenna: power receiving unit) 103 ... Rectifier circuit 104 ... Result display means 105 ... Self-inspection circuit 106 ... In-chip circuit 107 ... Capacitor 108 ... High frequency generating circuit (means) 201 Test pattern generating unit 202 Test pattern data storage unit 203 Comparing unit 204 Expected output value storage unit 205 Control / processing device (CPU) 301 Semiconductor device wafer 302 Chip forming area 501 Power supply area 502 Dicing Area 601 ... Inspection area

Front page continuation (51) Int.Cl. ⁷ Identification symbol FI theme code (reference) G06F 11/22 340 G01R 31/28 V H01L 21/66 Q F term (reference) 2G132 AA01 AA11 AB03 AE16 AF11 AG02 AK09 AK22 AK29 4M106 AA01 AC07 BA01 BA20 DD01 DD30 5B048 AA22 CC11 DD05 DD09 FF01

Claims (5)

[Claims] 1. A method of inspecting the quality of an electronic device having one or a plurality of electronic devices mounted on a wiring board, comprising: a self-inspection circuit and an internal circuit of the electronic device by electric power from high frequency electromagnetic waves from an external high frequency generating means. It drives, the test pattern is transmitted from the self-inspection circuit to the circuit in the electronic device, the response signal of the test pattern transmitted to the circuit in the electronic device is received, and the electronic device based on the received response signal. A method for inspecting the quality of an electronic device, comprising determining the quality of a circuit in the device and displaying the result of the determination. 2. A method for inspecting the quality of an electronic device having one or a plurality of electronic devices mounted on a wiring board, comprising LC resonance in a region different from the region where the electronic device is mounted on the wiring substrate. A first step of forming a circuit, a rectifying circuit, a result display means, a self-inspection circuit, and a circuit in an electronic device; A second step of converting the self-test circuit to the internal circuit of the electronic device with the obtained electric power; and a fourth step of transmitting a test pattern from the self-test circuit to the internal circuit of the electronic device. A step, a fifth step of judging pass / fail of the circuit in the electronic device based on a response signal of the test pattern transmitted to the circuit in the electronic device, and a judgment result of pass / fail of the circuit in the electronic device. And a sixth step of displaying the result on the result display means. 3. The method of inspecting the quality of an electronic device according to claim 2, wherein in the fourth step and the fifth step, the self-inspection circuit includes a test pattern data storage section, a test pattern generation section, a comparison section, An output expected value storage unit and a control / processing device are provided, and a test pattern required for inspection is extracted from the test pattern data stored in advance in the test pattern data storage unit, and the extracted test pattern is stored in the electronic device. The output response signal expected value transmitted to the circuit and expected as a response signal from the circuit in the electronic device with respect to the transmitted test pattern and the output expected value retrieved from the output expected value storage unit are compared. ,
A method for inspecting the quality of an electronic device, comprising determining the quality of a circuit in the electronic device. 4. One or a plurality of electronic devices mounted on a wiring board, and an LC resonance circuit, a rectifying circuit, and a result provided in a region different from a region of the wiring substrate on which the electronic device is mounted. An electronic device comprising a display means and a self-inspection circuit, wherein the LC resonance circuit resonance-amplifies a high-frequency electromagnetic wave from an external high-frequency generation means, and the rectifier circuit generates a high-frequency wave from the LC resonance circuit. The electromagnetic wave (energy) is converted into electric power, and the converted electric power is supplied to a self-inspection circuit and a circuit in the electronic device, and the self-inspection circuit is driven by the electric power supplied by the rectifier circuit, A test pattern is transmitted to the circuit, a response signal of the transmitted test pattern is received, the quality of the circuit in the electronic device is determined from the received response signal, and the result of the quality of the circuit in the electronic device is determined. An electronic device, which transmits the result to a result display unit, wherein the result display unit receives the signal from the self-inspection circuit and displays the quality of the circuit in the electronic device. 5. The electronic device according to claim 4, wherein the self-inspection circuit includes a test pattern data storage unit that stores a plurality of test patterns used for inspection of a circuit in the electronic device, and the test pattern data storage unit. Corresponding to a test pattern generation unit that extracts a test pattern necessary for inspecting a circuit in the electronic device from the device, and transmits the extracted test pattern to the circuit in the electronic device, and a response signal of the test pattern transmitted to the circuit in the electronic device. An expected output value storage section for storing an expected output value signal, a comparison section for comparing a response signal to the test pattern transmitted from the test pattern generation section and the expected output value signal, the test pattern storage section, a test pattern It is provided with a control / processing means for controlling the generation unit, the expected output value storage unit, and the comparison unit. Child apparatus.