JP2003051591A - Two-terminal thyristor - Google Patents

Two-terminal thyristor

Info

Publication number
JP2003051591A
JP2003051591A JP2001237564A JP2001237564A JP2003051591A JP 2003051591 A JP2003051591 A JP 2003051591A JP 2001237564 A JP2001237564 A JP 2001237564A JP 2001237564 A JP2001237564 A JP 2001237564A JP 2003051591 A JP2003051591 A JP 2003051591A
Authority
JP
Japan
Prior art keywords
semiconductor region
main surface
type
region
short
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001237564A
Other languages
Japanese (ja)
Inventor
Masaaki Tomita
昌明 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP2001237564A priority Critical patent/JP2003051591A/en
Publication of JP2003051591A publication Critical patent/JP2003051591A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a two-terminal thyristor in which the surge withstand strength is improved. SOLUTION: The two-terminal thyristor comprises an n-type first semiconductor region 2 formed on the main surface of a p-type semiconductor substrate 1, a p-type second semiconductor region 3 formed in the first semiconductor region 2, a first short-circuiting region 4 surrounded by the second semiconductor region 3, an n-type third semiconductor region 5 formed at the position opposing the second semiconductor region 3 on the second main surface, and a second short-circuiting region 8 surrounded by the third semiconductor region 5. The semiconductor regions and the short-circuiting regions are polygonal having at least five sides, oval, elliptical, or circular in plain view, resulting in improved surge withstand strength of the two-terminal thyristor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する分野】本発明は、通信回路等のサージ防
護に好適な二端子サイリスタに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-terminal thyristor suitable for surge protection of communication circuits and the like.

【0002】[0002]

【従来の技術】通信回路においては自然雷の直撃や誘導
によって大きなサージ電圧が発生することがある。通信
回路に接続された各種の装置や機器を保護するために小
形、安価であり動作が高速な二端子サイリスタ型のサー
ジ防護素子が用いられている。このサイリスタは、通信
回路の被防護回路の線間に接続使用され、線間に侵入し
たサージ電圧が素子の耐圧を越えたとき、ターンオンし
て素子に電流を流し、被防護回路に耐圧以上の電圧が印
加されないようにする。また素子を流れる電流が減少し
て素子の保持電流を下回ったとき、電流を遮断して、通
常状態、即ち、オフ状態に戻り、次のサージに備える動
作を行なう。
2. Description of the Related Art In a communication circuit, a large surge voltage may occur due to direct hit or induction of natural lightning. In order to protect various devices and equipment connected to a communication circuit, a small, inexpensive, high-speed, two-terminal thyristor type surge protection element is used. This thyristor is connected and used between the lines of the protected circuit of the communication circuit, and when the surge voltage that penetrates between the lines exceeds the withstand voltage of the element, it turns on and applies a current to the element, and the protected circuit has a voltage higher than the withstand voltage. Make sure no voltage is applied. When the current flowing through the element decreases and falls below the holding current of the element, the current is shut off and the normal state, that is, the off state is returned to perform an operation for the next surge.

【0003】二端子サージ防護素子を用いてよりよい防
護を行なうためには保持電流を大きくすることまたサー
ジ耐量を大きくする条件を満足させることが必要であ
る。このため、保持電流を大きく設計できる逆導通型の
素子が用いられる。
In order to perform better protection using the two-terminal surge protection element, it is necessary to increase the holding current and satisfy the conditions for increasing the surge resistance. For this reason, a reverse conduction type element that can design a large holding current is used.

【0004】図3は従来技術による二端子サイリスタで
あり、図3(b)は図3(a)のA−Aでの断面を示
す。従来技術による二端子サイリスタはp型の半導体基
板1の第一の主面側に形成されたn型の第一の半導体領
域2と、第一の半導体領域2内に形成されたp型の第二
の半導体領域3と、p型の第二の半導体領域3に囲まれ
て第一の主面からn型の第一の半導体領域2に延びる第
一の短絡領域4と、p型の半導体基板1の第一の主面と
反対の第二の主面側でp型の第二の半導体領域3と対向
する位置に形成されたn型の第三の半導体領域5と、n
型の第三の半導体領域5に囲まれ第二の主面側からp型
の半導体基板1に延びる第二の短絡領域と、第一の主面
側に形成された第二の半導体領域3と第一の短絡領域4
に接続する第一の主面上の第一の電極6と、前記第二の
主面側に形成された前記第三の半導体領域5と第二の短
絡領域8に接続する第二の主面上の第二の電極7を備え
るものであり、n型の第一の半導体領域2、p型の第二
の半導体領域3、n型の第三の半導体領域5、第一の短
絡領域4及び第二の短絡領域8の第一の主面または第二
の主面から見た平面形状は矩形である。
FIG. 3 shows a two-terminal thyristor according to the prior art, and FIG. 3 (b) shows a cross section taken along the line AA of FIG. 3 (a). The two-terminal thyristor according to the related art is an n-type first semiconductor region 2 formed on the first main surface side of a p-type semiconductor substrate 1 and a p-type first semiconductor region 2 formed in the first semiconductor region 2. A second semiconductor region 3, a first short-circuit region 4 surrounded by the p-type second semiconductor region 3 and extending from the first main surface to the n-type first semiconductor region 2, and a p-type semiconductor substrate. An n-type third semiconductor region 5 formed at a position facing the p-type second semiconductor region 3 on the side of the second main surface opposite to the first main surface of 1.
A second short-circuit region surrounded by the third semiconductor region 5 of the mold and extending from the second main surface side to the p-type semiconductor substrate 1, and a second semiconductor region 3 formed on the first main surface side. First short circuit area 4
The first electrode 6 on the first main surface connected to the second main surface and the second main surface connected to the third semiconductor region 5 and the second short-circuit region 8 formed on the second main surface side. The second upper electrode 7 is provided, and the n-type first semiconductor region 2, the p-type second semiconductor region 3, the n-type third semiconductor region 5, the first short-circuit region 4 and The planar shape of the second short-circuit region 8 viewed from the first main surface or the second main surface is rectangular.

【0005】図3におけるp型の半導体基板1に形成し
た従来技術による二端子サイリスタにおいて、第一の電
極6を第二の電極7に対して正の電位とする電圧の印加
方向を順方向、第一の電極6を第二の電極7に対して負
の電位とする電圧の印加方向を逆方向とする。
In the conventional two-terminal thyristor formed on the p-type semiconductor substrate 1 in FIG. 3, the direction of application of the voltage for making the first electrode 6 a positive potential with respect to the second electrode 7 is the forward direction, The application direction of the voltage that makes the first electrode 6 have a negative potential with respect to the second electrode 7 is the opposite direction.

【0006】順方向に電圧を印加した場合、p型の第二
の半導体領域3、n型の第一の半導体領域2、p型の半
導体基板1及びn型の第三の半導体領域5により形成さ
れる素子周辺部のpnpnのサイリスタ部において電流
が流れ、逆方向に電圧を印加した場合、p型の半導体基
板1及びn型の第一の半導体領域2により形成される素
子中央部のpn接合ダイオード部に電流が流れる。
When a voltage is applied in the forward direction, it is formed by the p-type second semiconductor region 3, the n-type first semiconductor region 2, the p-type semiconductor substrate 1 and the n-type third semiconductor region 5. When a current flows in the pnpn thyristor portion in the peripheral portion of the element to be applied and a voltage is applied in the opposite direction, the pn junction in the central portion of the element formed by the p-type semiconductor substrate 1 and the n-type first semiconductor region 2 Current flows through the diode section.

【0007】二端子サイリスタの順方向に電圧を印加す
るとn型の第一の半導体領域2とp型の半導体基板1に
より形成されるpn接合J1が逆バイアスされる。印加
電圧が、pn接合J1の降伏電圧V1に達するとこのp
n接合J1に電流I1が流れp型の第二の半導体領域
3、n型の第一の半導体領域2、p型の半導体基板1に
より構成されるpnpトランジスタをオンさせ、さらに
n型の半導体領域2、p型の半導体基板1、n型の第三
の半導体領域4により形成されるnpnトランジスタを
オンさせ、pnpnサイリスタをオンさせる。
When a voltage is applied in the forward direction of the two-terminal thyristor, the pn junction J1 formed by the n-type first semiconductor region 2 and the p-type semiconductor substrate 1 is reverse biased. When the applied voltage reaches the breakdown voltage V1 of the pn junction J1, this p
A current I1 flows through the n-junction J1 to turn on a pnp transistor formed by the p-type second semiconductor region 3, the n-type first semiconductor region 2 and the p-type semiconductor substrate 1, and further the n-type semiconductor region. 2. The npn transistor formed by the p-type semiconductor substrate 1 and the n-type third semiconductor region 4 is turned on, and the pnpn thyristor is turned on.

【0008】実際には、n型の第一の半導体領域2とp
型の半導体基板1により形成されるpn接合J1が均一
に降伏現象を起こし、均一にI1が流れるわけではな
い。n型の第一の半導体領域2のコーナ部が降伏しやす
く、コーナ部から電極6に至るまでのpnpトランジス
タのベース抵抗と降伏現象により流れる電流I1の積に
よる電圧によりサイリスタがオンする。従ってコーナ部
にサージ電流が集中しやすい。
In practice, the n-type first semiconductor region 2 and p
The pn junction J1 formed by the semiconductor substrate 1 of the type causes a uniform breakdown phenomenon, and I1 does not flow uniformly. The corner portion of the n-type first semiconductor region 2 easily breaks down, and the thyristor is turned on by the voltage due to the product of the base resistance of the pnp transistor from the corner portion to the electrode 6 and the current I1 flowing due to the breakdown phenomenon. Therefore, the surge current tends to concentrate on the corners.

【0009】従来技術による二端子サイリスタでは、n
型の第一の半導体領域2が矩形であり、n型の第一の半
導体領域2から第一の短絡領域4までのpnpトタンジ
スタのベース抵抗が均一でない。さらに、図3(a)に
見られるn型の半導体領域2の四隅のコーナ部分の接合
は、球面接合となり、電界が高くなり易く、他の部分よ
り先に四隅の部分で降伏が起こる。従って、オン状態も
この部分で起こりやすく、極端な電流集中を生じ、局所
的に温度上昇が起こり、サージに対して破壊しやすい。
In a two-terminal thyristor according to the prior art, n
The first semiconductor region 2 of the type is rectangular, and the base resistance of the pnp transistor from the first semiconductor region 2 of the n type to the first short-circuit region 4 is not uniform. Furthermore, the junctions at the corners at the four corners of the n-type semiconductor region 2 shown in FIG. 3A are spherical junctions, the electric field is likely to be high, and breakdown occurs at the four corners before the other portions. Therefore, an ON state is also likely to occur in this portion, an extreme current concentration occurs, a temperature rise locally occurs, and a surge is easily destroyed.

【0010】[0010]

【発明が解決しようとする課題】本発明は、上記従来技
術の問題点を鑑みてなされたもので、その目的は、半導
体拡散領域のパターン形状による降伏電圧の不均一さを
なくし、サージ耐量を向上させた二端子サイリスタを実
現することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and an object thereof is to eliminate the unevenness of the breakdown voltage due to the pattern shape of the semiconductor diffusion region and to improve the surge withstand capability. It is to realize an improved two-terminal thyristor.

【0011】[0011]

【課題を解決しようとする手段】請求項1に記載の発明
は第一導電型の半導体基板1の第一の主面側に形成され
た第一導電型とは逆の第二導電型の第一の半導体領域2
と、第一の主面側より第一の半導体領域2内に形成され
た第一導電型の第二の半導体領域3と、第二の半導体領
域3に囲まれて第一の主面から第一の半導体領域2に延
びる第一の短絡領域4と、前記半導体基板1の第一の主
面と反対の第二の主面側で第二の半導体領域3と対向す
る位置に形成された第二導電型の第三の半導体領域5
と、前記第三の半導体領域5に囲まれ第二の主面側から
半導体基板1に延びる第二の短絡領域8と、第一の主面
側に形成された第二の半導体領域3と第一の短絡領域4
に接続する第一の主面上の第一の電極6と、第二の主面
側に形成された第三の半導体領域5と第二の短絡領域8
に接続する第二の主面上の第二の電極を備える二端子サ
イリスタにおいて第一の半導体領域2、前記第二の半導
体領域3、第三の半導体領域5、第一の短絡領域4及び
第二の短絡領域8の第一の主面或は第二の主面から見た
平面形状が5辺以上からなる多角形、楕円、長円或は円
形であることを特徴とする二端子サイリスタを提供する
ものである。
According to a first aspect of the present invention, there is provided a first conductivity type semiconductor substrate 1 having a second conductivity type opposite to the first conductivity type formed on the first main surface side. One semiconductor region 2
And a second semiconductor region 3 of the first conductivity type formed in the first semiconductor region 2 from the first main surface side, and surrounded by the second semiconductor region 3 from the first main surface to the first main surface. A first short-circuit region 4 extending to one semiconductor region 2 and a first short-circuit region 4 formed at a position facing the second semiconductor region 3 on the second main surface side opposite to the first main surface of the semiconductor substrate 1. Second conductivity type third semiconductor region 5
A second short-circuit region 8 surrounded by the third semiconductor region 5 and extending from the second main surface side to the semiconductor substrate 1, a second semiconductor region 3 formed on the first main surface side, and a second semiconductor region 3 One short-circuit area 4
The first electrode 6 on the first main surface connected to the second main surface, the third semiconductor region 5 and the second short-circuit region 8 formed on the second main surface side.
In a two-terminal thyristor comprising a second electrode on the second main surface connected to the first semiconductor region 2, the second semiconductor region 3, the third semiconductor region 5, the first short-circuit region 4 and the second semiconductor region 3. A two-terminal thyristor characterized in that the planar shape of the second short-circuit area 8 viewed from the first main surface or the second main surface is a polygon having five or more sides, an ellipse, an ellipse, or a circle. It is provided.

【0012】請求項2に記載の発明は第二の電極7が第
二の主面上において第三の半導体領域5を囲む半導体基
板1に接続されている請求項1に記載の二端子サイリス
タを提供するものである。
The invention according to claim 2 provides the two-terminal thyristor according to claim 1, wherein the second electrode 7 is connected to the semiconductor substrate 1 surrounding the third semiconductor region 5 on the second main surface. It is provided.

【0013】請求項3に記載の発明は前記第一の半導体
領域2、前記第二の半導体領域3、前記第三の半導体領
域5、前記第一の短絡領域4及び前記第二の短絡領域8
の前記第一の主面或は前記第二の主面から見た平面形状
が同心円状に配置されていることを特徴とする請求項1
又は請求項2のいずれか1項に記載の二端子サイリスタ
を提供するものである。
According to a third aspect of the present invention, the first semiconductor region 2, the second semiconductor region 3, the third semiconductor region 5, the first short circuit region 4 and the second short circuit region 8 are provided.
2. The planar shape viewed from the first main surface or the second main surface of is arranged concentrically.
Alternatively, the two-terminal thyristor according to claim 2 is provided.

【0014】[0014]

【発明の実施の形態】図1は本発明の第一の実施の形態
にかかる二端子サイリスタであり、図1(b)は図1
(a)のA−Aでの断面を示す。p型の半導体基板1の
第一の主面側に円形状マスクを用いn型不純物を拡散し
n型の第一の半導体領域2を作成し、第一の主面側より
ドーナツ状マスクを用いn型の第一の半導体領域2内に
p型不純物を拡散し、p型の第二の半導体領域3を作
る。p型の第二の半導体領域3に囲まれて第一の主面に
露出するn型の第一の半導体領域2の部分が第一の短絡
領域4となる。ドーナツ状マスクを用いp型の半導体基
板1の第二の主面側より第一の主面側のp型の第二の半
導体領域3と対向する位置にn型不純物を拡散しn型の
第三の半導体領域5を作成する。n型の第三の半導体領
域5に囲まれ第二の主面に露出するp型の半導体基板1
の領域が第二の短絡領域8となる。第一の主面側に、金
属膜を蒸着しn型の第二の半導体領域3と第一の短絡領
域4に接続する第一の電極6を写真技術を利用し、エッ
チングによりでパターン化し、次に第二の主面側に金属
膜を蒸着しn型の第三の半導体領域5と第二の短絡領域
8に接続する第二の主面上の第二の電極7を形成する。
1 shows a two-terminal thyristor according to a first embodiment of the present invention, and FIG.
The cross section in AA of (a) is shown. A circular mask is used on the first main surface side of the p-type semiconductor substrate 1 to diffuse n-type impurities to form an n-type first semiconductor region 2, and a donut-shaped mask is used from the first main surface side. A p-type impurity is diffused in the n-type first semiconductor region 2 to form a p-type second semiconductor region 3. A portion of the n-type first semiconductor region 2 surrounded by the p-type second semiconductor region 3 and exposed on the first main surface becomes the first short-circuit region 4. Using a donut-shaped mask, n-type impurities are diffused from the second main surface side of the p-type semiconductor substrate 1 to a position on the first main surface side facing the p-type second semiconductor region 3. A third semiconductor region 5 is created. A p-type semiconductor substrate 1 surrounded by an n-type third semiconductor region 5 and exposed on the second main surface
The second area becomes the second short-circuit area 8. On the first main surface side, a first electrode 6 that is vapor-deposited with a metal film and connected to the n-type second semiconductor region 3 and the first short-circuit region 4 is patterned by etching using photographic technology, Next, a metal film is vapor-deposited on the second main surface side to form the second electrode 7 on the second main surface, which is connected to the n-type third semiconductor region 5 and the second short-circuit region 8.

【0015】本実施例においてn型の第一の半導体領域
2、p型の第二の半導体領域3、n型の第三の半導体領
域5、第一の短絡領域4及び第二の短絡領域は第一の主
面或は第二の主面から見た平面形状は同心円状に形成さ
れることが望ましいが5辺以上からなる多角形、楕円或
は長円であってもよい。またこれらの組み合わせであっ
てもよい。
In this embodiment, the n-type first semiconductor region 2, the p-type second semiconductor region 3, the n-type third semiconductor region 5, the first short-circuit region 4 and the second short-circuit region are The planar shape viewed from the first main surface or the second main surface is preferably concentric, but may be a polygon having five or more sides, an ellipse, or an ellipse. Also, a combination of these may be used.

【0016】図2は本発明の第二の実施の形態の二端子
サイリスタであり、図2(b)は図のA−Aでの断面を
示す。上記第一の実施の形態における第二の電極7の形
成において第二の電極7が第二の主面において第二の短
絡領域8とn型の第三の半導体領域5と、さらに、n型
の第三の半導体領域5を囲むp型の第一の半導体領域1
とを接続する。本実施の形態においてn型の第一の半導
体領域2、p型の第二の半導体領域3、n型の第三の半
導体領域5、第一の短絡領域4及び第二の短絡領域8は
第一の主面或は第二の主面から見た平面形状は同心円状
に形成されていることが望ましいが5辺以上からなる多
角形、楕円或は長円であってもよい。またこれらの組み
合わせであってもよい。
FIG. 2 shows a two-terminal thyristor according to a second embodiment of the present invention, and FIG. 2B shows a cross section taken along the line AA in the figure. In the formation of the second electrode 7 in the first embodiment, the second electrode 7 includes the second short-circuit region 8 and the n-type third semiconductor region 5 on the second main surface, and the n-type. P-type first semiconductor region 1 surrounding the third semiconductor region 5 of
And connect. In the present embodiment, the n-type first semiconductor region 2, the p-type second semiconductor region 3, the n-type third semiconductor region 5, the first short circuit region 4 and the second short circuit region 8 are The planar shape viewed from the one main surface or the second main surface is preferably concentric, but may be a polygon having five or more sides, an ellipse, or an ellipse. Also, a combination of these may be used.

【0017】上記の説明においてn型の第一の半導体領
域2は第一の主面より拡散したプレーナ構造について説
明したが、第一の主面側よりn型層を円形などの形状或
は全面に拡散し、この拡散領域の周辺を拡散深さ以上に
溝状、濠状にエッチングし、n型の第一の半導体領域2
を形成してもよい。この溝内をガラスで埋め込み、外部
雰囲気に対して安定した特性をしめす二端子サイリスタ
を作ることができる。
In the above description, the n-type first semiconductor region 2 has been described as having a planar structure in which it is diffused from the first main surface. However, the n-type layer has a circular shape or the entire surface from the first main surface side. And the periphery of this diffusion region is etched into a groove shape or a moat shape with a depth equal to or larger than the diffusion depth.
May be formed. By filling the groove with glass, a two-terminal thyristor exhibiting stable characteristics with respect to the external atmosphere can be manufactured.

【0018】以上p型基板について説明したが、n型基
板を用いてもよい。
Although the p-type substrate has been described above, an n-type substrate may be used.

【0019】[0019]

【発明の効果】本発明によれば、サージに強いしかも保
持電流の大きな、サージ防護に適した二端子サイリスタ
が得られる。
According to the present invention, it is possible to obtain a two-terminal thyristor which is strong against surges and has a large holding current and which is suitable for surge protection.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の第一の実施の形態を説明する図であ
る。
FIG. 1 is a diagram illustrating a first embodiment of the present invention.

【図2】 本発明の第二の実施の形態を説明する図であ
る。
FIG. 2 is a diagram illustrating a second embodiment of the present invention.

【図3】 従来技術による二端子サイリスタの形態を説
明する図である。
FIG. 3 is a diagram illustrating a form of a two-terminal thyristor according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 p型の半導体基板 2 n型の第一の半導体領域 3 p型の第二の半導体領域 4 第一の短絡領域 5 n型の第三の半導体領域 6 第一の電極 7 第二の電極 8 第二の短絡領域 1 p-type semiconductor substrate 2 n-type first semiconductor region 3 p-type second semiconductor region 4 First short circuit area 5 n-type third semiconductor region 6 First electrode 7 Second electrode 8 Second short circuit area

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 第一導電型の半導体基板と、前記半導体
基板の第一の主面側に形成された第一導電型とは逆の第
二導電型の第一の半導体領域と、前記第一の主面側より
前記第一の半導体領域内に形成された第一導電型の第二
の半導体領域と、前記第二の半導体領域に囲まれて前記
第一の主面から前記第一の半導体領域に延びる第一の短
絡領域と、前記半導体基板の前記第一の主面と反対の第
二の主面側で前記第二の半導体領域と対向する位置に形
成された第二導電型の第三の半導体領域と、前記第三の
半導体領域に囲まれ前記第二の主面側から半導体基板に
延びる第二の短絡領域と、前記第一の主面側に形成され
た前記第二の半導体領域と、前記第一の短絡領域に接続
する前記第一の主面上の第一の電極と前記第二の主面側
に形成された前記第三の半導体領域と前記第二の短絡領
域に接続する前記第二の主面上の第二の電極を備える二
端子サイリスタにおいて、前記第一の半導体領域、前記
第二の半導体領域、前記第三の半導体領域、前記第一の
短絡領域及び前記第二の短絡領域の前記第一の主面或は
前記第二の主面から見た平面形状が5辺以上からなる多
角形、楕円、長円或は円形であることを特徴とする二端
子サイリスタ。
1. A semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first main surface side of the semiconductor substrate, A second semiconductor region of the first conductivity type formed in the first semiconductor region from one main surface side, and surrounded by the second semiconductor region, the first main surface to the first A first short-circuit region extending to a semiconductor region, and a second conductivity type formed at a position facing the second semiconductor region on the second main surface side opposite to the first main surface of the semiconductor substrate. A third semiconductor region, a second short circuit region surrounded by the third semiconductor region and extending to the semiconductor substrate from the second main surface side, and the second short-circuit region formed on the first main surface side. A semiconductor region, a first electrode on the first main surface connected to the first short circuit region, and the first electrode formed on the second main surface side. A two-terminal thyristor comprising a third electrode and a second electrode on the second main surface connected to the second short-circuit region, wherein the first semiconductor region, the second semiconductor region, and the third Of the semiconductor region, the first short-circuit region and the second short-circuit region, the planar shape of the first main surface or the second main surface when viewed from the side is a polygon having five or more sides, an ellipse, an oval. Or a two-terminal thyristor characterized by being circular.
【請求項2】 前記第二の電極が前記第二の主面上にお
いて前記第三の半導体領域を囲む前記半導体基板に接続
されていることを特徴とする請求項1に記載の二端子サ
イリスタ。
2. The two-terminal thyristor according to claim 1, wherein the second electrode is connected to the semiconductor substrate surrounding the third semiconductor region on the second main surface.
【請求項3】 前記第一の半導体領域、前記第二の半導
体領域、前記第三の半導体領域、前記第一の短絡領域及
び前記第二の短絡領域の前記第一の主面或は前記第二の
主面から見た平面形状が同心円状に配置されていること
を特徴とする請求項1又は請求項2のいずれか1項に記
載の二端子サイリスタ。
3. The first main surface of the first semiconductor region, the second semiconductor region, the third semiconductor region, the first short-circuit region and the second short-circuit region or the first short-circuit region. The two-terminal thyristor according to claim 1, wherein the two-dimensional thyristor is concentrically arranged when viewed from the second main surface.
JP2001237564A 2001-08-06 2001-08-06 Two-terminal thyristor Pending JP2003051591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001237564A JP2003051591A (en) 2001-08-06 2001-08-06 Two-terminal thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001237564A JP2003051591A (en) 2001-08-06 2001-08-06 Two-terminal thyristor

Publications (1)

Publication Number Publication Date
JP2003051591A true JP2003051591A (en) 2003-02-21

Family

ID=19068631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001237564A Pending JP2003051591A (en) 2001-08-06 2001-08-06 Two-terminal thyristor

Country Status (1)

Country Link
JP (1) JP2003051591A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55148455A (en) * 1979-05-09 1980-11-19 Nec Corp Reverse mesa transistor element
JPH0677505A (en) * 1992-01-14 1994-03-18 Shindengen Electric Mfg Co Ltd Two-terminal surge protecting element and multi-line protecting method
JPH10214968A (en) * 1997-01-31 1998-08-11 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55148455A (en) * 1979-05-09 1980-11-19 Nec Corp Reverse mesa transistor element
JPH0677505A (en) * 1992-01-14 1994-03-18 Shindengen Electric Mfg Co Ltd Two-terminal surge protecting element and multi-line protecting method
JPH10214968A (en) * 1997-01-31 1998-08-11 Hitachi Ltd Semiconductor device

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