JP2003046120A - Light-emitting device, laminated structure therefor, lamp and light source - Google Patents
Light-emitting device, laminated structure therefor, lamp and light sourceInfo
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、ガリウム(Ga)
を含むIII−V族化合物半導体(含ガリウムIII−
V族化合物半導体)からなる発光層と、硼素(B)を含
むIII−V族化合物半導体(含硼素III−V族化合
物半導体)からなる障壁層とを備えた発光素子用積層構
造体と、その積層構造体から発光素子、ランプ及び光源
を構成するための技術に関する。TECHNICAL FIELD The present invention relates to gallium (Ga).
III-V group compound semiconductor containing (gallium-containing III-
A laminated structure for a light emitting device, which includes a light emitting layer made of a V group compound semiconductor) and a barrier layer made of a III-V group compound semiconductor containing boron (B) (boron-containing III-V group compound semiconductor), and the same. The present invention relates to a technique for forming a light emitting device, a lamp and a light source from a laminated structure.
【0002】[0002]
【従来の技術】従来より、ガリウム(Ga)を含むII
I−V族化合物半導体を発光層として備えた発光素子と
して、例えば、リン化ガリウム(GaP)を発光層とし
た緑色帯の発光ダイオード(LED)が知られている
(寺本 巖著、「半導体デバイス概論」((株)培風
館、1995年3月30日発行初版、118〜121頁
参照)。また、別の従来例として、砒化リン化ガリウム
(GaAs1-XPX:0≦X≦1)黄色帯LEDが知られ
ている(上記の「半導体デバイス概論」、114〜11
6頁参照)。これら実用に至っている含ガリウムIII
−V族化合物半導体層を発光層とする発光素子は、何れ
も、pn接合型単一(homo)接合構造の発光部を備
えた積層構造体から構成されているのが通例である。2. Description of the Related Art Conventionally, II containing gallium (Ga)
As a light-emitting element including a group IV compound semiconductor as a light-emitting layer, for example, a green band light-emitting diode (LED) including gallium phosphide (GaP) as a light-emitting layer is known (Iwao Teramoto, “Semiconductor Device”). Introduction ”(see Baifukan Co., Ltd., first edition issued March 30, 1995, pp. 118-121). As another conventional example, gallium arsenide phosphide (GaAs 1-X P X : 0 ≦ X ≦ 1) Yellow band LEDs are known (above-mentioned "Introduction to Semiconductor Devices", 114-11).
(See page 6). Gallium-containing III that has been put to practical use
Each of the light-emitting devices including the group-V compound semiconductor layer as a light-emitting layer is usually composed of a laminated structure including a light-emitting portion having a pn junction single (homo) junction structure.
【0003】III−V族化合物半導体の一種であるリ
ン化硼素(BP)は、イオン結合度が0.006と低く
(フィリップス著、「半導体結合論」((株)吉岡書
店、1985年7月25日発行、第3刷)、49〜51
頁参照)、特に、p形伝導性の半導体層を得られ易い特
徴を有している。この様なリン化硼素(BP)の特徴
は、例えば、pn接合構造を簡便に構成するに優位に作
用する。このため、従来から、リン化硼素系III−V
族化合物半導体層を備えた積層構造体から発光ダイオー
ド(LED)或いはレーザダイオード(LD)等の発光
素子を構成する技術が開示されている(特開平2−28
8388号公報参照)。従来において、リン化硼素系半
導体層を含む積層構造体は、例えば、リン化ガリウム
(GaP)及び窒化ガリウム(GaN)等のIII−V
族化合物半導体単結晶を基板として構成されている(
特開平2−275682号/日本国特許第280969
0号、及び特開平10−247745号各公報参
照)。また、別の基板材料として珪素(Si)単結晶
(シリコン)が知られている(米国特許6,069,0
21号参照)。また、炭化珪素(SiC)も基板材料と
して用いられている(上記の特許第2809690号参
照)。Boron phosphide (BP), which is a type of III-V compound semiconductor, has a low ionic bond level of 0.006 (see Phillips, "Semiconductor Coupling Theory" (Yoshioka Shoten Co., Ltd., July 1985). Published on 25th, 3rd printing), 49-51
(See page), in particular, a p-type conductive semiconductor layer is easily obtained. Such a feature of boron phosphide (BP) acts dominantly in, for example, simply forming a pn junction structure. Therefore, conventionally, boron phosphide-based III-V
A technique of forming a light emitting element such as a light emitting diode (LED) or a laser diode (LD) from a laminated structure including a group compound semiconductor layer is disclosed (Japanese Patent Laid-Open No. 2-28).
8388 publication). Conventionally, a laminated structure including a boron phosphide-based semiconductor layer is, for example, III-V such as gallium phosphide (GaP) and gallium nitride (GaN).
A group compound semiconductor single crystal is used as a substrate (
JP-A-2-275682 / Japanese Patent No. 280969
No. 0 and JP-A-10-247745). Further, silicon (Si) single crystal (silicon) is known as another substrate material (US Pat. No. 6,069,0).
21). Silicon carbide (SiC) is also used as a substrate material (see the above-mentioned Japanese Patent No. 2809690).
【0004】従来において、リン化硼素系半導体層は様
々な機能層として利用されている。例えば、特開平10
−242569号に記載の発明には、リン化硼素層を電
流阻止層として備えた電流狭窄型の緑色レーザダイオー
ド(LD)が開示されている。また、リン化硼素層をオ
ーミック(Ohmic)電極を形成するためのコンタク
ト(contact)層として積層構造体に具備させる
公知例もある(特開平10−242568号公報参
照)。また、リン化硼素層を緩衝層として備えたLED
も公知となっている(特開平10−242514号公報
参照)。特に、基板材料と積層構造体構成層との格子ミ
スマッチ(mismatch)をより良く緩和するため
に、比較的に低温で形成した、所謂、低温緩衝層をリン
化硼素系半導体層から構成する例が知られている(上記
の米国特許6,069,021号参照)。例えば、シリ
コン(Si)やリン化ガリウム(GaP)単結晶基板上
に、リン化硼素・ガリウム(BXGa1-XP:0≦X≦
1)或いはリン化硼素・インジウム(BXIn1-XP:0
≦X≦1)から緩衝層を構成する技術が開示されている
(特開平11−266006号公報参照)。Conventionally, boron phosphide-based semiconductor layers have been used as various functional layers. For example, JP-A-10
The invention described in No. 242569 discloses a current confinement type green laser diode (LD) including a boron phosphide layer as a current blocking layer. There is also a known example in which a laminated structure is provided with a boron phosphide layer as a contact layer for forming an ohmic electrode (see JP-A-10-242568). An LED provided with a boron phosphide layer as a buffer layer
Is also known (see Japanese Patent Laid-Open No. 10-242514). In particular, there is an example in which a so-called low-temperature buffer layer formed at a relatively low temperature is composed of a boron phosphide-based semiconductor layer in order to better alleviate the lattice mismatch between the substrate material and the laminated structure constituting layer. Known (see US Pat. No. 6,069,021 above). For example, on a silicon (Si) or gallium phosphide (GaP) single crystal substrate, boron phosphide / gallium (B X Ga 1-X P: 0 ≦ X ≦
1) or boron phosphide / indium (B X In 1-X P: 0
A technique of forming a buffer layer from ≦ X ≦ 1) is disclosed (see Japanese Patent Laid-Open No. 11-266006).
【0005】一方、従来より、リン化硼素(BP)の室
温での禁止帯幅は、約2eVであるとされている(R
CA Review,25(1964)、159〜16
7頁、Z.anorg.allg.chem.,34
9(1967)、151〜157頁、及び上記の「半
導体デバイス概論」、28頁参照)。約2eVと低い禁
止帯幅のリン化硼素を基材として、より高い禁止帯幅の
BP系混晶を形成する技術も開示されている。例えば、
アンドープ(undope)の窒化アルミニウム・ガリ
ウム混晶(Ga0.5Al0.5N)薄層(層厚=1nm)と
リン化硼素薄層(層厚=1nm)との超格子構造から
2.7eVの禁止帯幅が得られている(上記の特開平1
0−247745号参照)。また、例えば、Ga0.25A
l0.25B0.50N0.60P0.405元混晶として禁止帯幅を
2.7eVとする半導体層を得ている(特開平2−28
8371号公報参照)。On the other hand, conventionally, the band gap of boron phosphide (BP) at room temperature is said to be about 2 eV (R
CA Review, 25 (1964), 159-16.
Page 7, Z. anorg. allg. chem. , 34
9 (1967), pp. 151-157, and the above-mentioned "Introduction to Semiconductor Devices", page 28). A technique for forming a BP-based mixed crystal having a higher bandgap using boron phosphide having a bandgap as low as about 2 eV as a base material is also disclosed. For example,
A forbidden band of 2.7 eV from a superlattice structure of an undoped aluminum nitride / gallium mixed crystal (Ga 0.5 Al 0.5 N) thin layer (layer thickness = 1 nm) and a boron phosphide thin layer (layer thickness = 1 nm). The width has been obtained (see above-mentioned JP-A-1
0-247745). Also, for example, Ga 0.25 A
l 0.25 B 0.50 N 0.60 P 0.40 As a quaternary mixed crystal, a semiconductor layer having a band gap of 2.7 eV was obtained (Japanese Patent Laid-Open No. 2-28).
8371).
【0006】[0006]
【発明が解決しようとする課題】含ガリウムIII−V
族化合物半導体層を発光層とするLEDにあって、発光
部を従来の単一(SH)構造ではなく二重(DH)構造
とすれば、「光の閉じ込め」効果或いは「キャリア(担
体)の閉じ込め」効果により、発光強度が増大され、高
輝度のLEDの実現が期待される(上記の「半導体デバ
イス概論」、124〜126頁参照)。例えば、上記の
従来手段に依り禁止帯幅を高めたGaAlBNP5元混
晶を障壁層として発光層に接合させてDH構造の発光部
を構成する手段も勘案される。しかしながら、構成元素
の組成が安定している5元混晶等の多元混晶の構成元素
の組成を安定に維持することは困難であるのは周知であ
る(上記の「半導体デバイス概論」、24頁参照)。Problems to be Solved by the Invention Gallium-containing III-V
In an LED having a group compound semiconductor layer as a light emitting layer, if the light emitting portion has a double (DH) structure instead of the conventional single (SH) structure, a "light confinement" effect or a "carrier (carrier)" Due to the "confinement" effect, the emission intensity is increased, and it is expected that a high-brightness LED is realized (see "Introduction to Semiconductor Devices", pages 124 to 126). For example, means for forming a DH structure light emitting part by joining a GaAlBNP ternary mixed crystal having a forbidden band width increased by the above-mentioned conventional means as a barrier layer to the light emitting layer is also considered. However, it is well known that it is difficult to maintain a stable composition of constituent elements of a multi-element mixed crystal such as a quinary mixed crystal in which composition of constituent elements is stable (above-mentioned “Introduction to Semiconductor Devices”, 24). See page).
【0007】また、禁止帯幅を約2eVとするリン化硼
素を基材としてより高い禁止帯幅の半導体層を得ようと
する従来技術では、数nm程度の極薄膜を周期的に交互
に積層させて超格子構造としなければならず、極薄膜の
層厚並びに組成を安定して制御するために煩雑で冗長な
成膜操作を要求される。また、超格子構造を形成するた
めの特殊な成膜装置も要求されている(上記の特開平2
−288371号参照)。Further, in the conventional technique for obtaining a semiconductor layer having a higher bandgap using boron phosphide having a bandgap of about 2 eV as a base material, ultrathin films of about several nm are alternately laminated alternately. Therefore, a superlattice structure must be obtained, and a complicated and redundant film forming operation is required to stably control the layer thickness and composition of the ultrathin film. In addition, a special film forming apparatus for forming a superlattice structure is also required (see Japanese Patent Laid-Open No. Hei 2).
-288371).
【0008】最近では、従来の成長操作の煩雑性を回避
できる簡便な気相成長手段に依り、室温で従来に無く高
い禁止帯幅のリン化硼素(BP)を得る技術が開発され
ている。また、室温で高い禁止帯幅を有するリン化硼素
或いはそれを基材として構成される混晶を障壁(cla
d)層として利用して、砒化リン化ガリウム(GaAs
1-XPX:0≦X≦1)発光層とのヘテロ接合構造を構成
する技術が提案されている。Recently, the complexity of the conventional growth operation is avoided.
The simple and easy vapor phase growth method that can be used, resulting in a higher temperature than ever before at room temperature.
A technology for obtaining boron phosphide (BP) with a wide band gap was developed.
ing. Also, boron phosphide having a high band gap at room temperature
Alternatively, a mixed crystal composed of the base material is used as a barrier (cla).
d) gallium arsenide phosphide (GaAs)
1-XPX: 0 ≦ X ≦ 1) forming a heterojunction structure with the light emitting layer
The technology to do is proposed.
【0009】しかし、含硼素III−V族化合物半導体
層と含ガリウムIII−V族化合物半導体発光層とのヘ
テロ接合を構成する技術にあっても、より高い発光強度
の発光をもたらすに足る結晶性に優れる含ガリウムII
I−V族化合物半導体発光層を得るための接合構成が求
められていた。即ち、発光強度の高い例えば、GaAs
1-XPX系発光素子をもたらすに好適となる障壁(cla
d)層を含硼素III−V族化合物半導体から構成する
技術の更なる改良が要求されていた。However, boron-containing III-V compound semiconductors
Between the layer and the gallium-containing III-V compound semiconductor light emitting layer
Higher emission intensity even with the technology that constitutes terrorism junction
-Containing gallium II with excellent crystallinity to bring about luminescence
A junction structure for obtaining a group IV compound semiconductor light emitting layer is desired.
I was struck. That is, for example, GaAs with high emission intensity
1-XPXA barrier suitable for providing a light emitting device (cla)
d) Layer is composed of a boron-containing III-V group compound semiconductor
Further improvements in technology were required.
【0010】本発明は上記の従来技術の問題点を克服す
べくなされたもので、良質の含ガリウムIII−V族化
合物半導体層からなる発光層を安定して与えられる含硼
素III−V族化合物半導体層の構成を提示すると共
に、その構成からなる含硼素III−V族化合物半導体
層を備えた発光素子用積層構造体、発光素子、ランプ、
及び光源を提供するものである。The present invention has been made to overcome the above-mentioned problems of the prior art, and is a boron-containing III-V group compound capable of stably providing a light emitting layer composed of a good-quality gallium-containing III-V group compound semiconductor layer. A structure of a semiconductor layer is presented, and a laminated structure for a light emitting device, a light emitting device, a lamp, and a boron-containing III-V compound semiconductor layer having the structure are presented.
And a light source.
【0011】[0011]
【課題を解決するための手段】即ち、本発明は、単結晶
の基板と、基板上に積層された緩衝層と、緩衝層上に積
層された硼素(B)を含むIII−V族化合物半導体
(含硼素III−V族化合物半導体)からなる障壁層
と、ガリウム(Ga)を含むIII−V族化合物半導体
(含ガリウムIII−V族化合物半導体)からなる発光
層とを備えている発光素子用積層構造体を提供するもの
であって、特に、次の(1)乃至(6)項に記載の特徴
を有する発光素子用積層構造体を提供する。
(1)障壁層を、上記の緩衝層に対向する表面で緩衝層
に格子整合する硼素(B)組成比を有し、上記の発光層
に対向する表面で発光層に格子整合する硼素(B)組成
比を有する、層厚の増加方向に硼素(B)組成比に勾配
を付した含硼素III−V族化合物半導体からなる組成
勾配層から構成したことを特徴とする発光素子用積層構
造体。
(2)含ガリウムIII−V族化合物半導体からなる発
光層を、発光層に対向する障壁層の表面を構成する含硼
素III−V族化合物半導体と同一の材料から構成した
ことを特徴とする前記(1)に記載の発光素子用積層構
造体。
(3)発光層を、砒化リン化硼素・ガリウム(BYGa
1-YAs1-ZPZ:0≦Y<1、0<Z≦1)から構成し
たことを特徴とする前記(1)または(2)に記載の発
光素子用積層構造体。
(4)含硼素III−V族化合物半導体からなる障壁層
を、基板を構成する単結晶材料に格子整合する組成を有
する含硼素III−V族化合物半導体から構成した緩衝
層上に設けたことを特徴とする前記(1)乃至(3)の
何れか1項に記載の発光素子用積層構造体。
(5)単結晶基板を珪素単結晶(シリコン)とし、含硼
素III−V族化合物半導体層からなる障壁層を、リン
化硼素・ガリウム(BXGa1-XP:0<X≦1)から構
成したことを特徴とする前記(1)乃至(4)の何れか
1項に記載の発光素子用積層構造体。
(6)単結晶基板を珪素単結晶(シリコン)とし、含硼
素III−V族化合物半導体層からなる障壁層を、リン
化硼素・インジウム(BXIn1-XP:0<X≦1)から
構成したことを特徴とする前記(1)乃至(4)の何れ
か1項に記載の発光素子用積層構造体。That is, the present invention is directed to a III-V group compound semiconductor containing a single crystal substrate, a buffer layer laminated on the substrate, and boron (B) laminated on the buffer layer. For a light emitting device comprising a barrier layer made of (boron-containing III-V group compound semiconductor) and a light-emitting layer made of III-V group compound semiconductor containing gallium (Ga) (gallium-containing III-V group compound semiconductor) A laminated structure for a light emitting device, which has the characteristics described in the following items (1) to (6). (1) The barrier layer has a composition ratio of boron (B) lattice-matched to the buffer layer on the surface facing the buffer layer, and boron (B) lattice-matched to the light emitting layer on the surface facing the light emitting layer (B). ) A laminated structure for a light emitting device, comprising a composition gradient layer composed of a boron-containing III-V group compound semiconductor having a composition ratio and a boron (B) composition ratio gradient in an increasing direction of the layer thickness. . (2) The light emitting layer made of a gallium-containing III-V compound semiconductor is made of the same material as the boron-containing III-V compound semiconductor forming the surface of the barrier layer facing the light emitting layer. The laminated structure for a light emitting device according to (1). (3) The light emitting layer is formed of boron arsenide phosphide / gallium ( BY Ga).
1-Y As 1-Z P Z : 0 ≦ Y <1, 0 <Z ≦ 1), The laminated structure for a light-emitting element as described in (1) or (2) above. (4) A barrier layer made of a boron-containing III-V group compound semiconductor is provided on a buffer layer made of a boron-containing III-V group compound semiconductor having a composition lattice-matched to a single crystal material forming a substrate. The laminated structure for a light emitting device according to any one of (1) to (3), which is characterized. (5) The single crystal substrate is made of silicon single crystal (silicon), and the barrier layer made of a boron-containing III-V group compound semiconductor layer is formed of boron phosphide / gallium (B X Ga 1-X P: 0 <X ≦ 1). The laminated structure for a light-emitting element according to any one of (1) to (4) above, which is configured by: (6) The single crystal substrate is made of silicon single crystal (silicon), and the barrier layer made of a boron-containing III-V group compound semiconductor layer is formed of boron phosphide / indium (B X In 1-X P: 0 <X ≦ 1). The laminated structure for a light-emitting element according to any one of (1) to (4) above, which is configured by:
【0012】また本発明は、上記の積層構造体を利用し
た、
(7)前記(1)乃至(6)の何れか1項に記載の発光
素子用積層構造体を用いて構成したことを特徴とする発
光素子。
(8)同一の単結晶基板上に、発光素子と当該発光素子
からの発光の強度を制御するための電子部品を備えてい
ることを特徴とする前記(7)に記載の発光素子。
(9)電子部品を、含硼素III−V族化合物半導体か
らなる障壁層上に設けていることを特徴とする(8)に
記載の発光素子、を提供する。さらに本発明は、
(10)前記(7)乃至(9)の何れか1項に記載の発
光素子から構成したことを特徴とするランプ。
(11)前記(10)に記載のランプを用いて構成した
ことを特徴とする光源。を提供する。Further, the present invention is characterized in that the above laminated structure is used, and (7) the laminated structure for a light emitting device described in any one of (1) to (6) above is used. Light emitting element. (8) The light emitting device according to the above (7), which is provided with a light emitting device and an electronic component for controlling the intensity of light emitted from the light emitting device on the same single crystal substrate. (9) The light emitting device according to (8), wherein the electronic component is provided on a barrier layer made of a boron-containing III-V compound semiconductor. Further, the present invention provides (10) a lamp comprising the light emitting device according to any one of (7) to (9). (11) A light source comprising the lamp according to (10) above. I will provide a.
【0013】[0013]
【発明の実施の形態】図1に掲示する積層構造体1Aの
断面模式図を例にして、本発明に係わる第1の実施形態
を説明する。第1の実施形態に係わる積層構造体1A
は、例えば、{100}、{110}或いは{111}
結晶面を主面とするn形またはp形シリコンを基板10
1として構成する。主面より特定の結晶方位に向けて傾
斜した表面を有するシリコンも基板101として利用で
きる。例えば、[110]結晶方位に角度にして数度か
ら十数度傾斜させた表面を有する{100}を主面とす
るシリコンを基板101とできる。n形或いはp形リン
化ガリウム(GaP)または砒化ガリウム(GaAs)
或いはリン化硼素(BP)(J.Electroch
em.Soc.,120(1973)、p.p.802
〜806.、及び米国特許5,042,043号公報
参照)等のIII−V族化合物半導体単結晶も基板10
1として利用できる。BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to the schematic sectional view of the laminated structure 1A shown in FIG. 1 as an example. Laminated structure 1A according to the first embodiment
Is, for example, {100}, {110} or {111}
The substrate 10 is made of n-type or p-type silicon having a crystal plane as a main surface.
Configure as 1. Silicon having a surface inclined from the main surface toward a specific crystal orientation can also be used as the substrate 101. For example, the substrate 101 can be made of silicon having {100} as a main surface, which has a surface inclined at an angle of several degrees to several tens of degrees with respect to the [110] crystal orientation. n-type or p-type gallium phosphide (GaP) or gallium arsenide (GaAs)
Alternatively, boron phosphide (BP) (J. Electroch
em. Soc. 120 (1973), p. p. 802
~ 806. , And U.S. Pat. No. 5,042,043)).
Available as 1.
【0014】導電性の結晶材料を基板101とすれば、
基板101の電気的導通性に依り、基板101裏面に正
負、何れかの極性のオーミック(Ohmic)電極10
7を敷設できる。従い、導電性結晶基板は、サファイア
等の絶縁性結晶を基板とした場合に於ける、積層構造体
の一部を除去し、導電性の構成層表面を露出させた上で
電極を形成する煩雑な工程(特開平10−321907
号公報参照)を不要となし、簡便に発光素子を構成する
利便な技術手段を与える。特に、抵抗率を10ミリオー
ム(mΩ)以下、より望ましくは1mΩ以下とする低比
抵抗の導電性単結晶基板101は、順方向電圧(所謂、
Vf)を低く抑えたLED、また、放熱性に優れるた
め、安定した発振をもたらすLDを構成するに有効であ
る。If the conductive crystalline material is used as the substrate 101,
Depending on the electrical conductivity of the substrate 101, a positive or negative polarity ohmic electrode 10 is provided on the back surface of the substrate 101.
7 can be laid. Therefore, the conductive crystal substrate is complicated when the insulating crystal such as sapphire is used as the substrate, a part of the laminated structure is removed to expose the surface of the conductive constituent layer, and then the electrode is formed. Process (JP-A-10-321907)
(See Japanese Unexamined Patent Publication No. JP-A-2003-24035), and a convenient technical means for easily configuring a light emitting element is provided. In particular, the conductive single crystal substrate 101 having a low specific resistance, which has a resistivity of 10 milliohms (mΩ) or less, and more preferably 1 mΩ or less, has a forward voltage (so-called,
It is effective for constructing an LED that suppresses Vf) to a low level and an LD that provides stable oscillation because it has excellent heat dissipation.
【0015】単結晶基板101と障壁層103との中間
には、緩衝層102を設ける構成とするのが望ましい。
緩衝層102は、例えば、一般式BαAlβGaγIn
1- α - β - γP1- δAsδ(0<α≦1、0≦β<1、0
≦γ<1で且つ0<α+β+γ≦1、0≦δ<1)で表
記されるリン化硼素系半導体から好適に構成できる。ま
た、例えば、一般式BαAlβGaγIn1- α - β - γP
1- δNδ(0<α≦1、0≦β<1、0≦γ<1で且つ
0<α+β+γ≦1、0<δ<1)で表記される窒素
(N)を含むリン化硼素系半導体から構成できる。好ま
しくは、構成元素数が少なく、簡便に構成できる2元結
晶或いは3元混晶から構成する。例えば、単量体リン化
硼素(BP)、リン化アルミニウム・硼素混晶(BαA
lβP:0<α≦1、0≦β<1で且つα+β=1)、
リン化硼素・ガリウム混晶(BαGaδP:0<α≦
1、0≦γ<1で且つα+δ=1)、或いはリン化硼素
・インジウム混晶(BαIn1- αP:0<α≦1)など
から構成する。Intermediate between single crystal substrate 101 and barrier layer 103
Therefore, it is desirable that the buffer layer 102 be provided.
The buffer layer 102 has, for example, the general formula BαAlβGaγIn
1- α - β - γP1- δAsδ(0 <α ≦ 1, 0 ≦ β <1, 0
Table with ≦ γ <1 and 0 <α + β + γ ≦ 1, 0 ≦ δ <1)
The boron phosphide-based semiconductor described below can be preferably used. Well
For example, the general formula BαAlβGaγIn1- α - β - γP
1- δNδ(0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ <1, and
Nitrogen expressed as 0 <α + β + γ ≦ 1, 0 <δ <1)
It can be composed of a boron phosphide-based semiconductor containing (N). Preferred
Ideally, the number of constituent elements is small, and it is easy to form a binary structure.
It is composed of crystals or ternary mixed crystals. For example, monomer phosphorylation
Boron (BP), aluminum phosphide-boron mixed crystal (BαA
lβP: 0 <α ≦ 1, 0 ≦ β <1, and α + β = 1),
Boron phosphide / gallium mixed crystal (BαGaδP: 0 <α ≦
1, 0 ≦ γ <1 and α + δ = 1), or boron phosphide
・ Indium mixed crystal (BαIn1- αP: 0 <α ≤ 1) etc.
It consists of.
【0016】特に、緩衝層102を、基板101を構成
する単結晶材料に格子整合する組成の結晶層から構成す
ると、単結晶基板101と例えば、障壁層103等の積
層構造体1Aの構成層との格子不整合性が緩和される利
点が生ずる。このため、結晶性に優れる障壁層103或
いは発光層104を得るに特に、効果が挙げられる。こ
の効果をもたらすに好適な緩衝層102の構成材料とし
て、シリコン(格子定数≒5.431Å)に格子整合す
るリン化硼素・ガリウム(B0.02Ga0.98P:格子定数
≒5.431Å)を例示できる(上記の特開平11−2
66006号参照)。また、リン化硼素・ガリウム(B
0.32Ga0.68P:格子定数≒5.450Å)や砒化硼素
・ガリウム(B0.23Ga0.77As:格子定数≒5.45
0Å)等からはGaP単結晶(格子定数≒5.450
Å)基板と格子整合を果たす含硼素III−V族化合物
半導体混晶層を構成できる(特開2000−22211
号公報参照)。In particular, when the buffer layer 102 is composed of a crystal layer having a composition that lattice-matches the single crystal material forming the substrate 101, the single crystal substrate 101 and, for example, the constituent layers of the laminated structure 1A such as the barrier layer 103. There is an advantage that the lattice mismatch of is relaxed. Therefore, it is particularly effective in obtaining the barrier layer 103 or the light emitting layer 104 having excellent crystallinity. As a preferable constituent material of the buffer layer 102 for producing this effect, boron phosphide / gallium (B 0.02 Ga 0.98 P: lattice constant ≈5.431 Å) lattice-matched to silicon (lattice constant ≈5.431 Å) can be exemplified. (The above-mentioned JP-A-11-2
66006). In addition, boron phosphide / gallium (B
0.32 Ga 0.68 P: lattice constant ≈ 5.450Å) or boron arsenide / gallium (B 0.23 Ga 0.77 As: lattice constant ≈ 5.45)
GaP single crystal (lattice constant ≈ 5.450) from 0Å)
Å) A boron-containing III-V group compound semiconductor mixed crystal layer that achieves lattice matching with the substrate can be formed (Japanese Patent Laid-Open No. 2000-22211).
(See the official gazette).
【0017】緩衝層102を、非晶質または多結晶から
なる薄膜層から構成すると、基板101と障壁層103
を構成する材料間の熱膨張率の差異に起因する障壁層1
03の基板101表面からの剥離を防止するに効果が挙
げられる。特に、緩衝層102を、障壁層103と同一
の含硼素III−V族化合物半導体材料から構成する
と、障壁層103の剥離を防止するに顕著に効果を挙げ
られる。非晶質または多結晶のBαAlβGaγIn1-
α - β - γP1- δAsδ(0<α≦1、0≦β<1、0≦
γ<1で且つ0<α+β+γ≦1、0≦δ<1)緩衝層
102は、例えば、MOCVD法(Inst.Phy
s.Conf.Ser.,No.129(IOP Pu
blishing Ltd.,1993)、157〜1
62頁参照)により成膜温度を、比較的低温の250℃
〜750℃とすれば形成できる。約500℃以下の低温
では、非晶質を主体とする含硼素III−V族化合物半
導体層が得られ易い。大凡、500℃〜750℃のより
高温領域では多結晶の含硼素III−V族化合物半導体
層が得られる。非晶質或いは多結晶の緩衝層102を構
成する薄膜層の層厚は、約1nm以上で100nm以
下、更には、2nm以上で50nm以下であるのが望ま
しい。薄膜層が非晶質層か多結晶層の何れかであるか
は、例えば、一般的なX線回折法、電子線回折法に依る
回折像の解析から知れる。When the buffer layer 102 is composed of a thin film layer made of amorphous or polycrystalline, the substrate 101 and the barrier layer 103 are formed.
Barrier layer 1 due to the difference in the coefficient of thermal expansion between the materials constituting the
It is effective to prevent the peeling of 03 from the surface of the substrate 101. In particular, when the buffer layer 102 is made of the same boron-containing III-V group compound semiconductor material as that of the barrier layer 103, the effect of preventing peeling of the barrier layer 103 can be remarkably exhibited. Amorphous or polycrystalline B α Al β Ga γ In 1-
α - β - γ P 1- δ As δ (0 <α ≤ 1, 0 ≤ β <1, 0 ≤
The buffer layer 102 with γ <1 and 0 <α + β + γ ≦ 1, 0 ≦ δ <1 is formed by, for example, the MOCVD method (Inst. Phy).
s. Conf. Ser. , No. 129 (IOP Pu
blushing Ltd. , 1993), 157-1
(See page 62), the deposition temperature is set to a relatively low temperature of 250 ° C.
It can be formed at 750 ° C. At a low temperature of about 500 ° C. or lower, a boron-containing III-V group compound semiconductor layer mainly composed of an amorphous material is easily obtained. A polycrystalline boron-containing III-V group compound semiconductor layer is obtained in a higher temperature range of about 500 ° C to 750 ° C. The layer thickness of the thin film layer forming the amorphous or polycrystalline buffer layer 102 is preferably about 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 50 nm or less. Whether the thin film layer is an amorphous layer or a polycrystalline layer can be known from, for example, analysis of a diffraction image by a general X-ray diffraction method or electron beam diffraction method.
【0018】非晶質または多結晶からなる緩衝層102
はまた、基板101を構成する単結晶材料の表面をなす
結晶面の面指数に依らずに、その上層の障壁層103を
構成する結晶面を画一的に特定する作用を有する。例え
ば、シリコン等の立方晶基板表面上に設けた非晶質また
は多結晶の緩衝層102を介在させて障壁層103を設
ける構成とすると、{110}結晶面を主体としてなる
結晶層が安定して得られる。面指数を{110}とする
結晶面({110}結晶面)とは、(110)、(−
1,1,0)、(−1,−1,0)、(1,−1,0)
等の(110)に等価な結晶面の総称である。緩衝層1
02或いは障壁層103等を構成する結晶面は通常のX
線回折パターン或いは電子線回折パターンの解析から同
定できる。{110}結晶面を主体としてなる含硼素I
II−V族化合物半導体層、例えば、リン化硼素層は大
凡、750℃〜1200℃の範囲で形成できる。120
0℃を越える高温での成膜は、含硼素III−V族化合
物半導体層の構成元素、特に、V族構成元素の揮散に因
る孔(pit)を顕著に発生させ、平滑な表面の半導体
層を安定して帰結するに支障を来す。立方晶閃亜鉛鉱結
晶型の含硼素III−V族化合物半導体は、[110]
に明瞭な劈開性を呈する(河東田 隆著、「電子・情報
工学講座12 デバイス・プロセス」(1993年1月
15日、(株)培風館発行初版)、161頁参照)。従
って、{110}結晶面からなる含硼素III−V族化
合物半導体層には簡便に劈開を及ぼせる。従って、主に
{110}結晶面からなる結晶層を備えた積層構造体か
らは、例えば、劈開面を共振端面とする直方体状のレー
ザダイオードを簡便に構成できる利点がある。Buffer layer 102 made of amorphous or polycrystalline
Also has a function of uniformly specifying the crystal plane that forms the barrier layer 103 that is an upper layer of the single crystal material that does not depend on the plane index of the crystal plane that forms the surface of the substrate 101. For example, if the barrier layer 103 is provided with the amorphous or polycrystalline buffer layer 102 provided on the surface of a cubic substrate of silicon or the like interposed, the crystal layer mainly composed of the {110} crystal plane is stabilized. Obtained. The crystal planes ({110} crystal planes) whose plane index is {110} are (110) and (-
1,1,0), (-1, -1,0), (1, -1,0)
Is a general term for crystal planes equivalent to (110). Buffer layer 1
02 or the crystal planes constituting the barrier layer 103 and the like are normal X
It can be identified by analyzing the line diffraction pattern or the electron beam diffraction pattern. Boron-containing I mainly composed of {110} crystal planes I
The II-V group compound semiconductor layer, for example, the boron phosphide layer can be formed in the range of approximately 750 ° C to 1200 ° C. 120
The film formation at a high temperature exceeding 0 ° C. remarkably generates pores (pits) due to the volatilization of the constituent elements of the boron-containing III-V group compound semiconductor layer, particularly the group V constituent elements, and the semiconductor having a smooth surface. It hinders stable formation of layers. A cubic zinc blende crystal type boron-containing III-V group compound semiconductor is [110]
It exhibits a clear cleavage property (see Takashi Kawatoda, “Electronics and Information Engineering Course, 12 Device Process” (January 15, 1993, first edition published by Baifukan Co., Ltd.), p. 161). Therefore, the boron-containing III-V group compound semiconductor layer having the {110} crystal plane can be easily cleaved. Therefore, for example, a laminated laser body having a crystal layer mainly composed of {110} crystal faces has an advantage that a rectangular parallelepiped laser diode having a cleavage plane as a resonance end face can be easily configured.
【0019】緩衝層102上には、例えば、一般式Bα
AlβGaγIn1- α - β - γP1- δAsδ(0<α≦
1、0≦β<1、0≦γ<1で且つ0<α+β+γ≦
1、0≦δ<1)、或いは一般式BαAlβGaγIn
1- α - β - γP1- δNδ(0<α≦1、0≦β<1、0≦
γ<1で且つ0<α+β+γ≦1、0<δ<1)で表記
される含硼素III−V族化合物半導体層からなる障壁
層103を設ける。障壁層103を、基板101との接
合界面で緩衝層102と格子整合し、且つ発光層104
との接合界面で発光層104に格子整合する硼素組成比
を有する組成勾配層から構成する。障壁層103を、緩
衝層102と発光層104の双方に格子整合する組成勾
配層は、ミスフィット転位、積層欠陥等の結晶欠陥密度
の低い良質の発光層104をもたらすに貢献できる。含
硼素III−V族化合物半導体組成勾配層は、緩衝層を
構成する従来の含硼素III−V族化合物半導体層に見
られる如く(上記の特開2000−22211号参
照)、層厚の増加方向に一律に、または段階的に、或い
は非直線的に硼素組成比を増減させる何れの様式をもっ
てしても構成できる。例えば、シリコンからなる基板1
01上にリン化ガリウム(GaP)からなる発光層10
4を設けるに際し、シリコン基板101との界面で、硼
素組成比(=X)を0.02としGaP発光層との界面
で硼素組成比を0(零)に直線的に減じる様に硼素
(B)組成比(=α)に勾配を付したリン化硼素・ガリ
ウム(BαGaδP:α=0.02→0、対応して、δ
=0.98→1.00、α+δ=1)組成勾配層は、基
板101或いは緩衝層102と発光層104との間の格
子ミスマッチを緩和する機能層として有効に作用でき
る。On the buffer layer 102, for example, the general formula B α
Al β Ga γ In 1- α - β - γ P 1- δ As δ (0 <α ≦
1, 0 ≦ β <1, 0 ≦ γ <1, and 0 <α + β + γ ≦
1, 0 ≦ δ <1) or the general formula B α Al β Ga γ In
1- α - β - γ P 1- δ N δ (0 <α ≦ 1, 0 ≦ β <1, 0 ≦
A barrier layer 103 composed of a boron-containing III-V group compound semiconductor layer represented by γ <1 and 0 <α + β + γ ≦ 1, 0 <δ <1) is provided. The barrier layer 103 is lattice-matched with the buffer layer 102 at the bonding interface with the substrate 101, and the light emitting layer 104 is provided.
It is composed of a composition gradient layer having a boron composition ratio that is lattice-matched to the light emitting layer 104 at the junction interface with. The composition gradient layer in which the barrier layer 103 is lattice-matched to both the buffer layer 102 and the light emitting layer 104 can contribute to providing a high quality light emitting layer 104 with low crystal defect density such as misfit dislocations and stacking faults. The boron-containing III-V group compound semiconductor composition gradient layer has an increasing layer thickness direction as seen in the conventional boron-containing III-V group compound semiconductor layer forming the buffer layer (see Japanese Patent Laid-Open No. 2000-22211 above). It can be configured in any manner that the boron composition ratio is increased or decreased uniformly, stepwise, or non-linearly. For example, a substrate 1 made of silicon
01 on the light emitting layer 10 made of gallium phosphide (GaP)
4 is provided, the boron composition ratio (= X) at the interface with the silicon substrate 101 is set to 0.02, and the boron composition ratio is linearly reduced to 0 (zero) at the interface with the GaP light emitting layer. ) Boron phosphide / gallium (B α Ga δ P: α = 0.02 → 0, which has a gradient in the composition ratio (= α), correspondingly, δ
= 0.98 → 1.00, α + δ = 1) The composition gradient layer can effectively act as a functional layer that relaxes the lattice mismatch between the substrate 101 or the buffer layer 102 and the light emitting layer 104.
【0020】本発明の第4の実施形態では、組成勾配を
有する障壁層103を、基板101をなす単結晶材料に
格子整合する含硼素III−V族化合物半導体層から緩
衝層102上に設けるのを好適とする。例えば、基板1
01をシリコン(格子定数≒5.431Å)とし、緩衝
層102をリン化硼素・ガリウム(B0.02Ga0.98P:
格子定数≒5.431Å)から構成し、障壁層103を
緩衝層102との接合界面で硼素組成比(=X)を0.
02(=2%)とするBXGa1-XP組成勾配層から構成
する例が上げられる。緩衝層102を基板101の単結
晶材料に格子整合する材料から構成とすると、格子不整
合性に因るミスフィット転位等の結晶欠陥の発生を抑制
するに殊更、効果が挙げられ、結晶性に優れる良質の障
壁層103、しいては発光層104をもたらすことがで
きる。In the fourth embodiment of the present invention, the barrier layer 103 having a composition gradient is provided on the buffer layer 102 from a boron-containing Group III-V compound semiconductor layer lattice-matched to the single crystal material forming the substrate 101. Is preferred. For example, substrate 1
01 is silicon (lattice constant≈5.431Å), and the buffer layer 102 is boron phosphide / gallium (B 0.02 Ga 0.98 P:
Lattice constant≈5.431Å), and the boron composition ratio (= X) is 0.
An example of the composition is a B X Ga 1 -X P composition gradient layer having a content of 02 (= 2%). When the buffer layer 102 is made of a material that is lattice-matched to the single crystal material of the substrate 101, it is particularly effective in suppressing the generation of crystal defects such as misfit dislocations due to the lattice mismatch, and the crystallinity is improved. An excellent quality barrier layer 103 and thus a light emitting layer 104 can be provided.
【0021】障壁層103は、発光層104よりも大き
な禁止帯幅を与える硼素組成比を有する組成勾配層から
構成する。少なくとも、発光層104に対向する表面と
は反対側の緩衝層102に対向する表面側の領域は、発
光層104を越える禁止帯幅の含硼素III−V族化合
物半導体層から構成する。この様な高い禁止帯幅の障壁
層103はリン化硼素(BP)系半導体から好適に構成
できる。例えば、成長速度と、III族構成元素及びV
族構成元素の原料の供給比率(所謂、V/III比率)
を規定された範囲内に設定することにより得られる室温
での禁止帯幅を3.0±0.2eVとする単量体のリン
化硼素(BP)を基材として構成できる(上記の特願2
001−158282号参照)。例えば、室温での禁止
帯幅を3.0eVとする単量体BPを基材として、リン
化ガリウム(GaP)と混晶となせば、禁止帯幅を2.
3eV(GaPの禁止帯幅に相当する)以上で3.0e
V(BPの禁止帯幅に相当する)以下とするリン化硼素
・ガリウム(BXGa1-XP:0≦X≦1)組成勾配層を
構成できる。因みに、従来の禁止帯幅を約2.0eVと
するリン化硼素(BP)をGaPと混晶化させても2.
0eV以上で2.3eV以下の禁止帯幅の小さなBXG
a1-XPが帰結されるのみである。即ち、例えば、Ga
As1-ZPZ(0≦Z≦1)からなる発光層全般に対して
障壁作用を及ぼす障壁層を構成できない。禁止帯幅は例
えば、屈折率(=n)と消衰係数(=k)との積値で与
えられる複素誘電率(ε2=2・n・k)の波長(光子
エネルギー)依存性から求められる。The barrier layer 103 is composed of a composition gradient layer having a boron composition ratio that gives a larger bandgap than the light emitting layer 104. At least a region on the surface side facing the buffer layer 102 on the side opposite to the surface facing the light emitting layer 104 is composed of a boron-containing III-V compound semiconductor layer having a bandgap exceeding the light emitting layer 104. The barrier layer 103 having such a high forbidden band width can be preferably composed of a boron phosphide (BP) based semiconductor. For example, the growth rate, group III constituent elements and V
Supply ratio of raw materials of group constituent elements (so-called V / III ratio)
Can be constituted by using a monomeric boron phosphide (BP) having a bandgap at room temperature of 3.0 ± 0.2 eV, which is obtained by setting the above-mentioned value as a base material (the above-mentioned Japanese Patent Application No. Two
001-158282). For example, if a mixed crystal of gallium phosphide (GaP) is used as a base material of a monomer BP having a bandgap of 3.0 eV at room temperature, the bandgap of 2.
3.0e above 3eV (corresponding to the band gap of GaP)
A boron phosphide / gallium (B X Ga 1-X P: 0 ≦ X ≦ 1) composition gradient layer having a V (corresponding to the band gap of BP) or less can be formed. By the way, even if boron phosphide (BP) having a conventional band gap of about 2.0 eV is mixed with GaP, 2.
B X G with a small bandgap of more than 0 eV and less than 2.3 eV
It only results in a 1-X P. That is, for example, Ga
It is not possible to form a barrier layer that exerts a barrier action on the entire light emitting layer made of As 1 -Z P Z (0 ≦ Z ≦ 1). The band gap is obtained from the wavelength (photon energy) dependence of the complex permittivity (ε 2 = 2 · n · k) given by the product value of the refractive index (= n) and the extinction coefficient (= k), for example. To be
【0022】障壁層103上に設ける発光層104は、
例えば、ガリウム(Ga)とリン(P)とを含む含ガリ
ウムIII−V族化合物半導体層から構成する。一例と
して、砒化リン化ガリウム(GaAs1-ZPZ:0≦Z≦
1)から発光層104を構成する例を挙げられる。Ga
Pからは純緑色(波長≒555nm)から赤色帯光を放
射する発光層104を構成できる。例えば、亜鉛(Z
n)と酸素(O)とを添加したGaP層は赤色帯光を発
する発光層104として利用できる。また、GaAs
1-ZPZ混晶からは、例えば、黄色帯や橙色帯の発光をも
たらす発光層104を構成できる。また、窒素(N)を
添加した例えば、n形GaAs1-XPX層は、窒素(N)
の等電子的捕獲中心(isoelectronic t
rap)作用に依り高強度の発光をもたらせる発光層1
04として有用である。The light emitting layer 104 provided on the barrier layer 103 is
For example, it is composed of a gallium-containing III-V compound semiconductor layer containing gallium (Ga) and phosphorus (P). As an example, gallium arsenide phosphide (GaAs 1-Z P Z : 0 ≦ Z ≦
Examples of forming the light emitting layer 104 from 1) are given. Ga
From P, a light emitting layer 104 that emits pure green (wavelength≈555 nm) to red band light can be formed. For example, zinc (Z
The GaP layer to which n) and oxygen (O) are added can be used as the light emitting layer 104 that emits red band light. Also, GaAs
1-Z from P Z mixed crystal, for example, may constitute the light emitting layer 104 to bring the emission of yellow band or orange band. Further, for example, an n-type GaAs 1-X P X layer to which nitrogen (N) is added is nitrogen (N).
Isoelectronic traps of
rap) light-emitting layer 1 capable of producing high-intensity light emission by the action
It is useful as 04.
【0023】発光層104は、また、上記の障壁層10
3の発光層104に対向する表面をなす含硼素III−
V族化合物半導体層から構成することもできる。発光層
に格子整合する組成を有する組成勾配層上の表面に、更
にその表面をなす含硼素IIIV族化合物半導体層を所
望の層厚に積層して発光層104となすことができる。
障壁層103の表面に、障壁層103と同一の材料から
構成される発光層104を積層させれば、両層103、
104の格子定数の一致に依り、殊更、格子不整合に起
因する結晶欠陥密度の少ない発光層104を得ることが
できる。本発明の第2の実施形態の好例として、障壁層
103と発光層104の双方を導電性のリン化硼素・ガ
リウム(BαGaδP:0<α≦1、0≦δ<1、α+
δ=1)から構成する例が挙げられる。また、双方の層
103,104をリン化硼素・インジウム混晶(BαI
n1- αP:0<α≦1)から構成する例が挙げられる。The light emitting layer 104 also includes the barrier layer 10 described above.
Boron-containing III-
It can also be composed of a group V compound semiconductor layer. On the surface of the composition gradient layer having a composition that lattice-matches the light emitting layer, a boron-containing group IIIV compound semiconductor layer forming the surface can be further laminated to a desired thickness to form the light emitting layer 104.
If a light emitting layer 104 made of the same material as the barrier layer 103 is laminated on the surface of the barrier layer 103, both layers 103,
Due to the matching of the lattice constants of 104, it is possible to obtain the light emitting layer 104 with a low crystal defect density due to the lattice mismatch. As a good example of the second embodiment of the present invention, both the barrier layer 103 and the light emitting layer 104 are made of conductive boron phosphide gallium (B α Ga δ P: 0 <α ≦ 1, 0 ≦ δ <1, α +
There is an example in which δ = 1). Further, both layers 103 and 104 are formed of a boron phosphide / indium mixed crystal (B α I
An example including n 1- α P: 0 <α ≦ 1) is given.
【0024】発光層104は、特に、砒化リン化硼素・
ガリウム(BYGa1-YAs1-ZPZ:0≦Y<1、0<Z
≦1)から構成できる。BYGa1-YAs1-ZPZ(0≦Y
<1、0<Z≦1)にあって、硼素(B)組成比(=
Y)を増大させれば、従来の発光層の構成材料である砒
化リン化ガリウム(GaAs1-ZPZ:0≦Z≦1)以上
の禁止帯幅の含ガリウムIII−V族化合物半導体を構
成できる。従って、これらは、GaAs1-ZPZ(0≦Z
≦1)よりも短い波長の発光を出射する発光層104と
して好適に利用できる。本発明の第3の実施形態の好例
として、発光層をシリコン(格子定数≒5.431Å)
と格子整合するB0.02Ga0.98Pから構成する例があ
る。BYGa1-YAs1-ZPZ混晶の母体材料であるリン化
硼素(BP)及びリン化砒素(BAs)は、何れも間接
遷移(indirect transition)型の
III−V族化合物半導体である(上記の「半導体デバ
イス概論」、28頁参照)。従い、窒素(N)等の電気
陰性度の大きな元素を等電子的トラップとして添加した
BYGa1-YAs1-ZPZ混晶層は高強度の発光をもたらす
発光層104として優位に利用できる。The light emitting layer 104 is formed of boron arsenide phosphide.
Gallium (B Y Ga 1-Y As 1-Z P Z : 0 ≦ Y <1, 0 <Z
≦ 1). B Y Ga 1-Y As 1-Z P Z (0 ≦ Y
<1, 0 <Z ≦ 1, and the boron (B) composition ratio (=
If Y) is increased, a gallium-containing group III-V compound semiconductor having a forbidden band width of gallium arsenide phosphide (GaAs 1-Z P Z : 0 ≦ Z ≦ 1) or more, which is a conventional constituent material of the light-emitting layer, can be obtained. Can be configured. Therefore, these are GaAs 1-Z P Z (0 ≦ Z
It can be suitably used as the light emitting layer 104 that emits light having a wavelength shorter than ≦ 1). As a good example of the third embodiment of the present invention, the light emitting layer is made of silicon (lattice constant ≈5.431Å).
There is an example in which it is composed of B 0.02 Ga 0.98 P that lattice-matches with. B Y Ga 1-Y As 1 -Z P Z mixed crystals of boron phosphide is base material (BP) and phosphorus arsenic (BAs) are all indirect transition (indirect transition) type, group III-V compound semiconductor (See “Introduction to Semiconductor Devices” above, page 28). Therefore, the B Y Ga 1-Y As 1-Z P Z mixed crystal layer to which an element having a large electronegativity such as nitrogen (N) is added as an isoelectronic trap is predominantly used as the light-emitting layer 104 that provides high-intensity light emission Available.
【0025】本発明の第5の実施形態では、特に、基板
101をシリコンとし、基板101と発光層104との
中間の障壁層103を基板101のシリコンと同一の伝
導形のn形またはp形のBαGaδP(0<α≦1、0
≦δ<1、α+δ=1)層から構成する。また、本発明
の第6の実施形態では、特に、基板101をシリコンと
し、障壁層103を基板のシリコンと同一の伝導形のn
形またはp形のBαIn 1- αP(0<α≦1)層から構
成する。BαGaδP(0<α≦1、0≦δ≦1)及び
BαIn1- αP(0<α≦1)は硼素組成比如何に依っ
て、基板101をなすシリコン(格子定数≒5.431
Å)とBYGa1-YAs1-ZPZ発光層の双方に格子整合す
る組成勾配層を簡便に構成できる利点がある。p形障壁
層103を得るためのp形ドーパント(dopant)
として、亜鉛(Zn)、マグネシウム(Mg)やベリリ
ウム(Be)などの第II族元素を例示できる。また、
n形ドーパントとして珪素(Si)、錫(Sn)等の第
IV族元素、並びに硫黄(S)やセレン(Se)、テル
ル(Te)等の第VI族元素を例示できる。In the fifth embodiment of the present invention, in particular, the substrate
101 is silicon, and the substrate 101 and the light emitting layer 104
The intermediate barrier layer 103 has the same conductivity as the silicon of the substrate 101.
Conductive n-type or p-type BαGaδP (0 <α ≦ 1, 0
≦ δ <1, α + δ = 1) layers. Also, the present invention
In the sixth embodiment of the present invention, in particular, the substrate 101 is made of silicon.
The barrier layer 103 is of the same conductivity type as the substrate silicon.
Shaped or p-shaped BαIn 1- αConstructed from P (0 <α ≦ 1) layers
To achieve. BαGaδP (0 <α ≦ 1, 0 ≦ δ ≦ 1) and
BαIn1- αP (0 <α ≦ 1) depends on the boron composition ratio
As the substrate 101 (lattice constant ≈5.431)
Å) and BYGa1-YAs1-ZPZLattice matched to both emitting layers
There is an advantage that the composition gradient layer can be easily constructed. p-type barrier
P-type dopant for obtaining layer 103
As zinc (Zn), magnesium (Mg) and beryl
Illustrative examples are Group II elements such as um (Be). Also,
Silicon (Si), tin (Sn), etc. as the n-type dopant
Group IV elements, as well as sulfur (S), selenium (Se) and tellurium
Examples thereof include Group VI elements such as Ru (Te).
【0026】本発明に係わる障壁層103を、発光層1
04の上部に設ける構成とすると二重(DH)接合型発
光部を構成できる。また、例えば、量子井戸構造からな
る発光層を構成するための障壁(barrier)層と
して利用できる。また、LEDにあって発光の外部への
取り出し方向に設ける、発光を外部へ透過する窓(wi
ndow)層等として利用できる。The barrier layer 103 according to the present invention is used as the light emitting layer 1.
If the structure is provided on the upper part of 04, a double (DH) junction type light emitting part can be formed. Further, for example, it can be used as a barrier layer for forming a light emitting layer having a quantum well structure. In addition, a window (wi) that is provided in the LED in the direction of taking out the emitted light to the outside and that transmits the emitted light to the outside
It can be used as a layer.
【0027】本発明の第7の実施形態では、積層構造体
1Aを母体材料として発光素子を構成する。例えば、L
EDは、積層構造体1Aをなす表層の発光層104上に
表面オーミック電極106を設け、また、基板101の
裏面に裏面オーミック電極107を配置して構成する。
基板101を導電性の単結晶材料から構成すれば、その
裏面にオーミック電極を設けられ、発光素子を製造する
ための電極形成工程を簡略となすことができる。p形オ
ーミック電極は、例えば、金・亜鉛(Au・Zn)合
金、金・ベリリウム(Au・Be)合金等から構成でき
る。また、金・ゲルマニウム(Au・Ge)合金、金・
インジウム(Au・In)合金、並びに金・錫(Au・
Sn)合金などの金合金等からn形オーミック電極を形
成できる。良好なオーミック接触性を発揮する電極を形
成するために、表面電極106を良導性のコンタクト
(contact)層上に設けることもできる。本発明
に係わる高い禁止帯幅の含硼素III−V族化合物半導
体層は、発光を取り出し方向に透過できる表面電極10
6用途のコンタクト層を構成するに好適である。In the seventh embodiment of the present invention, the laminated structure 1A is used as a base material to form a light emitting element. For example, L
The ED is configured by providing a front surface ohmic electrode 106 on the surface light emitting layer 104 forming the laminated structure 1A and disposing a back surface ohmic electrode 107 on the back surface of the substrate 101.
If the substrate 101 is made of a conductive single crystal material, an ohmic electrode can be provided on the back surface of the substrate 101, and the electrode forming process for manufacturing a light emitting element can be simplified. The p-type ohmic electrode can be made of, for example, a gold / zinc (Au / Zn) alloy, a gold / beryllium (Au / Be) alloy, or the like. In addition, gold / germanium (Au / Ge) alloy, gold /
Indium (Au / In) alloy, and gold / tin (Au / In)
An n-type ohmic electrode can be formed from a gold alloy such as Sn) alloy. The surface electrode 106 may be provided on the contact layer having good conductivity in order to form an electrode exhibiting good ohmic contact. The high bandgap boron-containing III-V compound semiconductor layer according to the present invention is a surface electrode 10 capable of transmitting emitted light in the extraction direction.
It is suitable for forming a contact layer for 6 purposes.
【0028】また、積層構造体1Aの基板101上に発
光素子の動作を制御するため電子部品を付帯させて設け
ることにより一体化した複合発光素子を得ることができ
る。動作制御用途の電子部品には、例えば、MES(シ
ョットキー(Schottky)金属接合型)、MOS
型(金属/酸化物/半導体接合型)或いはpn接合型電
界効果型トランジスタ(FET)、pn接合型サージダ
イオード、受光素子等を例示できる。例えば、FETを
付帯させれば、例えば、ゲート(gate)電極への信
号入力の如何に依って、点灯と消灯の何れかの動作を発
光素子に選択して施せ、電気信号に依り発光素子の発光
強度を瞬時に変化させられる。また、サージダイオード
を付帯させれば、発光素子への大きな電流の不用意な入
力を回避でき、発光素子の安定動作並びに動作寿命を延
長するに効果が奏される。また、受光素子を付帯させれ
ば、受光素子により測光される発光素子の発光の強度を
電気信号として例えば、FETに送信し、FETの電流
増幅作用を介して、発光素子の発光強度を変調させられ
る複合素子を構成できる。これらの電子機能部品は、シ
リコン等からなる基板101の表面に例えば、貼付して
設けることができる。An integrated composite light emitting device can be obtained by additionally providing electronic components on the substrate 101 of the laminated structure 1A for controlling the operation of the light emitting device. Examples of electronic components for operation control include MES (Schottky metal junction type) and MOS.
Type (metal / oxide / semiconductor junction type) or pn junction type field effect transistor (FET), pn junction type surge diode, light receiving element and the like. For example, if an FET is attached, the light emitting element can be selectively turned on or off depending on, for example, a signal input to a gate electrode, and the light emitting element can be operated according to an electric signal. The emission intensity can be changed instantly. Further, by providing a surge diode, it is possible to avoid careless input of a large current to the light emitting element, and it is effective in stabilizing the light emitting element and extending the operating life. Further, if a light receiving element is attached, the intensity of light emitted from the light emitting element measured by the light receiving element is transmitted as an electric signal to, for example, the FET, and the light emission intensity of the light emitting element is modulated through the current amplification function of the FET. Composite element can be constructed. These electronic functional components can be attached, for example, to the surface of the substrate 101 made of silicon or the like.
【0029】発光素子の動作を制御するための上記の電
子部品は、上記の本発明の第8の実施形態に示す如く、
シリコン等の基板101表面上に直接、設けられる他、
伝導形の制御が容易に行える緩衝層102または障壁層
103をなす含硼素III−V族化合物半導体層上に設
けることができる。本発明の第9の実施形態の一例を次
に記す。積層構造体1Aを一旦、形成した後、例えば、
プラズマエッチング加工を施して、積層構造体1Aの一
部の領域に限り発光層104を除去して、障壁層103
の表面を露出させる。次に、露出させた障壁層103の
表面に、同層103とは反対の伝導形の例えば、含硼素
III−V族化合物半導体層を接合させる。この様に含
硼素III−V族化合物半導体層を利用すれば、簡便に
pn接合構造を構成でき、従って、例えば、発光素子を
サージに因る破壊から保護するpn接合型ツェナ(Ze
nner)ダイオードを簡易に構成できる。The above-mentioned electronic component for controlling the operation of the light emitting device is as shown in the above-mentioned eighth embodiment of the present invention.
Directly provided on the surface of the substrate 101 such as silicon,
It can be provided on the boron-containing III-V group compound semiconductor layer forming the buffer layer 102 or the barrier layer 103 whose conductivity type can be easily controlled. An example of the ninth embodiment of the present invention will be described below. After once forming the laminated structure 1A, for example,
The light emitting layer 104 is removed only in a partial region of the laminated structure 1A by performing a plasma etching process, and the barrier layer 103 is removed.
Expose the surface of. Next, for example, a boron-containing III-V group compound semiconductor layer having a conductivity type opposite to that of the exposed layer 103 is bonded to the exposed surface of the barrier layer 103. By using the boron-containing III-V group compound semiconductor layer in this manner, a pn junction structure can be simply constructed, and therefore, for example, a pn junction Zener (Ze) which protects a light emitting element from destruction due to surge.
(nner) diode can be easily configured.
【0030】本発明に依る発光素子からは高輝度のラン
プを構成できる。例えば、本発明の第10の実施形態の
ランプは次の如くの工程をもって構成できる。図6に例
示する如く、基板11上に本発明に係わる含硼素III
−V族化合物半導体層12を備えたLED10を、台座
15上の銀(Ag)或いはアルミニウム(Al)等の金
属を鍍金した碗体16の中央部に導電性の接合材で固定
する。これより、基板11の底面に設けた一極性の電極
14を台座15に付属する一端子17に電気的に接続さ
せる。また、ヘテロ接合構造発光部12上に設置した電
極13を台座15に付属する他の一方の端子18に結線
する。一般的な半導体封止用のエポキシ樹脂19で碗体
16を囲繞する様に封止すればランプを構成できる。ま
た、本発明に係わる積層構成からなる積層構造体には劈
開を容易に及ぼせるため、約200μm〜約300μm
角の小型LEDも形成でき、従って、特に、設置容積を
小とする表示器等として好適な小型の発光ダイオードラ
ンプを構成できる。A high brightness lamp can be constructed from the light emitting device according to the present invention. For example, the lamp of the tenth embodiment of the present invention can be constructed by the following steps. As illustrated in FIG. 6, the boron-containing III according to the present invention on the substrate 11
The LED 10 provided with the group V compound semiconductor layer 12 is fixed to the central portion of the bowl body 16 plated with a metal such as silver (Ag) or aluminum (Al) on the pedestal 15 with a conductive bonding material. Thus, the unipolar electrode 14 provided on the bottom surface of the substrate 11 is electrically connected to the one terminal 17 attached to the pedestal 15. Further, the electrode 13 installed on the heterojunction structure light emitting portion 12 is connected to the other terminal 18 attached to the pedestal 15. A lamp can be constructed by encapsulating the bowl 16 with a general epoxy resin 19 for encapsulating a semiconductor. In addition, the laminated structure having the laminated structure according to the present invention can be easily cleaved, so that the laminated structure has a thickness of about 200 μm to about 300 μm.
A small-angle LED can also be formed, and thus a small-sized light-emitting diode lamp can be constructed which is particularly suitable as an indicator or the like having a small installation volume.
【0031】また、本発明の第11の実施形態では、L
ED或いは樹脂封止されたダイオードランプを集合させ
て、光源を構成する。例えば、複数のLEDを電気的に
並列に接続させて、定電圧駆動型の光源を構成できる。
また、電気的に直列にダイオードランプを接続して定電
流駆動型の光源を構成できる。これらのLEDを利用す
る光源は、従来の白熱型のランプ光源とは異なり、点灯
によりさほど放熱を伴わないため、冷光源として特に有
用に利用できる。例えば、冷凍食品の展示用光源として
利用できる。また、例えば、屋外表示器、交通信号を提
示するための信号器、自動車用途の方向指示器或いは照
明機器等に好適に用いられる光源を構成できる。In the eleventh embodiment of the present invention, L
A light source is formed by assembling ED or resin-sealed diode lamps. For example, a constant voltage drive type light source can be configured by electrically connecting a plurality of LEDs in parallel.
Further, a constant current drive type light source can be configured by electrically connecting diode lamps in series. Unlike conventional incandescent lamp light sources, light sources using these LEDs do not radiate much heat when turned on, and thus can be particularly usefully used as cold light sources. For example, it can be used as a light source for displaying frozen foods. Further, for example, a light source suitably used for an outdoor display device, a traffic light for presenting a traffic signal, a direction indicator for an automobile, or a lighting device can be configured.
【0032】[0032]
【作用】単結晶基板と砒化リン化硼素・ガリウム(BY
Ga1-YAs1-ZPZ:0≦Y<1、0<Z≦1)発光層
との中間に設けられた含硼素III−V族化合物半導体
からなる障壁層は、基板をなす単結晶材料と発光層との
格子不整合性を緩和して結晶性に優れる良質の発光層を
もたらす作用を有する。Function: Single crystal substrate and boron arsenide phosphide / gallium (B Y
Ga 1-Y As 1-Z P Z : 0 ≦ Y <1, 0 <Z ≦ 1) The barrier layer made of a boron-containing III-V group compound semiconductor provided between the light-emitting layer and the light-emitting layer is a single substrate layer. It has an effect of relaxing the lattice mismatch between the crystalline material and the light emitting layer to provide a high quality light emitting layer having excellent crystallinity.
【0033】特に、砒化リン化硼素・ガリウム(BYG
a1-YAs1-ZPZ:0≦Y<1、0<Z≦1)発光層と
同一の格子定数を有する含硼素III−V族化合物半導
体からなる障壁層は、殊更、結晶性に優れる良質の発光
層をもたらす作用を有する。In particular, boron arsenide phosphide / gallium (B Y G
a 1-Y As 1-Z P Z : 0 ≦ Y <1, 0 <Z ≦ 1) The barrier layer made of a boron-containing group III-V compound semiconductor having the same lattice constant as that of the light emitting layer is particularly crystalline. It has an effect of providing a high quality light emitting layer excellent in
【0034】[0034]
【実施例】(第1実施例)珪素(Si)単結晶基板上
に、リン化硼素(BP)結晶層とリン化ガリウム(Ga
P)単結晶層との単一(SH)ヘテロ接合構造を備えた
積層構造体とその積層構造体からGaP系LEDを構成
する場合を例にして本発明を具体的に説明する。Example 1 First Example A boron (phosphide) (BP) crystal layer and gallium phosphide (Ga) were formed on a silicon (Si) single crystal substrate.
P) The present invention will be described in detail with reference to a laminated structure having a single (SH) heterojunction structure with a single crystal layer and a case where a GaP-based LED is formed from the laminated structure.
【0035】本実施例に係わるLED2Bの平面模式図
を図2に示す。また、図2の破線X−X’に沿ったLE
D2Bの断面構造を図3の模式図に示す。図2及び図3
において、図1に掲示したのと同一の構成要素について
は同一の符号を付すこととする。A schematic plan view of the LED 2B according to this embodiment is shown in FIG. Moreover, LE along the broken line XX ′ of FIG.
The cross-sectional structure of D2B is shown in the schematic diagram of FIG. 2 and 3
In FIG. 1, the same components as those shown in FIG. 1 are designated by the same reference numerals.
【0036】本発明に係わる発光素子用積層構造体2A
は、硼素(B)ドープp形{100}−Si単結晶を基
板101として構成した。基板101の表面を構成する
結晶面は、[110]方向に角度にして2度(°)傾斜
した{100}面である。基板101の表面上には、ト
リエチル硼素((C2H5)3B)/ホスフィン(PH3)
/水素(H2)系常圧MOCVD法により、350℃
で、as−grown状態で非晶質を主体としたリン化
硼素からなる緩衝層102を堆積した。緩衝層102の
層厚は約12nmに設定した。Laminated structure 2A for light emitting device according to the present invention
The substrate 101 was made of boron (B) -doped p-type {100} -Si single crystal. The crystal plane that forms the surface of the substrate 101 is a {100} plane that is inclined by 2 degrees (°) in the [110] direction. Triethyl boron ((C 2 H 5 ) 3 B) / phosphine (PH 3 ) is formed on the surface of the substrate 101.
/ Hydrogen (H 2 ) at 350 ° C. by atmospheric pressure MOCVD method
Then, in the as-grown state, a buffer layer 102 made of boron phosphide mainly composed of amorphous was deposited. The layer thickness of the buffer layer 102 was set to about 12 nm.
【0037】緩衝層102の表面上には、(C2H5)3
B/トリメチルインジウム((CH3) 3In)/PH3
/H2系常圧MOCVD法により、800℃でマグネシ
ウム(Mg)をドーピングしたp形BXIn1-XP組成勾
配層を障壁層103として積層した。p形BXIn1-XP
組成勾配層の硼素組成比(=X)は、緩衝層102との
接合界面で1.00とし表面で0.32となる様に直線
的に減少させた。下部クラッド層として利用したBXI
n1-XP組成勾配層103は、主に{110}結晶面か
ら構成されるものとなった。マグネシウム(Mg)のド
ーピング源には、ビス−シクロペンタジエニルマグネシ
ウム(分子式:bis−(C5H4)2Mg)を用いた。
下部障壁層103をなすp形BXIn1-XP組成勾配層の
キャリア濃度は約8×1018cm-3とした。層厚は約1
000nmとした。上記の緩衝層102を下地層とした
ため、p形BXIn1-XP(X=1.00→0.32)障
壁層103は亀裂(crack)も無い連続膜となっ
た。On the surface of the buffer layer 102, (C2HFive)3
B / trimethylindium ((CH3) 3In) / PH3
/ H2System at atmospheric pressure by the MOCVD method
P-type B doped with um (Mg)XIn1-XP composition
The layered structure was laminated as the barrier layer 103. p type BXIn1-XP
The boron composition ratio (= X) of the composition gradient layer is equal to that of the buffer layer 102.
Straight line so that the joint interface is 1.00 and the surface is 0.32
Have been reduced. B used as the lower clad layerXI
n1-XIs the P composition gradient layer 103 mainly composed of {110} crystal faces?
It was composed of Magnesium (Mg)
The bis-cyclopentadienyl magnesi
Um (Molecular formula: bis- (CFiveHFour)2Mg) was used.
P-type B forming the lower barrier layer 103XIn1-XP composition gradient layer
Carrier concentration is about 8 × 1018cm-3And Layer thickness is about 1
000 nm. The buffer layer 102 was used as a base layer
Therefore, p-type BXIn1-XP (X = 1.00 → 0.32) obstacle
The wall layer 103 becomes a continuous film without cracks.
It was
【0038】p形BXIn1-XP組成勾配層からなる障壁
層103上には、n形リン化ガリウム(GaP)からな
る発光層104を積層させた。発光層104は、表面
を、GaP(格子定数≒5.450Å)に格子整合する
組成のB0.32In0.68P障壁層103上に設ける構成と
したため、亀裂も無い連続膜となった。n形のドーパン
トとして珪素(Si)を用い、キャリア濃度は約1×1
017cm-3とした。発光層104の層厚は約180nm
とした。発光層104をトリメチルガリウム((C
H3)3Ga)/PH3/H2 系常圧MOCVD法に依
り、800℃で成長させる際には、アンモニア(N
H3)を使用して窒素(N)をアイソエレクトロニック
トラップとしてドーピングした。GaP発光層104内
部の窒素原子濃度は、2次イオン質量分析法(SIM
S)に依り、約7×1018原子/cm3と定量された。A light emitting layer 104 made of n-type gallium phosphide (GaP) was laminated on the barrier layer 103 made of the p-type B X In 1 -X P composition gradient layer. The light emitting layer 104 is a continuous film having no cracks because the surface is provided on the B 0.32 In 0.68 P barrier layer 103 having a composition that lattice-matches to GaP (lattice constant ≈ 5.450 Å). Silicon (Si) is used as the n-type dopant, and the carrier concentration is about 1 × 1.
It was set to 0 17 cm -3 . The layer thickness of the light emitting layer 104 is about 180 nm.
And The light emitting layer 104 is formed by trimethylgallium ((C
According to the H 3 ) 3 Ga) / PH 3 / H 2 system atmospheric pressure MOCVD method, ammonia (N 2
Nitrogen (N) doped as isoelectronic traps using H 3). The nitrogen atom concentration inside the GaP light emitting layer 104 is determined by the secondary ion mass spectrometry (SIM
According to S), the amount was determined to be about 7 × 10 18 atoms / cm 3 .
【0039】発光層104の表面上には、円形の結線用
の台座電極を兼用する表面電極106を配置した。表面
電極106は金(Au)・ゲルマニウム(Ge)真空蒸
着膜から構成した。表面電極106の直径は120μm
とした。また、p形Si基板101の裏面の略全面に
は、裏面オーミック電極107を配置してLED1Bを
構成した。p形裏面電極107はアルミニウム(Al)
真空蒸着膜から構成した。次に、{100}結晶面を主
面とするSi単結晶101を基板とする積層構造体2A
を[110]結晶方位に沿って劈開し、一辺を約300
μmとする正方形のLEDチップ2Bとした。On the surface of the light emitting layer 104, a surface electrode 106 which also serves as a pedestal electrode for circular connection is arranged. The surface electrode 106 was composed of a gold (Au) / germanium (Ge) vacuum deposition film. The diameter of the surface electrode 106 is 120 μm
And Further, the back surface ohmic electrode 107 is arranged on substantially the entire back surface of the p-type Si substrate 101 to form the LED 1B. The p-type back electrode 107 is aluminum (Al)
It was composed of a vacuum deposited film. Next, a laminated structure 2A having a Si single crystal 101 having a {100} crystal plane as a main surface as a substrate
Is cleaved along the [110] crystal orientation, and one side is approximately 300
A square LED chip 2B having a size of μm was used.
【0040】表面及び裏面電極106〜107間に順方
向に20ミリアンペア(mA)の動作電流を通流したと
ころ、LED2Bからは発光中心波長を約557nmと
する緑色光が出射された。一般的な積分球を利用して測
定されるチップ(chip)状態での輝度は約6ミリカ
ンデラ(mcd)となり、高発光強度のSH接合型緑色
LEDが提供された。I−V特性から求めた順方向電圧
(所謂、Vf)は約2.2V(順方向電流=20mA)
となった。また、逆方向電圧は約8V(逆方向電流=1
0μA)であり、高耐圧のLEDが提供された。When an operating current of 20 milliamperes (mA) was passed in the forward direction between the front and back electrodes 106 to 107, green light having an emission center wavelength of about 557 nm was emitted from the LED 2B. The brightness in a chip state measured using a general integrating sphere was about 6 millicandelas (mcd), and an SH junction green LED with high emission intensity was provided. The forward voltage (so-called Vf) obtained from the IV characteristic is about 2.2 V (forward current = 20 mA).
Became. The reverse voltage is about 8V (reverse current = 1
0 μA), and a high withstand voltage LED was provided.
【0041】(第2実施例)リン化ガリウム(GaP)
単結晶基板上に、{110}−リン化硼素・ガリウム
(BXGa1-XP:0≦X≦1)結晶層とリン化硼素ガリ
ウム(BXGa1-XP)発光層との二重(DH)ヘテロ接
合構造を備えた積層構造体とその積層構造体からGaP
系LEDを構成する場合を例にして本発明を具体的に説
明する。(Second Embodiment) Gallium phosphide (GaP)
A {110} -boron phosphide / gallium (B X Ga 1-X P: 0 ≦ X ≦ 1) crystal layer and a gallium boron phosphide (B X Ga 1-X P) light emitting layer are formed on a single crystal substrate. Laminated structure having double (DH) heterojunction structure and its laminated structure to GaP
The present invention will be specifically described by taking a case of forming a system LED as an example.
【0042】本実施例に係わるLED3Bの断面模式図
を図4に示す。図4において、図2乃び図3に掲示した
のと同一の構成要素については同一の符号を付すことと
する。A schematic sectional view of the LED 3B according to this embodiment is shown in FIG. 4, the same components as those shown in FIGS. 2 and 3 are designated by the same reference numerals.
【0043】本発明に係わる発光素子用積層構造体3A
は、珪素(Si)ドープn形{100}−GaP単結晶
を基板101として構成した。基板101の表面上に
は、トリエチル硼素((C2H5)3B)/トリメチルガ
リウム((CH3)3Ga)/ホスフィン(PH3)/水
素(H2)系常圧MOCVD法により、580℃で多結
晶のリン化硼素(BP)からなる緩衝層102を堆積し
た。緩衝層102の層厚は約30nmに設定した。Laminated structure 3A for light emitting device according to the present invention
Made a substrate 101 of silicon (Si) -doped n-type {100} -GaP single crystal. On the surface of the substrate 101, triethylboron ((C 2 H 5 ) 3 B) / trimethylgallium ((CH 3 ) 3 Ga) / phosphine (PH 3 ) / hydrogen (H 2 ) based atmospheric pressure MOCVD method is used. A buffer layer 102 made of polycrystalline boron phosphide (BP) was deposited at 580 ° C. The layer thickness of the buffer layer 102 was set to about 30 nm.
【0044】緩衝層102の表面上には、(C2H5)3
B/(CH3)3Ga/PH3/H2系常圧MOCVD法に
より、800℃でn形BXGa1-XP組成勾配層を障壁層
103として堆積した。p形BXGa1-XP障壁層103
の硼素組成(=X)は、緩衝層102との接合界面で硼
素(B)組成比を1.00とし、表面で硼素組成比を
0.05に直線的に減少させた。下部クラッド層として
利用したBXGa1-XP組成勾配層は、Si基板の表面に
平行に積重したBXGa1-XP(X=1.00→0.0
5)の{110}結晶面から構成されるものとなった。
また、{110}BXGa1-XP障壁層103は、成長速
度を毎分30nmとし、V/III比率(=PH3/
(CH3)3B供給比率)を50として形成したため、複
素誘電率の光子エネルギー依存性から求めた室温での禁
止帯幅は約3.0eVとなった。珪素(Si)のドーピ
ング源には、水素−ジシラン(Si2H6)混合ガスを使
用した。下部クラッド層をなすn形BXGa1-XP障壁層
103のキャリア濃度は約8×1018cm-3とした。層
厚は約1000nmとした。上記の緩衝層102を下地
層の効用に依り、n形BXGa1-XP障壁層103は亀裂
も無い連続膜となった。On the surface of the buffer layer 102, (C 2 H 5 ) 3
An n-type B X Ga 1 -X P composition gradient layer was deposited as the barrier layer 103 at 800 ° C. by the B / (CH 3 ) 3 Ga / PH 3 / H 2 system atmospheric pressure MOCVD method. p-type B X Ga 1-X P barrier layer 103
As for the boron composition (= X), the boron (B) composition ratio was set to 1.00 at the bonding interface with the buffer layer 102, and the boron composition ratio was linearly decreased to 0.05 on the surface. The B X Ga 1-X P composition gradient layer used as the lower clad layer is B X Ga 1-X P (X = 1.00 → 0.0) stacked in parallel with the surface of the Si substrate.
It was composed of the {110} crystal plane of 5).
The {110} B X Ga 1-X P barrier layer 103 has a growth rate of 30 nm / min and a V / III ratio (= PH 3 /
Since the (CH 3 ) 3 B supply ratio) was set to 50, the forbidden band width at room temperature obtained from the photon energy dependence of the complex dielectric constant was about 3.0 eV. A hydrogen-disilane (Si 2 H 6 ) mixed gas was used as a doping source of silicon (Si). The carrier concentration of the n-type B X Ga 1-X P barrier layer 103 forming the lower clad layer was set to about 8 × 10 18 cm -3 . The layer thickness was about 1000 nm. The n-type B X Ga 1 -X P barrier layer 103 was a continuous film without cracks due to the effect of the buffer layer 102 as the underlayer.
【0045】n形BXGa1-XP障壁層103上には、n
形リン化硼素・ガリウム(B0.05Ga 0.95P)からなる
発光層104を積層させた。n形のドーパントとして珪
素(Si)を用い、キャリア濃度は約1×1017cm-3
とした。発光層104の層厚は約150nmとした。発
光層104を(C2H5)3B/(CH3)3Ga/PH3/
H2 系常圧MOCVD法に依り、800℃で成長させる
際には、アンモニア(NH3)を使用して窒素(N)を
アイソエレクトロニックトラップとしてドーピングし
た。B0.05Ga0.95P発光層104内部の窒素原子濃度
は、2次イオン質量分析法(SIMS)に依り、約8×
1018原子/cm3と定量された。N type BXGa1-XOn the P barrier layer 103, n
Boron phosphide / gallium (B0.05Ga 0.95Consists of P)
The light emitting layer 104 was laminated. Silicon as n-type dopant
Using silicon (Si), the carrier concentration is about 1 × 1017cm-3
And The layer thickness of the light emitting layer 104 was about 150 nm. Departure
Light layer 104 (C2HFive)3B / (CH3)3Ga / PH3/
H2 Grow at 800 ° C according to the atmospheric pressure MOCVD method
At the time of ammonia (NH3) To use nitrogen (N)
Doped as an isoelectronic trap
It was B0.05Ga0.95Nitrogen atom concentration inside the P emission layer 104
Is about 8 × by secondary ion mass spectrometry (SIMS)
1018Atom / cm3Was quantified.
【0046】n形B0.05Ga0.95P発光層104の表面
上には、(C2H5)3B/PH3/H2系常圧MOCVD
法に依り、350℃で非晶質を主体とするp形リン化硼
素(BP)層を障壁層105として接合させた。p形の
ドーパントとしては上記のビスシクロペンタジエニルマ
グネシウムを用いた。キャリア濃度は約2×1019cm
-3とし、層厚は680nmとした。波長(=λ)とその
波長に於ける消衰係数(=k)とから算出した吸収係数
(=4・π・k/λ:cm-1)を利用して求めた障壁層
105を構成する非晶質を主体とするBP層の室温禁止
帯幅は約3.1eVであった。n形BXGa1-XP下部障
壁層103と、n形B0.05Ga0.95P発光層104、及
びp形BP層を上部障壁層105としてpn接合型ダブ
ルヘテロ(DH)構造の発光部を形成した。N type B0.05Ga0.95Surface of P light emitting layer 104
Above, (C2HFive)3B / PH3/ H2System atmospheric pressure MOCVD
P-type phosphide mainly composed of amorphous material at 350 ° C.
The elemental (BP) layer was bonded as the barrier layer 105. p-type
The above-mentioned biscyclopentadienylmer is used as the dopant.
Gnesium was used. Carrier concentration is about 2 x 1019cm
-3And the layer thickness was 680 nm. Wavelength (= λ) and its
Absorption coefficient calculated from extinction coefficient (= k) at wavelength
(= 4 ・ π ・ k / λ: cm-1) Obtained barrier layer
Room temperature prohibition of BP layer mainly composed of amorphous material constituting 105
The band width was about 3.1 eV. n type BXGa1-XP lower obstacle
Wall layer 103 and n-type B0.05Ga0.95P light emitting layer 104 and
And p-type BP layer as the upper barrier layer 105
A light emitting portion having a ruhetero (DH) structure was formed.
【0047】非晶質のリン化硼素を主体としてなる上部
障壁層105の表面の中央部には、円形の結線用の台座
電極を兼用するp形表面電極106を配置した。p形表
面電極106は金(Au)・亜鉛(Zn)真空蒸着膜か
ら構成した。表面電極106の直径は130μmとし
た。また、n形GaP基板101の裏面の略全面には、
n形裏面電極107を配置してLED3Bを構成した。
n形裏面電極107は、金(Au)・ゲルマニウム(G
e)真空蒸着膜から構成した。次に、{100}結晶面
を主面とするがGaP単結晶101を基板とする積層構
造体3Aを[110]結晶方位に沿って劈開し、一辺を
約250μmとする正方形のLEDチップ3Bとした。At the center of the surface of the upper barrier layer 105 composed mainly of amorphous boron phosphide, a p-type surface electrode 106 also serving as a circular connection base electrode was arranged. The p-type surface electrode 106 was composed of a gold (Au) / zinc (Zn) vacuum deposited film. The diameter of the surface electrode 106 was 130 μm. In addition, on the substantially entire back surface of the n-type GaP substrate 101,
The LED 3B was constructed by arranging the n-type back electrode 107.
The n-type back electrode 107 is made of gold (Au) / germanium (G).
e) It was composed of a vacuum deposited film. Next, a laminated structure 3A having a {100} crystal plane as a main surface but having a GaP single crystal 101 as a substrate is cleaved along the [110] crystal orientation to form a square LED chip 3B having a side of about 250 μm. did.
【0048】表面及び裏面電極106〜107間に順方
向に20ミリアンペア(mA)の動作電流を通流したと
ころ、LED3Bからは、発光中心波長を約540nm
とする緑色光が出射された。一般的な積分球を利用して
測定されるチップ(chip)状態での輝度は約5ミリ
カンデラ(mcd)となり、高発光強度の短波長可視L
EDが提供された。I−V特性から求めた順方向電圧
(所謂、Vf)は約2.3V(順方向電流=20mA)
となった。また、逆方向電圧は約8V(逆方向電流=1
0μA)であり、高耐圧のLEDが提供された。When an operating current of 20 milliamperes (mA) was passed in the forward direction between the front and back electrodes 106 to 107, the emission center wavelength was about 540 nm from the LED 3B.
And emitted green light. The brightness in a chip state measured by using a general integrating sphere is about 5 millicandelas (mcd), and a short wavelength visible light L with high emission intensity is obtained.
ED provided. The forward voltage (so-called Vf) obtained from the IV characteristic is about 2.3 V (forward current = 20 mA).
Became. The reverse voltage is about 8V (reverse current = 1
0 μA), and a high withstand voltage LED was provided.
【0049】(第3実施例)珪素(Si)単結晶基板上
に、Si単結晶に構成整合する緩衝層を備えた積層構造
体とその積層構造体からGaAsP系LEDを構成する
場合を例にして本発明を具体的に説明する。(Third Embodiment) A case where a GaAsP-based LED is formed from a laminated structure provided with a buffer layer that is structurally matched to a Si single crystal on a silicon (Si) single crystal substrate will be described as an example. The present invention will be specifically described below.
【0050】本実施例に係わるLED4Bの断面模式図
を図5に示す。図5において、図2乃至図4に掲示した
同一の構成要素については同一の符号を付すこととす
る。A schematic sectional view of the LED 4B according to this embodiment is shown in FIG. 5, the same components as those shown in FIGS. 2 to 4 are designated by the same reference numerals.
【0051】本発明に係わる発光素子用積層構造体4A
は、アンチモン(Sb)ドープn形{100}−Si単
結晶を基板101として構成した。基板101の表面上
には、トリエチル硼素((C2H5)3B)/トリメチル
インジウム((CH3)3In)/ホスフィン(PH3)
/水素(H2)系減圧MOCVD法により、400℃で
リン化硼素・インジウム(BXIn1-XP)からなる緩衝
層102を成膜した。硼素(B)組成比(=X)は、S
i単結晶と同一の格子定数(≒5.431Å)をもたら
す0.32に設定した。成膜時の圧力は約5×104パ
スカル(圧力単位:Pa)とした。緩衝層102の層厚
は約10nmに設定した。Laminated structure for light emitting device 4A according to the present invention
Was configured with an antimony (Sb) -doped n-type {100} -Si single crystal as the substrate 101. On the surface of the substrate 101, triethylboron ((C 2 H 5 ) 3 B) / trimethylindium ((CH 3 ) 3 In) / phosphine (PH 3 ) is formed.
/ Hydrogen (H 2 ) -based low pressure MOCVD method was used to form a buffer layer 102 of boron phosphide / indium (B X In 1-X P) at 400 ° C. The composition ratio of boron (B) (= X) is S
It was set to 0.32, which yields the same lattice constant (≈5.431Å) as the i single crystal. The pressure during film formation was about 5 × 10 4 Pascal (pressure unit: Pa). The layer thickness of the buffer layer 102 was set to about 10 nm.
【0052】緩衝層102の表面上には、(C2H5)3
B/(CH3)3In/PH3/H2系減圧MOCVD法に
より、800℃でSiドープBXIn1-XP組成勾配層を
障壁層103として堆積した。n形BXIn1-XP組成勾
配層102の硼素組成比(=X)は、緩衝層103との
接合界面で硼素(B)組成比を0.32とし、表面で硼
素組成比を0.24に直線的に減少させた。下部クラッ
ド層として利用したBXGa1-XP(X=0.32→0.
24)組成勾配層は、主にBXIn1-XP結晶の{11
0}結晶面から構成されるものとなった。また、{11
0}−BXIn1-XP組成勾配層は、成長速度を毎分20
nmとし、V/III比率(=PH3/(CH3)3B供
給比率)を40として形成したため、複素誘電率の光子
エネルギー依存性から求めた室温での禁止帯幅は約2.
8eVとなった。珪素(Si)のドーピング源には、水
素−ジシラン(Si2H6)混合ガスを使用した。下部ク
ラッド層をなすn形BXIn1-XP障壁層103のキャリ
ア濃度は約2×1018cm-3とした。層厚は約500n
mとした。上記の緩衝層102を下地層の効用に依り、
n形BXIn1-XP障壁層103は亀裂も無い連続膜とな
った。On the surface of the buffer layer 102, (C 2 H 5 ) 3
A Si-doped B X In 1-X P composition gradient layer was deposited as the barrier layer 103 at 800 ° C. by the B / (CH 3 ) 3 In / PH 3 / H 2 system low pressure MOCVD method. Regarding the boron composition ratio (= X) of the n-type B X In 1-X P composition gradient layer 102, the boron (B) composition ratio at the junction interface with the buffer layer 103 is 0.32, and the boron composition ratio at the surface is 0. .24 linearly. B X Ga 1-X P (X = 0.32 → 0.
24) The composition gradient layer is mainly composed of B X In 1 -X P crystal {11
0} crystal plane. Also, {11
0} -B X In 1-X P composition gradient layer has a growth rate of 20 per minute.
and the V / III ratio (= PH 3 / (CH 3 ) 3 B supply ratio) is 40, the forbidden band width at room temperature obtained from the photon energy dependence of the complex permittivity is about 2.
It became 8 eV. A hydrogen-disilane (Si 2 H 6 ) mixed gas was used as a doping source of silicon (Si). The carrier concentration of the n-type B X In 1-X P barrier layer 103 forming the lower cladding layer was set to about 2 × 10 18 cm -3 . Layer thickness is about 500n
m. Depending on the effect of the base layer, the buffer layer 102 is
The n-type B X In 1-X P barrier layer 103 was a continuous film without cracks.
【0053】n形BXIn1-XP障壁層103上には、n
形砒化リン化ガリウム(GaAs0.50P0.50)からなる
発光層104を積層させた。n形のドーパントとして珪
素(Si)を用い、キャリア濃度は約2×1017cm-3
とした。発光層104の層厚は約450nmとした。発
光層104を(CH3)3Ga/アルシン(AsH3)/
PH3/H2 系減圧MOCVD法に依り、800℃で成
長させる際には、アンモニア(NH3)を使用して窒素
(N)をアイソエレクトロニックトラップとしてドーピ
ングした。GaAs0.50P0.50発光層104内部の窒素
原子濃度は、2次イオン質量分析法(SIMS)に依
り、約5×1018原子/cm3と定量された。On the n-type B X In 1-X P barrier layer 103, n
A light emitting layer 104 made of gallium arsenide phosphide (GaAs 0.50 P 0.50 ) was laminated. Silicon (Si) is used as an n-type dopant, and the carrier concentration is about 2 × 10 17 cm −3.
And The layer thickness of the light emitting layer 104 was about 450 nm. The light emitting layer 104 is formed of (CH 3 ) 3 Ga / arsine (AsH 3 ) /
According to the PH 3 / H 2 -based low pressure MOCVD method, when growing at 800 ° C., nitrogen (N) was doped as an isoelectronic trap using ammonia (NH 3 ). The nitrogen atom concentration inside the GaAs 0.50 P 0.50 light emitting layer 104 was quantified by secondary ion mass spectrometry (SIMS) to be about 5 × 10 18 atoms / cm 3 .
【0054】n形GaAs0.50P0.50発光層104の表
面上には、(C2H5)3B/PH3/H 2 系減MOCVD
法に依り、350℃で非晶質を主体とするp形リン化硼
素(BP)層を上部障壁層105として接合させた。p
形のドーパントとしては上記のビスシクロペンタジエニ
ルマグネシウムを用いた。キャリア濃度は約2×1019
cm-3とし、層厚は1080nmとした。波長(=λ)
とその波長に於ける消衰係数(=k)とから算出した吸
収係数(=4・π・k/λ:cm-1)を利用して求めた
上部障壁層105を構成する非晶質を主体とするBP層
の室温禁止帯幅は約3.1eVであった。n形BXIn
1-XP下部障壁層103と、n形GaAs0. 50P0.50発
光層104、及びp形BP層を上部障壁層105として
pn接合型ダブルヘテロ(DH)構造の発光部を形成し
た。N-type GaAs0.50P0.50Surface of light emitting layer 104
On the surface, (C2HFive)3B / PH3/ H 2 System reduction MOCVD
P-type phosphide mainly composed of amorphous material at 350 ° C.
The elemental (BP) layer was bonded as the upper barrier layer 105. p
The above-mentioned biscyclopentadiene is used as
Lumagnesium was used. Carrier concentration is about 2 x 1019
cm-3And the layer thickness was 1080 nm. Wavelength (= λ)
And the extinction coefficient (= k) at that wavelength
Collection coefficient (= 4 ・ π ・ k / λ: cm-1) Was used
Amorphous BP layer mainly constituting the upper barrier layer 105
The room temperature bandgap of was about 3.1 eV. n type BXIn
1-XP lower barrier layer 103 and n-type GaAs0. 50P0.50Departure
The optical layer 104 and the p-type BP layer as the upper barrier layer 105
Forming a light emitting part of a pn junction type double hetero (DH) structure
It was
【0055】非晶質のリン化硼素を主体としてなる上部
障壁層105の表面の中央部には、円形の結線用の台座
電極を兼用するp形表面電極106を配置した。p形表
面電極106は金(Au)・亜鉛(Zn)真空蒸着膜か
ら構成した。表面電極106の直径は130μmとし
た。また、n形Si基板101の裏面の略全面には、n
形裏面電極107を配置してLED4Bを構成した。n
形裏面電極107は、金(Au)真空蒸着膜から構成し
た。次に、{100}結晶面を主面とするがSi単結晶
101を基板とする積層構造体4Aを[110]結晶方
位に沿って劈開し、一辺を約250μmとする正方形の
LEDチップ4Bとした。At the central portion of the surface of the upper barrier layer 105 mainly composed of amorphous boron phosphide, a p-type surface electrode 106 also serving as a circular connection base electrode was arranged. The p-type surface electrode 106 was composed of a gold (Au) / zinc (Zn) vacuum deposited film. The diameter of the surface electrode 106 was 130 μm. In addition, on the substantially entire back surface of the n-type Si substrate 101, n
The shaped back electrode 107 is arranged to form the LED 4B. n
The shaped back electrode 107 was composed of a gold (Au) vacuum deposition film. Next, a laminated structure 4A having a {100} crystal plane as a main surface but a Si single crystal 101 as a substrate is cleaved along the [110] crystal orientation to form a square LED chip 4B having a side of about 250 μm. did.
【0056】表面及び裏面電極106〜107間に順方
向に20ミリアンペア(mA)の動作電流を通流したと
ころ、LED4Bからは、発光中心波長を約600nm
とする緑色光が出射された。一般的な積分球を利用して
測定されるチップ(chip)状態での輝度は約7ミリ
カンデラ(mcd)となり、高発光強度の短波長可視L
EDが提供された。I−V特性から求めた順方向電圧
(所謂、Vf)は約2.3V(順方向電流=20mA)
となった。また、逆方向電圧は約5V(逆方向電流=1
0μA)であり、高耐圧のLEDが提供された。When a forward operating current of 20 milliamperes (mA) was passed between the front and back electrodes 106 to 107, the emission center wavelength was about 600 nm from the LED 4B.
And emitted green light. The luminance in a chip state measured by using a general integrating sphere is about 7 millicandelas (mcd), and a short wavelength visible L with high emission intensity is obtained.
ED provided. The forward voltage (so-called Vf) obtained from the IV characteristic is about 2.3 V (forward current = 20 mA).
Became. The reverse voltage is about 5V (reverse current = 1
0 μA), and a high withstand voltage LED was provided.
【0057】[0057]
【発明の効果】単結晶の基板上に設けられた、含ガリウ
ムIII−V族化合物半導体層を発光層として備えてい
る発光素子用積層構造体において、発光層を、硼素組成
に勾配を付した含硼素III−V族化合物半導体組成勾
配層上に設ける構成とすることに依り、基板を構成する
単結晶材料と発光層との格子不整合性が緩和されるた
め、良好な結晶性を有する発光層を備えた発光素子用積
層構造体を構成できる。また、含硼素III−V族化合
物半導体組成勾配層の発光層に対する障壁作用を及ぼす
障壁層としての作用と相俟って、本発明に係わる発光素
子用積層構造体からは高強度の発光をもたらす発光素
子、ランプ及び光源を提供できる。INDUSTRIAL APPLICABILITY In a laminated structure for a light emitting device, which is provided on a single crystal substrate and has a gallium-containing III-V group compound semiconductor layer as a light emitting layer, the light emitting layer is provided with a gradient in boron composition. With the structure provided on the boron-containing III-V group compound semiconductor composition gradient layer, the lattice mismatch between the single crystal material forming the substrate and the light emitting layer is relaxed, so that light emission with good crystallinity is achieved. A laminated structure for a light emitting device including layers can be formed. Further, in combination with the action of the boron-containing III-V group compound semiconductor composition gradient layer as a barrier layer exerting a barrier action to the light emitting layer, the laminated structure for a light emitting device according to the present invention provides high intensity light emission. A light emitting device, a lamp and a light source can be provided.
【図1】本発明の実施の形態を示す発光素子用積層構造
体の断面模式図である。FIG. 1 is a schematic cross-sectional view of a laminated structure for a light emitting device showing an embodiment of the present invention.
【図2】第1実施例に記載のLEDの平面模式図であ
る。FIG. 2 is a schematic plan view of the LED described in the first embodiment.
【図3】図2に掲示したLEDの破線X−X’に沿った
断面模式図である。FIG. 3 is a schematic cross-sectional view of the LED shown in FIG. 2 taken along the broken line XX ′.
【図4】第2実施例に記載のLEDの断面模式図であ
る。FIG. 4 is a schematic sectional view of an LED described in a second embodiment.
【図5】第3実施例に記載のLEDの断面模式図であ
る。FIG. 5 is a schematic sectional view of an LED described in a third embodiment.
【図6】本発明に係わるランプの断面構造を例示する模
式図である。FIG. 6 is a schematic view illustrating the cross-sectional structure of the lamp according to the present invention.
1A、2A、3A、4A 発光素子用積層構造体 2B、3B、4B 発光素子(LED) 11 基板 12 ヘテロ接合発光部 13 表面側電極 14 基板裏面電極 15 台座 16 碗体 17、18 端子 19 封止樹脂 101 単結晶基板 102 緩衝層 103 障壁層 104 発光層 105 上部障壁層 106 表面電極 107 裏面電極 1A, 2A, 3A, 4A Light emitting element laminated structure 2B, 3B, 4B Light emitting element (LED) 11 board 12 Heterojunction light emitting part 13 Front side electrode 14 Substrate backside electrode 15 pedestal 16 bowl 17, 18 terminals 19 Sealing resin 101 single crystal substrate 102 buffer layer 103 barrier layer 104 light emitting layer 105 upper barrier layer 106 surface electrode 107 Back electrode
Claims (11)
層と、緩衝層上に積層された硼素(B)を含むIII−
V族化合物半導体(含硼素III−V族化合物半導体)
からなる障壁(barrier)層と、ガリウム(G
a)を含むIII−V族化合物半導体(含ガリウムII
I−V族化合物半導体)からなる発光層とを備えている
発光素子用積層構造体であって、障壁層を、上記の緩衝
層に対向する表面で緩衝層に格子整合する硼素組成比を
有し、上記の発光層に対向する表面で発光層に格子整合
する硼素組成比を有する、層厚の増加方向に硼素組成比
に勾配を付した含硼素III−V族化合物半導体からな
る組成勾配層から構成したことを特徴とする発光素子用
積層構造体。1. A single crystal substrate, a buffer layer laminated on the substrate, and boron containing boron (B) laminated on the buffer layer.
Group V compound semiconductor (boron-containing III-V group compound semiconductor)
And a gallium (G) layer.
III-V group compound semiconductor containing a) (gallium-containing II
A laminated structure for a light emitting device, comprising a light emitting layer made of a group IV compound semiconductor), the barrier layer having a boron composition ratio lattice-matched to the buffer layer on a surface facing the buffer layer. And a composition gradient layer made of a boron-containing group III-V compound semiconductor having a boron composition ratio lattice-matched to the light emitting layer on the surface facing the light emitting layer and having a boron composition ratio gradient in the increasing direction of the layer thickness. A laminated structure for a light emitting device, which is characterized by comprising:
なる発光層を、発光層に対向する障壁層の表面を構成す
る含硼素III−V族化合物半導体と同一の材料から構
成したことを特徴とする、請求項1に記載の発光素子用
積層構造体。2. A light emitting layer made of a gallium-containing III-V group compound semiconductor is made of the same material as a boron-containing III-V group compound semiconductor forming a surface of a barrier layer facing the light emitting layer. The laminated structure for a light emitting device according to claim 1.
YGa1-YAs1-ZPZ:0≦Y<1、0<Z≦1)から構
成したことを特徴とする、請求項1または2に記載の発
光素子用積層構造体。3. The light emitting layer is formed of boron arsenide phosphide / gallium (B).
Y Ga 1-Y As 1-Z P Z : 0 ≦ Y <1, 0 <Z ≦ 1), The laminated structure for a light-emitting element according to claim 1 or 2, characterized in that:
障壁層を、基板を構成する単結晶材料に格子整合する組
成を有する含硼素III−V族化合物半導体から構成し
た緩衝層上に設けたことを特徴とする請求項1乃至3の
何れか1項に記載の発光素子用積層構造体。4. A barrier layer made of a boron-containing III-V group compound semiconductor is provided on a buffer layer made of a boron-containing III-V group compound semiconductor having a composition lattice-matched to a single crystal material constituting a substrate. The laminated structure for a light emitting device according to claim 1, wherein the laminated structure is a light emitting device.
し、含硼素III−V族化合物半導体層からなる障壁層
を、リン化硼素・ガリウム(BXGa1-XP:0<X≦
1)から構成したことを特徴とする請求項1乃至4の何
れか1項に記載の発光素子用積層構造体。5. A silicon single crystal (silicon) is used as a single crystal substrate, and a barrier layer made of a boron-containing III-V group compound semiconductor layer is formed of boron phosphide / gallium (B X Ga 1-X P: 0 <X ≦
The laminated structure for a light-emitting device according to claim 1, wherein the laminated structure for a light-emitting device is configured from 1).
し、含硼素III−V族化合物半導体層からなる障壁層
を、リン化硼素・インジウム(BXIn1-XP:0<X≦
1)から構成したことを特徴とする請求項1乃至4の何
れか1項に記載の発光素子用積層構造体。6. A single crystal substrate is made of silicon single crystal (silicon), and a barrier layer composed of a boron-containing III-V group compound semiconductor layer is formed of boron phosphide / indium (B X In 1-X P: 0 <X ≦
The laminated structure for a light-emitting device according to claim 1, wherein the laminated structure for a light-emitting device is configured from 1).
素子用積層構造体を用いて構成したことを特徴とする発
光素子。7. A light emitting device comprising the laminated structure for a light emitting device according to any one of claims 1 to 6.
光素子からの発光の強度を制御するための電子部品を備
えていることを特徴とする請求項7に記載の発光素子。8. A light emitting device according to claim 7, wherein the same single crystal substrate is provided with a light emitting device and an electronic component for controlling the intensity of light emitted from the light emitting device.
導体からなる障壁層上に設けていることを特徴とする請
求項8に記載の発光素子。9. The light emitting device according to claim 8, wherein the electronic component is provided on a barrier layer made of a boron-containing III-V group compound semiconductor.
光素子から構成したことを特徴とするランプ。10. A lamp comprising the light emitting device according to claim 7.
したことを特徴とする光源。11. A light source comprising the lamp according to claim 10.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014526145A (en) * | 2011-07-12 | 2014-10-02 | エヌアーエスペー スリー/ヴィー ゲーエムベーハー | Monolithic integrated semiconductor structure |
CN112072467A (en) * | 2019-06-11 | 2020-12-11 | 全新光电科技股份有限公司 | Semiconductor laser diode |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01239969A (en) * | 1988-03-22 | 1989-09-25 | Seiko Epson Corp | Semiconductor device |
JPH05283744A (en) * | 1991-12-20 | 1993-10-29 | Toshiba Corp | Semiconductor element |
JPH05315645A (en) * | 1992-05-08 | 1993-11-26 | Sharp Corp | Semiconductor light-emitting device |
JPH10247761A (en) * | 1989-01-13 | 1998-09-14 | Toshiba Corp | Semiconductor blue light emitting device |
JPH1153338A (en) * | 1997-08-08 | 1999-02-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit and external bus mode selection method therefor |
JPH1187856A (en) * | 1997-09-16 | 1999-03-30 | Toshiba Corp | Gallium nitride compound semiconductor laser and manufacture thereof |
JPH11260720A (en) * | 1998-03-10 | 1999-09-24 | Showa Denko Kk | Epitaxial wafer |
JPH11346001A (en) * | 1998-06-03 | 1999-12-14 | Kazutaka Terajima | Iii group nitride semiconductor light emitting element |
JP2000261106A (en) * | 1999-01-07 | 2000-09-22 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting element, its manufacture and optical disk device |
JP2000277868A (en) * | 1999-03-25 | 2000-10-06 | Sanyo Electric Co Ltd | Light emitting element |
JP2000311863A (en) * | 1999-02-26 | 2000-11-07 | Matsushita Electronics Industry Corp | Semiconductor device and manufacture thereof |
JP2000351692A (en) * | 1999-06-11 | 2000-12-19 | Toshiba Ceramics Co Ltd | Si WAFER FOR GROWING GaN SEMICONDUCTOR CRYSTAL, WAFER FOR GaN LIGHT EMISSION ELEMENT USING THE SAME Si WAFER AND THEIR PRODUCTION |
JP2001176804A (en) * | 1999-12-14 | 2001-06-29 | Inst Of Physical & Chemical Res | Method for forming semiconductor layer |
-
2001
- 2001-08-01 JP JP2001233428A patent/JP3557571B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01239969A (en) * | 1988-03-22 | 1989-09-25 | Seiko Epson Corp | Semiconductor device |
JPH10247761A (en) * | 1989-01-13 | 1998-09-14 | Toshiba Corp | Semiconductor blue light emitting device |
JPH05283744A (en) * | 1991-12-20 | 1993-10-29 | Toshiba Corp | Semiconductor element |
JPH05315645A (en) * | 1992-05-08 | 1993-11-26 | Sharp Corp | Semiconductor light-emitting device |
JPH1153338A (en) * | 1997-08-08 | 1999-02-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit and external bus mode selection method therefor |
JPH1187856A (en) * | 1997-09-16 | 1999-03-30 | Toshiba Corp | Gallium nitride compound semiconductor laser and manufacture thereof |
JPH11260720A (en) * | 1998-03-10 | 1999-09-24 | Showa Denko Kk | Epitaxial wafer |
JPH11346001A (en) * | 1998-06-03 | 1999-12-14 | Kazutaka Terajima | Iii group nitride semiconductor light emitting element |
JP2000261106A (en) * | 1999-01-07 | 2000-09-22 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting element, its manufacture and optical disk device |
JP2000311863A (en) * | 1999-02-26 | 2000-11-07 | Matsushita Electronics Industry Corp | Semiconductor device and manufacture thereof |
JP2000277868A (en) * | 1999-03-25 | 2000-10-06 | Sanyo Electric Co Ltd | Light emitting element |
JP2000351692A (en) * | 1999-06-11 | 2000-12-19 | Toshiba Ceramics Co Ltd | Si WAFER FOR GROWING GaN SEMICONDUCTOR CRYSTAL, WAFER FOR GaN LIGHT EMISSION ELEMENT USING THE SAME Si WAFER AND THEIR PRODUCTION |
JP2001176804A (en) * | 1999-12-14 | 2001-06-29 | Inst Of Physical & Chemical Res | Method for forming semiconductor layer |
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JP2014526145A (en) * | 2011-07-12 | 2014-10-02 | エヌアーエスペー スリー/ヴィー ゲーエムベーハー | Monolithic integrated semiconductor structure |
CN112072467A (en) * | 2019-06-11 | 2020-12-11 | 全新光电科技股份有限公司 | Semiconductor laser diode |
CN112072467B (en) * | 2019-06-11 | 2023-07-14 | 全新光电科技股份有限公司 | Semiconductor laser diode |
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