JP2003045739A - Large capacitance capacitor of laminated micro-structure - Google Patents
Large capacitance capacitor of laminated micro-structureInfo
- Publication number
- JP2003045739A JP2003045739A JP2001211897A JP2001211897A JP2003045739A JP 2003045739 A JP2003045739 A JP 2003045739A JP 2001211897 A JP2001211897 A JP 2001211897A JP 2001211897 A JP2001211897 A JP 2001211897A JP 2003045739 A JP2003045739 A JP 2003045739A
- Authority
- JP
- Japan
- Prior art keywords
- micro
- layer
- large capacitance
- electrode substrate
- microstructure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は一種の積層式マイク
ロ構造大容量コンデンサに係り、特にリソグラフィーと
エッチングの方式により、電極基板に適当な幅深さ比の
トレンチを形成した後、順に高誘電質層と導電材料層を
形成し、複数組を連結後に得られる適当な電容量の積層
式マイクロ構造大容量コンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a kind of laminated micro-structured large-capacity capacitor, and in particular, after forming a trench having an appropriate width-depth ratio in an electrode substrate by a method of lithography and etching, a high dielectric constant layer is formed. The present invention relates to a laminated microstructure large-capacity capacitor having an appropriate capacitance obtained by forming a layer and a conductive material layer and connecting a plurality of sets.
【0002】[0002]
【従来の技術】現在のスター産業であるモバイル通信
中、例えば携帯電話(cellularphone)、
ブルートゥース(bluetooth)モジュール、モ
バイルネットワークブラウザ、グローバルポジショニン
グシステム(global positioning
system;GPS)、携帯情報端末(person
al digital assistant;PD
A)、ページャ等の製品は、いずれも軽薄短小の要求を
有し、ゆえにその各種の部品体積も縮小しなければなら
ない。2. Description of the Related Art During the current mobile communications in the star industry, for example, a cellular phone,
Bluetooth module, mobile network browser, global positioning system (global positioning)
system; GPS), personal digital assistant (person)
al digital assistant; PD
Products such as A) and pagers have requirements of lightness, thinness, shortness, and smallness, and therefore the volume of various parts must be reduced.
【0003】コンデンサは各種の電子製品中にあって必
要な従動素子であり、電容量の計算公式、
C=kε0 A/d
から分かるように、電容量と誘電率、電極面積が正比例
し、誘電層の厚さと反比例し、ゆえにコンデンサの体積
を減少し並びにコンデンサの電容量を増加する方式は、
即ち、誘電定数を高め、電極の表面積を増加し、誘電層
の厚さを減少することである。Capacitors are required driven elements in various electronic products, and as can be seen from the calculation formula of capacitance, C = kε 0 A / d, the capacitance is directly proportional to the dielectric constant and the electrode area, A method that is inversely proportional to the thickness of the dielectric layer and therefore reduces the volume of the capacitor as well as increases the capacitance of the capacitor is
That is, increasing the dielectric constant, increasing the surface area of the electrode, and decreasing the thickness of the dielectric layer.
【0004】図1は、周知の積層セラミックコンデンサ
(MLCC)の断面図であり、それはコンデンサ中に数
層の電極1と誘電層21が増加され、現在行われている
電容量増加の方式は、コンデンサの表面積を増加するの
が主要な方法であり、一般にコンデンサ中にあって積層
の方式でコンデンサ表面積を増加し、その効用は複数の
コンデンサを並列に連接したのに等しい。しかし、積層
数の多さが技術ネックとなっており、コンデンサの体積
を縮小できないだけでなく、コンデンサの容量を増加で
きず、マイクロ構造コンデンサは元来平整な表面をトレ
ンチなどの三次元空間構造に改変してその表面積を増加
しているが、高い深さ幅比の深孔に薄膜を形成する技術
の難度は極めて高く、且つ工程のコストも極めて高い。FIG. 1 is a cross-sectional view of a well-known multilayer ceramic capacitor (MLCC), in which several layers of electrodes 1 and a dielectric layer 21 are added in the capacitor, and the method of increasing the capacitance currently being performed is as follows. The main method is to increase the surface area of the capacitor, and generally, in the capacitor, the surface area of the capacitor is increased in a laminated manner, and its effect is equivalent to connecting a plurality of capacitors in parallel. However, the large number of stacks is a technology bottleneck, not only can the volume of the capacitor be reduced, but also the capacity of the capacitor cannot be increased, and the microstructured capacitor has an originally flat surface with a three-dimensional spatial structure such as a trench. However, the technique of forming a thin film in a deep hole having a high depth-width ratio is extremely difficult, and the process cost is also very high.
【0005】[0005]
【発明が解決しようとする課題】本発明の主要な目的
は、上述の欠点を解決し、上述の欠点の存在を防止する
ことにあり、即ち本発明は一種の積層式マイクロ構造大
容量コンデンサを提供し、それはマイクロ構造の方式で
表面積を増加した構造であるものとする。SUMMARY OF THE INVENTION The main object of the present invention is to solve the above-mentioned drawbacks and prevent the existence of the above-mentioned drawbacks, that is to say that the present invention provides a kind of laminated microstructure high-capacity capacitor. Provided that it is a structure with increased surface area in a microstructured manner.
【0006】本発明のもう一つの目的は、一種の積層式
マイクロ構造大容量コンデンサを提供することにあり、
それは高誘電質を薄膜化したものとする。Another object of the present invention is to provide a kind of laminated microstructure high capacity capacitor,
It is a high dielectric thin film.
【0007】本発明のさらにもう一つの目的は、積層式
マイクロ構造大容量コンデンサを提供することにあり、
それは、適当な幅深さ比で膜形成難度を低くし、しかし
接合技術で容量が減少しないようにした構造であるもの
とする。Yet another object of the present invention is to provide a laminated microstructure high capacity capacitor,
It is assumed that the film formation difficulty is lowered at an appropriate width-depth ratio, but the capacity is not reduced by the bonding technique.
【0008】[0008]
【課題を解決するための手段】請求項1の発明は、電極
基板と、リソグラフィーとエッチング工程で、電極基板
の一面に適当な幅深さ比で形成されたトレンチと、除去
ホトレジスト層と、該電極基板の表面に形成された高誘
電質層と、該高誘電質層の表面に形成された導電材料層
と、で形成されたマイクロ構造大容量コンデンサの基本
組成ユニットが、それぞれの導電材料層で連結されて一
つの単層式マイクロ構造大容量コンデンサが形成され、
複数の単層式マイクロ構造大容量コンデンサが積み重ね
られて、適当な容量を有するものとされたことを特徴と
する、積層式マイクロ構造大容量コンデンサとしてい
る。請求項2の発明は、電極基板と、リソグラフィーと
エッチング工程で、電極基板の二面それぞれに適当な幅
深さ比で形成されたトレンチと、除去ホトレジスト層
と、該電極基板の二面に形成された高誘電質層と、各高
誘電質層の表面に形成された導電材料層と、で形成され
たマイクロ構造大容量コンデンサの基本組成ユニットが
複数組連結されて、適当な容量を有するものとされたこ
とを特徴とする、積層式マイクロ構造大容量コンデンサ
としている。According to a first aspect of the present invention, there is provided an electrode substrate, a trench formed on one surface of the electrode substrate at an appropriate width / depth ratio in a lithography and etching process, a removed photoresist layer, and The basic composition unit of the microstructure large-capacity capacitor formed by the high-dielectric layer formed on the surface of the electrode substrate and the conductive material layer formed on the surface of the high-dielectric layer has respective conductive material layers. Connected to form a single-layer microstructure large-capacity capacitor,
A laminated micro-structure large-capacity capacitor is characterized in that a plurality of single-layer micro-structure large-capacity capacitors are stacked to have an appropriate capacity. According to a second aspect of the present invention, an electrode substrate, a trench formed in each of the two surfaces of the electrode substrate by a lithography and etching process with an appropriate width-depth ratio, a removed photoresist layer, and formed on the two surfaces of the electrode substrate. A plurality of basic composition units of a micro-structure large-capacity capacitor formed by a high-dielectric layer formed by the above and a conductive material layer formed on the surface of each high-dielectric layer, and having an appropriate capacitance The laminated microstructure large-capacity capacitor is characterized in that
【0009】[0009]
【発明の実施の形態】本発明は一種の積層式マイクロ構
造大容量コンデンサを提供し、それは、リソグラフィー
とエッチングの方式により、電極基板に適当な幅深さ比
のトレンチを形成した後、ホトレジスト層を除去した後
に、順に高誘電質層と導電材料層を形成し、これにより
マイクロ構造大容量コンデンサの基本組成ユニットを形
成し、二組の基本組成ユニットの導電材料層を相互に連
結させて一つの単層式マイクロ構造大容量コンデンサを
形成し、複数組の単層式マイクロ構造大容量コンデンサ
を堆積連結して積層式マイクロ構造大容量コンデンサと
なす。一つの電極基板の二面に上述のステップでマイク
ロ構造大容量コンデンサの基本組成ユニットを形成し、
複数のマイクロ構造大容量コンデンサの基本組成ユニッ
トを連結して積層式マイクロ構造大容量コンデンサを形
成することにより、表面積を増加でき、高誘電質薄膜化
が行え、且つ容量を減少しない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a kind of laminated micro-structure high-capacity capacitor, which comprises forming a trench having a proper width-depth ratio in an electrode substrate by a method of lithography and etching, and then forming a photoresist layer. Then, a high-dielectric layer and a conductive material layer are sequentially formed to form a basic composition unit of the microstructure large-capacity capacitor, and the conductive material layers of the two basic composition units are connected to each other to form a single layer. One single-layer microstructure large-capacity capacitor is formed, and a plurality of sets of single-layer microstructure large-capacity capacitors are deposited and connected to form a laminated microstructure large-capacity capacitor. The basic composition unit of the microstructure large-capacity capacitor is formed on the two surfaces of one electrode substrate by the above steps,
By forming a laminated micro-structure large-capacity capacitor by connecting basic composition units of a plurality of micro-structure large-capacity capacitors, it is possible to increase the surface area, achieve a high dielectric thin film, and not reduce the capacity.
【0010】[0010]
【実施例】図2から図7は本発明の積層式マイクロ構造
大容量コンデンサの製造フロー断面図であり、厚さ0.
02〜0.5mmのn形シリコン、p形シリコン或いは
金、銅金属電極基板1の一面にあって、リソグラフィー
工程で、該電極基板1上に適当なパターンのホトレジス
ト層4を形成し、エッチング工程で電極基板1上に、電
化学エッチング、ウエットエッチング或いはドライエッ
チングにより幅0.002〜0.1mm、深さ0.00
2〜0.5mm、幅深さ比が1:1〜1:50の適当な
トレンチを形成し、該ホトレジスト層4を除去した後、
PVD法或いはCVD法で順に、厚さ10〜500nm
の高誘電質層22と厚さ100〜2000nmの導電材
料層3を電極基板1の表面に形成し、即ち一つのマイク
ロ構造大容量コンデンサの基本組成ユニット51を形成
し、二組のマイクロ構造大容量コンデンサの基本組成ユ
ニットの導電材料層3をウエハーボンディング技術で連
結して一つの単層式マイクロ構造大容量コンデンサ6を
形成し、複数の単層式マイクロ構造大容量コンデンサを
堆積した後、金属高温接合で連結し、積層式マイクロ構
造大容量コンデンサ7を得る。2 to 7 are sectional views showing the manufacturing flow of a laminated microstructure large-capacity capacitor according to the present invention.
A photoresist layer 4 having an appropriate pattern is formed on the electrode substrate 1 by a lithography process on one surface of the n-type silicon, p-type silicon or gold or copper metal electrode substrate 1 having a thickness of 02 to 0.5 mm, and an etching process is performed. Then, a width of 0.002 to 0.1 mm and a depth of 0.002 are formed on the electrode substrate 1 by electrochemical etching, wet etching or dry etching.
After forming an appropriate trench having a width-depth ratio of 2 to 0.5 mm and a width-to-depth ratio of 1: 1 to 1:50 and removing the photoresist layer 4,
The thickness is 10 to 500 nm in order by PVD method or CVD method.
The high dielectric layer 22 and the conductive material layer 3 having a thickness of 100 to 2000 nm are formed on the surface of the electrode substrate 1, that is, the basic composition unit 51 of one microstructure large capacity capacitor is formed, and two sets of microstructure large size are formed. The conductive material layer 3 of the basic composition unit of the capacitive capacitor is connected by a wafer bonding technique to form one single-layer type microstructure large-capacity capacitor 6, and after depositing a plurality of single-layer type microstructure large-capacity capacitors, The layers are connected by high temperature bonding to obtain the laminated microstructure large capacity capacitor 7.
【0011】積層式マイクロ構造大容量コンデンサ7の
高誘電質層22は、その材質が、バリウムストロンチウ
ムチタン酸塩(BaX Sr1-X TiO3 ,X =0〜1;
BST)、タンタル酸化物、チタン酸化物、鉛ジルコニ
ウムチタン酸塩(Pb(Zr,Ti)O3 ;PZT)、
鉛ランタンジルコニウムチタン酸塩((Pb,La)
(Zr,Ti)O3 ;PLZT)、ストロンチウムビス
マスタンタル酸塩(SrBi2 Ta2 O9 ;SBT)、
ダイヤモンド、類ダイヤモンドより選択され、積層式マ
イクロ構造大容量コンデンサ7の導電材料層はアルミニ
ウム、白金、ルテニウム、チタン、タングステンのいず
れかとされる。The material of the high dielectric layer 22 of the laminated microstructure large capacity capacitor 7 is barium strontium titanate (Ba X Sr 1-X TiO 3 , X = 0 to 1;
BST), tantalum oxide, titanium oxide, lead zirconium titanate (Pb (Zr, Ti) O 3 ; PZT),
Lead lanthanum zirconium titanate ((Pb, La)
(Zr, Ti) O 3 ; PLZT), strontium bismastantalate (SrBi 2 Ta 2 O 9 ; SBT),
The conductive material layer of the laminated microstructure large-capacity capacitor 7 is selected from diamond and diamonds, and is made of aluminum, platinum, ruthenium, titanium, or tungsten.
【0012】図8に示されるのは、本発明のもう一つの
応用例の断面図であり、電極基板1の二面それぞれにあ
って、リソグラフィーとエッチング工程で、幅0.00
2〜0.1mm、深さ0.002〜0.5mm、幅深さ
比が1:1〜1:50の適当なトレンチを形成し、PV
D法或いはCVD法で順に、厚さ10〜500nmの高
誘電質層22と厚さ100〜2000nmの導電材料層
3を電極基板1の表面に形成し、即ち一つのマイクロ構
造大容量コンデンサの基本組成ユニット52を形成し、
二組のマイクロ構造大容量コンデンサの基本組成ユニッ
ト52の単層式マイクロ構造大容量コンデンサを堆積後
に、金属高温接合連結し、積層式マイクロ構造大容量コ
ンデンサ7を得る。FIG. 8 is a cross-sectional view of another application example of the present invention, in which the width 0.00
2 to 0.1 mm, a depth of 0.002 to 0.5 mm, and a width / depth ratio of 1: 1 to 1:50 are formed in an appropriate trench, and PV is formed.
A high dielectric layer 22 having a thickness of 10 to 500 nm and a conductive material layer 3 having a thickness of 100 to 2000 nm are sequentially formed on the surface of the electrode substrate 1 by the D method or the CVD method, that is, the basic of one microstructure large capacity capacitor. Forming the composition unit 52,
After depositing the single-layer microstructure large-capacity capacitors of the basic composition unit 52 of the two sets of microstructure large-capacity capacitors, metal high-temperature bonding connection is performed to obtain the laminated microstructure large-capacity capacitor 7.
【0013】以上の実施例は本発明の説明するためのも
ので本発明の請求範囲を限定するものではなく、本発明
に基づきなしうる細部の修飾或いは改変は、いずれも本
発明の請求範囲に属するものとする。The above examples are for the purpose of explaining the present invention and are not intended to limit the scope of the claims of the present invention, and any modifications or changes in details that can be made based on the present invention are within the scope of the claims of the present invention. Shall belong.
【0014】[0014]
【発明の効果】本発明によると、リソグラフィーとエッ
チングの方式により、電極基板に適当な幅深さ比のトレ
ンチを形成した後、順に高誘電質層と導電材料層を形成
し、これによりマイクロ構造大容量コンデンサの基本組
成ユニットを形成し、二組の基本組成ユニットの導電材
料層を相互に連結させて一つの単層式マイクロ構造大容
量コンデンサを形成し、複数組の単層式マイクロ構造大
容量コンデンサを堆積連結して積層式マイクロ構造大容
量コンデンサとなす。一つの電極基板の二面に上述のス
テップでマイクロ構造大容量コンデンサの基本組成ユニ
ットを形成し、複数のマイクロ構造大容量コンデンサの
基本組成ユニットを連結して積層式マイクロ構造大容量
コンデンサを形成することにより、表面積を増加でき、
高誘電質薄膜化が行え、且つ容量を減少しない。According to the present invention, a trench having an appropriate width-depth ratio is formed in an electrode substrate by a lithography and etching method, and then a high dielectric layer and a conductive material layer are sequentially formed. The basic composition unit of the large-capacity capacitor is formed, and the conductive material layers of the two sets of basic composition units are interconnected to form one single-layer microstructure large-capacity capacitor. Capacitors are stacked and connected to form a laminated microstructure large capacity capacitor. The basic composition unit of the micro-structure large-capacity capacitor is formed on the two surfaces of one electrode substrate by the steps described above, and the basic composition unit of the plurality of micro-structure large-capacity capacitors is connected to form the laminated micro-structure large-capacity capacitor. By doing so, the surface area can be increased,
A high dielectric thin film can be formed and the capacity is not reduced.
【図1】周知の積層セラミックコンデンサの断面図であ
る。FIG. 1 is a cross-sectional view of a known monolithic ceramic capacitor.
【図2】本発明の積層式マイクロ構造大容量コンデンサ
の製造フロー断面図である。FIG. 2 is a manufacturing flow sectional view of the laminated microstructure large capacity capacitor of the present invention.
【図3】本発明の積層式マイクロ構造大容量コンデンサ
の製造フロー断面図である。FIG. 3 is a manufacturing flow sectional view of a laminated microstructure large capacity capacitor of the present invention.
【図4】本発明の積層式マイクロ構造大容量コンデンサ
の製造フロー断面図である。FIG. 4 is a manufacturing flow sectional view of a laminated microstructure large capacity capacitor of the present invention.
【図5】本発明の積層式マイクロ構造大容量コンデンサ
の製造フロー断面図である。FIG. 5 is a manufacturing flow sectional view of the laminated microstructure large capacity capacitor of the present invention.
【図6】本発明の積層式マイクロ構造大容量コンデンサ
の製造フロー断面図である。FIG. 6 is a manufacturing flow sectional view of a laminated microstructure large capacity capacitor of the present invention.
【図7】本発明の積層式マイクロ構造大容量コンデンサ
の製造フロー断面図である。FIG. 7 is a manufacturing flow sectional view of a laminated microstructure large capacity capacitor of the present invention.
【図8】本発明のもう一つの応用例の断面図である。FIG. 8 is a cross-sectional view of another application example of the present invention.
1 電極 21 誘電層 22 高誘電質層 3 導電材料層 4 ホトレジスト層 51 基本組成ユニット 52 基本組成ユニット 6 単層式マイクロ構造大容量コンデンサ 7 積層式マイクロ構造大容量コンデンサ 1 electrode 21 Dielectric layer 22 High dielectric layer 3 Conductive material layer 4 Photoresist layer 51 Basic composition unit 52 Basic composition unit 6 Single Layer Micro Structure Large Capacitor 7 Laminated Micro Structure Large Capacitance Capacitor
───────────────────────────────────────────────────── フロントページの続き (72)発明者 黄 戎巖 台湾桃園縣中▲れき▼市中堅里台貿十村 114號 Fターム(参考) 5E082 AA01 AB03 BC39 EE14 EE15 EE26 EE45 FG03 FG26 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Huang Jian Taiwan Taoyuan 縣 中 ▲ Reki ▼ City Nakasatodai Trade Ten Village 114 F-term (reference) 5E082 AA01 AB03 BC39 EE14 EE15 EE26 EE45 FG03 FG26
Claims (2)
適当な幅深さ比で形成されたトレンチと、 除去ホトレジスト層と、 該電極基板の表面に形成された高誘電質層と、 該高誘電質層の表面に形成された導電材料層と、 で形成されたマイクロ構造大容量コンデンサの基本組成
ユニットが、それぞれの導電材料層で連結されて一つの
単層式マイクロ構造大容量コンデンサが形成され、複数
の単層式マイクロ構造大容量コンデンサが積み重ねられ
て、適当な容量を有するものとされたことを特徴とす
る、積層式マイクロ構造大容量コンデンサ。1. An electrode substrate, a trench formed in one surface of the electrode substrate by lithography and etching with an appropriate width-depth ratio, a removed photoresist layer, and a high dielectric constant formed on the surface of the electrode substrate. Layer and a conductive material layer formed on the surface of the high dielectric layer, and a basic structure unit of a microstructure large-capacity capacitor formed by A laminated microstructure large-capacity capacitor, characterized in that a large-capacity capacitor is formed and a plurality of single-layer microstructure large-capacity capacitors are stacked to have an appropriate capacity.
れぞれに適当な幅深さ比で形成されたトレンチと、 除去ホトレジスト層と、 該電極基板の二面に形成された高誘電質層と、 各高誘電質層の表面に形成された導電材料層と、 で形成されたマイクロ構造大容量コンデンサの基本組成
ユニットが複数組連結されて、適当な容量を有するもの
とされたことを特徴とする、積層式マイクロ構造大容量
コンデンサ。2. An electrode substrate, a trench formed on the two surfaces of the electrode substrate at a suitable width / depth ratio by lithography and etching, a photoresist layer removed, and a trench formed on the two surfaces of the electrode substrate. A high dielectric layer, a conductive material layer formed on the surface of each high dielectric layer, and a plurality of basic composition units of a microstructure large-capacity capacitor formed by are connected to each other to have an appropriate capacitance. This is a laminated micro-structured large-capacity capacitor.
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JP2001211897A JP2003045739A (en) | 2001-07-12 | 2001-07-12 | Large capacitance capacitor of laminated micro-structure |
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Family
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100568306B1 (en) | 2004-07-23 | 2006-04-05 | 삼성전기주식회사 | Thin film type multi-layered ceramic capacitor and method of producing the same |
JP2009010371A (en) * | 2007-06-26 | 2009-01-15 | Headway Technologies Inc | Capacitor and method of manufacturing the same, and capacitor unit |
JP2015111671A (en) * | 2013-11-22 | 2015-06-18 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | Integrated capacitor and method for producing the same |
JPWO2017026233A1 (en) * | 2015-08-10 | 2018-05-24 | 株式会社村田製作所 | Capacitor |
WO2018174191A1 (en) * | 2017-03-24 | 2018-09-27 | 株式会社村田製作所 | Capacitor |
-
2001
- 2001-07-12 JP JP2001211897A patent/JP2003045739A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100568306B1 (en) | 2004-07-23 | 2006-04-05 | 삼성전기주식회사 | Thin film type multi-layered ceramic capacitor and method of producing the same |
JP2009010371A (en) * | 2007-06-26 | 2009-01-15 | Headway Technologies Inc | Capacitor and method of manufacturing the same, and capacitor unit |
JP2013065902A (en) * | 2007-06-26 | 2013-04-11 | Headway Technologies Inc | Capacitor and method of manufacturing the same, and capacitor unit |
JP2015111671A (en) * | 2013-11-22 | 2015-06-18 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | Integrated capacitor and method for producing the same |
US9455151B2 (en) | 2013-11-22 | 2016-09-27 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Integrated capacitor and method for producing the same |
JPWO2017026233A1 (en) * | 2015-08-10 | 2018-05-24 | 株式会社村田製作所 | Capacitor |
WO2018174191A1 (en) * | 2017-03-24 | 2018-09-27 | 株式会社村田製作所 | Capacitor |
JPWO2018174191A1 (en) * | 2017-03-24 | 2019-11-07 | 株式会社村田製作所 | Capacitors |
US10879347B2 (en) | 2017-03-24 | 2020-12-29 | Murata Manufacturing Co., Ltd. | Capacitor |
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