KR100957763B1 - Thin film multi-layered ceramic capacitor and method of fabricating the same - Google Patents

Abstract

A thin film multilayer ceramic capacitor and a method of manufacturing the same are disclosed. The thin film type multilayer ceramic capacitor according to the present invention includes a substrate having an upper surface on which a plurality of holes are formed, between three or more electrode films sequentially stacked from the upper surface of the substrate along the holes, and between two adjacent electrode films. The capacitor layer including a thin film capacitor made of a dielectric film includes a multilayer structure in which two or more layers are stacked. The electrode films of the respective capacitor layers are alternately connected to the first external electrode and the second external electrode. According to the present invention, by increasing the surface area of the thin film capacitor using the hole, the capacitance is increased as compared to the capacitor of the planar structure, and further, by implementing two or more layers of the thin film capacitor on the hole, it is possible to reduce the number of stacked layers in the laminated structure. Therefore, it is possible to provide a thin-film multilayer ceramic capacitor that can be miniaturized while having a higher capacitance.

Description

Thin film multi-layered ceramic capacitor and method of fabricating the same

1 is a cross-sectional view showing a conventional thin film multilayer ceramic capacitor.

2 is a cross-sectional view of a thin film multilayer ceramic capacitor according to a first embodiment of the present invention.

3A to 3I are cross-sectional views illustrating a method of manufacturing a capacitor layer included in a thin film multilayer ceramic capacitor according to a first embodiment of the present invention.

4A and 4B illustrate a lamination process for completing a thin film multilayer ceramic capacitor according to a first embodiment of the present invention.

5 is a cross-sectional view of a thin film multilayer ceramic capacitor according to a second exemplary embodiment of the present invention.

6A through 6H are cross-sectional views illustrating a method of manufacturing a capacitor layer included in a thin film multilayer ceramic capacitor according to a second exemplary embodiment of the present invention.

7A to 7C illustrate a lamination process for completing a thin film multilayer ceramic capacitor according to a second embodiment of the present invention.

<Code Description of Main Parts of Drawing>

100 ... substrate 101 ... top

105 ... hole 110, 110a, 114, 114a, 118, 118a ... electrode film

112, 116 dielectric film 130, 130a thin film capacitor

140, 140a, 140b, 140c, 140d, 140e, 140f ... capacitor layer

142, 164 Passivation layer 144 Dielectric spacer

150, 152 ... first contact plug 154 ... second contact plug

160 ... first wiring 162 ... second wiring

170 ... Adhesive G ... Polishing Process

180, 180a ... Multilayer structure 182, 182a ... First external electrode

184, 184a ... Second external electrode 190, 190a ... Thin film multilayer ceramic capacitor

The present invention relates to a thin-layered multilayer ceramic capacitor (MLCC), and more particularly, to a thin-film MLCC capable of miniaturization while ensuring high capacitance and a manufacturing method thereof.

In general, a MLCC is a chip capacitor having a structure in which a plurality of dielectric layers printed with electrodes are stacked, and is widely used in various electronic products. Recently, as the market for mobile communication devices and portable electronic devices expands, the demand for miniaturization and large capacity for MLCC products is increasing.

The conventional MLCC is manufactured by stacking a plurality of green sheets coated with electrode paste to form a multilayer structure, and forming electrodes on both sides of the multilayer structure. Through such a bulk process, there is a limit in miniaturizing and enlarging the MLCC.

In order to solve such a problem, researches to introduce a semiconductor thin film process are actively conducted in the MLCC field. For example, Japanese Patent Laid-Open No. 2001-181839 uses a thin film type to deposit a (Ba, Sr) TiO ₃ (hereinafter referred to as BST) film having a high dielectric constant by using metal organic chemical vapor deposition (MOCVD). MLCC manufacturing methods have been proposed. 1 is a cross-sectional view of a conventional thin film MLCC that can be manufactured by this technique.

As shown in FIG. 1, the conventional thin film type MLCC includes a plurality of Pt electrode films 12 and 16 and a plurality of BST dielectric films 14 formed on a substrate 11 such as MgO. The MLCC may be manufactured by forming an electrode film and a dielectric film through a plurality of sputtering processes and a MOCVD process, respectively, and then patterning each film as shown in FIG. 1 through a photolithography process and an etching process.

However, since the conventional thin film MLCC is formed on the upper surface of the limited substrate in plan view, the effective area for substantially determining the capacitance is inevitably limited. Therefore, in order to secure a higher capacitance, the number of laminations must be increased, resulting in an increase in photolithography and etching processes, which complicates the entire process.

As such, the conventional thin film type MLCC has a limitation in securing a high capacitance of 10 ㎌ or more, which is required due to limitations due to the flat plate structure.

In another prior art, US Patent No. 6,421,224 discloses a microcapacitor using a silicon on insulator (SOI) substrate. According to this document, a microcapacitor having a three-dimensional structure is formed by using an insulating layer as an etching stop in an SOI substrate to provide uniform porosity to upper and lower silicon layers, and forming a dielectric film and a metal film on the etched upper and lower surfaces. To provide. In addition, by stacking such a microcapacitor structure, it is possible to provide a capacitor which is miniaturized and has high capacitance characteristics. The microcapacitor has an effect of increasing the surface area using a porous structure and securing a high capacitance by implementing a laminated structure, but there is an insulating layer used as a residual silicon layer and an etch stop layer in addition to the dielectric film between the upper and lower electrodes. Therefore, there is a risk of deteriorating the capacitor characteristics, and there is a problem in that the input / output terminal configuration is complicated in the laminated structure.

In contrast, U.S. Patent No. 6,503,791 uses a method of forming a thin film structure capacitor on a surface where holes are formed by forming holes as a method of constituting a memory cell in a semiconductor device. It is only proposed as a cell structure and is not provided as a method of manufacturing a high capacity single capacitor product such as MLCC.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a thin film type multilayer ceramic capacitor which can be miniaturized while having a higher capacitance.

Another object of the present invention is to provide a method of manufacturing the thin film multilayer ceramic capacitor using a semiconductor thin film process.

In order to achieve the above object, a thin-film multilayer ceramic capacitor according to the present invention, a substrate having a top surface with a plurality of holes, three or more electrode films sequentially stacked from the upper surface of the substrate along the hole and adjacent to each other A multilayer structure includes two or more capacitor layers including a thin film capacitor made of a dielectric film interposed between two electrode films. The electrode film of each capacitor layer is alternately connected to the first external electrode and the second external electrode.

In the first embodiment, the first external electrode is connected to the electrode film by a first contact plug that is connected to the electrode film while passing through the thin film capacitor, and the second external electrode is the thin film capacitor. The electrode film is connected to the electrode film through a second contact plug connected to an electrode film which is not connected to the first contact plug.

In the second embodiment, the stacking form of the electrode film of each capacitor layer is alternately stacked with a first electrode film extending on one side of the substrate and a second electrode film extending on the other side opposite to the one side. The first external electrode is formed on one side of the multilayer structure and connected to the first electrode film, and the second external electrode is formed on the other side of the multilayer structure and connected to the second electrode film. It is. Here, preferably, stepped portions are formed on both side surfaces of the substrate so that the first and second external electrodes are more firmly attached. Further, the plurality of holes may be formed to have a constant depth, in this case, the stepped portion may be formed to have substantially the same height as the bottom surface of the hole.

In addition, in order to protect the thin film capacitor and improve the flatness of the upper surface, a passivation layer having a flat upper surface on the upper surface of the thin film capacitor may be further included.

The holes employed in the thin-film multilayer ceramic capacitor according to the present invention are to increase the surface area of the upper surface of the substrate, and are formed in various shapes such as hemispherical grain structure, fin hole or cylinder type. Can be.

However, in order to increase the surface area increase rate, it is preferable that the hole has an aspect ratio of 1 or more and an aspect ratio of 50 or less in consideration of the limit of the coverage on the inner surface of the hole when forming the electrode film or the dielectric film. That is, the plurality of holes preferably have an aspect ratio of 1 to 50 in each hole.

The electrode film is at least one metal selected from the group consisting of Pt, Ru, Ir, Au, Ni, Mo, W, Al, Ta, Ag and Ti or Pt, Ru, Sr, La, Ir, Au, Ni, Co, It may be formed of a conductive oxide or a conductive nitride of at least one metal selected from the group consisting of Mo, W, Al, Ta and Ti.

In addition, the dielectric film may be formed of TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , HfO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) TiO ₃ , PbTiO 3, SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ and Pb (Zr, Ti) O ₃ It may be formed of one or more high dielectric constant material selected from the group consisting of or a material added dopant thereto.

Furthermore, two or more capacitor layers constituting the multilayer structure may be bonded using a thermosetting adhesive, an ultraviolet curing adhesive, and a mixture thereof, and in the case of using a thermosetting adhesive, considering the deterioration of the dielectric film due to high temperature, the temperature may be 100 ° C. or lower. Preference is given to using adhesives curable at.

In addition, in order to achieve the above object, the present invention also provides a method of manufacturing a thin-film multilayer ceramic capacitor, which method comprises a substrate having an upper surface formed with a plurality of holes, and sequentially from the upper surface of the substrate along the hole Forming at least two capacitor layers including thin film capacitors composed of three or more electrode films stacked thereon and a dielectric film interposed between two adjacent electrode films; Forming a multi-layer structure by laminating upper and lower surfaces of the two or more capacitor layers to be bonded to each other; And alternately connecting the electrode films of the respective capacitor layers to the first external electrode and the second external electrode.

In the first embodiment, the connecting of the first external electrode and the second external electrode may include: forming a first contact plug that passes through the thin film capacitor and is alternately connected to the electrode films of the respective capacitor layers. ; Forming the first external electrode by connecting to the first contact plug; Forming a second contact plug penetrating the thin film capacitor and connected to an electrode film not connected to the first contact plug of each of the capacitor layers; And forming the second external electrode by connecting to the second contact plug.

The method of claim 2, wherein the electrode film comprises: forming a first electrode film extending on one side of the substrate by patterning the electrode material after deposition; And patterning after electrode material deposition to sequentially form a second electrode film extending on the other side of the substrate. The first external electrode is formed on one side of the multilayer structure and connected to the first electrode film, and the second external electrode is formed on the other side of the multilayer structure and connected to the second electrode film.

In the method according to the present invention, it is preferable that the electrode film and the dielectric film are obtained by depositing by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Forming a passivation layer on upper and side surfaces of the plurality of capacitors, and after forming the multilayer structure, before forming the first and second external electrodes, the one side and the other of the electrode films The method may further include selectively removing the passivation layer to expose the side portion.

If necessary, in the step of forming the two or more capacitor layers, in order to further reduce the size of the final product, the step of polishing the lower surface of the substrate to further reduce the thickness of the capacitor layer can be carried out.

 Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings illustrating embodiments of the present invention, like numerals in the drawings refer to like elements.

2 is a cross-sectional view of a thin film multilayer ceramic capacitor according to a first embodiment of the present invention.

Referring to FIG. 2, the thin film type multilayer ceramic capacitor 190 according to the first exemplary embodiment includes a multilayer structure 180 in which two or more capacitor layers are stacked. In this embodiment, an example in which three capacitor layers 140a, 140b, and 140c are stacked is shown. However, two or more capacitor layers may be used depending on the required capacitance and the allowable product size. Each capacitor layer 140a, 140b, 140c is held laminated by the adhesive 170. The adhesive 170 may be a thermosetting adhesive, an ultraviolet curing adhesive, or a mixture thereof.

Looking at the configuration of each capacitor layer (140a, 140b, 140c), first, the substrate 100 having a top surface 101, a plurality of holes 105 are formed, and the upper surface of the substrate 100 along the hole 105 And a thin film capacitor 130 comprising three electrode layers 110, 114 and 118 sequentially stacked from the dielectric layers 112 and 116 interposed between two adjacent electrode layers. The electrode films 110, 114, 118 are at least one metal selected from the group consisting of Pt, Ru, Ir, Au, Ni, Mo, W, Al, Ta, Ag and Ti or Pt, Ru, Sr, La, Ir It may be formed of a conductive oxide or a conductive nitride of at least one metal selected from the group consisting of Au, Ni, Co, Mo, W, Al, Ta and Ti. Hereinafter, for convenience, the three electrode layers 110, 114, and 118 will be referred to as a lower electrode layer 110, an intermediate electrode layer 114, and an upper electrode layer 118, respectively. The dielectric films 112 and 116 include TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , HfO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) TiO ₃ , PbTiO 3, SrBi ₂ It may be formed of at least one high dielectric constant material selected from the group consisting of Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ and Pb (Zr, Ti) O ₃ or a material to which a dopant is added thereto. For example, a single film made of (Ba, Sr) TiO ₃ may be used, or a double film of Al ₂ O ₃ / HfO ₂ may be used. Or a film in which Hf is added as a dopant to Al ₂ O ₃ or a film in which Hf is added as a dopant to TiO ₂ . Instead, the dielectric films 112 and 116 may be laminated films of SiO ₂ and Si ₃ N ₄ .

The hole 105 formed in the substrate 100 is used to increase the surface area of the upper surface 101 of the substrate 100. The hole 105 is formed in various shapes such as a hemispherical grain structure, a fin hole, or a cylinder type. It may be formed in a shape. However, in order to increase the surface area increase rate, the aspect ratio of the hole 105 is formed to be 1 or more, and when the electrode film 110, 114, 118 or the dielectric film 112, 116 is formed, the aspect ratio of the hole 105 is increased. In consideration of the limit of coating property, it is preferable to form an aspect ratio of 50 or less.

The passivation layers 142 and 164 are formed on the upper surfaces of the capacitor layers 140a, 140b and 140c, and the electrode films 110, 114 and 118 of the capacitor layers 140a, 140b and 140c are alternated. The first external electrode 182 and the second external electrode 184 are connected to each other. The first external electrode 182 and the second external electrode 184 connect the thin film capacitors 130 formed in the capacitor layers 140a, 140b, and 140c in parallel to have opposite polarities.

In detail, the lower electrode layer 110 and the upper electrode layer 118 of the electrode layers 110, 114, and 118 of the capacitor layers 140a, 140b, and 140c may be connected to the first contact plugs 150 and 152. The intermediate electrode layer 114 of the electrode layers 110, 114, and 118 of each of the capacitor layers 140a, 140b, and 140c is connected to the second contact plug 154 by the first wiring 160. The second wiring 162 is connected to the second wiring 162. The first wiring 160 of each of the capacitor layers 140a, 140b, and 140c is connected to a first external electrode 182 formed on one side of the multilayer structure 180, and each of the capacitor layers 140a, The second wires 162 of the 140b and 140c are connected to the second external electrode 184 formed on the other side of the multilayer structure 180. As a result, the first external plug 182 penetrates the thin film capacitor 130 and is alternately connected to the electrode films 110, 114, and 118 of the capacitor layers 140a, 140b, and 140c, respectively. (150, 152) are connected to the electrode film (110, 118) of each of the capacitor layers (140a, 140b, 140c), the second external electrode 184 penetrates through the thin film capacitor 130 Second contact plugs 154 connected to the electrode films 114 that are not connected to the first contact plugs 150 and 152 among the electrode films 110, 114, and 118 of the capacitor layers 140a, 140b, and 140c, respectively. Are connected to the electrode films 114 of the capacitor layers 140a, 140b, and 140c. Reference numeral 144 denotes a dielectric spacer for insulating an electrode film other than the electrode film connected to each contact plug 150, 152, 154.

However, the electrode connection structure shown is merely an example, and the electrode films 110, 114, and 118 of the respective capacitor layers 140a, 140b, and 140c without using the first and second wires 160 and 162 may be used. ) Is also directly connected to the first and second external electrodes 182 and 184 alternately.

In the thin film multilayer ceramic capacitor 190 shown in FIG. 2, each of the capacitor layers 140a, 140b, 140c comprises three electrode films 110, 114, 118 and two dielectric films 112, 116. In this case, the two-layer thin film capacitor is actually formed on the hole 105. However, in the present invention, the electrode film of each capacitor layer can be formed in three or more layers. Therefore, the present invention includes the n + 1 layer electrode film and the n layer dielectric film, so that the n-layer thin film capacitor is actually a hole. It will correspond to the stacked structure (where n is a natural number of 2 or more). For example, if the size of the hole 105 is 3 μm and each film such as the electrode films 110, 114, and 118 and the dielectric films 112 and 116 is laminated to a thickness of 100 μs, the film may be completely filled up to the hole 105. 15 layers can be stacked in total, and this is a calculation that the thin film capacitor can be 7 layers because the electrode film corresponds to 8 layers and the dielectric film corresponds to 7 layers. By increasing the surface area of the thin film capacitor by using the holes, the capacitance is increased as compared to the capacitor of the planar structure, and further, by implementing two or more layers of the thin film capacitor on the hole, the number of stacked layers in the stacked structure 180 can be reduced. Therefore, it is possible to provide a thin-film multilayer ceramic capacitor that can be miniaturized while having a higher capacitance.

Conventionally, the surface area of a thin film capacitor is increased by using a hole, but since only one layer of a thin film capacitor is implemented on the hole, in order to increase the capacitance in such a structure, the number of stacks in the stack structure may be increased or the cost may be increased. By changing the lithography, the hole size can be reduced to increase the surface area. However, in the present invention, since the electrode film and the dielectric film constituting the thin film capacitor are thinned to implement two or more thin film capacitors on the hole, the desired capacitance can be sufficiently obtained even if the number of stacked layers in the laminated structure is small. There is no need to change expensive photolithography processes. For example, if a desired capacitance can be achieved by stacking 50 layers of capacitor layers having one layer of thin film capacitors on a hole, in the present invention, the thin film capacitors are formed on the holes by further thinning each film constituting the capacitor. In a layer implementation, stacking ten such capacitor layers can achieve the same capacitance as before, while dramatically reducing the size of the device. In addition, as the thickness of each film constituting the capacitor decreases, the capacitance of a single capacitor increases as compared to the existing capacitor.

3A to 3I are cross-sectional views illustrating a method of manufacturing a capacitor layer included in a thin film multilayer ceramic capacitor as shown in FIG. 2.

First, a method of manufacturing a capacitor layer included in a thin film multilayer ceramic capacitor according to a first embodiment of the present invention as shown in FIG. 3A starts with forming a plurality of holes 105 on an upper surface 101 of a substrate 100. . The plurality of holes 105 may have various shapes as a means for increasing the surface area of the upper surface of the substrate 100 and may be easily formed using a selective etching process used in a semiconductor process. For example, the hole 105 may have a hemispherical grain structure, a pin shape or a cylinder shape. The hole 105 employed in this embodiment is formed into a cylindrical shape having the same depth by using anisotropic etching. Further, in order to sufficiently increase the surface area, each hole 105 is formed to have an aspect ratio of 1 or more, but in order to ensure uniform covering of the inner surface of the hole 105, the aspect ratio is preferably 50 or less. The substrate 100 employed in the present embodiment may be a silicon substrate generally used in a semiconductor process, but is not limited thereto and may be suitably used in the present invention as long as it is a non-conductive substrate that can be processed by a semiconductor process.

Subsequently, as shown in FIG. 3B, the lower electrode layer 110 is formed on the upper surface 101 of the substrate 100 as the first electrode layer. The lower electrode film 110 forming process may be performed by a semiconductor film forming process such as CVD or ALD including MOCVD.

Since the deposition process is excellent in step coverage, the lower electrode layer 110 may be deposited as a film having a desired uniform thickness up to an inner surface of the plurality of holes 105. In addition, the material used for the lower electrode layer 110 is not limited thereto, but may include at least one selected from the group consisting of Pt, Ru, Ir, Au, Ni, Mo, W, Al, Ta, Ag, and Ti. Conductive oxides or nitrides of a metal or at least one metal selected from the group consisting of Pt, Ru, Sr, La, Ir, Au, Ni, Co, Mo, W, Al, Ta and Ti may be used. In addition, the formation method may be different according to the selected film. For example, in the case of selecting and depositing Ru as the lower electrode film 110, the substrate 100 is first thermally oxidized to form a thin thermal oxide film. It may be by a method of depositing Ru after depositing a Ta ₂ O ₅ film to increase the adhesion of Ru.

Next, as shown in FIG. 3C, the first dielectric layer 112 is formed on the lower electrode layer 110 positioned on the upper surface 101 of the substrate 100. The present process may be performed by a semiconductor film forming process such as CVD or ALD including MOCVD, similarly to the process of forming the lower electrode film 110.

Examples of the material used for the first dielectric film 112 include TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , HfO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) At least one high dielectric constant material selected from the group consisting of TiO ₃ , PbTiO 3, SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, and Pb (Zr, Ti) O ₃ or a dopant-added material It can be formed as. If necessary, before the first dielectric film 112 is formed, plasma nitridation or thermal nitridation using NH ₃ gas may be performed on the surface of the lower electrode film 110. By this treatment, a silicon nitride film having a thickness of about 10-20 μs may be formed on the surface of the lower electrode film 110, which prevents a reaction that may occur between the lower electrode film 110 and the first dielectric film 112. In addition, if necessary, an annealing process may be added after the formation of the first dielectric film 112.

Subsequently, as shown in FIG. 3D, the intermediate electrode layer 114 is formed on the upper surface of the first dielectric layer 112 to form the lower electrode layer 110, the first dielectric layer 112, and the intermediate electrode layer 114. A thin film capacitor of one layer is obtained first. The process of forming the intermediate electrode layer 114 may be performed by a semiconductor deposition process such as CVD or ALD including MOCVD, similarly to the process of forming the lower electrode layer 110, but is not limited thereto. At least one metal selected from the group consisting of Ir, Au, Ni, Mo, W, Al, Ta, Ag and Ti or Pt, Ru, Sr, La, Ir, Au, Ni, Co, Mo, W, Al, Ta And conductive oxides or conductive nitrides of at least one metal selected from the group consisting of Ti.

 Next, as shown in FIG. 3E, a second dielectric film 116 is formed on the intermediate electrode film 114. The present process may be performed by a semiconductor film forming process such as CVD or ALD including MOCVD, similarly to the process of forming the first dielectric film 112.

As the material used for the second dielectric film 116, TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , HfO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) At least one high dielectric constant material selected from the group consisting of TiO ₃ , PbTiO 3, SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, and Pb (Zr, Ti) O ₃ or a dopant-added material It can be formed as. If necessary, a plasma nitridation treatment or a thermal nitridation treatment for the intermediate electrode film 114 and an annealing process for the second dielectric film 116 may be added.

Next, as shown in FIG. 3F, the upper electrode film 118 is formed on the upper surface of the second dielectric film 116 to form the lower electrode film 110, the first dielectric film 112, and the intermediate electrode film 114. In addition to the thin film capacitor formed of one layer, a thin film capacitor of one layer consisting of the intermediate electrode film 114, the second dielectric film 116, and the upper electrode film 118 is further obtained. Get The process of forming the upper electrode layer 118 may be performed by a semiconductor deposition process such as CVD or ALD including MOCVD, similarly to the process of forming the lower electrode layer 110, but is not limited thereto. At least one metal selected from the group consisting of Ir, Au, Ni, Mo, W, Al, Ta, Ag and Ti or Pt, Ru, Sr, La, Ir, Au, Ni, Co, Mo, W, Al, Ta And conductive oxides or conductive nitrides of at least one metal selected from the group consisting of Ti.

As described above, in the method of manufacturing the capacitor layer included in the thin film multilayer ceramic capacitor according to the first embodiment of the present invention, the lower electrode film 110 and the intermediate electrode film 114 are formed by repeating the electrode film and the dielectric film forming process. And three or more electrode films sequentially stacked from the upper surface of the substrate 100, such as the upper electrode film 118, and two electrode films adjacent to each other, such as the first dielectric film 112 and the second dielectric film 116. The capacitor layer 140 may be manufactured by forming a thin film capacitor 130 including a dielectric film interposed therebetween on the upper surface 101 of the substrate 100 on which the plurality of holes 105 are formed. Although in the present embodiment, since the capacitor layer 140 includes three electrode films and two dielectric films, an example is described in which a two-layer thin film capacitor is actually formed on the hole 105. As described above, according to the present invention, the number of electrode films and dielectric films can be further increased. When the electrode film and the dielectric film are further thinned and deposited, more layers of the electrode film and the dielectric film can be deposited even if the size of the holes is maintained. By increasing the surface area of the thin film capacitor using the hole, the capacitance is increased as compared with the capacitor having a planar structure, and the number of stacked layers can be reduced by implementing two or more thin film capacitors on the hole. Therefore, it is possible to provide a thin-film multilayer ceramic capacitor that can be miniaturized while having a higher capacitance.

The capacitor layer 140 may be further processed by selectively introducing a passivation layer forming process and a polishing process as necessary. 3G-3I show additional passivation layer forming and polishing processes that can be employed in the first embodiment.

First, as shown in FIG. 3G, both sides of the thin film capacitor 130 are patterned and removed, and then the passivation layer 142 is formed on the upper surface of the capacitor layer 140 to be planarized. The patterning of both sides of the thin film capacitor 130 is to prevent a short circuit when connecting to the external electrodes in a subsequent process. In the case where there is no risk of short circuit due to the change in the structure of the external electrodes to be adopted, the thin film capacitor 130 The process of patterning both sides of the) may be omitted. The passivation layer 142 may be formed of an oxide such as SiO ₂ and a nitride such as Si ₃ N ₄ as in a conventional protective layer. In the present invention, the passivation layer 142 may be additionally used as a means for planarizing the top surface of the capacitor layer 140. Are employed.

However, if the hole 105 is filled through the process of forming the electrode films 110, 114, and 118 and the dielectric films 112 and 116, and the top surface of the final upper electrode film 118 is maintained flat, passivation is performed. Although the process of the layer 142 can be omitted, the effective surface area increase effect only when the electrode films 110, 114, 118 and the dielectric films 112, 116 are formed along the inner surface of the hole 105 as shown. Since it can be expected, it may not be easy to form a flat surface of the upper electrode film 118.

Next, as illustrated in FIG. 3H, first contact plugs 150 and 152 alternately connected to the electrode layers 110, 114, and 118 while passing through the thin film capacitor 130 are formed. In the present exemplary embodiment, the first contact plug 150 connected to the lower electrode film 110 and the first contact plug 152 connected to the upper electrode film 118 are formed. The first contact plugs 150 and 152 may be surrounded by the dielectric spacer 144 to insulate the electrode films 110, 114, and 118 from the electrode films other than the electrode films connected to the first contact plugs 150 and 152. Form. Then, the first wire 160 is formed by connecting to the first contact plugs 150 and 152. The illustrated first wiring 160 can be thought of as an intermediate electrode for connecting to the first external electrode after the capacitor layer 140 is stacked.

Next, an electrode film penetrating the thin film capacitor 130 and not connected to the first contact plugs 150 and 152 among the electrode films 110, 114, and 118, that is, the intermediate electrode film 114 in the present embodiment, The connected second contact plug 154 is formed. The second contact plug 154 is formed to be surrounded by the dielectric spacer 144 in order to insulate the electrode film other than the electrode film connected to the second contact plug 154 among the electrode films 110, 114, and 118. Then, the second wire 162 is formed by connecting to the second contact plug 154. The illustrated second wiring 163 can be considered as an intermediate electrode for connecting to the second external electrode after the capacitor layer 140 is stacked. Then, the passivation layer 164 is further formed to facilitate the lamination process.

The detailed process sequence may proceed as follows.

First, a contact hole etching process for forming the first contact plugs 150 and 152 and the second contact plugs 154 is performed. This process may be performed through one or more etching mask operations and etching. Then, the dielectric spacer 144 is worked on the inner wall of the contact hole. The dielectric spacer 144 may be formed of the same material as the first and second dielectric layers 112 and 116. Then, the first contact plugs 150 and 152 and the second contact plugs 154 are formed by filling conductive materials in the contact holes. The first wire 160 and the second contact connected to the first contact plugs 150 and 152 by depositing and patterning a conductive material such as Ru on the first contact plugs 150 and 152 and the second contact plugs 154. A second wiring 162 connected to the plug 154 is formed. The passivation layer 164 is formed on the first and second wirings 160 and 162.

Subsequently, as shown in FIG. 3I, the polishing process G is applied to the lower surface of the substrate 100 of the capacitor layer 140 to reduce the thickness of the capacitor layer 140 from h ₁ to h ₂ . In the polishing step (G), chemical mechanical polishing (CMP) may be used. The final product can be further miniaturized by removing the lower part of the unnecessary substrate 100 through this polishing step (G). This process is a process that can be selectively employed as shown in Figure 3g may be omitted when processing using a substrate having a sufficiently thin thickness, but a substrate of a rather large thickness to facilitate handling in the above-described film forming process and etching process In this case, it is preferable to perform this process additionally to reduce the thickness of the capacitor layer 140.

In the thin film type multilayer ceramic capacitor according to the first embodiment of the present invention, two or more capacitor layers manufactured through the processes of FIGS. 3A to 3I are manufactured and stacked, and alternately the first external layers of the electrode layers of the multilayer structure. It is completed by connecting to the electrode and the second external electrode. A lamination process for completing the thin film type multilayer ceramic capacitor according to the first embodiment of the present invention will be described with reference to FIGS. 4A and 4B.

First, as shown in Figure 4a, after the three capacitor layers (140a, 140b, 140c) prepared through the process of Figures 3a to 3i is provided, the capacitor to be in contact with the lower surface of the other capacitor layers (140a, 140b) when stacked Adhesive 170 is applied to the top surfaces of layers 140b and 140c. In the present exemplary embodiment, the adhesive 170 is applied to the upper surfaces of the capacitor layers 140b and 140c (eg, the passivation layer 164). However, as will be apparent to those skilled in the art, the application position of the adhesive 170 is The same effect can also be obtained by applying to at least one of the upper and lower surfaces of the capacitor layers 140b, 140c or 140a, 140b. The adhesive 170 may be an adhesive made of an insulating resin, but preferably a thermosetting adhesive, an ultraviolet curing adhesive, and a mixture thereof. However, it is preferable that the adhesive agent used, especially the thermosetting adhesive, can stably maintain the adhesiveness under normal soldering temperature conditions. In addition, in the present embodiment, three capacitor layers to be stacked are illustrated, but two or four or more capacitor layers may be used depending on the required capacitance and the allowable product size.

Subsequently, as illustrated in FIG. 4B, the multilayer structures 180 including the three capacitor layers 140a, 140b, and 140c are stacked in the state in which the adhesive 170 is applied, and then, the first and second sides of the multilayer structure 180 are formed. The first external electrode 182 is formed on one side of the multilayer structure 180 to be connected to the first wiring 160 and the second wiring 162, and the second external surface is formed on the other side of the multilayer structure 180. The thin film multilayer ceramic capacitor 190 is completed by forming the electrode 184. The external electrode process may use a known electrode forming process such as a deposition process, a plating process, a printing process, and the like, and materials for the first external electrode 182 and the second external electrode 184 include Ru, Au, and Pd. Known materials such as Ni, Ag or alloys thereof can be used. The first external electrode 182 and the second external electrode 184 connect the thin film capacitors 130 formed in the capacitor layers 140a, 140b, and 140c in parallel to implement a multilayer structure.

As will be apparent to those skilled in the art, the present embodiment is described as using the adhesive 170, it is also possible to form a desired multilayer structure through a known pressure heating process. More specifically, the dielectric films 112 and 116 are heated to a high temperature in a temperature range that does not deteriorate and compressed at a high pressure, thereby forming a multilayer structure as shown in FIG. 4B without the adhesive 170.

5 is a cross-sectional view of a thin film multilayer ceramic capacitor according to a second exemplary embodiment of the present invention.

Referring to FIG. 5, the thin film type multilayer ceramic capacitor 190a according to the second embodiment of the present invention includes a multilayer structure 180a in which two or more capacitor layers are stacked. In the present exemplary embodiment, an example in which three capacitor layers 140d, 140e, and 140f are stacked is illustrated. However, as described above, the number of stacked capacitor layers may be changed.

Looking at the configuration of each of the capacitor layer (140d, 140e, 140f), first, a substrate 100 having a top surface 101 formed with a plurality of holes 105, and the upper surface of the substrate 100 along the hole 105 And a thin film capacitor 130a consisting of three electrode layers 110a, 114a, and 118a sequentially stacked from the dielectric layers 112 and 116 interposed between two adjacent electrode layers.

The electrode layers 110a, 114a, and 118a of the capacitor layers 140d, 140e, and 140f are alternately connected to the first external electrode 182a and the second external electrode 184a. The first external electrode 182a and the second external electrode 184a connect thin film capacitors formed in each of the capacitor layers 140d, 140e, and 140f in parallel.

In detail, the stacked form of the electrode layers 110a, 114a, and 118a of the capacitor layers 140d, 140e, and 140f may include the electrode layers 110, 118a and the one extending on one side of the substrate 100. The electrode films 114a extending on the other side opposite to the side surfaces are alternately stacked. Hereinafter, for convenience, the electrode films 110 and 118a extending on one side are referred to as first electrode films 110a and 118a, and the electrode film 114a extending on the other side is also referred to as a second electrode film 114a. The first electrode films 110a and 118a extending on one side of the substrate 100 are connected to the first external electrode 182a formed on one side thereof, and the second electrode film 114a extending on the other side thereof is the same. It is connected to the second external electrode 184a formed on the other side.

In the thin film multilayer ceramic capacitor 190a shown in FIG. 5, each of the capacitor layers 140d, 140e, and 140f includes three electrode films 110a, 114a, and 118a and two dielectric films 112 and 116. In this case, the two-layer thin film capacitor is actually formed on the hole 105. However, as mentioned above, the electrode film of each capacitor layer can be formed of three or more layers. Therefore, the present invention includes n + 1 layer electrode films and n layer dielectric films, whereby practically n-layer thin film type It will correspond to a structure in which a capacitor is stacked on a hole (where n is a natural number of 2 or more). By increasing the surface area of the thin film capacitor by using the holes, the capacitance is increased as compared to the capacitor of the planar structure. Furthermore, by implementing two or more layers of the thin film capacitor on the hole, the number of stacked layers in the stacked structure 180a can be reduced. Therefore, it is possible to provide a thin-film multilayer ceramic capacitor that can be miniaturized while having a higher capacitance.

6A through 6H are cross-sectional views illustrating a method of manufacturing a capacitor layer included in a thin film multilayer ceramic capacitor as shown in FIG. 5.

First, as shown in FIG. 6A, a plurality of holes 105 are formed in the upper surface 101 of the substrate 100. In this case, the stepped portions 106 may be formed on both side surfaces of the substrate 100. Of course, it is not necessary to form the stepped portion 106 as in the first embodiment. The stepped portion 106 may be formed simultaneously with the hole 105 through a selective etching process used in the hole 105 forming process, in which case the stepped portion 106 is the same as the bottom surface of the hole 105. It is formed to a height.

Subsequently, as shown in FIG. 6B, the lower electrode layer 110a is formed on the upper surface of the substrate 100 as the first electrode layer extending to one side of the substrate 100. The process of forming the lower electrode layer 110a may be performed using the deposition method and the material as described above with respect to the lower electrode layer 110. As shown in the drawing, the lower electrode layer 110a is formed on the upper surface of the substrate 100 including the inner surface of the hole 105 and up to one side thereof, and is not formed on the other side of the lower electrode layer 110a. This is to prevent unwanted short-circuits of the external electrodes (182a and 184a in FIG. 5) respectively formed on both sides.

The lower electrode layer 110a may be formed by depositing an electrode material on the upper surface 101 of the substrate 100 and etching a portion of the other side of the substrate 100. As shown in FIG. 6B, in the etching process, an intermediate electrode film (114a of FIG. 6D) to be subsequently grown by additionally removing the upper surface portion d1 adjacent to the other side of the substrate 100 of the lower electrode film 110a. Short circuit with can be prevented more stably.

Next, as shown in FIG. 6C, the first dielectric layer 112 is formed on the lower electrode layer 110a positioned on the upper surface 101 of the substrate 100. If necessary, a patterning process for the first dielectric layer 112 may be added.

6D, the lower electrode film 110a, the first dielectric film 112, and the intermediate electrode film 114a are formed by forming the intermediate electrode film 114a as a second electrode on the upper surface of the first dielectric film 112. The thin film capacitor of one layer consisting of) is obtained first. The process of forming the intermediate electrode layer 114a may be performed using a deposition method and a material as described above with respect to the lower electrode layer 110. As illustrated, the intermediate electrode film 114a is formed to extend not only to the top surface of the first dielectric film 112 but also to the other side of the substrate 100, and is not formed on the opposite side of the first dielectric film 112. Therefore, the intermediate electrode film 114a and the lower electrode film 110a may be separated from each other and connected to the external electrodes to be formed on both sides.

The intermediate electrode film 114a may be formed through a deposition process of an electrode material and a selective etching process, similar to the lower electrode film 110a process. Preferably, the etching process is illustrated in FIG. 6D. In the intermediate electrode layer 114a, a short circuit with the lower electrode layer 110a may be effectively prevented by additionally removing the upper surface portion d2 adjacent to one side of the substrate 100.

 Next, as shown in FIG. 6E, a second dielectric film 116 is formed on the intermediate electrode film 114a. Similar to the process of forming the first dielectric film 112, the present process may be performed by a conventional semiconductor film forming process such as chemical vapor deposition or atomic layer deposition.

Next, as shown in FIG. 6F, the upper electrode film 118a is formed again on the upper surface of the second dielectric film 116 as the first electrode film, whereby the lower electrode film 110a, the first dielectric film 112, and the intermediate film are formed. In addition to the thin film capacitor formed of the electrode film 114a, a thin film capacitor formed of the intermediate electrode film 114a, the second dielectric film 116, and the upper electrode film 118a was further obtained. ). The process of forming the upper electrode film 118a may be performed using a deposition method and a material as described above with respect to the lower electrode film 110A. As shown in the drawing, the upper electrode layer 118a is formed on the upper surface of the substrate 100 including the inner surface of the hole 105 and up to one side thereof, but is not formed on the other side of the upper electrode layer 118a.

As described above, the stacked form of the electrode films 110a, 114a, and 118a may include a first electrode film 110a and 118a extending on one side of the substrate 100 and an agent extending on the other side facing the one side. The two electrode films 114a are stacked alternately. In the method for manufacturing a capacitor layer included in the thin film multilayer ceramic capacitor according to the present invention, the lower electrode film 110a, the intermediate electrode film 114a, and the upper electrode film 118a are formed by repeating the electrode film and the dielectric film forming process. Three or more electrode films 110a, 114a, and 118a sequentially stacked from the top surface of the substrate 100, and two electrode films adjacent to each other, such as the first dielectric film 112 and the second dielectric film 116. The capacitor layer 140 is manufactured by forming the thin film capacitor 130a including the dielectric film interposed therebetween on the upper surface of the substrate 100 on which the plurality of holes 105 are formed. Although in the present embodiment, since the capacitor layer 140 includes three electrode films and two dielectric films, an example is described in which a two-layer thin film capacitor is actually formed on the hole 105. As described above, the present invention will correspond to a structure in which n thin film capacitors are actually stacked on a hole by including an n + 1 electrode film and an n dielectric film (where n is a natural number of 2 or more). By increasing the surface area of the thin film capacitor using the hole, the capacitance is increased as compared with the capacitor having a planar structure, and the number of stacked layers can be reduced by implementing two or more layers of the thin film capacitor on the hole. Therefore, it is possible to provide a thin-film multilayer ceramic capacitor that can be miniaturized while having a higher capacitance.

The capacitor layer 140 may be further processed by selectively introducing a passivation layer forming process and a polishing process as necessary. 6G and 6H show additional passivation layer forming and polishing processes that may be employed in this embodiment.

First, as shown in FIG. 6G, the passivation layer 142 is formed on the upper surface of the capacitor layer 140 to be planarized. However, if the hole 105 is filled through the process of forming the electrode films 110a, 114a, and 118a and the dielectric films 112 and 116, and the top surface of the final upper electrode film 118 is kept flat, passivation is performed. Although the process of the layer 142 can be omitted, the effective surface area increase effect only when the electrode films 110a, 114a, 118a and the dielectric films 112, 116 are formed along the inner surface of the hole 105 as shown. Since it can be expected, it may not be easy to form a flat surface of the upper electrode film 118.

Subsequently, as illustrated in FIG. 6H, a polishing process G is applied to the lower surface of the substrate 100 of the capacitor layer 140 to reduce the thickness of the capacitor layer 140 from h ₁ to h ₂ .

In the multilayer multilayer ceramic capacitor according to the present invention, two or more capacitor layers manufactured through the processes of FIGS. 6A to 6H are manufactured and stacked, and the electrode layers of the multilayer structure are alternately disposed between the first external electrode and the second external electrode. It is completed by connecting to the electrode.

A lamination process for completing the thin film multilayer ceramic capacitor according to the present invention will be described with reference to FIGS. 7A to 7C.

First, as shown in FIG. 7A, after the three capacitor layers 140d, 140e and 140f manufactured through the processes of FIGS. 6A to 6H are prepared, the capacitors to be contacted with the lower surfaces of the other capacitor layers 140d and 140e at the time of lamination. Adhesive 170 is applied to the top surfaces of layers 140e and 140f.

Subsequently, as shown in FIG. 7B, electrodes formed on both sides of the multilayer structure 180a after forming the multilayer structure 180a in which the three capacitor layers 140d, 140e, and 140f are stacked in the state where the adhesive 170 is applied are formed. The passivation layer 142 is etched to expose portions of the films 110a, 114a, 118a. First, the lamination process may be implemented by forming a curing condition (eg, heating and / or ultraviolet irradiation) of the adhesive 170 while maintaining a predetermined pressure. By removing a portion of the passivation layer 142 disposed on the side of the multilayer structure 180a, the first electrode layers 110a and 118a of the electrode layers 110a, 114a and 118a are disposed on one side of the substrate 100. The electrode film 114a is exposed to the other side of the substrate 100.

Finally, as shown in FIG. 7C, the first and second external electrodes 182a and 184a are formed on the electrode films 110a, 114a, and 118a exposed to the side surfaces of the multilayer structure 180a, respectively. To complete). That is, the first external electrode 182a is formed on one side of the multilayer structure 180a to be connected to the first electrode films 110a and 118a, and the second external electrode 184a is the multilayer structure 180a. It is formed on the other side of the and is connected to the second electrode film 114a. The first and second external electrodes 182a and 184a may be more firmly attached through the stepped portion 106 prepared in advance as described with reference to FIG. 6A.

On the other hand, the thin film type multilayer ceramic capacitor manufacturing method according to the present invention can be carried out more easily at the wafer level. That is, forming the two or more capacitor layers, as described in the first and second embodiments above, may include a plurality of wafer levels different from each other by the capacitor layers constituting each layer of the multilayer structure. Wherein a plurality of wafers are used as substrates of the capacitor layer, have the same size as each other, and at least one capacitor layer is formed in each wafer in the same arrangement, and then the multilayer structure is formed. The forming may be performed by stacking a plurality of wafers on which the at least one capacitor layer is formed, and cutting the wafer multilayer structure so that at least one multilayer structure is formed. .

First, the wafer level capacitor layer manufacturing method may be performed similarly to the process described with reference to FIGS. 3A to 3I or the process described with reference to FIGS. 6A to 6H. However, when forming the holes 105 of FIG. 3A or 6A, isolation regions having the same depth as the holes are formed so that each capacitor layer has a predetermined distance from each other. In addition, in order to form a stacked structure, at least two wafers, each having two or more capacitor layer structures formed thereon, are manufactured through separate wafer level processes. Here, the wafers constituting each layer are manufactured to have the same size as each other, and at least one or more capacitor layers are formed in the same arrangement on each wafer.

Subsequently, a plurality of wafers are laminated using an adhesive means such as an adhesive. As the adhesive, as described above, a thermosetting adhesive, an ultraviolet curable adhesive, or a mixture thereof may be used, and the coating method may be applied by bonding to at least one surface of the upper and lower surfaces of each wafer. Alternatively, according to the embodiment it may be bonded by a pressing process using a high temperature / high pressure.

Next, the multilayer structure is cut along the separation region to separate the multilayer structures of the plurality of wafers obtained in the lamination process into respective thin film multilayer ceramic capacitor structures. As described above, a plurality of thin film type multilayer ceramic capacitor structures obtained in the wafer level process can be mass produced in a batch through the present cutting process.

Finally, in the case of the first embodiment, the first and second wirings located on both sides of the multilayer structure are exposed, and in the case of the second embodiment, the first and second electrode films are exposed, and the first and second electrodes are exposed on each side. A second external electrode is formed.

 While the preferred embodiments of the present invention have been described above, it is apparent that various modifications can be made without departing from the scope of the present invention.

As described above, the thin film multilayer ceramic capacitor of the present invention is formed by stacking two or more unit capacitor layers in which two or more thin film capacitors are actually stacked on the holes by forming three or more electrode films and two or more dielectric films on the holes. . By increasing the surface area of the thin film capacitor by using the holes, the capacitance is increased as compared to the capacitor of the planar structure. Furthermore, by implementing two or more layers of the thin film capacitor on the hole, the number of stacked layers in the laminated structure can be reduced. Therefore, it is possible to provide a thin-film multilayer ceramic capacitor that can be miniaturized while having a higher capacitance.

Claims (21)

A capacitor including a substrate having an upper surface having a plurality of holes formed therein, and a thin film capacitor including three or more electrode films sequentially stacked from the upper surface of the substrate along the holes, and a dielectric film interposed between two adjacent electrode films; And a multilayer structure in which two or more layers are stacked, wherein the electrode films of the respective capacitor layers are alternately connected to the first external electrode and the second external electrode. The thin film capacitor of claim 1, wherein the first external electrode is connected to the electrode film by a first contact plug that is alternately connected to the electrode film while passing through the thin film capacitor, and the second external electrode connects the thin film capacitor. The thin film type multilayer ceramic capacitor of claim 1, wherein the electrode film is connected to the electrode film by a second contact plug which is connected to the electrode film which is not connected to the first contact plug. The method of claim 1, wherein the stacked layers of the electrode layers of each capacitor layer are formed by alternately stacking a first electrode film extending on one side of the substrate and a second electrode film extending on the other side opposite to the one side. Thin film multilayer ceramic capacitor, characterized in that the form. The second electrode layer of claim 3, wherein the first external electrode is formed on one side of the multilayer structure to be connected to the first electrode layer, and the second external electrode is formed on the other side of the multilayer structure to form the second electrode layer. Thin-film multilayer ceramic capacitor, characterized in that connected with. The thin film type multilayer ceramic capacitor of claim 4, wherein a stepped portion is formed on both side surfaces of the substrate. The thin film type multilayer ceramic capacitor of claim 5, wherein the plurality of holes have a constant depth, and the stepped portion has the same height as the bottom surface of the hole. The thin film type multilayer ceramic capacitor of claim 1, wherein the two or more capacitor layers further include a passivation layer having a flat top surface formed on the top surface of the thin film capacitor. The thin film type multilayer ceramic capacitor of claim 1, wherein the plurality of holes are formed to have a predetermined depth. The thin film multilayer ceramic capacitor of claim 1, wherein the plurality of holes have a hemispherical grain structure, a fin hole, or a cylinder type. The thin film type multilayer ceramic capacitor according to claim 1, wherein the plurality of holes have an aspect ratio of 1 to 50 in each hole. The thin film multilayer ceramic capacitor of claim 1, wherein the electrode film is made of at least one metal selected from the group consisting of Pt, Ru, Ir, Au, Ni, Mo, W, Al, Ta, Ag, and Ti. The method of claim 1, wherein the electrode film is a conductive oxide or conductive nitride of at least one metal selected from the group consisting of Pt, Ru, Sr, La, Ir, Au, Ni, Co, Mo, W, Al, Ta, and Ti. Thin film multilayer ceramic capacitor, characterized in that made. The dielectric film of claim 1, wherein the dielectric film is formed of TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , HfO ₂ , SrTiO ₃ , BaTiO ₃ , (Ba, Sr) TiO ₃ , PbTiO 3, SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ and Pb (Zr, Ti) O ₃ At least one high dielectric constant material selected from the group consisting of or a dopant added thereto Thin film multilayer ceramic capacitors. The thin film type multilayer ceramic capacitor according to claim 1, wherein the two or more capacitor layers constituting the multilayer structure are bonded using a thermosetting adhesive, an ultraviolet curing adhesive, and a mixture thereof. A capacitor including a substrate having an upper surface having a plurality of holes formed therein, and a thin film capacitor including three or more electrode films sequentially stacked from the upper surface of the substrate along the holes, and a dielectric film interposed between two adjacent electrode films; Forming at least two layers; Forming a multilayer structure by stacking the two or more capacitor layers; And And connecting the electrode films of the respective capacitor layers to the first external electrode and the second external electrode alternately. The method of claim 15, wherein the connecting to the first external electrode and the second external electrode comprises: Forming a first contact plug passing through the thin film capacitor and alternately connected to an electrode film of each capacitor layer; Forming the first external electrode by connecting to the first contact plug; Forming a second contact plug penetrating the thin film capacitor and connected to an electrode film not connected to the first contact plug of an electrode film of each capacitor layer; And And connecting the second contact plug to form the second external electrode. The method of claim 15, wherein the electrode film, Patterning the electrode material after deposition to form a first electrode film extending on one side of the substrate; And And forming a second electrode film extending on the other side of the substrate by patterning the electrode material after deposition. The method of claim 17, wherein the first external electrode is formed on one side of the multilayer structure and connected to the first electrode layer, and the second external electrode is formed on the other side of the multilayer structure to form the second electrode layer. Thin film multilayer ceramic capacitor manufacturing method characterized in that the connection with. 16. The method of claim 15, wherein the electrode film and the dielectric film are obtained by depositing by chemical vapor deposition (CVD) or atomic layer deposition (ALD). 19. The method of claim 18, further comprising forming a passivation layer on the top and side surfaces of the plurality of capacitors, After the forming of the multilayer structure, before the forming of the first and second external electrodes, selectively removing the passivation layer to expose portions of the electrode film on the one side and the other side. Thin film multilayer ceramic capacitor manufacturing method characterized in that. The method of claim 15, wherein the forming of the two or more capacitor layers further comprises polishing a lower surface of the substrate to reduce the thickness of the capacitor layer.

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