JP2003045185A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a state before cut off can be held for some period even after the cut off of a power source without using a non-volatile memory, a leak current is reduced, and power consumption is reduced. SOLUTION: Before a power source is cut off, a switch 5 is turned on and a switch 6 is tuned off by control voltage of a first control input terminal 7. Next, switches 9, 10 are turned on by control voltage of a second control input terminal 13, a first capacitor 8 stores a state of a feedback loop, while a second capacitor 12 is charged. After a power source is cut off, when a power source is applied again before discharge of the capacitors 8, 12, a state of the feedback loop is made a state before the cut off of a power source by the first capacitor 8. At the time, a switch 11 is turned off by the second capacitor 12, and input data from a data input terminal 3 is cut off. Next, the switches 9, 11 are turned off and the switch 11 is turned on by the second control input terminal 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for achieving both high performance and reduced leakage current in a semiconductor memory device which has been miniaturized.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor manufacturing technology has advanced,
The power supply voltage applied to the semiconductor integrated circuit tends to decrease. Along with this, the threshold voltage tends to decrease as miniaturization progresses in order to realize the operation as a transistor. With the decrease in the threshold voltage, the leak current between the source and the drain increases. further,
In order to realize a high-performance transistor, it is necessary to further reduce the threshold voltage, and the leak current will increase more and more. In the miniaturization process, this leak current is becoming a major cause of an increase in current consumption of the LSI. Therefore, in order to reduce the power consumption of the LSI in the miniaturization process, it is an important issue to reduce not only the power consumption during operation but also the leakage current.

As a method of reducing this leakage current,
Although the operating speed of the transistor is reduced, the threshold voltage is increased, and the threshold voltage can be controlled by controlling the back gate bias as in VTCMOS to reduce the leak current during standby and increase the speed during operation. Method, a method of preparing a non-volatile semiconductor memory device such as a flash memory separately, saving the data therein and then turning off the power, and a method of replacing the semiconductor memory element itself such as a flip-flop with a non-volatile semiconductor memory device There is.

With further miniaturization, not only the leak current between the drain and the source, which has been remarkable in the past, but also the ratio of the leak current from the gate increases. This is largely due to the thinning of the gate oxide film due to the miniaturization, but the method of shutting off the power supply is the best method for reducing the leak current from the gate.

[0005]

However, in the case of the method of increasing the threshold voltage of the transistor, although the leak current is reduced, the operating speed of the transistor is reduced, and it is difficult to realize high performance.

Further, a method of controlling the back gate bias to change the threshold voltage according to the operation mode like VTCMOS, after the process of the 0.10 μm generation, if the scaling for improving the operation speed of the circuit is performed, the The dependence of the threshold voltage on the gate bias voltage tends to decrease, and even if the back gate bias voltage control technology is used, the threshold voltage cannot be changed sufficiently, and reduction of leakage current and higher performance are aimed at. Becomes difficult.

Further, in a method of separately preparing a nonvolatile semiconductor memory device such as a flash memory and saving the data in the standby mode and then turning off the power, it is necessary to mount a mechanism for saving the data. In particular, it is difficult to save the data of the volatile semiconductor memory device other than the bus interface.

Further, the method of replacing the semiconductor storage element itself such as a flip-flop with a non-volatile semiconductor storage device has a problem that the rewriting speed of the non-volatile semiconductor storage device is slow and the number of rewritings is limited.

The present invention has been made in view of the above problems, and an object of the present invention is to cut off the power without using the non-volatile semiconductor memory device at the time of standby and to maintain the state before the power is cut off even after the power is cut off. It is to provide a semiconductor memory device in which leakage current is reduced and power consumption is reduced by holding it for a certain period.

[0010]

In order to achieve the above-mentioned object, a semiconductor memory device according to the present invention has a feedback loop composed of two inverters, a data input terminal, a data output terminal, and a data input terminal. Switch for fetching input data from the controller into the feedback loop, a first control input terminal connected to the control terminal of the first switch, and a first capacitor for storing the state of the feedback loop when the power is cut off. A second switch for connecting or disconnecting the connection between the input terminal or output terminal of the two inverters forming the feedback loop and the first capacitor; and a second switch for connecting or disconnecting input data from the data input terminal. 3 switch and the control terminals of the second and third switches,
Before the power is turned off, the second
A second control input terminal to which a control voltage for turning on the switch and turning off the third switch is applied, and one terminal is grounded and the other terminal is connected to the second control input terminal. By the voltage level charged before the power is cut off, the second switch and the third switch are kept in the conductive state after the power is cut off, and the input data from the data input terminal is cut off when the power is turned on again. And a second capacitor for stably returning the state of the feedback loop before the power is cut off.

In the semiconductor memory device according to the present invention, during normal operation, the second switch is turned off and the third switch is turned on by the control voltage from the second control input terminal. Characterize.

According to the above configuration, the state of the feedback loop can be maintained for a certain period even after the power is cut off by the first capacitor, and the state of the feedback loop can be input when the power is turned on again by the second capacitor. It can be recovered without data interference. Therefore, it is not necessary to separately prepare a non-volatile memory in order to maintain the state before power-off. Further, a feedback loop composed of the same inverter as that of a semiconductor memory device such as a conventional flip-flop is used, and the first capacitor is separated from the feedback loop by the second switch during the normal operation, so that the rewriting speed decreases. There is no limit on the number of rewrites. This makes it possible to solve the conventional problems, reduce the leak current, and reduce the power consumption.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a circuit diagram showing a configuration example of a semiconductor memory device according to the embodiment of FIG. In FIG. 1, 1 and 2 are inverters that form a feedback loop of a semiconductor memory device, 3 is an input terminal for data input to the feedback loop, and 4 is an output terminal for data output. Reference numerals 5 and 6 are switches (first switches), and as shown in FIG. 2, the terminals 15 and 16 are turned on / off depending on the voltage level applied to the control terminal 17. When the control terminal 17 is in the "High" level state, the switch 1
4 conducts as shown in FIG. On the other hand, the control terminal 17 is
When in the "ow" level state, switch 14 shuts off as shown in FIG. By controlling the voltage level applied to the first control input terminal 7, the switches 5 and 6 operate complementarily, and the data value from the data input terminal 3 is set in the feedback loop. A conventional semiconductor memory device such as a flip-flop is basically configured using inverters 1 and 2, a data input terminal 3, a data output terminal 4, switches 5 and 6, and a first control input terminal 7. .

Reference numeral 8 is a capacitor (first capacitor),
This is for maintaining the state of the semiconductor memory device for a certain period even after the power is cut off. Reference numerals 9 and 10 denote switches (second switches) having the same function as the switch 5. The switches 9 and 10 are turned on by setting the second control input terminal 13 to the “High” level immediately before turning off the power supply. Then, the state of the feedback loop is set in the capacitor 5. Further, during the normal operation in which the power is not cut off, the second control input terminal 13 is set to the “Low” level, so that the capacitor 8 is separated from the feedback loop and the charging and discharging of the capacitor 8 is prevented. As a result, it is possible to prevent power consumption due to the added capacitor 8 and to prevent a decrease in operating speed of the semiconductor memory device.

Reference numeral 11 is a switch (third switch) having the same function as the switch 5, and reference numeral 12 is a capacitor (second capacitor). In preparation for shutting off the power supply, the capacitor 12 is charged when the second control input terminal 13 is set to the “High” level. When the power is turned on again, the capacitor 12 turns off the switch 11 to cut off the input data from the data input terminal 3. This is when the power is turned on again.
There is a period when the state of the first control input terminal 7 is not stable,
This is because the input data from the data input terminal 3 may collide with the data held in the capacitor 8. Also, at this time, the capacitor 12 has the switches 9 and 10
Turn on. With these functions, the state of the feedback loop becomes the holding state of the capacitor 8.

FIG. 5 is similar to the configuration of FIG. 1, but shows an example in which the switch 9 and the output of the inverter 2 in the feedback loop are directly connected without passing through the switch 5. This configuration also provides the same functions as in FIG.

FIG. 6 is an example of a configuration in which the switch 5 of FIG. 1 is omitted. By setting the output current capability of the inverter 2 in the feedback loop to be weaker than the input current capability from the data input terminal 3 when the switch 6 and the switch 11 are on, the state of the feedback loop can be overwritten. This configuration is advantageous in that it has fewer switches than the configuration of FIG.

7 and 8 show an example in which the connection of the data output terminal 4 in FIG. 1 is changed. The data output terminal 4 can be connected to any position of the feedback loop and differs from the configuration of FIG. 1 only in the polarity of the data output terminal and provides the same function.

FIG. 9 is an example of a configuration in which the switch 9 of FIG. 1 is omitted. There is no switch 9 as shown in FIG.
In the case of only, the effect of preventing power consumption due to charging / discharging of the capacitor 8 during the normal operation in which the power is not shut off is weaker than in FIG. be able to. Also, the switch 10
The same applies when the switch 9 is omitted and only the switch 9 is used.

FIG. 10 shows the switch 5 and the switch 6 of FIG.
This is an example in which the polarities of are replaced. In this case, the logic of the control by the first control input terminal 7 is inverted, but the function is the same as in FIG.

Next, the operation of these devices will be described step by step.

(A) Before shutting off the power supply, the system clock is stopped to bring it to a steady state. In the case of FIG. 1, the switch 5 is turned on and the switch 6 is turned off by setting the first control input terminal 7 to the “Low” level.

(B) The second control input terminal 13 is set to "High".
By setting to the “h” level, the switch 9 and the switch 10 are turned on to charge the capacitor 8, and the state of the feedback loop is stored in the capacitor 8. At the same time, the capacitor 12 is charged.

(C) Turn off the power supply.

(D) The power is turned on again before the capacitors 8 and 12 are discharged.

(E) The capacitor 8 brings the state of the feedback loop into the state before the power is cut off. At this time, the capacitor 1
Since the switch 11 is turned off and the input data from the data input terminal 3 is cut off by the “High” level charged to 2, even if the state of the first control input terminal 7 is unstable, the data input terminal is unstable. The input data from 3 does not interfere with the return of the feedback loop.

(F) The second control input terminal 13 is set to "Lo
By setting the w level, the switches 9 and 10 are turned off and the switch 11 is turned on.

(G) A clock is supplied to restart the system processing.

With the above flow, power consumption by the capacitor 8 during normal operation is prevented, the operation speed of the semiconductor memory device is prevented from decreasing, the state of the feedback loop is safely maintained even after the power is cut off, and further leakage is caused by the power cutoff. The current can be reduced.

The semiconductor memory device according to the present embodiment has a larger chip area as compared with the conventional flip-flop or the like because the number of capacitors and switches increases. Replacing the semiconductor memory device of the entire system with the semiconductor memory device according to the present embodiment increases the chip area. However, since only some semiconductor memory devices have to hold the state when the power is cut off, the chip area is slightly increased. Then, the semiconductor memory device according to the present embodiment can be mounted.

If the power is turned on again within a certain period after the power is cut off, the capacitor 8 can restore the state when the power was cut off. Since the capacitor is used to store the state and it is volatile, it is necessary to turn on the power again within a certain time after the power is turned off. That is, the semiconductor memory device according to the present embodiment has a limitation that it is volatile, but if it is applied to a system that operates intermittently, it is possible to cut off the power while maintaining the state during standby, thus reducing power consumption. It is effective because it can be reduced.

On the other hand, when the semiconductor memory device according to the present embodiment is used to shut off the power supply in a system that is on standby for a long time, it is necessary to periodically turn on the power again after shutting down the power supply. The current can be reduced and the power consumption can be reduced.

[0034]

As described above, according to the present invention,
By shutting off the power supply, leakage current is reduced, and even if the power supply is shut off, the state is maintained for a certain period of time. It is possible to realize a semiconductor memory device that solves the problem.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention.

[Figure 2] Switch circuit diagram

[Figure 3] Circuit diagram when the switch is on

FIG. 4 is a circuit diagram when the switch is off.

FIG. 5 is a circuit diagram showing another configuration example of the semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a circuit diagram showing another configuration example of the semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a circuit diagram showing another configuration example of the semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a circuit diagram showing another configuration example of the semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is a circuit diagram showing another configuration example of the semiconductor memory device according to the embodiment of the present invention.

FIG. 10 is a circuit diagram showing another configuration example of the semiconductor memory device according to the embodiment of the present invention.

[Explanation of symbols]

1, 2 inverter 3 data input terminals 4 Data output terminal 5, 6, 9, 10, 11 switch 7 First control input terminal 8 and 12 capacitors 13 Second control input terminal

Claims (2)

[Claims] 1. A feedback loop composed of two inverters, a data input terminal, a data output terminal, a first switch for taking input data from the data input terminal into the feedback loop, and the first switch. A first control input terminal connected to the control terminal of the first switch, a first capacitor that stores the state of the feedback loop when the power is cut off, and an input terminal or an output terminal of two inverters that form the feedback loop. A second switch for connecting or disconnecting the connection between the first capacitor and the first capacitor; a third switch for connecting or disconnecting input data from the data input terminal; and a second switch for connecting the second and third switches. Connected to the control terminal,
Before the power is cut off, to maintain the state of the feedback loop,
A second control input terminal to which a control voltage is applied to turn on the second switch and turn off the third switch, and one terminal is grounded and the other terminal is the second control. With the voltage level connected to the input terminal and charged before the power is cut off, the conduction state of the second switch and the cutoff state of the third switch are maintained after the power is cut off, and the data input is performed when the power is turned on again. A semiconductor memory device comprising: a second capacitor for interrupting input data from a terminal to stably restore the state of the feedback loop before power off. 2. In a normal operation, the second switch is turned off and the third switch is turned on by a control voltage from the second control input terminal. Item 2. The semiconductor memory device according to item 1.