JP2003044847A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor which does not need a configuration in which a circuit scale such as a line memory is made large and also can obtain a high dithering effect. SOLUTION: This image processor is provided with quantizers 5 and 6 capable of quantizing the pixel value of each pixel by two or more different methods, a selector 7 for selecting any method among two or more methods, error calculating means 8 and 9 for calculating a gradation error in each pixel caused when a pixel value is quantized, and an adding means 4 for adding quantity related to the gradation error of a pixel quantized by at least one ahead to the pixel value of each pixel when a plurality of pixels ranging on one line are continuously quantized by one at a time. The quantizers 5 and 6 quantize a pixel value subjected to addition processing by the adding means 4, and the selector 7 also switches quantizing methods in each group of a plurality of continuous pixels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for processing image data, for example, a technique useful when applied to an image processing device for quantizing an input image signal in accordance with the number of gradations of a display device.

[0002]

2. Description of the Related Art For example, the number of displayable colors (the number of gradations) is 16
When a 24-bit color digital image is displayed and output to a bit-color display device, it is necessary to quantize the image data and reduce the number of gradations from 24-bit color to 16-bit color. When the image data is quantized, if the quantization is simply performed for each pixel, an apparently large deterioration in image quality may occur such as a boundary line called a pseudo contour. Therefore, conventionally, the dithering process such as the systematic dither method or the error diffusion dither method is performed to suppress the apparent deterioration of the image quality.

The above-mentioned systematic dither method is, for example, a method in which a plurality of quantizers having slightly different threshold values are used and these quantizers are switched at predetermined intervals to quantize each pixel. is there. In addition, the error diffusion dither method is a method in which, when quantizing a pixel, the tone error of several surrounding pixels such as the upper side and the left side of the pixel is added before the quantization.

[0004]

However, although the above-described systematic dither method can prevent the occurrence of pseudo contours, for example, when the entire screen is filled with an intermediate color whose quantization result differs among a plurality of quantizers. In addition, there is a problem that the switching cycle of the quantizer appears in the display image, and the image quality is apparently deteriorated.

Further, in the error diffusion dither method, since error diffusion is performed by a plurality of pixels arranged in the vertical direction when quantizing each pixel, a line memory for storing the gradation error of these vertical pixels is used. This is necessary, which leads to an increase in circuit scale, power consumption, and cost. The increase in circuit scale and power consumption becomes a particularly serious problem when mounted on a small-sized portable display such as a mobile phone or a portable information terminal. In addition, the error diffusion dither method has a problem that the effect of the dithering process does not appear so much when the number of pixels around which error diffusion is performed is small.

In view of the above situation, an object of the present invention is to eliminate the need for a configuration such as a line memory which increases the circuit scale.
Another object of the present invention is to provide an image processing device that can sufficiently obtain the effect of the dithering process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, a quantizer capable of quantizing the pixel value of each pixel by two or more different methods, an error calculating means for calculating a gradation error for each pixel generated when quantizing the pixel value, and one line And a quantizing means for adding an amount relating to a gradation error of at least one previously quantized pixel to a pixel value of each pixel when successively quantizing a plurality of aligned pixels one by one, and The image processing apparatus is configured so that the method can be switched for each group of a plurality of continuous pixels.

Desirably, a storage means is provided for storing the gradation error generated by the quantization of the pixel value of the first pixel in one line during the quantization processing for one line, and the adding means is provided in the one line. It is preferable to add at least an amount related to the gradation error of the leading pixel one line before stored in the storage means to the pixel value of the leading pixel.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of an image data processing circuit suitable for applying the present invention. The image data processing circuit of this embodiment, for example, a quantization process for reducing the number of gradations of the input digital image data,
This is a circuit that carries out dithering processing that prevents deterioration of image quality due to quantization. Hereinafter, this is referred to as a quantization & dither processing circuit 100.

In FIG. 1, 1 is an input port for digital image data, 5 is a first quantizer for quantizing with a predetermined threshold, and 6 is a threshold slightly different from the first quantizer 5. 2 is a second quantizer set to 7, a selector for selectively passing the output of either the first quantizer or the second quantizer, 8 is the first or second quantizer 5 , 6 is an inverse quantizer for returning the image data quantized by the first and second quantizers 5 and 6 to a data format adapted to the number of gradations of the input image data. A subtracter 10 that subtracts the image data and the image data that has passed through the inverse quantizer 8 to calculate a gradation error for each pixel is a delay that delays the calculated gradation error for a period of data input of one pixel. The circuit 4 weights the input image data with a gradation error of one pixel before by a predetermined weighting (for example, 1/3, 1 (2, 1 etc.) to perform addition, 2 is a control terminal to which a signal for controlling the state of the selector 7 is input, and 3 is an output port for outputting a quantized and dithered image signal. . The digital image data input from the input port 1 has a pixel value of, for example, R
The gradation value data of each of the three primary colors of GB (red, green, blue) is included in each pixel. Further, the inverse quantizer 8 and the subtractor 9 constitute error calculation means.

FIG. 2 shows the quantization contents of the first quantizer of FIG. 1, FIG. 3 shows the quantization contents of the second quantizer, and FIG. 4 shows the quantization contents of the inverse quantizer. A graph for explaining each of the contents is shown. In this embodiment, the first quantizer 5 and the second quantizer 5
The quantizer 6 quantizes a pixel value of 3 bits and 8 gradations to a pixel value of 2 bits and 4 gradations, for example. As shown in FIGS. 2 and 3, the threshold values of the first quantizer 5 and the second quantizer 6 are set so as to deviate from each other. For example, when the input is "1", the first quantizer The output is "0" at 5 and the output is "1" at the second quantizer 6.

Further, the inverse quantizer 8 converts a pixel value of 2 bits and 4 gradations into a data format of 3 bits and 8 gradations with a threshold value as shown in FIG. It is preferable to set the conversion threshold value of the inverse quantizer 8 so that its output value is equal to the gradation level displayed and output on the display, because an accurate gradation error can be obtained.

FIG. 5 is a diagram for explaining the processing contents of the quantization & dither processing circuit 100 of FIG. Quantization above &
According to the dither processing circuit 100, the pixel value of each pixel is sequentially input from the input port 1 as image data. The order of inputting pixel values is such that pixel values are input pixel by pixel along the line direction of the display image, and when the end of the line is reached, the pixel value is continued to the first pixel of the line below.

When the pixel value is input, first, in the adder 4, the gradation error of the previous pixel is added with a predetermined weighting. The value of the operation result is the same as that of the first quantizer 5 and second
The data is quantized by the quantizer 6 respectively, and any data (quantized pixel value Y) is selected by the selector 7 and output from the output port 3. Switching of the selector 7 is controlled from the outside, and for example, the state of the selector 7 is switched every time one line of image data is processed. As a result, each pixel value of the input image data is quantized for each line by the first quantizer 5 and the second quantizer 6 and output.

For example, when paying attention to an arbitrary one pixel "T" of the display image, at the time of quantizing this pixel "T",
The gradation error that occurs when the previous pixel “A” is quantized is added and then quantized. That is, the first quantizer 5
Is expressed as a function φ1, a pixel value of input image data is expressed as an input pixel value, a pixel value after quantization is expressed as an output pixel value, and a weighting constant is expressed as gm (eg, 1, 1/2, 1/3, etc.). , Is as follows. T output pixel value = φ1 [T input pixel value + gm · A pixel gradation error value]

On the other hand, the data quantized and selectively output by the selector 7 is also sent to the inverse quantizer 8 and converted into 3-bit data corresponding to the number of gradations of the input image data. Then, the dequantized data is subtracted from the pixel value X before quantization of the pixel currently being processed, and the gradation error value of the pixel is obtained. This gradation error value is held by the delay circuit 10 during the processing of one pixel, and is added by the adder 4 in the processing of the next pixel.
Is output to.

According to such a quantizing and dithering process, the quantizing method is different between the lines and an error diffusion action occurs between a plurality of adjacent pixels on the same line. High effect of the ring can be obtained. Further, the conventional dithering method for performing the error diffusion between the lines requires the line memory, but since the line memory is not necessary in this embodiment,
Therefore, the circuit scale can be reduced.

The quantization & dither processing circuit 100
In the above configuration, the leading pixel in one frame and the leading pixel in one line are also quantized after adding the tone error of the pixel processed immediately before. 1 for the first pixel and the first pixel in one line
The gradation error of the immediately preceding pixel may not be added. Such a configuration is possible by providing a counter that counts the number of pixels and the number of lines, and controlling the adder 4 based on the count value of the counter.

In the quantizer & dither processing circuit 100 of the above embodiment, the selector 7 is switched every line, but the selector 7 is switched every half of one line and every one line. It may be performed for each group of a plurality of pixels, such as every 1/3 of the above.

Further, in the quantization & dither processing circuit 100 of the above embodiment, the error diffusion processing is performed by adding only the gradation error of one pixel before to the pixel value of the pixel to be quantized. By providing a plurality of circuits 10 and adding the output of each delay circuit to the pixel value, the error diffusion may be performed by adding the values related to the gradation error of the plurality of pixels on the front side. I can.

Further, as shown in FIG. 6 which shows another example of the structure of the quantizer, the parts of the first quantizer 5, the second quantizer 6 and the selector 7 of FIG. It is also possible to substitute the circuit including the adder 451, the selector 452, and the 1/2 circuit 453. That is, "0" or "1" is added to the pixel value X before quantization by the selector 452 and the adder 451, and the resulting data is halved by the 1/2 circuit,
Fractions are rounded down and output as a quantized pixel value Y.
Then, by switching addition of "0" or "1" by the selector 452, quantization of two methods is performed as in the circuit of FIG.

Further, as shown in FIG. 7, which is a block diagram of another example of the quantizing & dithering circuit, a plurality of quantizers 24a, 24b whose thresholds are set to be slightly different from each other.
, 24z are provided, and the plurality of quantizers 24a, 24 are provided.
.., 24z may be switched to quantize the input image data. In this way, by using a large number of quantizers, the effect of dithering processing can be enhanced.

FIG. 8 is a block diagram showing the overall configuration of an image processing apparatus equipped with the above quantization & dither processing circuit 100. This image processing apparatus is, for example, mounted on a mobile phone, a portable information terminal, or the like, and is an apparatus that converts image data having a high gradation number into image data that matches the gradation number of a display and outputs the image data.

In FIG. 8, 101 is an image memory for storing image data, 103 is a pixel counter for counting the number of pixels processed in one line, 104 is a line counter for counting the number of lines being processed, and 102 is a line counter. Is an address generator that generates the address of the image memory 101 in which the next pixel value is stored from the count values of the pixel counter 103 and the line counter 104, and 105 is the quantizer & dither processing circuit 100 from the count value of the line counter 104. It is a quantization selection unit that generates a control signal for the selector 7.

According to the image processing apparatus having such a configuration,
For example, in a state where image data having a high gradation number is written in the image memory 101, the address generator 10
2, the address is output, and the display image data is read from the image memory 101 for each pixel in a predetermined order. Then, the read display image data is sequentially input to the quantization & dither processing circuit 100, and the quantization processing and the dithering processing are performed by the method described above. Then, the processed image data is output to the driver circuit of the display device.

FIG. 9 is a block diagram showing a second embodiment of the quantization & dither processing circuit. Quantization of this second embodiment &
The dither processing circuit 500 has the same configuration as that of the quantization & dither processing circuit 100 of the first embodiment, and further includes 1 of the display image.
The configuration is such that an error diffusion process is performed on the head pixel of the frame and the head pixel of each line.

In FIG. 9, an input port 1, a control terminal 2, an output port 3, an adder 4, first and second quantizers 5, 6, a selector 7, an inverse quantizer 8, a subtractor 9, The delay circuit 10 has the same configuration as that of the first embodiment. The newly added circuit has a storage circuit 63 that stores the gradation error value of the first pixel in the immediately preceding line, a switch 62 that sends and blocks data to and from the storage circuit 63, and a predetermined fixed value. The data register 65 for output and the second selector 6 for selecting the data to be output to the adder 4 to any of the outputs of the delay circuit 10, the storage circuit 63, and the data register 65.
4, the second selector 64 and the control terminal 52 to which the control signals of the switch 62 are input.

FIG. 10 is a diagram for explaining the processing contents of the quantization & dither processing circuit of the second embodiment. In the quantization & dither processing circuit 500 of the second embodiment, when processing the second and subsequent pixels of each line, the second selector 64 causes the delay circuit 1 to operate in response to a control signal input to the control terminal 52.
The connection is on the 0 side, and the same quantization and dithering processing as in the first embodiment is performed.

Further, in the quantizing & dithering processing circuit 500 of the second embodiment, at the time of processing the leading pixel of the frame and the leading pixel of each succeeding line, the control signal inputted from the control terminal 52 causes The second selector 64 and the switch 62 are switched as follows, and the dithering process described below is performed.

That is, the switch 62 is the delay circuit 10
Is turned on when the grayscale error data of the first pixel of one line is output, and is turned off otherwise. By this switching, the gradation error data of the leading pixel of each line is stored in the storage circuit 63 until the timing of the quantization processing of the leading pixel of the next line.

Further, the second selector 64 selects the input on the data register 65 side during the period in which the leading pixel of one frame of the display image is quantized, and quantizes the leading pixels of other lines. The input on the side of the storage circuit 63 is selected during the period of performing the control, and the input on the side of the delay circuit 10 is controlled to be selected during the period of performing the quantization processing for the other pixels. Here, the value of the data register 65 is “0”.

By such switching control, when the leading pixel "Tb" of one frame of the display pixel is quantized, the fixed value "0" of the data register 65 is added to the input pixel value and quantized. Is done. Further, when quantizing the leading pixel (for example, pixel “Tc”) of each of the second and subsequent lines, the tone error of the leading pixel “C” of the preceding line is added and the quantization is performed.

According to such quantization and dithering processing, in addition to the effect of the first embodiment, the effect of error diffusion can be obtained for the leading pixel of the frame and the leading pixel of each line, so that the dithering effect is obtained. Further increase. Further, although a configuration such as the memory circuit 63 and the second selector 64 is newly required, the circuit scale is not so large as compared with the case where the line memory is provided. In the quantizer & dither processing circuit 500 of the second embodiment, the switching timing of the first quantizer 5 and the second quantizer 6 can be changed appropriately.

Further, when quantizing the head pixel (eg pixel “Tc”) of each line, only the tone error of the head pixel (eg pixel “C”) one line before is added. The error diffusion may be performed by adding the gradation errors of the respective leading pixels of the plurality of lines processed in step 1. In such a configuration, a plurality of storage circuits 63 are provided to shift and store the storage data, and each storage circuit 6
This can be realized by configuring the storage data of No. 3 to be output to the adder 4.

FIG. 11 is a block diagram showing the overall construction of an image processing apparatus equipped with the quantization & dither processing circuit of the second embodiment. 11, the image memory 101, the pixel counter 103, the line counter 104, the address generator 102, and the quantization selection unit 105 are the same as those in FIG. The image processing apparatus of the second embodiment is additionally provided with a quantization error selection unit 506 that generates control signals for the second selector 64 and the switch 62 from the count values of the pixel counter 103 and the line counter 104, respectively. ing. The control signal from the quantization error selection unit 506 realizes the switching control of the second selector 64 described above.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the embodiment, the image processing apparatus including the image memory as a constituent element has been described, but the image data may be directly input from the outside without the image memory. Further, although the configuration has been described in which digital image data having a high gradation is input and digital image data having a low gradation is output, it is also applicable to a circuit for inputting an analog image signal and quantizing it into digital image data. is there.

In the above description, the invention made by the present inventor was mainly described as an image processing apparatus of a mobile phone or a portable information terminal, which is a field of use which is the background of the invention, but the present invention is not limited thereto. Instead, for example, it can be widely used for an image processing device that processes video data on a large display, an image processing device that performs a dithering process of image data, such as a display control module of a computer.

[0040]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, the dithering effect is exerted between the plurality of lines due to the different quantization method, and the dithering effect is exerted between the plurality of pixels on the same line by the error diffusion. The effect of the dithering process can be enhanced. Further, since the configuration of the present invention does not require a configuration such as a line memory which causes an increase in circuit scale, which is required in the conventional error diffusion dither method, the circuit scale can be reduced to reduce power consumption and cost. There is an effect that can be achieved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a suitable quantization & dither processing circuit to which the present invention is applied.

FIG. 2 is a graph illustrating the details of quantization performed by the first quantizer shown in FIG.

FIG. 3 is a graph illustrating the details of quantization performed by the second quantizer shown in FIG.

FIG. 4 is a graph illustrating the details of quantization performed by the inverse quantizer shown in FIG.

FIG. 5 is a diagram for explaining processing contents of the quantization & dither processing circuit of the first embodiment.

6 is a diagram showing another configuration example of the first and second quantizers and the selector of FIG. 1. FIG.

FIG. 7 is a configuration diagram showing another embodiment of the quantization & dither processing circuit.

FIG. 8 is a block diagram showing an overall configuration of an image processing apparatus including the quantization & dither processing circuit of the first embodiment.

FIG. 9 is a configuration diagram showing a second embodiment of a quantization & dither processing circuit.

FIG. 10 is a diagram illustrating processing contents of a quantization & dither processing circuit according to a second embodiment.

FIG. 11 is a block diagram showing an overall configuration of an image processing apparatus including a quantization & dither processing circuit according to a second embodiment.

[Explanation of symbols]

4 adder 5 First quantizer 6 Second quantizer 7 selector 8 Inverse quantizer 9 subtractor 10 Delay circuit 62 switch 63 Memory circuit 64 Second selector 65 data register 101 image memory 102 address generator 103 pixel counter 104 line counter 105 Quantization selection unit 506 Quantization error selection unit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Junko Nakase             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F term (reference) 5B057 AA20 CA01 CA08 CA12 CA16                       CB01 CB07 CB12 CB16 CC01                       CE13                 5C066 AA03 CA05 GA01 HA03                 5C077 LL19 MP01 NN15 RR06 SS06                 5C080 BB05 DD01 DD22 EE29 JJ01                       JJ02 JJ05                 5C082 BA35 BA39 DA51 MM07 MM10

Claims (5)

[Claims] 1. An image processing apparatus comprising a quantizing circuit for quantizing a pixel value of each pixel included in an image signal with a predetermined gradation number, wherein the quantizing circuit has a different pixel value of each pixel. Quantizer that can be quantized by two or more methods, a selector that selects one of the above two or more methods, and an error that calculates a gradation error for each pixel that occurs when quantizing a pixel value Calculation means,
An addition unit that adds an amount relating to a gradation error of the pixel quantized at least one before to the pixel value of each pixel when the plurality of pixels arranged on one line are continuously quantized one by one, The quantizer quantizes the pixel value after the addition processing by the adding means, and the selector switches the quantization method for each group of a plurality of continuous pixels. An image processing device characterized by being provided. 2. A storage unit for storing a gradation error generated by quantization of a pixel value of a leading pixel in one line during a quantization process for one line, wherein the adding unit is a leading unit in one line. The pixel value of the pixel is at least 1 stored in the storage means.
The image processing apparatus according to claim 1, wherein the image processing apparatus is configured to add an amount related to a gradation error of a leading pixel before the line. 3. The adding means is 1 in the image data.
3. The structure according to claim 1, wherein the pixel value of the first pixel of the frame is added with a predetermined fixed value.
The image processing device according to item 1. 4. The group of consecutive pixels is
The image processing apparatus according to claim 1, wherein the image processing apparatus is a set of all pixels in one line. 5. The dequantizer, wherein the error calculating means reduces the quantized pixel value to a data format corresponding to the number of gradations before quantization, and the dequantization from the pixel value before quantization. The image processing device according to claim 1, further comprising a subtractor that subtracts the pixel value that has passed through the image processing unit.