JP4892222B2 - Image display device and its correction device - Google Patents

Description

The present invention relates to an image display device and a correction device for an image display device, and in particular, gradation characteristics on a display screen, so-called display screen uniformity such as brightness unevenness or color unevenness, so-called brightness per pixel or The present invention is suitable for application to an image display device that can improve color variation.

In recent years, with an increase in the size of the display screen, various display devices such as a CRT projector, a liquid crystal projector, a plasma display, and a liquid crystal display have entered the market in addition to the conventional CRT direct-view television. In these image display apparatuses, screen uniformity with high levels of brightness and chromaticity is required depending on the application.

Hereinafter, a three-plate liquid crystal projector as an example of an image display device according to the prior art will be described.

In other words, with the increase in the display area of projectors in recent years, unevenness in brightness and color unevenness on the screen caused by variations in the characteristics of the light source, optical system, and liquid crystal display device that is an image display element constituting the apparatus Defects are a problem.

Therefore, it has become necessary to incorporate a circuit for correcting a uniformity defect due to superposition of factors into an image display apparatus. As such a technique, the technique described in Patent Document 1 can be cited. The technique described in Patent Document 1 will be described below. FIG. 23 shows the configuration of this prior art.

As shown in FIG. 23, the liquid crystal projector according to this prior art includes an image signal input terminal 1, a signal processing circuit 90, a synchronization separation circuit 201, a phase synchronization circuit (PLL circuit) 202, a timing signal generator 20, and an addition circuit 91. The memory device 96 includes an AD conversion circuit 92, a drive circuit 93, a memory 94, and an address counter 95.

First, a certain level of video signal is input to the image signal input terminal 1 of the image display device, and this video is displayed on the screen. Next, as shown in FIG. 24, the luminance level is measured by a video camera or the like for each area where the display screen is appropriately divided, and DC difference data with the target luminance level is recorded in the memory 94 as luminance correction data. Is done.

The memory 94 in which the correction data is recorded is incorporated in the luminance correction circuit of the image display device. The correction data is read by calculating the address of the memory 94 corresponding to the display area divided at the time of luminance measurement from the horizontal and vertical synchronization signals of the input signal.

The correction data is converted into an analog value by the DA conversion circuit 92. This analog correction value is a video signal added to the input video signal using the adder circuit 91, and drives the liquid crystal display device via the drive circuit 93 of the image display device. Thereby, the uniformity defect on the display screen is corrected.
JP 61-243495 A

However, according to the knowledge and examination of the present inventors, the luminance measurement that is the basis of the correction data is
Since it is performed at a certain luminance level, uneven luminance and uneven color are corrected over the entire area from input of a low luminance (near black level) video signal to input of a high luminance (near white level) video signal. There is no possibility.

In addition, since the correction according to the conventional technique is performed using the representative correction value for each area obtained by appropriately dividing the above-described display area, in the corrected display image, the boundary between the areas on the screen is set. Unnatural color and brightness discontinuities tend to appear.

An object of the present invention is to provide a display device capable of performing appropriate variation correction with a small amount of memory.

To achieve the object, a first aspect of the invention, a correcting device of an image display apparatus for correcting the brightness or color variations in the display unit of the image display apparatus, an image signal of each pixel , And a gradation correction unit that performs correction using correction data corresponding to the gradation value of the image signal, the pixel address in the horizontal direction, and the line address. The gradation correction unit includes correction data for each gradation value. When an image signal of one pixel is input, a first memory that outputs correction data corresponding to the gradation value of the input image signal, and one line for each line address Corresponding to the horizontal pixel address and line address of the input image signal in accordance with the second memory for storing the correction data in the differential compression format and the timing at which the image signal of each pixel is input to the first memory The correction data for all the gradation values is reproduced from the correction data in the differential compression format stored in the second memory, and the correction data for all the reproduced gradation values is written to the first memory. And a data reproducing unit . Note that variations in brightness can include variations in luminance. Further, as in the case of using a device that performs pulse width modulation, a configuration that expresses light and dark by modulating an integral value within a predetermined period of luminance may be employed. In that case, the variation in the integrated value of the luminance within a predetermined period can be adopted as the variation in brightness. One horizontal selection period can be adopted as the predetermined period.

According to a second aspect of the present invention, there is provided a correction device according to the first aspect, and a display unit that displays an image based on an image signal corrected by the gradation correction unit of the correction device. This is an image display device.

According to the second aspect of the present invention, it is not necessary to hold all data of necessary correction data related to pixels that need correction in the first memory at a time. Further, according to the second aspect of the present invention, the correction data (compressed data) compressed from the second memory is decompressed into a part of the correction data and rewritten in the first memory, so that it is necessary. The increase in the size of the memory to be performed can be suppressed. In addition, according to the second aspect of the invention, the first memory and the second memory are provided and the correction data is held in the image display device, so that the compressed data can be reduced in order to reduce the storage capacity. Even when it is used, pixel brightness or color variation can be corrected without reducing the processing speed. Furthermore, it is possible to easily realize a configuration that performs both correction of variation in brightness and correction of variation in color.

According to the present invention, appropriate correction can be performed with a small amount of memory.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the following embodiments, the same or corresponding parts are denoted by the same reference numerals.

(First embodiment)
First, an image display apparatus according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram of the image display apparatus according to the first embodiment.

As shown in FIG. 1, the image display device according to the first embodiment includes image signal input terminals 1, 2, 2 to which primary color image signals of red (R), green (G), and blue (B) are input, respectively. 3, AD converters 4, 5, and 6, gradation correction units 7, 8, and 9, DA converters 10, 11, and 12, liquid crystal drive units 13, 14, and 15, liquid crystal display units 16, 17, and 18, synchronization signals The input terminal 19 and the microcomputer unit 21, and a timing signal generation unit 20 including a synchronization separation circuit 201, a PLL circuit 202, and a timing signal generation circuit 203 are configured.

Red (R), green (G), and blue (B) primary color image signals are input to the image signal input terminals 1, 2, and 3, respectively. These primary color image signals are supplied to the AD conversion units 4, 5, and 6 at the subsequent stage and quantized. In the first embodiment, the primary color image signals of red (R), green (G), and blue (B) are each quantized with 8 bits (8 bits).

Next, the quantized red (R), green (G), and blue (B) 8-bit digital image signals are supplied to the gradation correction units 7, 8, and 9, respectively. In the gradation correction units 7, 8, and 9, as will be described later, gradation correction and so-called screen uniformity correction such as brightness unevenness (brightness unevenness) and color unevenness between pixels are simultaneously performed. . In the first embodiment, the red (R), green (G), and blue (B) digital output image signals respectively output from the gradation correction units 7, 8, and 9 are 10 respectively. Output in bits (10 bits).

Next, 10-bit digital output image signals of red (R), green (G), and blue (B) in the gradation correction units 7, 8, 9 are respectively converted into red ( R), green (G), and blue (B) analog image signals. Subsequently, in the liquid crystal drive units 13, 14, and 15, polarity inversion and optimum level drive signals for the subsequent liquid crystal display units 16, 17, and 18 are appropriately generated and supplied to the liquid crystal display units 16, 17, and 18, respectively. It is displayed as a unique image of red (R), green (G), and blue (B).

The liquid crystal display units 16, 17, and 18 include a plurality of scanning lines and a plurality of data lines (none of which are shown), and pixel electrodes arranged in a matrix corresponding to the intersections of the scanning lines and the data lines. And a liquid crystal driving unit having a switching element, a data line driving circuit for supplying a data line signal or a scanning signal to a data line or a scanning line at a predetermined timing, a scanning line driving circuit, etc. This is a TFT liquid crystal display unit made of crystalline silicon or the like. In the first embodiment, the effective display area is described as red (R), green (G), and blue (B) as horizontal 1024 pixels and vertical 768 lines.

Next, the three-plate liquid crystal projector according to the first embodiment will be described. FIG. 2 shows an optical configuration example in the projection unit of the three-plate liquid crystal projector.

As shown in FIG. 2, the three-plate liquid crystal projector according to the first embodiment includes liquid crystal display units 16, 17, 18 corresponding to red (R), green (G), and blue (B), a metal halide lamp, and the like. The light source 1001 includes color separation dichroic mirrors 1002 and 1003, optical path changing mirrors 1004, 1005, and 1006, a cross dichroic prism 1007 that synthesizes three-color images, a projection lens 1008, and a screen 1009. ing.

In addition, the display images of the liquid crystal display units 16, 17, and 18 corresponding to red (R), green (G), and blue (B) are red (R) and green (G) in the projection optical system shown in FIG. ), Blue (B) inherent illumination light, a projection image is obtained, synthesized by a dichroic prism image synthesis unit, and projected and displayed on a screen as a color image.

Further, as shown in FIG. 1, the synchronization signal accompanying the input image signal input simultaneously with the input image signal described above is input as a composite synchronization signal from the synchronization signal input terminal 19 and input to the timing signal generator 20. The

Then, the sync separation circuit 201 separates the signal into a horizontal sync signal and a vertical sync signal. Of these signals, a basic clock signal having a frequency that is an integral multiple of the frequency of the horizontal synchronizing signal is generated in the PLL circuit 202 by the horizontal synchronizing signal and supplied to the timing signal generating circuit 203.

In the timing signal generation circuit 203, optimization of the clock phase is executed, and AD conversion units 4, 5, and 6, gradation correction units 7, 8, and 9, DA conversion units 10, 11, and 12, respectively, and a liquid crystal drive unit. 13, 14, 15, the liquid crystal display units 16, 17, 18, etc. are supplied at a predetermined timing and are driven. The setting of each unit shown in FIG. In the first embodiment, digital image signals may be input using a digital interface without using the AD conversion units 4, 5, and 6. Further, when the liquid crystal display units 16, 17, 18 and the image signal inputs of these drive units are digital signals, the DA conversion units 10, 11, 12 are not necessary.

(Tone correction part)
Next, the gradation correction units 7, 8, and 9 in FIG. 1 will be described. The configurations of the gradation correction units 7, 8, and 9 are the same as each other, and therefore the configuration and operation will be described using the red (R) gradation correction unit 7 as an example. FIG. 3 shows a circuit block configuration example of the red signal (R) gradation correction unit 7.

As shown in FIG. 3, the gradation correction unit 7 includes an image signal input unit 701 for a digitally converted red signal, a first look-up table (LUT) unit 702 as a first memory, and a second memory. The second LUT unit 706, the initial value generation unit 708, and the correction data reproduction unit 710 are configured. The second LUT unit 706 is used to store color unevenness and gradation correction value data in a display image in advance, and includes 256 memory cells 707 ranging from 0 to 255.

The initial value generation unit 708 includes 256 initial value setting units 709. The correction data reproducing unit 710 includes 256 switching circuits 712 from 0 to 255, an addition / subtraction circuit 713 as 256 arithmetic units from 0 to 255, and an output of the addition / subtraction circuit 713 as one pixel. The latch unit 714 includes 256 latch circuits 715 of 0 to 255 that are held for (one clock) period. Also, the red image signal output terminal 716 is connected to the DA converter 10 shown in FIG.

(First LUT part)
The first LUT unit 702 includes an address decoding unit 703 and a first memory table unit 704 including 256 memory cells 705 from 0 to 255. That is, the first LUT unit 702 receives an 8-bit (8 bit) digital image input signal (Di-R), decodes and outputs 256 parallel ports, and 0 to 255 levels. The first memory table section 704 is composed of 256 memory cells 705 corresponding to the key.

The address decoding unit 703 is a decimal demodulation circuit. That is, the 8-bit red input digital signal (Di-R) input to the address decoding unit 703 is demodulated in the address decoding unit 703 and output from a total of 256 demodulated demodulation output ports S0 to S255. The

Further, in FIG. 3, S0 input to the memory cell 705 is a gray scale with an input value of 0, and S255 is an active output when the input value has a maximum value of 255 gray levels. Similarly, the outputs of the other demodulation output ports S1 to S254 output active outputs from the ports corresponding to the demodulation output of the digital gradation value of the input digital signal (Di-R).

S0 is a gradation with an input value of 0, and S255 is an active output when the input value has a maximum value of 255 gradations. Similarly, regarding the outputs of the other demodulated output ports S1 to S254, the active output is output from the port corresponding to the demodulated output of the digital gradation value of the address decoding unit 703 of the red image input signal (Di-R). Is done. The first memory table portion 704 includes 256 memory cells 705 corresponding to gradations from 0 to 255. Hereinafter, each circuit block will be described as a hierarchy corresponding to each gradation of 0-255.

FIG. 4 shows the configuration of the memory cell 705. As shown in FIG. 4, the memory cell 705 has a 10-bit digital input terminal, one data output enable terminal, one clock input terminal, and a 10-bit digital output terminal.

The 10-bit digital input is input to a 10-bit latch circuit. The latch circuit can be configured by arranging 10 D flip-flops in parallel, and the output of the 10 D flip-flop circuits is one output of the memory cell 705 having 10-bit output. The output of the 10-bit memory cell 705 by the outputs from these 10 D flip-flop circuits outputs data with low impedance when activated by the data output enable terminal.

Also, the respective digital data output terminals of 256 memory cells 705 from 0 to 255 are connected in parallel, and the Do-R signal is output from the first LUT unit 702 shown in FIG. 3 as one output data bus. Is output to the subsequent DA conversion circuit (not shown in FIG. 3) via the image signal output terminal 716.

On the other hand, when the data enable terminal of one memory cell 705 shown in FIG. 4 is inactive, the 10-bit memory cell output becomes high impedance, and the output of the other active memory cell 705 is given priority.

In addition, 256 memory cells 705 are not activated at the same time, the memory cell 705 that matches the digital signal value of the input signal Di-R is activated, and the output digital signal Do-R is output in 10 bits. Is done. Data is written into the memory cell 705 by an active edge of a clock signal for each pixel input to the clock input terminal. Note that write data to the memory cell 705 is supplied from an addition / subtraction circuit 713 of a correction data reproducing unit 710 described later.

The first LUT unit 702 described above is sequentially rewritten to the output correction data of the addition / subtraction circuit 713 of the correction data reproduction unit 710 at high speed in units of pixel clocks in the display unit. With the correction data sequentially rewritten by the first LUT unit 702, tone correction and color / brightness unevenness correction (brightness variation correction) are performed on the red image input signal Di-R.

The first LUT unit 702 reads correction data from a correction data reproduction unit 710 (to be described later) at the data write timing using an address input of a random access memory (RAM) as an image input signal Di-R, At the read timing, the tone-corrected red image output signal Do-R is caused to function as an output.

(Second LUT part)
As shown in FIG. 3, the second LUT unit 706 includes 256 memory cells 707 having 0 to 255 hierarchies. These hierarchically provided memory cells 707 are distinguished from each other by being referred to as memory cells 707 of 0 to 255 levels.

In the second LUT unit 706, as will be described later, the gradation correction data of the display image is stored in advance corresponding to the pixels in the entire display screen. One memory cell 707 has the address space shown in FIG. Note that the effective scan line 768 line address configuration shown in FIG. 5 is L0 to L767, respectively. These scanning lines L0 to L767 have a data width of 2 bits (2 bits) of P and S. Therefore, the line address of the memory cell 707 is composed of L0P to L767P and L0S to L767S corresponding to the number of effective display scanning lines of 768 lines.

Next, each scan line address includes 10 initial data addresses L0PJ to L0PA of J, I, H, G, F, E, D, C, B, and A, and L0P0 to L0P0 corresponding to 1 to 1024 pixels. L0P1023 and 2048 pixel correction data addresses L0S0 to L0S1023.

(Initial value generator)
As illustrated in FIG. 3, the initial value generation unit 708 includes 256 initial value setting units 709 having 0 to 255 hierarchies. Each initial value setting unit 709 includes a shift register including 10 flip-flop circuits, and has a serial-parallel conversion function.

Further, the 10-bit initial value data of the addresses from J to A of the second LUT unit 706 is input as serial data to the shift register of the initial value setting unit 709 in units of pixel clocks, and is corrected later as 10-bit parallel data. The data is output to the first input of the switching circuit 712 of the data reproducing unit 710.

(Correction data playback section)
The correction data reproducing unit 710 uses the initial value data output from each of the 256 initial value setting units 709 in the 0 to 255 layers as the first input and the input from the second LUT unit 706 as the first input. It has 256 switching circuits 712 of 0 to 255 layers, which are 2 inputs.

The outputs of these switching circuits 712 are respectively supplied to the second inputs of 256 addition / subtraction circuits 713 in the 0-255 hierarchy. Each addition / subtraction circuit 713 includes a first input, a second input, and an addition / subtraction control terminal (not shown).

Here, in the first embodiment, “subtraction” is to subtract the second input value from the first input value of the addition / subtraction circuit 713. As the first input of each addition / subtraction circuit 713 in the 0-255 hierarchy, 256 outputs of the latch circuit 715 in the 0-255 hierarchy in the latch unit 714 described later are supplied.

In addition, data selected by the switching circuit 712 in the correction data reproducing unit 710 is input to the second input of the 256 addition / subtraction circuits 713 including the 0 to 255 layers.

The addition / subtraction control terminal (not shown) of the addition / subtraction circuit 713 receives S data sequentially from the 2-bit output from the second LUT unit 706. Of these 2-bit outputs of the second LUT unit 706, data specifying whether to add or subtract is stored in the S data table. The P data table stores absolute value data for addition / subtraction.

In this manner, the designation of addition or subtraction at the addition / subtraction control terminal of the addition / subtraction circuit 713 is sequentially supplied from the S data table of 2-bit (2-bit) output in each memory cell 707 of the second LUT unit 706. And controlled.

As described above, by the 256 addition / subtraction circuits 713 in the 0 to 255 hierarchy in the correction data reproducing unit 710, the result of addition or subtraction between the first input and the second input is obtained in the subsequent 0 to 255 hierarchy. The data is supplied to 256 latch circuits 715 and 10-bit data input terminals of 256 memory cells 705 corresponding to the 0-255 hierarchy of the first LUT unit 702.

(Latch part)
The latch unit 714 includes a 10-bit input terminal and a 10-bit output terminal, and 256 10-bit latch circuits 715 having 0 to 255 layers each having a clock terminal.

A 10-bit calculation output is input from the above-described addition / subtraction circuit 713 to the input terminal of the latch circuit 715. The inputted 10-bit data is taken into the internal latch circuit by the active edge of the clock inputted to the clock input terminal. The data is held until the active edge timing of the next clock, and is output from the output terminal of the latch circuit 715 to the first input terminal of the addition / subtraction circuit 713 corresponding to the 0 to 255 hierarchy in the correction data reproduction unit 710 described above. Supplied respectively.

The latch unit 714 is a data holding unit that holds data for one pixel clock period in the latch circuit 715 and provides the operation result of the addition / subtraction circuit 713 one pixel clock before to the addition / subtraction circuit 713. It is also possible to use a memory circuit, a delay circuit, a delay element, or the like.

Next, a specific gradation correction operation by the function of each unit shown in FIG. 1 configured as described above will be described.

(Measurement of display data and data processing)
In the display characteristics of the display device, first, the gradation correction of the gradation correction unit is turned off. next,
A red signal at the maximum input level of the display device is input from the test signal generator, and a display image is captured by, for example, a video camera and captured as a capture image on a PC, and display unevenness in the display area is measured.

Next, the output red signal level of the test signal generator is attenuated, and the measurement is similarly performed as (254/255). Sequentially, the output red signal of the test signal generator is attenuated to (253/255), (252/255), and (251/255), and the display unevenness of the display screen at each input level is measured. This measurement is performed until the output red signal level of the test signal generator becomes (1/255), (0/255). Similarly, for green (G) and blue (B), as described above, the green signal level and the blue signal level are 256 levels from (255/255) to (1/255) and (0/255), respectively. Measurements are made at.

As a result of the above measurement, display unevenness data for each color of red, green, and blue having an input level of 255 to 0 is taken into the PC. Next, color unevenness correction data is generated by a PC calculation.

In the first embodiment, the correction data group corresponds to the total number of pixels for horizontal 1024 pixels and vertical 768 lines corresponding to the number of display pixels. An example of the gradation correction characteristic of one pixel described above is shown in FIG. When the image has two-dimensional unevenness, this characteristic varies depending on the two-dimensional coordinates. In other words, it has three-dimensionality.

As shown in FIG. 6, examples of correction characteristics in the first embodiment include a degamma correction characteristic for an input image signal and a non-linear display characteristic that is a so-called voltage versus transmission (or reflection) characteristic of a liquid crystal display unit. The correction characteristic is included. In the first embodiment, the input image signal is generated with a gradation of 8 bits and a corrected gradation output of 10 bits.

(Writing display correction data to the second LUT unit)
In addition, the correction data corresponding to the above-described correction characteristics shown in FIG. 5 is a total of 786432 2 bits each indicated by P and S in 256 memory cells 707 in the 0-255 hierarchy of the second LUT unit 706. Are written to a total of 7680 initial value data address configurations in 2 bits indicated by the pixel-corresponding gradation correction address and P and S corresponding to each scanning line.

In the second LUT unit 706 described above, the memory of the 256 memory cells 707 in the 0 to 255 levels is, for example, ROM (read only memory), EEPROM (electrically rewritable read only memory), EPROM, or one-time ROM. And a memory such as a flash memory. These memories are classified as non-volatile memories. In such a memory, data is written in a data format to be described later by calculation and processing of the PC.

Furthermore, in a third embodiment to be described later, the second LUT unit 706 can be configured by a random access memory (RAM). In such a case, the data is read from the storage unit in the same device via the microprocessor or the like to be described later when the device is turned on or based on an arbitrary setting condition, and the second LUT configured from the RAM is read. This is possible by writing data in the unit 706.

(Initial correction data)
In the address configuration of each memory cell 707 of the second LUT unit 706 shown in FIG. 5, first, before the pixel address 0 corresponding to the first effective display pixel in each horizontal scanning period, J to A Ten addresses are provided, and gradation correction initial data is generated for this period.

(hierarchy)
The gradation correction data in this case is composed of 256 layers from 0 to 255 corresponding to the gradation of the input image signal to the gradation correction unit 7 shown in FIG. That is, as shown in the example of the gradation correction characteristics of one pixel in FIG. 6 described above, the gradation levels of all 256 gradations of 8 bits of the image input signal (Di-R) to the gradation correction unit 7 are as follows. Are assigned to 256 memory cells 707 of 0 to 255 in the second LUT unit 706, respectively.

Next, as one layer generated by the above-described PC, FIG. 5 shows an address configuration using the memory cell 707 in the 255th layer corresponding to the 255th gradation as an example.

(Address configuration)
As shown in FIG. 5, L0P as the first bit of L0 corresponding to the first scanning line of the display image first stores data for a total of 10 bits for the initial value data address period J to A respectively. Store at address. In the hierarchy of 255, as an example of the correction data, from the correction characteristic shown in FIG. 6 described above, the maximum value is 1023. First, in L0P, “1, 1, 1, 1, 1, 1, 1 , 1, 1, 1 "are stored at addresses J to A, respectively.

In the example shown in FIG. 5, the data is arranged with the address A side closest to address 0 as the LSB value. Further, the data of the addresses J to A of L0S is an unquestioned period in which no data exists in the first embodiment.

In addition, for the effective display pixel addresses 0 to 1023 following the address data from J to A of L0P and L0S, correction data is stored in 2 bits as P and S in each pixel. Here, S indicates designation data indicating whether the correction value is increased or decreased by “1” when increasing and “0” when decreasing, and P is “1” or “0” as the absolute value of the change value for the previous pixel. Is shown.

That is, when the value of the second pixel is “1022” with respect to the initial value (first pixel) “1023” as the gradation correction value of the line address L0, the address of L0P1 is “1” and the address of L0S1 is “0” is used as correction data. Similarly, correction data of L0P2 to L0P1023 and L0S2 to L0S1023 are recorded.

The above is an example of the configuration of the correction data address in one horizontal period of the 255th layer. Then, as shown in FIG. 5, 10 initial value addresses from J to A and pixels from 0 to 1023 are used as line addresses L1P to L767 and L1S to L767S from 2 lines to 768 lines following one line. A total of 1034 data of correction value addresses are recorded.

(Example of horizontal unevenness correction data)
As an example, a correction characteristic that finally attenuates by 20% from the left to the right of the display image (specifically, from pixel address 0 to address 1023) is required from the color unevenness data obtained by measurement when the correction data is red. In this case, if the change value per pixel is expressed by a quantization level, the maximum value is set to 1024 levels (1024 × 0.2) /1024=0.2.
Thus, the quantization level is 0.2.

Further, the minimum level unit handled in the first embodiment is one quantization level value, and the number of target pixels in the horizontal direction until the one quantization level fluctuates is from 1 / 0.2 = 5. ,
The data attenuates by about 1 every 5 pixels.

Specifically, for example, by the program operation of the personal computer (hereinafter referred to as PC), the addresses from J0 to L0P of the memory cell 707 of the second LUT unit 706 described above are set to 1023 in decimal as described above. It corresponds to. “1,1,1,1,1,1,1,1,1,1” (MSB: LSB) is stored in order with address J as MSB and address A as LSB.
Next, 0 at the address L0P0
0 at address L0P0,
0 at address L0S0,
0 at address L0P1,
0 at address L0S1;
0 at address L0P2.
0 at address L0S2,
0 at address L0P3,
0 at address L0S3,
0 at address L0P4,
0 at address L0S4,
1 at address L0P5
0 at address L0S5,
0 at address L0P6,
0 at address L0S6,
In other words, the data structure that attenuates by 1 every 5 line addresses is stored by the PC up to the address L0P1023 and the L0S address 1023, respectively. This example is an example on the premise that there is no color unevenness in the vertical direction of the screen, that is, in the vertical direction of the screen from the first line to the 768th line. The correction values include L1P to L767P and L1S to L767S. Similar correction data is written. The correction data described above is data writing related to the 255th layer.

Similarly, the correction data of each layer shown in the example of the gradation correction characteristics shown in FIG. 6 is written into each memory cell 707 corresponding to the layer from 254 to 0.

(Example of vertical unevenness correction data)
Next, for example, when the correction data along the vertical direction are different, taking as an example a case where the first line is the maximum level of 1023 and the final line (768th line) is linearly attenuated to 20%. The initial value of the eye is 1023, and the attenuation value of the second line is (1024 × 0.2) /768=0.2666, which is 1023 because the attenuation is less than one level. Similarly, for the third line, the initial value is 1023, and since 1 / 0.2666 = 3.75, the level is attenuated by 1.75 pixels, so the initial value is the fourth line. 1022. Similarly, it is 1022 in the fifth line, and is attenuated by 2 in the 7.5th pixel. Therefore, it becomes 1021 in the 8th line.

As a result, the initial value of the 768th line is (1024 × 0.2) /768=0.2666, 1023- (1024 × 0.2) = 818.

Therefore, first, initial value data of the first line is stored with initial value addresses L0PJ to L0PA of “1023” in the decimal value of 10 bits. Thereafter, “1023” is stored as a decimal value in 10 bits for each of the initial value addresses L1PJ to L1PA and the initial value addresses L2PJ to L2PA.

Also, “1022” is stored as a decimal value in the initial value addresses L3PJ to L3PA of the fourth line. In the initial value addresses L4PJ to L4PA, the initial value addresses L5PJ to L5PA, and the initial value addresses L6PJ to L6PA, “1022” is stored as a decimal value. In the initial value addresses L7PJ to L7PA of the eighth line, “1021” is stored as a decimal value. The initial value addresses L767PJ to L767PA in the 768th line store the decimal value “718”.

Each pixel correction address corresponding to pixels 1 to 1024, LXP0 to LXP1023, and LXS0 to LXS1023 (where X is a line address value) following the 10 bits from the initial value J to A of the line address. , And stored as a difference value between the pixels in the horizontal direction described above.

Further, as described above, the 256 memory cells 707 from the 0th to 255th layers of the second LUT unit 706 include initial value data of each scan line and a difference between each pixel in the horizontal direction. The gradation correction data as values is written as a 256-layer data table.

(Data writing)
The writing is performed from the PC by the communication control of the microcomputer unit 21 through the interface. A similar function can be obtained even if a pre-written ROM or flash memory is mounted.

The memory of the second LUT unit 706 is configured by a memory such as a ROM (read-only memory), an EEPROM (electrically rewritable read-only memory), an EPROM, a one-time ROM, or a flash memory. These memories are classified as non-volatile memories. These memories are written in a data format to be described later based on the above-described calculation by the PC. Furthermore, in a third embodiment to be described later, the second LUT unit 706 is configured by a random access memory (RAM).

(Read correction data)
As described above, the “difference value data” in the gradation correction value one pixel before written in the second LUT unit 706 shown in FIG. 3 is the timing signal generation unit shown in FIG. In synchronization with the horizontal synchronization and vertical synchronization from 20, the data is read according to the read timing of the clock signal, and supplied to the initial value generation unit 708 as the data of the respective layers described above. The timing of read data in this case is shown in FIG.

In FIG. 7, data P and data S are sequentially read out along the memory address shown in FIG. 5 as a data string in units of clock signals. The read timing is generated and supplied from the timing generation circuit 203 shown in FIG.

(1) First, although not shown in the drawing, in accordance with the vertical image start timing, the memory addresses J, I, H, G, F, E, D, C, B, and A are initialized from the horizontal reading start pulse of the first scanning line. The value data address is read, and correction value addresses up to 0, 1, 2, 3, and -1023 are read. The read correction value data is output with 2 bits of data P and data S for each layer as described above.

(2) After reading to the correction value address 1023, the reading is waited until a horizontal synchronous read start pulse for the next scanning line is generated.

(3) From the horizontal readout start pulse of the second horizontal line, in the same manner as in (1),
The initial value data addresses of memory addresses J, I, H, G, F, E, D, C, B, and A of the second line are read and corrected to 0, 1, 2, 3,. The value address is read.

(4) Similarly, the third horizontal line to the 768th line are read out, and the readings (1) to (4) are executed according to the clock timing at every vertical synchronization timing.

(Initial value generation)
As described above, the correction data read from the memory cells 707 in the 0th layer to the 255th layer in the second LUT unit 706 is supplied to the initial value generation unit 708. The memory addresses J, I, H, G, F, E, D, C, B, and A described above are added to the shift registers of the initial value setting unit 709 provided in the respective levels 0 to 255 of the initial value generation unit 708. The read initial value data P at the address is sequentially input for each clock and stored as serial data in 10 flip-flop circuits (hereinafter Q1 to Q10).

For each of the memory address timings J, I, H, G, F, E, D, C, B, and A shown in FIG. 7, the data stored in the respective flip-flop circuits Q1 to Q10 of the initial value setting unit 709 is stored. Examples are shown as Q1-Q10 in FIG. As described above, the data P of the first line of the memory of the hierarchy 255 is 1, 1, 1, 1, in address reading of J, I, H, G, F, E, D, C, B, A. It is sequentially read out as 1, 1, 1, 1, 1, 1, data.

Further, the data of all the shift registers Q1 to Q10 are stored by reading the address A, and the second timing of the addition / subtraction circuit 713 is passed through the switching circuit 712 at the timing of accessing the memory address 0 which is the next timing. Input to input.

At this stage, the output of the latch circuit 715 is input to the first input of the addition / subtraction circuit 713. At the timing of accessing the memory address 0, the latch circuit 715 is immediately after reset, and the addition / subtraction circuit 713 is obtained as 10-bit parallel data of 0, 0, 0, 0, 0, 0, 0, 0, 0, 0. To the first input.

Therefore, at the timing of accessing the memory address 0, the output of the addition / subtraction circuit 713 is “1, 1, 1, 1, 1, 1, 1” input to the second input of the addition / subtraction circuit 713. , 1, 1, 1 "is output. The decimal value “1023” is shown in the first input value of the addition / subtraction circuit 713 at the pixel address timing 0 and the output of the addition / subtraction circuit 713 shown in FIG.

Through the above operation, the correction value data of the layer 255 at the timing of the address 0 of the line 0 is output from the addition / subtraction circuit 713 and stored in 255 10-bit inputs in the table of the 255 layer of the first LUT unit 702. The

At the same time, the data at the pixel address timing 0 output from the addition / subtraction circuit 713 of the correction data reproducing unit 710 is taken into the latch circuit 715 of the hierarchy 255 of the latch unit 714 by the clock signal timing and until the next clock. Stored. Thereafter, the latch circuit 715 stores the output data of the addition / subtraction circuit 713 in the corresponding hierarchy in the correction data reproducing unit 710 connected for each clock for one clock period.

(Generation of correction value from difference value)
Thereafter, as shown in the data reproduction timing in FIG. 7, at the pixel address timing 1 of the line address L0 of the memory cell 707 in the second LUT unit 706, the data P is output as “0” and the data S is “ 1 "is output. With this data S, designation of addition or subtraction in the addition / subtraction circuit 713 of the hierarchy 255 of the correction data reproducing unit 710 is performed. In the designation in the first embodiment, 1 functions as addition and 0 functions as subtraction.

The data P is input as 1-bit difference value data, the correction value data P read at this timing is 0, and the output of the addition / subtraction circuit 713 of the layer 255 is “1, 1, 1, 1, 1 , 1, 1, 1, 1, 1, (MSB: LSB) ”as the decimal value“ 1023 ”as it is, the correction value data in the layer 255 at the pixel address timing 1 of the line address L0 is The data is output from the addition / subtraction circuit 713 of the correction data reproducing unit 710 and stored as 10-bit data in the memory cell 705 in the 255th layer of the first LUT unit 702.

Similarly, “0” is output to the data P and “0” is output to the data S at the pixel corresponding address timings 1 to 4 of the line address L0.

Therefore, the output of the addition / subtraction circuit 713 of the layer 255 in the correction data reproducing unit 710 is not changed, and the decimal value “1023” is a memory cell in the 255th layer of the layer from 0 to 255 of the first LUT unit 702. The data is sequentially written by inputting 705 10-bit data.

Next, at the pixel corresponding address timing 5 of the line address L0, the data P outputs “1”, and the data S outputs “0”. This data S is supplied to the addition / subtraction control terminal of the addition / subtraction circuit 713. Accordingly, the addition / subtraction circuit 713 of the hierarchy 255 in the correction data reproducing unit 710 subtracts the second input data from the first input data. Then, the value “1023” of the timing one clock before is input to the first input. Also, the value “1” is input to the second input. On the other hand, the output of the addition / subtraction circuit 713 of the layer 255 in the correction data reproducing unit 710 is (1023-1 =) 1022. This value is stored in the memory cell 705 in the 255th layer of the first LUT unit 702.

Next, the pixel address timings 6 to 9 of the line address 0 have no addition / subtraction, and the output of the addition / subtraction circuit 713 of the layer 255 in the correction data reproducing unit 710 remains 1022, and this value is the first LUT unit 702. Are sequentially written in the memory cell 705 of the 255th hierarchy. At the pixel address timing 10, the data P becomes “1” and the data S becomes “0”, and the addition / subtraction circuit 713 performs 1 subtraction to output “1022”, which is the first LUT unit 702. Stored in the memory cell 705 of 255 levels.

Thereafter, in the first embodiment, until the pixel address timing 1023 of the line address L0, the data P becomes 1 and the data S becomes 0 once every 5 pixel clock timings, and the correction data reproducing unit 710 has 255 layers. In the addition / subtraction circuit 713 of the eye, 1 is subtracted from the data output value before one clock timing, and this value is sequentially written into the memory cell 705 in the 255th layer of the first LUT unit 702.

Similarly, the data in the memory cell 707 is read from the line addresses L1 to L767, the correction value is reproduced, and sequentially stored in the memory cell 705 in the 255th layer of the first LUT circuit 702.

As described above, the initial value data of the correction values of the respective scanning lines in the 256 layers written in the 256 memory cells 707 of the 0th to 255th layers of the second LUT unit 706 and the respective pixels A gradation correction difference value between addresses is generated as a gradation correction value for each pixel in 256 addition / subtraction circuits 713 from 0 to 255, and 256 memory cells 705 of the first LUT unit 702 are generated. In addition, writing is sequentially performed at each pixel clock timing.

(Gradation correction in the first LUT)
On the other hand, in the first LUT unit 702, the 8-bit red image signal Di-R is input to the address decoding unit 703 shown in FIG. 3, and the input image input signal Di-R is decoded in the address decoding unit 703. Is done.

In each memory cell 707 of the second LUT unit 706, the input value of the 8-bit red image input signal Di-R at the timing of the memory address 0 as the first pixel in the display unit of the line address L0. Is 1, 1, 1, 1, 1, 1, 1, 1 (MSB: LSB) 8 bits, the decode value of the address decode unit 703 is “255”, and the output signal of this address decode unit 703 S255 becomes active, and output enable of the memory cell 705 in the 255th layer of the first LUT unit 702 becomes active. From the memory cell 705 in the 255th hierarchy, the 11-bit output correction value “1, 1, 1, 1, 1, 1, 1, 1, 1, 1” (MSB: LSB) from the addition / subtraction circuit 713 is stored. The parallel red image output signal Do-R is supplied to the subsequent DA converter 10 via the image signal output terminal 716, and after DA conversion, the liquid crystal drive signal of the liquid crystal driver 13 is obtained to obtain the liquid crystal It is supplied to the display unit 16.

The 255-bit 10-bit digital output of each memory cell 705 of the first LUT unit 702 is connected in parallel in units of binary values to form a 10-bit data bus. Of the 255 memory cells 705, only one is selected by the address decoding unit 703 described above.

Next, similarly, the input value of the 8-bit red image signal Di-R that is input via the image signal input unit 701 for the red signal from the first pixel to the 1024th pixel of the L0 is displayed. In the first embodiment, assuming a 100% white signal, a binary value of 1,1,1,1,1,1,1,1,1 (MSB: LSB) decimal value of “255” is used. In the first memory table unit 704, the memory cell 705 in the 255th layer is always active.

That is, the output gradation correction data value of the first LUT unit 702 at the timing of the pixel address 0 of the display line address L0 is “1023”, and the pixel address is decreased by 1 to 5 addresses thereafter, and the pixel address 1023 Decreases to about “818”.

Similarly, the unevenness-corrected red image output signal Do-R output from the first LUT unit 702 for display line addresses 1 to L767 is output in the same manner as the line address L0 in the first embodiment. After the value is supplied to the DA converter of the rear stage 10 and DA converted, the liquid crystal drive signal of the liquid crystal driver 13 is obtained and supplied to the liquid crystal display 16 to display an image.

Displayed on the liquid crystal display units 17 and 18, respectively, without being corrected for other green and blue unevenness, and projected.

As described above, in the color unevenness according to the first embodiment in which the color unevenness described above becomes reddish from the left to the right of the screen and the red component increases by 20% at the right end of the screen, the right end of the screen with respect to the left end of the screen. The display screen of the display device at the output value of the output red image signal Do-R in the first LUT unit 702 is determined by the output value of the linearly and slowly changing red image output signal Do-R with 20% attenuation. The left and right color unevenness is corrected to obtain a uniform white image.

Similarly, in the case of the input level “254”, 10-bit data of the memory cell 705 in the 254th layer of the first LUT unit 702 is output as a red image from the first LUT unit 702 of the gradation correction unit 7. It is output as signal Do-R. Hereinafter, also at the input levels “253” to “0”, 10-bit data of each of the memory cells 705 in the hierarchy “253” to “0” of the first LUT unit 702 corresponding to the input level is output. The uneven color of the display image is corrected.

In the above example, regarding the color unevenness in red, the color unevenness is reduced by correcting the gradation correction characteristics of the red image signal in units of pixels, but the red, green, and blue image signals are reduced. The gradation correction characteristics are performed in units of pixels by the gradation correction units 7, 8, and 9 shown in FIG. 1, respectively, so that display is performed for all gradations of all colors corresponding to the logical level of the input image. Color unevenness correction with high image accuracy can be realized.

As described above, in the configuration of this embodiment, correction data for correcting an image signal for designating the gradation level of a predetermined pixel is stored in the first LUT unit that is the first memory. . In the first memory, a plurality of correction data respectively corresponding to a plurality of gradation levels that can be taken by the image signal are stored in advance in a second LUT unit (corresponding to a plurality of pixels and each pixel). The correction data corresponding to each gradation level is compressed and held) and held at the same time. However, in order to reduce the capacity of the first memory, decompression of compressed correction data to an uncompressed state (making it easier to use than compressed correction data) corresponds to all pixels. Thus, it is configured not to perform in advance.

That is, paying attention to the point that it is only necessary to sequentially correct the image signal sequentially input as the image signal corresponding to each pixel, the expansion of the compressed data into the first memory may be performed on some pixels (one or a plurality (compressed)). In consideration of the calculation time for data expansion, a plurality of pixels (not all pixels of the display device) may be expanded.In this case, the first memory stores each gradation of each of the plurality of pixels. It has a capacity to hold correction data corresponding to the level simultaneously))). Since a configuration in which compressed correction data corresponding to all pixels is not expanded in advance is adopted, the memory capacity can be greatly reduced. Furthermore, by developing in advance correction data corresponding to each gradation level of the pixel to which the image data to be corrected corresponds, it is possible to perform correction that exactly corresponds to the gradation level that the image signal can take. It has become.

(Second Embodiment)
Next explained is a display device according to the second embodiment of the invention. In the display device according to the second embodiment, the same configuration as the overall signal processing configuration shown in FIG. 1 in the first embodiment is adopted, and the configuration operations of the gradation correction units 7, 8, 9 are performed. Different. Note that the number of display pixels of the display unit in the display device according to the second embodiment is 1920 pixels in the horizontal direction and 1080 lines (pixels) in the vertical direction. Further, in the case of a three-plate projection, each display unit has the number of pixels.

FIG. 8 shows a red signal system gradation correction unit according to the second embodiment. As shown in FIG. 8, the red image signal input unit 701 is an input unit to which an input image signal is input from the preceding AD conversion unit 4. Then, the Di-R signal is input as an 8-bit red digital image signal through this input unit, and is supplied to the first LUT unit 702.

(First LUT part)
As shown in FIG. 8, the first LUT unit 702 has the same configuration as that of the first embodiment. Similarly to the first embodiment, 10-bit correction data is supplied to the first LUT unit 702 from the correction data reproduction unit 710 in units of pixel clock timing for each layer. The 256 memory cells 705 provided in the first LUT unit 702 from 0 to 255 are controlled so as to be rewritten sequentially in units of pixel clock timing.

(Second LUT part)
Next, the second LUT unit 706 will be described. The second LUT unit 706 stores gradation correction data of a display image for 256 image input gradations in advance, and 256 memory cells 707 for a total of 256 layers corresponding to the gradations of 0 to 255. Is provided.

The second LUT unit 706 according to the second embodiment differs from the second LUT unit 706 according to the first embodiment in the memory address structure of one memory cell of the memory cell 707. FIG. 9 shows this memory address structure. FIG. 9 is a model of the memory address configuration of the memory cell 707 corresponding to one layer of the second LUT unit 706 shown in FIG. In the second embodiment, the gradation correction data for one pixel of the memory cell 707 is composed of 4 bits. Hereinafter, these 4-bit correction data are referred to as P0, P1, P2, and P3, respectively.

The number of pixels in the vertical direction of the display screen, that is, the number of horizontal lines is 1080 lines, and the number of pixels arranged in the horizontal direction is 1920 dots. First, addresses L0 to L1079 corresponding to scanning lines from 1 to 1080 are provided, and each line L0 to L1079 has a 4-bit data width indicated by P0, P1, P2, and P3 as described above. .

The address L0 corresponding to the first line includes the line addresses L0P0, L0P1, L0P2, and L0P3. Similarly, the second line includes line addresses L1P0, L1P1, L1P2, and L1P3. Similarly, the 1080th line includes L1079P0, L1079P1, L1079P2, and L1079P3.

The line addresses from L0P0, L0P1, L0P2, L0P3 to L1079P0, L1079P1, L1079P2, and L1079P3 are 10 pixel clocks indicated by J, I, H, G, F, E, D, C, B, and A, respectively. It has 10 initial value addresses corresponding to the period.

This line address has correction data pixel addresses corresponding to 1920-dot display pixels arranged in the horizontal direction of the display screen from 0 to 1919, respectively. Here, unlike the first embodiment, the correction data pixel address is compressed and stored as 4-bit correction data indicated by P0, P1, P2, and P3 for the horizontal display pixels from 1 to 1920. Thus, the storage address is small with respect to the compression rate corresponding to the 1920 horizontal pixel array. This address is indicated by a numerical value of 0 to n, and n changes according to the change state of the gradation correction value of each pixel in the horizontal pixel direction of the correction data.

(Initial value generator)
The initial value generation unit 708 according to the second embodiment illustrated in FIG. 8 includes 256 initial value setting units 709 as in the first embodiment.

This initial value setting unit 709 is given to one memory cell 707 among the memory cells 707 corresponding to the respective layers 0 to 255 in the second LUT unit 706 described above, as shown in FIG. The initial value data of 10 bits at the initial value address of .about.A is fetched as a 10-bit shift register. Then, the initial value generation unit 708 converts the data into 10-bit parallel data, and the first input of the switching circuit 712 of the correction data reproduction unit 710 connected to each initial value setting unit 709 as shown in FIG. To supply.

(Data playback part)
Similarly to the 256 decompression processing units 711 provided corresponding to the 0 to 255 levels, the correction data reproducing unit 710 includes 256 switch circuit units 764 provided corresponding to the 0 to 255 levels. , And 256 addition / subtraction circuits 713 provided corresponding to the hierarchy of 0 to 255.

In the correction data reproducing unit 710, the outputs from the 256 initial value setting units 709 from 0 to 255 of the initial value generation unit 708 are the 256 switching circuits 712 from 0 to 255 as the first input. Are input in accordance with each hierarchy.

Read data from each of the 256 memory cells 707 of the second LUT unit 706 is supplied to the decompression processing unit 711. The output of the decompression processing unit 711 is supplied as a second input to 256 switching circuits 712 corresponding to the 0 to 255 hierarchies.

The outputs from the 256 switching circuits 712 corresponding to the 0 to 255 hierarchies are supplied to the second input of the addition / subtraction circuit 713 as the 256 arithmetic units provided corresponding to the 0 to 255 hierarchies. Is done. Then, the outputs of 256 latch circuits 715 in the 0th to 255th hierarchies of the latch unit 714 in the subsequent stage are supplied to the first inputs of the addition / subtraction circuits 713 in the corresponding hierarchies.

The outputs of the 256 addition / subtraction circuits 713 are branched into two, and one is supplied to the data input of the memory cell 705 in the corresponding hierarchy of the first LUT unit 702. The other is input to 256 latch circuits 715 in the 0-255 hierarchy of the latch unit 714.

(Latch part)
As in the first embodiment, the latch unit 714 according to the second embodiment includes 256 10-bit latch circuits 715 of 0 to 255 levels each having a 10-bit input terminal, a 10-bit output terminal, and a clock terminal. It is comprised.

Further, as described in the correction data reproducing unit 710, the data input of each of the 256 latch circuits 715 in the 0-255 hierarchy is a 10-bit operation output from the 256 addition / subtraction circuits 713 in the 0-255 hierarchy. Are supplied respectively.

The 10-bit data input to the latch circuit 715 is taken into the latch circuit 715 by the active edge of the pixel timing clock input to the clock input terminal of the latch circuit 715. Further, the data is held until the active edge timing of the next pixel timing clock, and the data is delayed by one pixel timing period from the output terminal of the latch circuit 715, and each of the 0 to 255 layers of the correction data reproducing unit 710 is provided. The signals are respectively supplied to the first input terminals of the connected addition / subtraction circuit 713.

That is, the period data of one pixel clock is held, and the calculation result of the addition / subtraction circuit 713 of the correction data reproduction unit 710 before one pixel clock is provided to the addition / subtraction circuit 713 of the correction data reproduction unit 710.

Next, a specific gradation correction operation in the display device according to the second embodiment configured as described above will be described.

(Measurement of display data and data processing)
As in the first embodiment, the display characteristic before correction of the display device is measured, for example, when a red signal of the maximum input level of the display device is input from a test signal generator, and a display image is captured by, for example, a video camera or the like. Then, it is captured as a captured image by a computer (hereinafter referred to as PC), and the display unevenness of the display area is measured.

Next, the output red signal level of the test signal generator is attenuated in steps, and the measurement is similarly performed as (254/255). Then, the output white signal of the test signal generator is sequentially attenuated to (253/255), (252/255), and (251/255), and the display unevenness of the display screen at each input level is measured. This measurement is performed until the output white signal level of the test signal generator becomes (1/255), (0/255). Similarly, for green and blue, the measurement is performed at 255 levels from (254/255) to (1/255) and (0/255).

Through the above measurement, display unevenness data of red, green, and blue colors with input levels from 255 to 0 are captured in the PC.

Next, color unevenness correction data is generated by a PC calculation. The correction data in this case is a correction data group corresponding to the total number of pixels for horizontal 1920 pixels and vertical 1080 lines corresponding to the number of display pixels of the second embodiment. An example of gradation correction for one pixel is shown in FIG.

This correction characteristic includes a degamma correction characteristic for the input image signal and a correction characteristic for a non-linear display characteristic which is a so-called voltage versus transmission (or reflection) characteristic of the liquid crystal display unit in the second embodiment. In the second embodiment, the input image signal is generated with a gradation of 8 bits and a corrected gradation output of 10 bits.

Further, in order to write the generated data as display correction data to the second LUT unit 706 in the PC, the data is converted into a predetermined format. Hereinafter, writing of the data into the second LUT unit 706 will be described.

(Write display correction data to the second LUT)
Next, the display correction data writing operation to the second LUT unit 706 will be described. That is, as described in the configuration of the second LUT unit described above, the correction data address configuration of 256 memory cells 707 corresponding to the 0 to 255 levels of the second LUT unit 706 as shown in FIG. On the other hand, the line addresses from L0P0, L0P1, L0P2, L0P3 to L1079P0, L1079P1, L1079P2, and L1079P3 are indicated by J, I, H, G, F, E, D, C, B, and A, respectively. For 10 initial value addresses corresponding to 10 pixel clock periods, 10-bit initial values of gradation correction values of the respective lines are sequentially stored.

In the second embodiment, as shown in FIG. 9, the address configuration has a 4-bit data width indicated by P0, P1, P2, and P3. However, in order to avoid complicated explanation, In the following description, only 1 bit is targeted for the initial value data address, and the other 3-bit data widths of P1, P2, and P3 are not questioned. That is, it is an unnecessary address and can be deleted.

The initial value of each line in each layer is 10 bits. For this reason, if all the bit data widths of P0, P1, P2, and P3 are used, a data area corresponding to three clocks of C, B, and A for each line address is sufficient. In this case, C-stage, B-stage, and 3-stage capture are executed in the 4-bit latch circuit so that the data is read out simultaneously as parallel data in accordance with the initial pixel display, that is, the timing of address 0 in the horizontal direction. Similarly, the initial value data can be reproduced. Therefore, the remaining 28 bits of the initial value address of J, I, H, G, F, E, and D, which is a total of 28 bits, reduce the memory. In all screens, the number of lines is 30240 bits, and in all layers, 7741440 bits are reduced.

Next, after the corrected initial value address of each line indicated by J, I, H, G, F, E, D, C, B, and A, from the first pixel after the initial value to the 1920th pixel Is stored as correction data having a 4-bit data width indicated by P0, P1, P2, and P3.

The correction values from the first pixel to the 1920th pixel written in 4 bits are indicated by whether the data value is increased by 1 or decreased by 1 or not changed as shown in FIG. The data of the number of pixels up to is provided. Therefore, instead of the data value for each pixel as described in the first embodiment, compression is performed according to the amount of change in the correction value, and correction values for a plurality of pixel periods are recorded at one address. Therefore, the data amount of gradation correction data for the entire screen is reduced. That is, as described in the first embodiment, it is not necessary to have all the pixel addresses fixed for each line address, and the data amount in the pixel address direction is constant depending on the change value of the correction data. Don't be.

With the data format in the horizontal direction as described above, 1080 lines of data are written in the vertical direction. The correction data for one layer described above is a storage format stored in one corresponding memory cell 707. Further, the data for the remaining 254 layers are similarly recorded in 254 memory cells 707 as correction values for the respective layers.

(Example of correction data)
Next, generation of the correction data and writing to the memory cell will be described. In the generation of the correction data and the writing to the memory, the process until the correction data required from the color unevenness data obtained by measurement is written will be described below using red as an example. As an example here, the screen unevenness is an example of correction of a display image in which the white balance on the left side of the screen has a white balance and redness increases as it goes to the right side of the display screen even though a white signal is input. It is.

First, paying attention to the hierarchy of the maximum display level, as a result of this measurement, the hierarchy of the maximum display level is the red signal from the left to the right of the display image, specifically, from the horizontal pixel address 0 to the horizontal pixel address 1919. When a correction characteristic for attenuating the signal level by 20% with respect to the final horizontal address 1919 is required,
The amount of attenuation during the horizontal display period is
All gradations × attenuation amount = (1023 × 0.2) = 204.6 (quantization level)
The amount of reduction per pixel is
Reduction amount in horizontal display period / number of horizontal effective pixels = 204.6 / 1920≈0.1065
Approximate number of pixels that change one quantization level 1 ÷ 0.1065≈9.38
Thus, the data attenuates by about 1 every 9.38 pixels.

Further, as described above, the initial value data address indicated by J, I, H, G, F, E, D, C, B, A of L0P0 is set to 1023 in decimal notation by the PC application software. “1,1,1,1,1,1,1,1,1,1,1” is stored, assuming that the value corresponding to is binary, J is MSB, and A is LSB.

Following the initial value data address described above, the correction data from 1 pixel to 1920 pixels is encoded and recorded based on the table shown in FIG.

In the table of FIG. 10, a process for reading and reproducing previously recorded data is defined for a code indicated by a 4-bit data value indicated by P3, P2, P1, and P0.

First, the correction value address 0 of addresses L0P0, L0P1, L0P2, and L0P3 corresponding to the first line is given as 0111 (P3 to P0). The correction value address 1 to be reproduced next is given data as 0100 (P3 to P0). The meanings of these symbols are “6 progress without change” and “4 forward 1 decrease”, as shown in the table of FIG.

Similarly, the correction value address 2 of the addresses L02P0, L2P1, L2P2, and L2P3 corresponding to the first line is given as 0111 (P3 to P0). The correction value address 3 to be reproduced next is given as 0100 (P3 to P0). Similarly, 0111 (P3 to P0) and 0100 (P3 to P0) are alternately stored up to the memory address 191 of the correction value. Thus, the initial value and correction data for one line are configured.

In this case, there is no color unevenness in the vertical direction of the screen, that is, in the direction from the first line to the 1080th line, and the initial value data and correction value data similar to those for the first line are recorded as correction values. The correction data described above is data writing related to the hierarchy of 255.

Similarly, the initial value data and the correction value data are recorded for the layers from 254 to 0 as well. If attention is paid to one pixel in the 254 to 0 layers and the gradation characteristics thereof are observed, for example, the characteristics shown in FIG. 6 are obtained.

In FIG. 6, the X axis is an input, and the Y axis is a gradation correction value. The X-axis input indicates the input level of the gradation correction unit 7 and is a maximum of 255 quantization levels. The Y-axis gradation square value is indicated by a signal level, and the Y-axis gradation correction value level is 1023 at the maximum. This characteristic changes depending on the pixel.

Next, when the correction data is different in the vertical direction, specifically, for example, when the first line has a maximum level of 1023 and the 1080th line as the final line linearly attenuates to 20%, (1024- (L × ((1024 × 0.2) / 1080))). Here, L is the number of lines.

Hereinafter, when the initial value for each scanning line is expressed to 3 digits after the decimal point,
The initial value of the first line is 1023
The initial value for the second line is 102.81.
From the third line,
3rd line: 1022.621
Fourth line: 1022.432
5th line: 1022.242
6th line: 1022.053
7th line: 1021.863
9th line: 1021.674
10th line: 1021.484
11th line: 1021.295
12th line: 1021.106
13th line: 1029.916
14th line: 1027.727
15th line: 1020.537
16th line: 1020.3348
17th line: 1020.158
18th line: 1019.969
19th line: 1019.779
Then, at the 1080th line, 818.589 is obtained.

Since these values are basically not integers and the resolution of the logic level in an actual circuit is 1, integers are displayed by rounding off after the decimal point. Thus, the initial value of the first line is 1023, the initial value of the second line is 1023, and thereafter, the third line is 1023, the fourth line to the eighth line is 1022, the ninth line to the fourteenth line is 1021, The 15th to 19th lines change to 1020, and the 20th line changes to 1019. Then, 819 at the 1079th line and 819 at the 1080th line. As described above, the initial value of each scanning line in the vertical direction changes.

In the latter example, since the color unevenness is treated only in the vertical direction, the correction values of the addresses L0P0, L0P1, L0P2, and L0P3 corresponding to the first line following the initial value data address in the horizontal direction of each scanning line. Address 0 is given as 0111 (P3 to P0). Thereafter, 0111 (P3 to P0) is repeated 319 times from the correction value address 1.

As described above, the correction value data for unevenness is obtained by setting the initial value of each scanning line in the horizontal direction and the vertical direction in accordance with the initial value address of each line, and 4 bits for the pixel address of each scanning line. Expressed. Further, regarding the detailed configuration and operation, the decompression processing unit 711 described later determines whether the addition / subtraction circuit 713 performs no calculation, performs an addition calculation, or performs a subtraction calculation. The number of pixels to be advanced in a non-operation is encoded and stored. Therefore, if the data has little change, the correction data for one line is small.

For example, in the case of the first embodiment described above, the correction data for one line per layer is 1920 × 2 (bit) = 3840 (bit), but in the case of the change according to the second embodiment, The correction data for one line per layer is approximately 191 × 4 (bit) = 764 (bit). As described above, the change value of the gradation correction characteristic in the horizontal direction of the display pixel is encoded and compressed and recorded in the second LUT unit 706.

Next, reading of “unevenness” correction data stored in the second LUT unit 706 described above, reproduction, and “unevenness” correction will be described. In the following description, the correction data reading operation from the second LUT unit 706 will be described.

(Reading correction data from the second LUT)
In the second LUT unit 706 shown in FIG. 8, the correction value code data written in the memory cell 707 in the 255th layer among the 256 memory cells 707 corresponding to the 256th layer from 0 to 255 is displayed on the display. In this display, data is read from the memory cell 707 in accordance with the timings of the vertical synchronization signal, horizontal synchronization signal, and clock signal from the timing signal generator 20 shown in FIG.

As described above, the memory cell 707 in the 256th layer is stored in the address format as shown in FIG. 9. First, as shown in the timing diagram of FIG. 11, the first scan is performed according to the vertical image start timing. From the horizontal read start pulse of horizontal synchronization of the line, first, 10 initial value data addresses of J, I, H, G, F, E, D, C, B, A of the memory address L0P0 of the line L0 are sequentially Read in a total of 10 pixel clock periods. Here, in the second embodiment, for the sake of simplicity, the remaining 3-bit data of P1, P2, and P3 are the initial value data J, I, H, G, F, E, and D. , C, B, and A are handled as unquestioned data during the reading period.

Similarly, for each horizontal synchronization, initial value data J, I, H, G, F, E, D, C, B, A at L1P0, L2P0,..., L1079P0 at the initial timing of each scanning line. Is read out.

(Initial value generation)
As described above, the initial value data read from the memory cell 707 provided corresponding to the hierarchy from 0 to 255 of the second LUT unit 706 is supplied to the initial value generation unit 708. As described above, the initial value generation unit 708 includes 256 initial value setting units 709 provided in each of the levels 0 to 255. Hereinafter, as a typical example of the initial value setting unit 709, an example of generating an initial value of the 255th layer of a red signal will be described.

The initial value data of J, I, H, G, F, E, D, C, B, and A at the memory line address L0P0 of the 255-th layer memory cell 707 is sequentially read in units of pixel clock timing. From the serial data input of the initial value setting unit 709, it is sequentially read as serial data into 10 flip-flop circuits (hereinafter referred to as Q1 to Q10). Here, from the example at the time of writing, the data of J, I, H, G, F, E, D, C, B, and A are “1, 1, 1, 1, 1, 1, 1, 1, 1, 1. 1, (MSB: LSB) ". Further, when the address of A is taken in at the pixel clock timing, a 10-bit parallel output “1” composed of outputs of the ten flip-flop circuits Q1 to Q10 constituting the shift register of the initial value setting unit 709. , 1, 1, 1, 1, 1, 1, 1, 1, 1, (MSB: LSB) ”is input to the first input of the switching circuit 712 corresponding to the 255th layer of the correction data reproducing unit 710 at the subsequent stage. Supplied.

With the above operation, initial value data corresponding to the 255th hierarchy is reproduced and input to the second input of the addition / subtraction circuit 713 corresponding to the 255th hierarchy via the switching circuit 712 corresponding to the 255th hierarchy.

Here, the output of the latch circuit 715 corresponding to the 255th layer of the latch unit 714 is connected to the first input of the addition / subtraction circuit 713 corresponding to the 255th layer. At the timing of accessing the memory address 0 after the initial value generation stage, the latch circuit 715 is immediately after reset, and “0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {MSB: LSB} ”is supplied to the first input of the addition / subtraction circuit 713 as 10-bit parallel data.

Therefore, at the timing of accessing the correction value data address 0 at the line address address L0P0 of the memory cell 707 corresponding to the 255th hierarchy, the output of the addition / subtraction circuit 713 corresponding to the 255th hierarchy is the second of the addition / subtraction circuit 713. The initial value data of “1, 1, 1, 1, 1, 1, 1, 1, 1, 1 (MSB: LSB)” input to the input is output. The output signal of the addition / subtraction circuit 713 is supplied to the 10-bit data input of the memory cell 705 in the 255th layer of the first LUT unit 702.

At the same time, at the pixel address timing 0 output from the addition / subtraction circuit 713, the gradation correction data is taken into the latch circuit 715 corresponding to the layer 255 of the latch unit 714 in synchronization with the pixel clock timing. This is held until the next pixel clock timing. Thereafter, the latch circuit 715 fetches the output data of the addition / subtraction circuit 713 in the corresponding hierarchy of the correction data reproduction unit 710 to be connected for each pixel clock timing, and holds the data one clock period at a time.

(Generation of correction values from correction data)
Next, after reading the initial value data from the memory cell 707 provided corresponding to the hierarchy from 0 to 255 of the second LUT unit 706, as shown in the “memory address configuration” of FIG. Reading data from the initial value addresses J, I, H, G, F, E, D, C, B, and A in the memory cell 707 of the second LUT unit 706 described for writing data to the LUT unit 706 Subsequently, the correction data is read out subsequently.

As described above, the correction data read at this time is composed of 4-bit data of P0, P1, P2, and P3 as shown in the “memory cell read timing diagram” shown in FIG. Is input to the decompression processing unit 711. In the decompression processing unit 711, the data is decrypted.

The data decoded in the decompression processing unit 711 is supplied to the second input of the switching circuit 712, switched to the initial value data via the switching circuit 712, and supplied to the second input of the addition / subtraction circuit 713. .

(Operation of the decompression processor)
Next, the operation of the above-described decompression processing unit 711 will be described in detail. FIG. 12 shows a configuration example of the decompression processing unit 711 and its peripheral circuits. The same configuration is applied to the other layers 0 to 254.

As shown in FIG. 12, 4-bit correction data of P0 to P3 is supplied from the memory cell 707 to the decompression processing unit 711 of the correction data reproducing unit 710. Of the 4-bit P0 to P3, P1 and P2 are directly supplied to the counter 759. Further, P0 is switched by the switch circuit 757 through the inverting circuit 756 or directly without passing through the inverting circuit 756, and is supplied to the input of the counter 759. The counter 759 is a down counter.

P3 is supplied to a 1-bit latch circuit 763. At the same time, 3-bit data from P0 to P2 in the memory cell 707 is divided and input to the decoder 758. The output from the decoder 758 is input to the control terminal of the changeover switch circuit 757 and further supplied to the input of the latch circuit 762. Note that serial data is supplied from the output P 0 of the memory cell 707 to the initial value setting unit 709 of the initial value generation unit 708.

Next, the output of the zero value decoder 760 is connected to the input of the data switch 761. The output of the data switch 761 is supplied to the second input of the switching circuit 712. Further, the output of the latch circuit 761 is supplied to the ON / OFF control terminal of the data switch 761. The output of the latch circuit 723 is input to the addition / subtraction control terminal of the addition / subtraction circuit 713. Note that the connection between the memory cell 705 of the first LUT unit 702, the addition / subtraction circuit 713, the latch circuit 715, the initial value setting unit 709 of the initial value generation unit 708, and the switching circuit 712 is the connection configuration shown in FIG. Is based.

A specific decompression processing operation of encoded data output from the memory cell 707 by the above decompression processing unit 711 and its peripheral circuit configuration will be described below.

(1) For example, when the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 0110 (P3: P0), the data from the memory cell 707 of the second LUT unit 706 110 of P2 to P0 is preset in the counter 759 at the pixel timing at which is read out.

Next, the counter 759 performs a subtraction count every pixel clock, and the counter output becomes 000 at the sixth pixel. In the subsequent zero-value decoder 760, 000 (P2: P
0) “1” is output as detection, and the value of the second input of the addition / subtraction circuit 713 becomes “1” at the sixth pixel. In this case, the data switch 761 is ON, and the second input is selected by the switching circuit 712.

Since the output P3 of the memory cell 707 of the second LUT unit 706 is 0 at the read timing, the output value of the latch circuit 723 at the subsequent stage remains 0, and the addition or subtraction of the addition / subtraction circuit 713 is performed. The designation is “subtraction”.

Therefore, the addition / subtraction circuit 713 performs “1” subtraction from the first input value at the sixth pixel timing from the timing when the data of 0110 (P3: P0) is read from the memory cell 707.

That is, if the initial value is, for example, 1023, 1022 is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702 at the sixth pixel timing from the data read timing.

(2) Next, when the read data (P3 to P0) from the memory cell 707 of the second LUT unit 706 is, for example, 0101 (P3: P0), P2 to P0 at the pixel timing of reading this data. 101 is preset in the counter 759. The counter 759 performs subtraction every pixel clock, the counter output becomes 000 at the fifth pixel, 1 is output from the 0-value decoder 760 in the subsequent stage, and the value of the second input of the addition / subtraction circuit 713 is “ 1 ". In this case, the data switch 761 is ON, and the switching circuit 712 selects the second input. Further, the output P3 of the memory cell 707 of the second LUT unit 706 is zero. Therefore, the output value of the latch circuit 723 remains 0, and the addition or subtraction designation of the addition / subtraction circuit 713 is “subtraction”.

Therefore, “1” is subtracted from the first input value by the addition / subtraction circuit 713 at the timing of the fifth pixel from the timing of reading the data of 0101 (P3 to P0) output from the memory cell 707.

That is, if the initial value is 1023, the value of 1022 is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702 at the timing of the fifth pixel from the timing of reading data.

(3) Similarly, when the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 0100 (P3: P0), the second input value of the addition / subtraction circuit 713 (B) becomes 1 at the fourth pixel, and the output of the value obtained by subtracting “1” from the first input value at the addition / subtraction circuit 713 is output from the latch circuit 715 and the first LUT unit 702 to the fourth pixel. And supplied to the memory cell 705.

(4) Similarly, when the read data from the memory cell 707 of the second LUT unit 706 is 0011 (P3: P0), the second input value (B) of the addition / subtraction circuit 713 is 1 at the third pixel. In the third pixel, the addition / subtraction circuit 713 supplies an output of a value obtained by subtracting “1” from the first input value to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

(5) Similarly, when the read data from the memory cell 707 of the second LUT unit 706 is 0010 (P3: P0), the second input value (B) of the addition / subtraction circuit 713 becomes 1 for the second pixel. In the second pixel, the addition / subtraction circuit 713 supplies an output of a value obtained by subtracting “1” from the first input value to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

(6) Similarly, when the read data from the memory cell 707 of the second LUT unit 706 is 0001 (P3: P0), the second input value (B) of the addition / subtraction circuit 713 becomes 1 for the first pixel. In the first pixel, the addition / subtraction circuit 713 supplies an output of a value obtained by subtracting “1” from the first input value to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

(7) Next, when the read data (P3 to P0) from the memory cell 707 of the second LUT unit 706 is 0000 (P3: P0), the output of the counter 759 is 000 at the timing of reading this data. Thus, 1 is output from the 0-value decoder 760 at the subsequent stage, and the value of the second input of the addition / subtraction circuit 713 is “1”. Further, since the output P3 of the memory cell 707 of the second LUT unit 706 is taken into the latch circuit 723 and its output is 0, the addition / subtraction designation in the addition / subtraction circuit 713 is “subtraction”. .

Therefore, at the timing when data of 0000 (P3: P0) is read from the memory cell 707 of the second LUT unit 706, the addition / subtraction circuit 713 calculates the second input value from the first input value of the addition / subtraction circuit 713. The input value “1” is subtracted, and the output of the addition / subtraction circuit 713 is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

That is, if the initial value is 1023, 1022 is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702 at the timing of reading data.

(8) Next, when the read data (P3 to P0) from the memory cell 707 of the second LUT unit 706 is 0111 (P3: P0), at the pixel timing at which this data is read, first from the AND circuit The 111 decoder 758 detects the 111 value and outputs 1. This output 1 is supplied to the counter 759 together with the data of P1 and P2, after the data output of the memory output P0 from the memory cell 707 is inverted in the polarity switching unit constituted by the inverter 756 and the changeover switch circuit 757. Is done.

That is, a value of 0110 (P3: P0) is preset for the counter 759. Further, 1 is detected in the 111 decoder 758, held in the latch circuit 762, and the decoder data output that outputs “1” when the input 000 (P0: P2) of the zero-value decoder 760 is input to the data switch It is turned OFF by 761 and the output of the 0-value decode signal to the second input of the addition / subtraction circuit 713 is stopped. That is, it is not set to “1”.

The counter 759 counts down for each pixel clock, the output of the counter 759 becomes 000 at the sixth pixel, the output of the zero value decoder 760 is output as 1, and the counter 759 is initialized at the rising edge of the next pixel clock timing. It becomes.

Therefore, when the read data (P3 to P0) from the memory cell 707 of the second LUT unit 706 is 0111 (P3: P0), the counter 759 counts in the 6 pixel clock timing period from the data read timing from the memory cell 707. Counting is performed, and the operation in the addition / subtraction circuit 713 is not executed.

If the initial value is 1023, a value of 1023 is supplied for each pixel clock timing to the data input between the latch circuit 715 and the memory cell 705 of the first LUT unit 702 during the 6-pixel clock timing period.

As described above, the read data P3 to P0 from the memory cell 707 of the second LUT unit 706 are 0110 (P3: P0), 0101 (P3: P0), 0100 (P3: P0), 0.
In the case of 011 (P3: P0), 0010 (P3: P0), 0001 (P3: P0), 0000 (P3: P0), 0111 (P3: P0), the fourth digit (P3) is 0, The calculation of the addition / subtraction circuit 713 is executed as subtraction.

Next, (9) when the read data (hereinafter referred to as P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1110 (P3: P0), the memory cell 707 of the second LUT unit 706 Of the read data at the pixel timing at which data is read, 110 (P2 to P0) P2 to P0 is preset in the counter 759.

The counter 759 performs a subtraction count every pixel clock, and the output of the counter 759 becomes 000 at the sixth pixel. Further, “1” is output as 000 (Q2: Q0) detection in the 0-value decoder 760 at the subsequent stage, and is supplied to the second input of the addition / subtraction circuit 713, and this value becomes “1” at the sixth pixel. Become.

Also, P3 which is one of the output data of the memory cell 707 of the second LUT unit 706 is “1” at the read timing, the output value of the latch circuit 723 in the subsequent stage is held as “1”, and the addition is performed. The subtraction circuit 713 enters the addition control state.

Therefore, from the timing when the data of 1110 (P3: P0) in the memory cell 707 of the second LUT unit 706 is read, the addition is performed to the value of the first input of the addition / subtraction circuit 713 at the timing of the sixth pixel. The second input value “1” of the subtraction circuit 713 is added.

That is, if the initial value is “256”, for example, “257” is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

(10) Next, when the read data (P3 to P0) from the memory cell 707 of the second LUT unit 706 is, for example, 1101 (P3: P0), the data is read from the memory cell 707 of the second LUT unit 706. Of the readout data at the pixel timing at which the data is read out, 101 (P2: P0) of P2 to P0 is preset in the counter 759. The counter 759 performs a subtraction count every pixel clock. Then, the counter output becomes 000 at the fifth pixel, “1” is output as 000 (Q2: Q0) detection in the subsequent zero value decoder 760, and the second input value of the addition / subtraction circuit 713 becomes “1”. . Also, P3 which is one of output data of the memory cell 707 of the second LUT unit 706 is 1 at the read timing, the output value of the latch circuit 715 at the subsequent stage is held as 1, and the addition / subtraction circuit 713 The addition control state is entered.

Therefore, the value of the first input of the addition / subtraction circuit 713 is changed to the value of the first input of the addition / subtraction circuit 713 at the timing of the fifth pixel from the timing of reading the data of 1101 (P3: P0) of the memory cell 707 of the second LUT unit 706. Addition of the second input value “1” of the addition / subtraction circuit 713 is performed. That is, if the initial value is “256”, for example, “257” is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

(11) Similarly, when the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1100 (P3: P0), the second input value (B) of the addition / subtraction circuit 713 is It becomes 1 at the fourth pixel, and the addition / subtraction circuit 713 supplies an output of a value obtained by adding “1” to the first input value to the latch circuit 715 and the memory cell 707 of the first LUT unit 702.

(12) Similarly, when the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1011 (P3 to P0), the second input value (B) of the addition / subtraction circuit 713 is It becomes 1 at the third pixel, and the addition / subtraction circuit 713 supplies an output of a value obtained by adding “1” to the first input value to the latch circuit 715 and the memory cell 707 of the first LUT unit 702. Is done.

(13) Similarly, when the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1010 (P3 to P0), the second input value (B) of the addition / subtraction circuit 713 is The value becomes 1 at the second pixel, and the addition / subtraction circuit 713 supplies an output value obtained by adding “1” to the first input value to the latch circuit 715 and the memory cell 707 of the first LUT unit 702. .

(14) Similarly, when the read data (hereinafter referred to as P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1001 (P3: P0), the second input value (B ) Becomes 1 in the first pixel, and the addition / subtraction circuit 713 supplies an output value obtained by adding “1” to this first input value to the latch circuit 715 and the memory cell 707 of the first LUT unit 702. The

(15) Next, when the read data (hereinafter referred to as P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1000 (P3: P0), for example, at the timing of reading this data, the counter 759 The output is 0h, 1 is output from the 0 value decoder 760 in the subsequent stage, and the value of the second input of the addition / subtraction circuit 713 is “1”. Also, P3, which is one of the output data of the memory cell 707 of the second LUT unit 706, is 1 at the read timing, the output value is held as 1 in the latch circuit 723 in the subsequent stage, and the addition / subtraction circuit 713 The addition control state is entered.

Therefore, at the timing when data of 1000 (P3: P0) is read from the memory cell 707 of the second LUT unit 706, the second input value of the addition / subtraction circuit 713 is set to the first input value of the addition / subtraction circuit 713. The input value “1” is added. The output of the addition / subtraction circuit 713 is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702. For example, if the initial value is “256”, “257” is supplied to the latch circuit 715 and the memory cell 705 of the first LUT unit 702.

(16) Next, when the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1111 (P3: P0), at the pixel timing of reading this data, first, three inputs The 111 (P0: P3) value is detected by a 111 decoder 758 composed of the AND circuit and 1 is output.

With the output of 1, the memory output P0 is inverted in the polarity switching section composed of the inverter 756 and the changeover switch circuit 757, and then supplied to the data input of the counter 759 together with P1 and P2, and preset. That is, the lower 3 bits of the input data 1111 (P3: P0) are converted into the data value 110 (P2: P0) and supplied to the counter 759.

Further, 1 is detected by the 111 decoder 758, and this value is held by the latch circuit 762 at the subsequent stage. The data switch 761 is turned OFF and supplied to the second input of the switching circuit 712 by the output of the zero-value decoder 760 (1 output at the time of 000 input), and further to the second input of the subsequent addition / subtraction circuit 713. Then, the output of this 0-value decode signal is stopped. The logical value in this case is 0 by being pulled down to 0 value by the pull-down resistor. In addition, it is possible to perform the same function using an AND logic gate circuit.

The counter 759 counts down for each pixel clock from the timing of reading data from the memory cell 707, and the counter value becomes 000 at the sixth pixel. Further, the output of the 0-value decoder 760 at the subsequent stage is output as “1”, and the counter 759 is initialized at the rising edge of the next pixel clock as an initialization signal.

With the above operation, the value of the first input of the addition / subtraction circuit 713 in the 6 pixel timing period from the timing when the data of 1111 (P3: P0) in the memory cell 707 of the second LUT unit 706 is read out. The value of the second input of the addition / subtraction circuit 713 is “0”, and the next address data of the memory cell 707 of the second LUT unit 706 is read at the next pixel timing.

That is, in the case of 1111 (P3: P0), if the initial value is 256, 256 is supplied to the data input between the latch circuit 715 and the memory cell 705 of the first LUT unit 702 during the 6-pixel clock timing period. .

As described above, the read data (hereinafter P3 to P0) from the memory cell 707 of the second LUT unit 706 is 1110 (P3: P0), 1101 (P3: P0), 1100 (P3: P0), 1011 ( If P3: P0), 1010 (P3: P0), 1001 (P3: P0), 1000 (P3: P0), 1111 (P3: P0), the fourth digit (P3) is 1, and the addition The calculation of the subtraction circuit 713 is executed as addition.

The decompression processing unit 711 shown in FIGS. 8 and 12 is configured and operated as described above, and is recorded as encoded data in the memory cell 707 of the second LUT unit 706 having the color unevenness correction value shown in FIG. The encoded data for color unevenness gradation correction is decompressed in synchronization with the pixel clock timing in the screen display, and is decompressed and decoded in the memory cell 705 of the first LUT unit 702 at the pixel clock timing. Correction data can be sequentially written.

The above has described the correction data writing process from the memory cell 707 of the second LUT unit 706 to the first LUT unit 702 in the circuit block hierarchy corresponding to the 255 gradation of 255. FIG. The same decompression process is also executed in the 254 to 0 hierarchy of the circuit block configuration of 255 hierarchy shown in FIG.

Data reading from the memory cell 707 in the second LUT unit 706, decompression decoding processing in the correction data reproducing unit 710, and writing correction data to the memory cell 705 in the first LUT unit 702 in the above 255th hierarchy. The same processing is performed for each of the 0 to 254 levels.

(Gradation correction in the first LUT)
Next, in the first LUT unit 702, as in the first embodiment described above, the 8-bit red image input signal Di-R is input to the address decoding unit 703 shown in FIG. The input image input signal Di-R is demodulated by the address decoding unit 703.

At the timing of the memory address 0 as the first pixel in the display unit of the line address L0 in each memory cell 707 of the second LUT unit 706, the input value of the 8-bit red image signal Di-R is For example, in the case of 1, 1, 1, 1, 1, 1, 1, 1 (MSB: LSB) 8 bits, the decode value of the address decode unit 703 is “255”, and the output signal S255 of the address decode unit 703 is Become active. Accordingly, the output enable of the memory cell 705 in the 255th layer of the first LUT unit 702 becomes active. From the memory cell 705 in the 255th hierarchy, the output correction value of the addition / subtraction circuit 713, “1, 1, 1, 1, 1, 1, 1, 1, 1, 1, (MSB: LSB)” is parallel. The red image output signal Do-R is supplied to the subsequent DA conversion unit 10 via the red image signal output unit of the image signal output terminal 716. In the DA conversion unit 10, after the red image output signal Do-R is DA-converted, a liquid crystal drive signal of the liquid crystal drive unit 13 is obtained and supplied to the liquid crystal display unit 16.

Note that the 10-bit digital outputs of the 255 memory cells 705 of the first LUT unit 702 are connected in parallel in units of binary values to form a 10-bit data bus. Note that only one memory cell 705 that is active at a time is selected by the above-described address decoding unit 703 out of 255.

Similarly, the display addresses from the first pixel to the 1920th pixel of the 0th line are input via the red signal image signal input unit 701. The input value of the 8-bit red image signal Di-R is assumed to be a white 100% signal in this second embodiment, and is a binary value of 1,1,1,1,1,1,1,1. 1 (MSB: LSB) continuous signal. In the first LUT unit 702, the memory cell 705 in the 255th layer is always active.

That is, the output gradation correction data value of the first LUT unit 702 at the timing of the pixel address 0 of the display line address 0 is “1023”, and thereafter, the data is attenuated by 1 every 9.37 pixels at the pixel address. The pixel address 1919 decreases to about “818”. Note that the reproduction data in this case is an integer quantization level unit.

Similarly, the output tone correction data value Do-R of the first LUT unit 702 for the display line addresses L1 to L1079 is output in the same way as the 0th line.

In this way, in the color unevenness of the present example in which the color unevenness increases in redness from the left to the right of the screen and the red component increases by 20% at the right end of the screen, the output red image signal Do− of the first LUT unit 702. The output value of the red image output signal Do-R, which has a linearly gradual change of 20% attenuation at the right end of the screen with respect to the left end of the screen, of the output value of R, the display screen of the display device of the second embodiment Left and right color unevenness is corrected.

Similarly, when the input level is “254”, 10-bit data of the memory cell 705 in the 254th layer of the first LUT unit 702 is output as a red image from the first LUT unit 702 of the gradation correction unit 7. It is output as signal Do-R. Similarly, at the input levels “253” to “0”, 10-bit data of each of the memory cells 705 in the layers 253 to 0 of the first LUT unit 702 corresponding to the input level is output, and color unevenness of the display image is generated. It is corrected.

In the above example, regarding the color unevenness in red, the color unevenness is reduced by correcting the gradation correction characteristics of the red image signal in units of pixels, but the levels of the red, green, and blue image signals are reduced. The tone correction characteristics are performed in units of pixels by the tone correction units 7, 8, and 9 shown in FIG. 1, so that the accuracy of the display image can be improved in all the tone levels of all colors corresponding to the logical level of the input image. High color unevenness correction can be realized by gradation correction for each pixel.

In the first and second embodiments, examples of gradation correction, luminance unevenness (brightness variation), and color unevenness correction as a liquid crystal projection device have been described. For example, a plasma display device, a liquid crystal Similar effects can be obtained with respect to other display devices such as a display device and an EL display device.

(Third embodiment)
Next explained is a display device according to the third embodiment of the invention. The third embodiment is the same as the first and second embodiments except for writing display correction data to the second LUT unit 706, and thus the description thereof is omitted.

(Write display correction data to the second LUT)
That is, in writing the display correction data to the second LUT unit 706 in the first and second embodiments described above, the memory of the second LUT unit 706 is ROM (read only memory) or EEPROM (electrically rewritable). Read-only memory), EPROM, one-time ROM, flash memory and the like. These memories are generally classified as non-volatile memories.

These memories are configured to be written in a data format to be described later by a PC operation. However, a non-volatile memory as described above is further provided, and a third memory as a third memory is provided as shown in FIG. The LUT unit 23 is provided.

In the nonvolatile memory as the third LUT unit 23, compressed or non-compressed data based on the gradation correction data written in the second LUT unit in the first and second embodiments is recorded. In the initial setting sequence of the system control microprocessor such as when the apparatus is turned on, the data stored in the third LUT unit 23 is randomly transmitted via the microprocessor or a bus controlled by the microprocessor. The same correction processing as in the first and second embodiments is performed by copying or moving to the second LUT unit 706 configured by an access memory (RAM). As a result, the effects of the first and second embodiments can be obtained, and in general, a device having a high operation speed can be easily obtained with respect to the second LUT unit, so that the circuit can be easily realized.

(Fourth embodiment)
Next explained is the fourth embodiment of the invention. In contrast to the circuit block diagram of the gradation correction unit 7 according to the first embodiment shown in FIG. 3, FIG. 14 shows a circuit block diagram of the gradation correction unit 7 according to the fourth embodiment. In addition, in order to make an understanding easy, the description regarding the hierarchy of 255 is abbreviate | omitted.

In FIG. 14, the same input as the latch circuit 715 is provided, and 256 second latch circuits 755 corresponding to 0 to 255 layers are provided in parallel. The output of the second latch circuit 755 is connected to the third input c of the switching circuit 713.

Next, as shown in FIG. 15, in the address structure of the memory cell corresponding to the 256 layers of the second LUT, 10 bits from the initial value data J to A are set immediately before the first scan line L0. Provide. Thereafter, 1 bit given by the address A is provided as the initial value data from the second scanning line to the final scanning line.

Each address is 10 bits from L0PJ to L0PA, followed by L1PA and L2PA, followed by L1023PA, further followed by L1SA and L2SA, and each line address up to L1023SA is provided with a 2-bit A address.

In addition, in 10 bits of addresses L0PJ to L0PA, initial value data of the first scanning line L0 is stored. The 1-bit initial value L1PA of the second scanning line L1 stores the absolute value of the difference value between the initial value of the second scanning line and the initial value of the first scanning line.

Similarly, in the 1-bit initial value L1SA of the second scanning line L1, the difference value of the initial value of the second scanning line with respect to the initial value of the first scanning line is increased or attenuated, that is, the difference value of L1PA. The sign of whether to add or subtract the absolute value of is stored.

Next, in the initial value L2PA of the third scanning line L2, the absolute value of the difference value between the initial value of the second scanning line and the initial value of the second scanning line is stored.

Similarly, in the initial value L2SA of the second scanning line L1, whether the difference value of the initial value of the second scanning line with respect to the initial value of the first scanning line is increased or attenuated, that is, the difference value of L2PA. The sign of whether to add or subtract the absolute value of is stored. Thereafter, similarly, the initial value is stored in 2 bits of P and S up to the 768th line.

After the initial value of each scanning line, as in the first scanning line L0, correction data of 0 to 1023 pixel addresses similar to that of the first embodiment for the initial value of each line is one pixel before. The data as the difference value of the gradation correction data is stored at each pixel address 2 bits together with the sign of increase or decrease.

In the circuit block configuration of the gradation correction unit 7 shown in FIG. 14 as described above, the memory cell 707 in the hierarchy from 0 to 255 of the second LUT unit 706 has a display address of the first scan line. First, the 10-bit initial value of L0PJ to L0PA of the line address L0 is read out in synchronization with the sequential display. This initial value is taken into the initial value setting unit 709 of each layer of the initial value generation unit 708 in units of clocks. At the pixel address timing A after 10 clocks, an initial value of 10 bits is reproduced and supplied as parallel data to the subsequent correction data reproduction unit 710.

At the same time, this data is supplied to 256 second latch circuits 755 corresponding to the 0 to 255 levels, and held for one scanning line period.

Next, as in the first embodiment, the correction data reproducing unit 710 reproduces the correction data corresponding to the pixel display addresses from 0 to 1023 at the timing following the pixel address timing A, and the first data This is supplied to the LUT unit 702, and the gradation correction characteristics of the input image signal Di-R are changed to perform unevenness correction and gradation correction.

Next, in the second scanning line, at the timing B as the initial value address of the line address L1, the data of the second latch circuit 755 is fetched into the addition / subtraction circuit 713 as a subsequent operation unit, and the initial value address In A, an operation is performed on the initial value data one line before that is taken into the latch circuit 715 and held for one pixel clock period.

In this case, the next read 1-bit data is added to or subtracted from the initial value data of the previous line, and this addition or subtraction depends on the 1-bit S data read simultaneously. The case is determined by 1 or 0 of L1SA. Thus, the initial value of the second scanning line can be reproduced with 10-bit data, and is supplied to the subsequent correction data reproducing unit 710 as with the first scanning line.

At the same time, this data is supplied to and fetched into 256 second latch circuits 755 corresponding to the above-described 0 to 255 levels and held for one scanning line period.

Next, similarly to the first line, the correction data reproducing unit 710 reproduces the correction data corresponding to the pixel display addresses from 0 to 1023 at the timing following the pixel address timing A, and the first LUT. This is supplied to the unit 702, and the gradation correction characteristics of the input image signal Di-R are changed to perform uneven gradation correction.

Similarly, in each of the subsequent scanning lines, the initial value data one line before the second latch circuit 755 is read out at the initial value address timing B of each line address, and the correction data reproducing unit performs the addition / subtraction circuit 713. Input from the second input and stored in the latch circuit 715. In this case, the first input in the addition / subtraction circuit 713 is a “0” value immediately after reset.

Next, at the initial value address timing A, in the addition / subtraction circuit 713 of the correction data reproducing unit, the LnPA of the initial value address A of the memory cell 707 is compared with the initial value one line before stored in the latch circuit 755 described above. And LnSA are read out, LnPA data is supplied to the second input of the addition / subtraction circuit 713, and calculation is performed by the sign “1” or “0” of addition or subtraction of LnSA. To get. In the correction data reproducing unit 710, the correction data is reproduced corresponding to the pixel display addresses from 0 to 1023 at the timing subsequent to the pixel address timing A, and is supplied to the first LUT unit 702 to be input image signal Di. The gradation correction characteristic of -R is changed to perform uneven gradation correction.

In the above correction method, as the memory value for the initial value in the second LUT unit 706, in the first embodiment, 10-bit initial value addresses exist for 768 lines in 256 hierarchies. This is 1582080 bits, but in the fourth embodiment, the initial value address of 10 bits is for 256 layers and the initial value address of 2 bits is for 767 lines in 256 layers, and a 395264 bit memory is sufficient. This is about 1180 kbit.

In the fourth embodiment, the number of scanning lines is 768. However, in the case of a multi-line display unit such as 1080 or 1400, an even greater effect can be achieved.

(Fifth embodiment)
Next explained is the fifth embodiment of the invention. The overall configuration of the image display apparatus according to the fifth embodiment is the same as that shown in FIG. 1, and the image signal input terminals 1, 2, and 3 are respectively red (R), green (G), and blue (B). Primary color image signals are input. Moreover, the microcomputer part 21 as an information processing part is provided. In the fifth embodiment, the primary color image signals of red (R), green (G), and blue (B) are each quantized with 8 bits.

Next, the quantized red (R), green (G), and blue (B) 8-bit digital image signals are respectively supplied to the gradation correction units 7, 8, and 9. The so-called screen uniformity correction of tone correction and luminance unevenness and color unevenness is performed simultaneously. The red (R), green (G), and blue (B) digital output image signals respectively output from the gradation correction units 7, 8, and 9 are each output in 10 bits in the fifth embodiment. Is.

Next, 10-bit digital output image signals of red (R), green (G), and blue (B) of the gradation correction units 7, 8, 9 are respectively converted into red (R) by the DA conversion units 10, 11, 12. ), Green (G), and blue (B) analog image signals. Further, in the liquid crystal drive units 13, 14, and 15, polarity inversion and optimum level drive signals are appropriately generated for the subsequent liquid crystal display units 16, 17, and 18 and supplied to the liquid crystal display units 16, 17, and 18. Then, unique images of red (R), green (G), and blue (B) are displayed, respectively.

The liquid crystal display units 16, 17, and 18 have a plurality of scanning lines and a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to the intersections between the scanning lines and the data lines. A liquid crystal driving unit, a data line driving circuit for supplying a data line signal, a scanning signal, etc. to a data line, a scanning line, etc. at a predetermined timing, and a scanning line driving circuit (all not shown), This is a TFT liquid crystal display unit made of so-called transmissive polycrystalline silicon.

In the following description of the fifth embodiment, the effective display area is red (R), green (G), and blue (B) as horizontal 1024 pixels and vertical 768 lines. Further, the three-plate liquid crystal projector used in the fifth embodiment is the same as that in the first embodiment, and a detailed description thereof will be omitted.

(Second LUT part)
The second LUT unit 706 according to the fifth embodiment stores the gradation correction data of the display image in advance as described later corresponding to the pixels in the entire display screen. FIG. 16 shows the address space of one memory cell 707 according to the fifth embodiment.

As shown in FIG. 16, it has a line address configuration called L0 to L767 corresponding to 768 effective scanning lines, and these scanning lines L0 to L767 have a 2-bit data width called P and S, respectively. Therefore, the line address is composed of L0P to L767P and L0S to L767S corresponding to 768 effective display scanning lines.

Next, each scan line address includes 10 initial data addresses of J, I, H, G, F, E, D, C, B, and A and 512 pixel correction data addresses of 0 to 511. .

Also in the fifth embodiment, the “subtraction” is to subtract the second input value from the first input value of the addition / subtraction circuit 713 as the calculation unit. Further, the addition / subtraction control terminal of the addition / subtraction circuit 713 sequentially inputs S data from the 2-bit output of the second LUT unit 706.

Of the 2-bit outputs of P and S of the second LUT unit 706, data specifying whether to add or subtract is stored in the S data table, and the P data table is used for addition or subtraction. Is stored. In the fifth embodiment, the absolute value is represented by “1” when increasing or decreasing, and “0” when not increasing or decreasing.

In this manner, the designation of addition or subtraction at the addition / subtraction control terminal of the addition / subtraction circuit 713 is sequentially supplied from the S data table in each memory cell 707 of the second LUT unit 706 and controlled.

As described above, by the 256 addition / subtraction circuits 713 in the 0 to 255 hierarchy in the correction data reproducing unit 710, the result of addition or subtraction between the first input and the second input is obtained in the subsequent 0 to 255 hierarchy. The data is supplied to 256 latch circuits 715 and 10-bit data input terminals of 256 memory cells 705 corresponding to the 0-255 hierarchy of the first LUT unit 702.

(Latch part)
The clock input to the latch circuit 715 according to the fifth embodiment has a period twice as long as the pixel clock timing described above. Although not shown, the pixel drive timing clock output from the PLL circuit 202 of the synchronization generator of FIG. 1 is once divided by 2 in the frequency dividing means, and then supplied to the clock input terminal of the latch circuit 715 for driving.

The latch unit 714 holds data during the period of two pixel clocks, and may be any means that provides the calculation result of the addition / subtraction circuit 713 before two pixel clocks to the addition / subtraction circuit 713. A circuit, a delay circuit, a delay element, or the like may be used.

(Measurement of display data and data processing)
A specific gradation correction operation in the function of each unit as described above will be described below.

In the display characteristics of the display device, first, the gradation correction of the gradation correction unit is turned off. Next, a red signal of the maximum input level of the display device is input from the test signal generator, and a display image is captured by, for example, a video camera and captured as a captured image on a PC, and display unevenness in the display area is measured. Next, the output white signal level of the test signal generator is attenuated, and the measurement is similarly performed as (254/255).

Sequentially attenuate the output white signal of the test signal generator to (253/255), (252/255), and (251/255) and measure the display unevenness at each input level to generate the test signal This is repeated until the output white signal level of the device becomes (1/255), (0/255). Similarly, measurements are made at 255 levels from (254/255) to (1/255) and (0/255) for green and blue.

By the above measurement, display unevenness data of red, green, and blue colors with input levels from 255 to 0 are taken into the PC. Next, color unevenness correction data is generated by the calculation of the PC.

In the fifth embodiment, the correction data group corresponds to the total number of pixels for horizontal 1024 pixels and vertical 768 lines corresponding to the number of display pixels. Further, as correction data reduction, the horizontal correction data is set to 512 which is a half value of 1024. That is, the first pixel and the second pixel are set as the same correction data. Similarly, correction data is generated in the PC in units of two pixels, such as the third pixel, the fourth pixel, the fifth pixel, and the sixth pixel.

An example of the above-described gradation correction in pixel units is shown in FIG. The correction characteristics shown in FIG. 6 correspond to a degamma correction characteristic for an input image signal and a non-linear display characteristic which is a so-called voltage versus transmission (or reflection) characteristic in a display unit (a liquid crystal display unit unit in the fifth embodiment). The correction characteristic is included. In the fifth embodiment, the input image signal is generated with a gradation of 8 bits and a corrected gradation output of 10 bits.

(Write display correction data to the second LUT)
The correction data corresponding to the correction characteristics described above is 256 memory cells 707 up to 0 to 255 levels of the second LUT unit 706 shown in FIG. 14 shown in the description of the “second LUT unit 706”. Are written to a total of 393216 pixel-corresponding gradation correction addresses indicated by P and S, and a total of 7680 initial value data addresses indicated by 2 bits indicated by P and S corresponding to each scanning line.

The memory of the 256 memory cells 707 up to 0 to 255 in the second LUT unit 706 described above can be configured by, for example, a ROM, a memory such as an EEPROM, an EPROM, a one-time ROM, or a flash memory. is there. These memories are classified as non-volatile memories.

In the address configuration of each memory cell 707 in the second LUT unit 706 as shown in FIG. 16, first, J˜ before the pixel address 0 corresponding to the first effective display pixel in each horizontal scanning period. 10 addresses of A are provided, and gradation correction initial data is generated for this period.

(hierarchy)
The gradation correction data in this case is composed of 256 layers from 0 to 255 corresponding to the gradation of the input image signal to the gradation correction unit 7 shown in FIG. That is, as in the example of the gradation correction of one pixel shown in FIG. 6 described above, each of the gradation levels of all 256 gradations of 8 bits of the image input signal to the gradation correction unit 7 is the second LUT. It is assigned to 256 memory cells 707 of 0 to 255 in the unit 706 and corresponds.

(Memory address configuration)
Next, FIG. 16 shows an example of the memory address configuration, taking as an example the memory cell 707 in the 255th layer corresponding to the 255th gradation as one layer generated by the PC.

As shown in FIG. 16, L0P as the first bit of L0 corresponding to the first scanning line of the display image firstly stores a total of 10 bits of data for the initial value data address period J to A respectively. Store at address. In the hierarchy of 255, as an example of the correction data, the maximum value 1023 from the gradation correction characteristics shown in FIG. 6 is assumed. First, in L0P, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 are stored at addresses J to A.

In the example of FIG. 16, data is arranged with the address A side closest to address 0 as the LSB value.

Next, regarding the data of the addresses J to A of L0S, in the fifth embodiment, it is an unquestioned period in which no data exists. Of course, the same data can be handled in the 5-clock period by using L0P and L0S for the data of the addresses J to A.

Next, in the fifth embodiment, as described in the generation of the correction data, the effective display pixel addresses 0 to 1023 following the address data from J to A of L0P and L0S described above are used. The correction address data of the second LUT unit 706 is stored every other pixel, that is, as correction data common to two pixels.

In this case, the correction data is stored in 2 bits of L0P and L0S, where S is “1” when the data value increases by 2 pixels before, that is, 1 data clock before the correction data rate. The data indicating whether the correction value is increasing or decreasing is “0”, and P is “1” or “0” as the absolute value of the change value with respect to two pixels before, that is, one data clock before the correction data rate.

For example, when the value of the third pixel decreases to “1022” with respect to the initial value as the gradation correction value of the line address L0, that is, the value “1023” of the first pixel, it corresponds to the third pixel and the fourth pixel. The correction data address L0P1 is “1”, and the address of L0S1 is “0”. Similarly, correction data for 1024 pixels in the horizontal direction is recorded in units of two pixels from L0P2 to L0P512 in units of two pixels.

The above is an example of the configuration of the correction data address in one horizontal period of the layer 255. From line 1 to line 768, the line addresses L1P to L767P and L1S to L767S as shown in FIG. A total of 523 data of the 10 addresses up to and the correction data addresses from 0 to 512 are recorded. Similarly, correction data is recorded for each of the levels 254 to 0.

(Example of correction data)
As an example, a correction characteristic that finally attenuates by 20% from the left to the right of the display image (specifically, from pixel address 0 to address 1023) is required from the color unevenness data by measurement when the correction data is red. In this case, if the change value per pixel is expressed by a quantization level, the maximum value is set to 1024 levels,
(1023 × 0.2) / (1024) = 0.2
Thus, the quantization level is 0.2.

Further, the minimum level unit handled in the fifth embodiment is one quantization level value, and the number of target pixels in the horizontal direction until the one quantization level is changed is approximately 1 / 0.2 = 5. The data attenuates by 1 every 5 pixels.

Further, if this value is viewed in the correction data unit of the second LUT unit 706 shown in FIG. 16 described above, as described above, since one correction data period is a two-pixel address, a correction data address of 2.5 is obtained. It changes by one correction value every time. Actually, in the case of the correction data whose level is linearly attenuated as in the fifth embodiment, the data value alternately changes between the two correction data clocks and the three correction data clocks.

(Data storage)
For example, by the program operation of a computer (hereinafter referred to as PC), the addresses from J to A of L0P are assigned to “1,1,1,1,1,1,1” corresponding to 1023 in decimal as described above. , 1, 1, 1, (MSB: LSB) ", address J is MSB, address A is LSB
Are stored in order.

Subsequently, 0 at the L0P address 0 corresponding to the first and second pixels, 0 at the L0S address 0, 0 at the L0P address 1 corresponding to the third and fourth pixels, 0 at the L0S address 1, and the fifth pixel L0P address 2 corresponding to the sixth pixel, 0 in L0S address 2, 0 in L0P address 3 corresponding to the seventh and eighth pixels, 0 in L0S address 3, and so on. A data structure that attenuates by 1 for every five pixel addresses up to address 512 is stored from the PC.

In the fifth embodiment, there is no color unevenness in the vertical direction of the screen, that is, in the vertical direction from the first line to the 768th line, and the correction values are the same for L0P to L767P and L0S to L767S. Write the correction data.

The above correction data is data writing to the memory cell corresponding to the layer 255 of the second LUT unit 706.

Similarly, the memory cells 707 in the layers 254 to 0 are similarly written as data unique to each layer as described.

(Vertical unevenness correction)
Next, for example, when the correction data is different in the vertical direction, specifically, for example, when the first line is the maximum level of 1023 and the final line 768 is linearly attenuated to 20%, the initial of the first line The value is 1024
The initial value of the second line is (1024 × 0.2) /768=0.2666, which is 1024 because it is less than one level attenuation.
The same applies to the third line, the initial value is 1024, and the level is attenuated by 1 from 1 / 0.2666 = 3.75 is the 3.75th pixel in the calculation,
The initial value is 1023 on the fourth line.
Similarly, since it is 1023 in the fifth line and attenuates by 2 in the 7.5th pixel, it becomes 1022 in the eighth line.
As described above, the attenuation is proportional, and the initial value of the 768th line is
(1024 × 0.2) /768=0.2666
1024- (1024 × 0.2) = 819
It becomes.

As described above, the correction value data for unevenness is the initial value address of each line in the horizontal direction and the vertical direction, and the pixel address of each line is set every two pixels as described above. As one data address, a difference value with respect to a correction value two pixels before, that is, one data address before is stored as memory data in each memory cell for each layer, and about 2 minutes for the above-described fifth embodiment. The second LUT unit 706 is stored with a small capacity of one.

(Data writing to the second LUT part)
Writing is performed from the PC under the control of the microcomputer via the interface, but a similar function can be obtained by mounting a ROM or flash memory that has been written in advance.

(Read correction data)
As described above, the “difference value data” of the gradation correction value one pixel before written in the second LUT unit 706 shown in FIG. 16 is the timing signal generation unit shown in FIG. In synchronization with the horizontal synchronization and the vertical synchronization from 20, the data is read according to the read timing of the clock signal TCK1, and supplied to the initial value generation unit 708 as the data of the respective layers described above. Here, in the fifth embodiment, the timing of the clock signal TCK1 is set to twice the pixel display clock cycle. An example of the timing of read data in this case is shown in FIG.

As shown in FIG. 15, on the basis of the pixel display clock (clock signal), the initial value data address of (memory addresses J to A) shown in FIG. The subsequent correction value address is a memory address clock in units of a period twice as long as the pixel display clock timing. An example of the data read timing of the second LUT unit 706 in this case is shown in FIG.

The data P and data S in FIG. 17 are sequentially read according to the memory address in FIG. 17 as a data string in units of clock signals.

(1) First, although not shown in the figure, according to the vertical image start timing, L0P (data P of line address 0) corresponding to the first scanning line is shown in the memory addresses J and I shown after a predetermined time from the horizontal read start pulse. , H, G, F, E, D, C, B, and A are read out. In the fifth embodiment, it is 1,1,1,1,1,1,1,1,1,1,1.

(2) Subsequently, the correction value addresses 0 to 512 of the memory addresses L0P and L0S are read as shown in FIG. 15 at a cycle twice that of the clock signal described above. The read correction value data is output with 2 bits of data P and data S for each layer as described above.

(3) After reading to the correction value addresses L0P512 and L0S512, the reading is waited until the horizontal synchronous read start pulse of the next scanning line is generated.

(4) From the horizontal read start pulse of the second horizontal line, the memory addresses J, I, H, G, F, E, D, C, B, and A of the memory address of the second line are the same as in (1) described above. Initial value data addresses are read out, and correction value addresses from 0, 1, 2, 3, to 512 are read out.

(5) Similarly, reading is performed from the third horizontal line to the 768th line, and similarly, readings (1) to (4) are performed according to the clock timing at each vertical synchronization timing. (6) The above data reading is performed from 255 to 0 layers.

(Initial value playback)
As described above, the correction data read from the memory cells 707 of the second to 0th layers of the second LUT unit 706 is supplied to the initial value generation unit 708. In the shift register of the initial value setting unit 709 provided for each of the levels 0 to 255 of the initial value generation unit 708, the memory addresses J, I, H, G, F, E, D, C, B, and A are stored. Address read initial value data P is sequentially input for each clock, and is stored as serial data in ten flip-flop circuits (hereinafter Q1 to Q10).

Examples of data stored in the respective flip-flops Q1 to Q10 for each of the memory addresses J, I, H, G, F, E, D, C, B, and A in FIG. 17 are denoted as Q1 to Q10 in FIG. Show. As described above, in the address reading of the initial value data J, I, H, G, F, E, D, C, B, and A of the first line address L0P of the memory cell 707 in the layer 255, 1, 1, 1 1, 1, 1, 1, 1, 1, and the data is sequentially read, and at the read timing of the address L 0 PA, all the data of the shift registers Q 1 to Q 10 are stored and the next timing The signal is input to the second input of the addition / subtraction circuit 713 via the switching circuit 712 at the timing of accessing the memory address 0.

At this stage, the output of the latch circuit 715 is connected to the first input of the addition / subtraction circuit 713. At the timing of accessing the memory address 0, the latch circuit is immediately after reset, and the 10th bit parallel data of 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 is added to the first of the addition / subtraction circuit 713 1 input.

Therefore, at the timing of accessing the memory address 0 in FIG. 17, 1, 1, 1, 1, 1, 1, 1, 1 input to the second input from the output of the addition / subtraction circuit 713. , 1, 1 (decimal value 1023) is output.

Through the above operation, the correction value data in the layer 255 at the access timing of the memory address 0 of the line address 0 is output from the addition / subtraction circuit 713 of the correction data reproducing unit 710, and the memory in the 255th layer of the first LUT unit 702 Stored in cell 705 via 10-bit input.

At the same time, the data at the pixel address timing 0 output from the addition / subtraction circuit 713 of the correction data reproducing unit 710 is taken into the latch circuit 715 of the hierarchy 255 of the latch unit 714 by the memory data clock signal timing, and the next memory Stored until data clock timing (two pixel clock period).

Thereafter, the latch circuit 715 stores the output data of the addition / subtraction circuit 713 in the corresponding hierarchy of the correction data reproducing unit 710 connected for each clock for one memory data clock timing (two pixel clocks) period.

(Generation of correction value from difference value)
(Pixel address timing 0)
Thereafter, as shown in FIG. 17, the memory address timing of line 0 indicated by L0P0 and L0S0 of the memory cell 707 in the second LUT unit 706 corresponding to the first pixel and the second pixel as the display timing of the display unit. At 0, data P outputs “0”, and data S also outputs “0”. As described above, the data S is designated to be added or subtracted to the addition / subtraction circuit 713 of the hierarchy 255 of the correction data reproducing unit 710. In the fifth embodiment, 1 functions as addition and 0 functions as subtraction.

As the data P, the absolute value of the difference data of the correction value from the previous pixel is input. At this timing, the read correction value data P is 0, and the output of the addition / subtraction circuit 713 of the layer 255 is output. 1, 1, 1, 1, 1, 1, 1, 1 (MSB: LSB) initial value data as the decimal value 1023, the hierarchy at the time of memory address timing 0 of line 0 The correction value data in 255 is output from the addition / subtraction circuit 713 of the correction data reproducing unit 710 and stored as 10-bit data in the memory cell 705 in the 255th hierarchy of the first LUT unit 702.

(Address timing 1)
Similarly, the memory address timing 1 corresponding to the third and fourth pixels of the line address L0, that is, the data P indicated by L0P1 and L0S1 of the memory cell 707 is “0”, and the data S is “0”. It becomes.

Accordingly, the output of the addition / subtraction circuit 713 of the layer 255 in the correction data reproducing unit 710 does not change, and the decimal value 1023 of the memory cell 705 in the layer 255 of the layer from 0 to 255 of the first LUT unit 701 is not changed. Stored sequentially in 10-bit input.

(Address timing 2)
Similarly to the above, at the memory address timing 2 of the line address L0, “1” is output as the data P and “0” is output as the data S. This corresponds to the pixel corresponding address timings 4 and 5 of the line address L0.

Therefore, at this timing, the addition / subtraction circuit 713 in the hierarchy 255 in the correction data reproducing unit 710 subtracts the second input data from the first input data. Then, the timing of 2 pixel clocks before, that is, the value of the correction value “1023” before 1 memory address timing is input to the first input, and the value “1” of the data P is input to the second input. The The output of the addition / subtraction circuit 713 of the hierarchy 255 in the correction data reproducing unit 710 becomes 1022 when 1023-1 = 1022, and this value is stored in the memory cell 705 of the 255th hierarchy of the first LUT unit 701.

(Address timing 3-4)
Next, until the memory address timings 3 and 4 of the line address L0, there is no addition / subtraction in the addition / subtraction circuit 713, and the output of the addition / subtraction circuit 713 in the 255th hierarchy in the correction data reproduction unit 710 remains at 1022. Are sequentially written to the memory cell 705 in the 255th layer of the first LUT unit 702.

(Address timing ~ 511)
Thereafter, in the fifth embodiment, up to the memory address 511 of the line address L0, that is, up to 1023 as the pixel address timing, and as the memory address timing, the data P is alternately displayed once every two data timings and three data timings. Is “1” and data S is “0”. In this data value, the addition / subtraction circuit 713 in the 255th layer of the correction data reproducing unit 710 sets 1 to the data output value immediately before the memory address. Subtraction is performed, and this value is sequentially stored in the memory cell 705 in the 255th layer of the first LUT unit 702. Similarly, the same correction data is reproduced from the line addresses L1 to L767.

(0 to 255 layer data playback)
As described above, the initial value data of the correction values of the respective scan lines from the line addresses L1 to L767 written to the 256 memory cells 707 corresponding to the 0th to 255th hierarchies of the second LUT unit 702 In the 256 addition / subtraction circuits 713 corresponding to the hierarchy from 0 to 255 of the correction data reproducing unit 710, the gradation correction difference values between the respective memory address data are stored in the respective memory cells 707 as shown in FIG. Reproduction is performed as a non-uniformity correction value at every two pixel clock timing corresponding to the read data unit, and 256 memory cells 705 corresponding to 0 to 255 hierarchies of the first LUT unit 702 are read out from the respective memory cells 707. Writing is performed sequentially at every two pixel clock timing corresponding to a data unit.

In this case, the memory address 0 for reading from the memory cell 707 described above corresponds to the display pixel addresses 0 and 1, and sequentially corresponds to the display address of two pixels in one data address.

(Tone correction in the first LUT unit)
On the other hand, in the first LUT unit 702, the 8-bit red image signal Di-R is input to the address decoding unit 703 shown in FIG. 3, and the input red image signal Di-R is input to the address decoding unit. At 703, it is decoded.

(Correction at address 0)
At the timing of the memory address 0 corresponding to the display pixel addresses 0 and 1 in the display unit of the line address L0 in the memory cell 707 of the second LUT unit 706, an 8-bit red input image to the first LUT unit 702 If the input value of the signal Di-R is, for example, 1, 1, 1, 1, 1, 1, 1, 1 (MSB: LSB) 8 bits, the decode value of the address decode unit 703 is 255. In this case, the port of the output signal S255 of the address decoding unit 703 is activated, and the output enable of the memory cell 705 in the 255th layer of the first LUT unit 702 is activated. From the memory cell 705 in the 255th hierarchy, the stored value 1,1,1,1,1,1,1,1,1,1,1, (MSB: LSB) as described above is displayed as an image. The signal is supplied to the DA converter 10 at the subsequent stage shown in FIG.

Note that the 10-bit digital outputs of the 255 memory cells 705 of the first LUT unit 702 are connected in parallel in units of binary values to form a data bus. However, only one memory cell 705 is activated at a time and is selected by the address decoding unit 703 out of 255 cells.

Following the timing of the display pixel addresses 0 and 1 of the line address L0 in the above-described display unit, the display pixel address timings of the display pixel addresses 2 to 1023 of the line address L0 are continued through the image signal input unit 701. The red signal is input in units of pixel clocks.

In this fifth embodiment, the value of the 8-bit red image input signal Di-R is assumed to be a white 100% signal and is a binary value of 1,1,1,1,1,1,1,1. (MSB: LSB) is a continuous signal, and in the first LUT unit 702, the memory cell 705 in the 255th layer is always active while this value is input.

The table value of the memory cell 705 in the 255th layer of the first LUT unit 702 is rewritten in units of two pixels as described above, and the first address is set at the timing of the pixel addresses 0 and 1 of the line address L0. The output signal of the LUT unit 702 outputs a value “1023” that is a table value of the memory cell 705 corresponding to the input signal level of the first LUT unit 702.

Thereafter, the table value of the memory cell 705 is decreased by 2 every 10 pixel addresses, that is, alternately by 2 memory addresses and 3 memory addresses, and at the pixel addresses 1022 and 1023, that is, the memory address 512, about “819”. To the value of "".

Therefore, the output of the memory cell 705, that is, the inputted decimal value of “1023” decreases from “1023” to “819” in units of two pixel clock periods. This value is supplied as the red output image signal Do-R of the first LUT unit 702 to the subsequent DA conversion unit 10 via the image signal output terminal 716.

Similarly, the red output image signal Do-R of the first LUT unit 702 from the line addresses L1 to L767 outputs the same output value as that of the line address L0 in the fifth embodiment. As a result, the left and right color balance can be obtained.

In this way, in the case of the color unevenness according to the fifth embodiment in which the above-described color unevenness in the display unit becomes more reddish from the left to the right of the screen and the red component increases by 20% at the right end of the screen. The output value of the output red image signal Do-R of the first LUT unit 702 is determined by the output value of the red image signal having a linear and gentle change of 20% attenuation at the right end of the screen with respect to the left end of the screen. Color unevenness on the left and right of the display screen is corrected.

(Correction at gradation below input level 254)
Similarly, in the case of the input level “254”, the 10-bit data of the memory cell 705 corresponding to the 254th layer of the first LUT unit 702 is the red color of the first LUT unit 702 of the gradation correction unit 7. Output as an output image signal Do-R. Similarly, at the input levels “253” to “0”, the 10-bit table value of the memory cell 705 in the hierarchy corresponding to the input level in the hierarchy “253” to “0” of the first LUT unit 702 is output. Then, the uneven color of the display image is corrected.

(Correction in red, green and blue)
In the above example, regarding the color unevenness in red, the color unevenness is reduced by correcting the gradation correction characteristics of the red image signal in units of pixels, but the red, green, and blue image signals are reduced. The gradation correction characteristics are performed in units of pixels or in units of a plurality of pixels by the gradation correction units 7, 8, and 9 shown in FIG. High-precision color unevenness correction can be realized.

As described above, in the fifth embodiment, the unevenness correction data in the horizontal direction is obtained as difference value data from the correction value of the previous two pixels of the memory cell 707 in the second LUT unit 706 in units of two pixels. The correction data reproducing unit 710 reproduces the correction value data in synchronization with the display pixel address and supplies the unevenness correction value in units of two pixels to the first LUT unit 702. The table value of the target hierarchy of the unit 702 is rewritten in units of two pixel display periods, and the table value corresponding to the input image signal is output as the output image signal to perform image display. Thereby, compared with the first embodiment described above, the memory capacity value required by the second LUT unit 706 can be reduced to almost half, and further cost reduction and downsizing can be realized.

(Data unit of 3 pixels or more)
Furthermore, the horizontal unevenness correction data described above is stored in advance in the second LUT unit 706 as one representative data in units of two pixel periods, and is reproduced as correction data in units of two pixel display periods during display. Nonuniformity correction in units of multiple pixels stored in the second LUT unit 706 as a single representative data in units of multiple pixels of three or more pixel periods, and stored in the second LUT unit 706 during display Play back the data to correct unevenness. As a result, the memory capacity required for the second LUT unit 706 can be further reduced.

(Sixth embodiment)
(Correction correction in units of multiple lines)
In the fifth embodiment, the unevenness correction in the horizontal direction of the display image is stored in the second LUT unit 706 in units of a plurality of pixels, and when the image is displayed, the correction data common to the units of the plurality of pixels is stored in a plurality of pixels. Each unit is reproduced by the correction data reproducing unit 710 and supplied to the second LUT unit 706 to correct the unevenness of the input image signal. On the other hand, a common correction value is stored in units of a plurality of lines, and when the image is displayed, the correction data in units of the plurality of lines is reproduced in the same way in a plurality of lines and supplied to the second LUT unit 706. An embodiment for correcting the unevenness of the input image signal will be described in detail below.

(Recording correction data)
As described in the first embodiment, when the display characteristics of the display screen are white, the white balance is maintained in the upper part of the vertical direction with respect to the vertical direction. When red is emphasized in proportion to the screen position toward the bottom of the screen and red is emphasized by 20% at the lower end of the screen, the color unevenness correction characteristic is that red is the last line from the first scan line. When the correction characteristic that linearly attenuates 20% up to the 768th line is required, the initial value data represented by L0PJ to L0PA on the first line is “1023” as a decimal value as the level of the red signal. The initial value data for the second to third lines is also “1023”, and the initial value data for the fourth line is “1022”. Then, the value attenuates in proportion to “1021” or more at the 8th line, and the initial value data is “819” at the 768th line.

In the case where such correction data is stored in advance in the second LUT unit 706, in the sixth embodiment, one hierarchy of the second LUT unit 706 as shown in FIG. Constitutes the memory address.

In the memory address of the second LUT unit 706 shown in FIG. 18, the initial value data common to the first line and the second line corresponding to the display address is stored in the addresses L0PJ to L0PA with 10 bits. In this sixth embodiment, the initial value data in this case is “1023” as a decimal value and “1,1,1,1,1,1,1,1,1,1” as a binary value. .

Next, the correction data as the above-described difference values corresponding to the respective pixels from the first pixel to the 1024th pixel is stored in the addresses of L0P0 to L0P1023 and L0S0 to L0S1023 in common for the first line and the second line. Is done.

Next, the initial value data common to the third line and the fourth line is stored as “1023” in the addresses of L1PJ to L1PA with 10 bits as described above.

Next, the correction data as the above-described difference value corresponding to each pixel from the first pixel to the 1024th pixel is stored in the addresses of L1P0 to L1P1023 and L1S0 to L1S1023 in common for the third line and the fourth line. Is done.

Next, the initial value data common to the 5th and 6th lines is stored as 1022 in the addresses of L2PJ to L2PA as “1022” as described above.

Next, the correction data as the above-described difference values corresponding to the respective pixels from the first pixel to the 1024th pixel are stored in the addresses of L2P0 to L2P1023 and L2S0 to L2S1023 in common with the fifth line and the sixth line. .

Thereafter, similarly, initial value data and correction data as the above-described difference values corresponding to the respective pixels from the first pixel to the 1024th pixel are stored in units of two lines. The initial value data is about “819” attenuated by about 20% in the final line in the sixth embodiment. Similarly, in the hierarchies 0 to 254, memory addresses are configured in the second LUT unit 706 to store data.

As described above, in the memory address shown in FIG. 18, the area indicated by the solid line is an area for storing data, and the area indicated by the broken line is an area that is not required to be stored in the sixth embodiment. Compared to the first embodiment described above, the memory capacity value required by the second LUT unit 706 can be reduced to almost half, and further cost reduction and size reduction can be realized.

(In case of display)
Next, when displaying an image signal, although not shown in the figure, the correction data stored in the second LUT unit 706 described above corresponds to the second LUT unit 706 in the first line of image display. The initial value data stored in the addresses L0PJ to L0PA of the memory cell 707 is read, and the data stored in the addresses L0P0 to L0P1023 and L0S0 to L0S1023 up to the 1st to 1024th pixels are then described in the first embodiment. As shown in FIG. 6, the correction data reproducing unit 710 sequentially reproduces the data as correction data, supplies the data to the first LUT unit 702, and rewrites the table value of the first LUT unit 702.

The red input image signal Di-R is converted by the first LUT unit 702 using the above-described input correction table value, and the unevenness corrected red output image signal Do-R is passed through the image signal output terminal 716. Then, the image is output to the DA converter unit shown in FIG.

Next, in the second line of image display, as in the first line, the initial value data stored in the addresses L0PJ to L0PA of the corresponding memory cells 707 of the second LUT unit 706, L0P0 to L0P1023, The data stored in the addresses L0S0 to L0S1023 is reproduced in the same manner as the first line, the table value of the first LUT unit 702 is rewritten, and the red input image signal Di-R is the first LUT unit 702. 1 is converted to the input correction table value and output to the DA converter unit shown in FIG. 1 as a red output image signal Do-R corrected for unevenness to the DA converter unit shown in FIG. Is displayed.

Next, in the third line and the fourth line, similarly to the first line and the second line, at the timing of the third line and the fourth line, the corresponding memory cells 707 of the second LUT unit 706 are respectively stored. Read initial value data of L1PJ to L1PA. Thereafter, the correction data reproduction unit 710 sequentially reproduces the correction data stored at the addresses L1P0 to L1P1023 and L1S0 to L1S1023 and supplies the correction data to the first LUT unit 702. The red input image signal Di-R is converted by the correction table value input in the first LUT unit 702, and the unevenness corrected red output image signal Do-R is passed through the image signal output terminal 716. The data is output to the DA converter unit shown in FIG.

Further, on the 5th and 6th lines, the 10-bit initial value data of L2PJ to L2PA of the corresponding memory cell 707 of the second LUT unit 706 is read, and the correction stored in the addresses of L2P0 to L2P1023 and L2S0 to L2S1023 The data is sequentially reproduced and supplied to the first LUT unit 702. The red input image signal Di-R is converted by the input correction table value in the first LUT unit 702, and unevenly corrected red color is corrected. The output image signal Do-R is output to the DA converter unit shown in FIG. 1 through the image signal output terminal 716 and displayed as an image.

In this case, the initial value of L2PJ to L2PA is “1022” as the decimal value, and the value of “1022” is the same as the value “255” of the input image signal Di-R of the first LUT unit 702. The first pixel of the two scanning lines is output via the image signal output unit 716.

Thereafter, the initial value data is attenuated in units of two scanning lines up to the final line, and the initial value data of the final line has a decimal value of almost “819” as described in the recording in the second LUT unit 706. .

As described above, the initial value data indicated by P and the subsequent pixel correction data indicated by P and S, which are common to the two lines read from the second LUT unit 706, are read for each scanning line. Then, the correction data reproducing unit 710 performs data reproduction of the correction value and sequentially supplies the data to the first LUT unit 702. Thereby, this table value is rewritten. Based on the table value of the first LUT unit 702, the output image signal Do-R corrected for unevenness corresponding to the value of the input image signal Di-R to the first LUT unit 702 is converted into an image signal output terminal 716. Then, an image that is output to the DA converter section shown in FIG. 1 shown later and corrected for color unevenness in the vertical direction is displayed.

(Correction of 0th to 254th hierarchy)
With the above operation, it is possible to correct unevenness in the vertical direction for the 255th layer of the input image signal. Further, as in the first embodiment, the correction data is similarly applied to the pixel display address of the display for the memory addresses of the memory cells 707 corresponding to the 254th to 0th layers of the second LUT unit 706. The initial value and the pixel correction data are reproduced in units of two lines in synchronization with each other, and the table values of the memory cells 705 in the 254th to 0th layers of the first LUT unit 702 are rewritten. Accordingly, the 10-bit gradation correction is executed in the first LUT unit 702 for all the gradations from 0 to 255 of the red input image signal Di-R. The corrected output image signal Do-R is output to the DA converter unit shown in FIG. 1 of the subsequent stage via the image signal output terminal 716, and the image corrected for color unevenness in the vertical direction is input from 0 to 255. Can be displayed in all gradations.

The unevenness correction by the above processing is an example in the red signal processing circuit for the red signal, but the same processing is also performed for blue and green, so that the color unevenness and brightness unevenness in all colors are Correction can be performed while maintaining and correcting continuous gradation specific to the display pixel. In the sixth embodiment, the correction value may be stored for every two lines, and the data amount can be halved compared to the example of the vertical unevenness correction according to the first embodiment described above.

In this embodiment, correction data is stored in the second LUT unit 706 every two lines to reduce the memory capacity. However, the correction data is stored in the second LUT unit 706 for each of a plurality of lines exceeding two lines. The correction data is continuously reproduced for each of the plurality of lines at the time of display on the display, and supplied to the first LUT unit 702, whereby the memory capacity of the second LUT unit 706 can be further reduced. .

(Seventh embodiment)
(Correction in units of multiple lines and multiple pixels)
Next explained is the seventh embodiment of the invention. In the above two embodiments, correction data is shared in units of two pixels and in units of two lines and stored in the second LUT unit 706, so that the second LUT is compared with the first embodiment. The storage capacity of the memory is ¼, and practical brightness and unevenness correction can be performed for all input gradations including gradation correction. An example of the data structure of the memory cell in one layer in this case is shown in FIG.

Further, in the vertical direction, a memory area is not required alternately for one scanning line indicated by a broken line, and a memory for one data is not required for two pixels in the horizontal direction.

Further, in the case of processing in units of n pixels and m lines, correction can be performed with a data amount that is approximately the inverse of the product of n and m. That is, when n is 3 and m is 3, the correction can be comprehensively performed with a memory amount of 1/9 compared to the first embodiment.

(Eighth embodiment)
Next, an eighth embodiment of the invention will be described. In the embodiment described above, correction data is stored in the second LUT unit 706 for each of a plurality of lines, and the correction data includes an initial value in the horizontal direction of the plurality of lines and each pixel in the horizontal direction following the initial value. It is configured as difference data of correction values between pixels or between a plurality of pixels with respect to the unevenness correction value. On the other hand, as shown in the above-described second embodiment, the horizontal unevenness correction data for a plurality of units of the scanning line is set to the initial value of the line, and the horizontal unevenness correction data following this value is determined in advance in the horizontal direction. It is possible to further reduce the memory of the second LUT unit 702 by configuring, for example, run-length encoded data obtained by encoding the number of pixels changing by the specified value or the value indicated by the time in units of a plurality of pixels. Become.

(Ninth embodiment)
In the embodiment described above, the storage address of the memory cell of the second LUT unit 706 is shared in the horizontal direction and the vertical direction corresponding to the image. As a result, the storage capacity of the second LUT unit 706 is reduced. In contrast to the memory cells 707 of 0 to 255 in the second LUT unit 706 according to the first embodiment described above, in the ninth embodiment, memory cells are shared in units of a plurality of layers.

Next, the configuration according to the ninth embodiment and the operation thereof will be described. FIG. 20 shows a circuit block configuration of a part of the second LUT unit 706, the initial value generation unit 708, and the correction data reproduction unit 710 in the ninth embodiment.

As shown in FIG. 20, except for the second LUT unit 706, the initial value generation unit 708, and a part of the correction data reproduction unit 710, the circuit block (see FIG. 3) according to the first embodiment described above is used. Therefore, the description thereof is omitted.

That is, the image signal input unit 701, the first LUT unit 702, the address decoding unit 703, the first memory table unit 704, and the first memory table unit 704 of the red signal digitally converted according to the ninth embodiment are provided. The 256 memory cells 705 provided from 0 to 255 are not shown. The second LUT unit 706 that stores the color unevenness and gradation correction value data of the display image in advance, the 128 memory cells 707 from 0 to 127 constituting the half of the second LUT unit 706, and the second LUT 128 memory cells 717 ranging from 0 to 127 constituting half of the portion 706 are provided.

The initial value generation unit 708 includes 256 initial value setting units 709. The initial value generation unit 708 also includes correction data reproduction units 710, 256 switching circuits 712 from 0 to 255, 256 addition / subtraction circuits 713 from 0 to 255, and 256 from 0 to 255. The latch unit 714 includes a latch circuit 715 and a red signal image signal output terminal 716.

In the circuit block as described above, the second LUT unit 706 includes 128 memory cells 707 according to the first embodiment, which is a half of 256. One memory cell 707 forms an address shown in FIG. The second LUT unit 706 further includes 128 memory cells 717.

The address configuration of one memory cell 717 is shown in FIG. As shown in FIG. 21, one memory cell 717 includes line addresses from L0 to L767, and in the first embodiment, 10 bits from initial value data addresses J to A are provided in the same manner as the address configuration shown in FIG. Is provided.

However, in the address configuration of the memory cell 717 according to the ninth embodiment, the horizontal pixel addresses 0 to 1023 are not provided. The second LUT unit 706 is configured with 128 memory cells 707 and 128 memory cells 717 alternately corresponding to layers 0 to 255, respectively. The configuration will be described below.

First, at the gradation 0, the data in the memory cell 707 in the hierarchy 0 is supplied to the initial value setting unit 709 in the hierarchy 0 of the initial value generation unit 708, and at the same time, the switching circuit 712 in the hierarchy 0 of the correction data reproducing unit 710. At the same time as the second input of the switching circuit 712 of the hierarchy 1 of the correction data reproducing unit 710.

In the gradation 1, the data in the memory cell 717 in the hierarchy 0 is supplied to the initial value setting unit 709 in the hierarchy 1 of the initial value generation unit 708.

Subsequently, in the gradation 2, the data of the memory cell 707 in the hierarchy 1 is supplied to the initial value setting unit 709 in the hierarchy 2 of the initial value generation unit 708, and at the same time, the hierarchy 2 switching circuit in the correction data reproduction unit 710 712 is supplied to the second input of the switching circuit 712 of the hierarchy 3 of the correction data reproducing unit 710.

In the gradation 3, the data in the memory cell 717 in the hierarchy 1 is supplied to the initial value setting unit 709 in the hierarchy 3 of the initial value generation unit 708.

Further, in the gradation 4, the data in the memory cell 707 in the hierarchy 2 is supplied to the initial value setting unit 709 in the hierarchy 4 in the initial value generation unit 708, and at the same time, the switching circuit 712 in the hierarchy 4 in the correction data reproducing unit 710. At the same time as the second input of the switching circuit 712 of the hierarchy 5 of the correction data reproducing unit 710.

In the gradation 5, the data in the memory cell 717 in the hierarchy 2 is supplied to the initial value setting unit 709 in the hierarchy 5 of the initial value generation unit 708.

Thereafter, similarly, in each gradation, the data of the memory cell 707 in each hierarchy and the memory cell 717 in each hierarchy are alternately supplied to a predetermined hierarchy corresponding to each of the initial value generation units 708, and the gradation 254 , The data in the memory cell 707 in the hierarchy 127 is supplied to the initial value setting unit 709 in the hierarchy 254 of the initial value generation unit 708.

At the same time, it is supplied to the second input of the switching circuit 712 of the hierarchy 254 of the correction data reproducing unit 710. At the same time, it is supplied to the second input of the switching circuit 712 of the hierarchy 255 of the correction data reproducing unit 710. At the gradation 255, the data in the memory cell 717 in the hierarchy 127 is supplied to the initial value setting unit 709 in the hierarchy 255 of the initial value generation unit 708.

Next, in the connection configuration as illustrated in FIG. 20, in the blanking period before the display of the scanning line L0, the display timing for sequentially displaying the scanning lines L0 to L767 as the display address of the display unit Initial addresses of the respective layers in which 10 addresses from the initial value addresses L0PJ to L0PA and J to A of the memory cell 707 shown in FIG. 5 are connected to the initial value generation unit 708 in FIG. 20 at the display pixel clock rate, respectively. It is taken into the value setting unit 709. At the display address A, as in the first embodiment described above, the parallel data is supplied to the first input of the switching circuit 712 of each layer of the correction data reproducing unit 710 at the subsequent stage.

At the same time, ten addresses from the initial value addresses L0PJ to L0PA and J to A of the memory cell 717 shown in FIG. 21 are displayed in the respective layers shown in FIG. 20 of the initial value generator 708 at the display pixel clock rate. The initial value setting unit 709 of FIG. At the display address A, as in the first embodiment, parallel data is supplied to the first input of the switching circuit 712 in each hierarchy of the correction data reproducing unit 710 at the subsequent stage.

All switching circuits 712 in the hierarchy of 255 corresponding to a total of 255 gradations including the above memory cell 707 and memory cell 717 select the first input at the display address A, and each hierarchy in the subsequent stage Are supplied to the second input of the addition / subtraction circuit 713 corresponding to.

Therefore, at the timing of the display address A, a unique initial value is supplied to the second input of the addition / subtraction circuit 713 from 0 to 255, respectively.

At the timing of the display address A, the output of the addition / subtraction circuit 713 in the hierarchy from 0 to 255 is connected to the first input of the addition / subtraction circuit 713 as the operation unit in the hierarchy from 0 to 255 in FIG. The latch circuit 715 in the 0 to 255 level in FIG. 3 (not shown) is immediately after reset, becomes “0”, outputs the initial value, and has the same 0 to 255 level in FIG. 3 as shown in FIG. Each data input of the latch circuit 715 is supplied to each of the memory cells 705 in the hierarchy from 0 to 255 of the first LUT unit 702 similar to that in FIG. 3 illustrated in FIG.

Data values generated at this timing and supplied to the memory cells 705 in the 0-255 hierarchy of the first LUT unit 702 are 256 values from 0 to 255 as shown in FIG. 6 in the first embodiment, for example. The 10-bit precision smooth gradation correction characteristic indicated by the data range of 0 to 1023 corresponding to the input gradation.

Next, at the display address 0 at the timing next to the initial value address A, all the switching circuits 712 in the respective layers of the correction data reproducing unit 710 are switched, and the second input is selected.

Next, 2 bits of L0P0 and L0S0 of the data address 0 of the line address 0 shown in FIG. 5 are read in each of the memory cells 707 in the hierarchy from 0 to 127 of the second LUT unit 706.

At this display address 0, as in the first embodiment, L0P0 is the absolute value of the change in the correction data. L0S0 is data designating addition or subtraction of addition / subtraction, and L0P0 is the second input of the addition / subtraction circuit 713 of the hierarchy of 0 to 255 via the second input of the switching circuit 712 of the hierarchy of 0 to 255, respectively. Supplied to the input.

Here, as in the connection of the circuit block diagram shown in FIG. 20, 128 memory cells 707 in the hierarchy from 0 to 127 are arranged every other 256 addition / subtraction circuits 713 corresponding to the hierarchy from 0 to 255. In the ninth embodiment, as described above, data is supplied by selecting and connecting to the even-numbered layers following the 0th layer, the second layer, and the fourth layer. Further, as in the connection of the circuit block diagram shown in FIG. 20, the data of 128 memory cells 707 corresponding to the above-mentioned hierarchy of 0-127 is 256 addition subtractions corresponding to the hierarchy of 0-255 at the same time. Similar data is supplied to the remaining one layer, three layers, and five layers of the circuit 713 and the odd-numbered layers that follow.

That is, hierarchy 0 and hierarchy 1, hierarchy 2 and hierarchy 3, hierarchy 4 and hierarchy 5, and the second input of addition / subtraction circuit 713 corresponding to hierarchy 254 and hierarchy 255 have the same data value in each pair. Is supplied.

FIG. 22 is an example of input and output values of the addition / subtraction circuits 713 in the hierarchy 255 and the hierarchy 254 and a timing diagram for explaining the operation thereof. In FIG. 22, a clock signal coincident with the pixel display timing, and memory addresses at timings J to A and 0 to 20 corresponding to the line L1 of the memory cell 707 are shown.

Further, the read values of the data P and data S in the hierarchy 255 and the hierarchy 254, the output value (decimal value) of the initial value sanction circuit, the first input, the second input, and the output of the addition / subtraction circuit, respectively The data value (decimal value) is displayed in units of clocks corresponding to memory addresses J to A and 0 to 20. The memory address of each line of memory cells 707 continues to 1023. Note that illustration of this part in FIG. 21 is omitted.

In FIG. 22, up to J to A of the memory address L0P of the hierarchy 127 of the memory cell 717 are sequentially read every clock, and simultaneously, the memory address L0P of the hierarchy 127 of the memory cell 707 is also read up to J to A at the same timing. .

The read serial data of 10 clock periods is omitted in FIG. 22, but the initial value setting unit 709 of the layer 255 and the initial value setting unit 709 of the layer 254 are the same as in the first embodiment. In addition, parallel data is output as initial values.

Also, the initial value setting unit 709 of the hierarchy 255 at the timing A shown in FIG. 22 is “1023” here, and the initial value setting unit 709 of the hierarchy 254 is “1022” here, and the hierarchy 255 and the hierarchy 254, respectively. The first input of the addition / subtraction circuit 713 is supplied to and selected by the second input of the switching circuit 712 and supplied to the second input of the addition / subtraction circuit 713 of the hierarchy 255 and 254 respectively. As described above, the value is “0”, and the second input value is input to the latch circuits of the layer 255 and the layer 254, which are not shown, and held until the next clock timing.

Next, as shown in FIG. 22, at the read timing 0 of the addresses L0P0 and L0S0 of the memory cell 707, the switching circuits 713 of the hierarchies 255 and 254 are switched at the predetermined timing, respectively. The P data of the memory cell 707 is connected to the second input of the addition / subtraction circuit 713 of the hierarchy 255 and the hierarchy 254, respectively. Further, the S data of the memory cell 707 in the hierarchy 127 is supplied in parallel to the addition / subtraction control terminals of the addition / subtraction circuit 713 in the hierarchy 255 and the hierarchy 254 as it is.

At the same time, the first input of the addition / subtraction circuit 713 of the hierarchy 255 and the hierarchy 254 includes the initial value of the hierarchy 255 and the initial value of the hierarchy 254 at the timing A held in the latch circuits of the hierarchy 255 and 254, respectively. Is input from the output of the addition / subtraction circuit 713 of the hierarchy 255 and the hierarchy 254, respectively. As shown in FIG. 21, the values are “1023” and “1022”, respectively.

Similarly, at addresses 1 to 4 of the memory cell 707, the P data and S data are “0”, and there is no change, and they are output from the addition / subtraction circuit 713 of the hierarchy 255 and the hierarchy 254 as shown in FIG. The values are “1023” and “1022”, respectively.

Next, at the address 5 of the memory cell 707, the P data is “1” and the S data is “0”. In the addition / subtraction circuit 713 of the hierarchy 255 and the hierarchy 254, the latch circuit of the hierarchy 255 and the hierarchy 254 is used. The P data is decremented by “1” and the S data is decremented by designating “0” to the stored values “1023” and “1022,” and the values “1022” and “1021” are output, respectively. These are held in the latch circuits 715 of the subsequent layers 255 and 254 and supplied to the memory cells 705 of the layers 255 and 254 of the first LUT unit 702 (not shown).

Similarly, as shown in FIG. 22, in the ninth embodiment, addition and subtraction of the layer 255 and the layer 254 are sequentially performed in units of the addresses 5, 10, and 15 of the memory cell 707 and in units of 5 pixel clocks. In the circuit 713, a value obtained by subtracting “1” is output and held in the latch circuit 715 of the layers 255 and 254 for one clock period, while the layers 255 and 254 of the first LUT unit 702 are stored. To the memory cell 705.

Similarly, in the hierarchy 253 to the hierarchy 0, the data in the hierarchy from 126 to 0 of the memory cells 707 in the respective hierarchies is reproduced by P and S every two hierarchies, and the hierarchy from the hierarchy 253 of the first LUT unit 702 is reproduced. It is supplied to memory cells 705 up to zero.

As described above, the correction value data is stored in the second LUT unit 706 with the initial value in each hierarchical unit and the correction value between pixels in two hierarchical units, and the data is reproduced when the image is displayed. This is supplied to the first LUT unit 702, and unevenness correction of pixel display addresses from 0 to 1023 is performed.

The line address 0 has been described above. Similarly, up to the line address 767, reproduction of initial values of the respective lines, and a similar hierarchy using uneven correction values of pixel addresses from 1 to 1024 corresponding to the number of horizontal pixels. Is performed.

By performing the correction described above for each of the blue and green image signals in addition to the red signal, it is possible to correct all the colors of the image input. Therefore, it is possible to realize optimum luminance unevenness and color unevenness correction at the same time while performing optimum gradation correction for each pixel. Therefore, in the second LUT unit 706, the required memory capacity is approximately halved compared to the case of the first embodiment, and it is possible to realize cost reduction and circuit scale reduction.

(Multiple levels)
Further, in the structure of the memory cell in the hierarchy from 0 to 255 in the second LUT unit 706 corresponding to 256 gradations, a memory cell 707 including an initial value data area and an inter-pixel correction data area, and an initial value A memory cell 717 consisting only of a data area is configured every other gradation, an initial value stores a unique value in each layer, an inter-pixel correction value stores common data in units of two layers, and uneven correction is performed. went. As described above, the memory cell 707 in one layer
On the other hand, the memory cell 717 is configured by a plurality of units of two or more hierarchies, the initial value stores a unique value in each layer, and the inter-pixel correction value stores the common data in a plurality of three or more hierarchies. The memory capacity required for the second LUT unit can be further reduced.

(Tenth embodiment)
(Correction in multiple layers, multiple lines, and multiple pixel units)
In the first to ninth embodiments described above, unevenness correction data is stored in the pixel display address area of the second LUT unit 706 in units of a plurality of layers, thereby reducing the memory capacity of the second LUT unit 706. ing. On the other hand, the pixel display address area hierarchy of the second LUT unit 706 is stored in common in a plurality of units, and at the same time, as described above, for example, correction is performed in a plurality of units of two pixel units and two line units. By sharing data and storing it in the second LUT unit 706, the memory capacity required for the second LUT unit 706 can be further reduced.

For example, by sharing the pixel correction address data of the second LUT unit 706 in units of two layers, two pixels, and two lines, the memory capacity required for the pixel correction address of the second LUT unit 706 is the first Compared with the memory capacity in the embodiment, the value can be reduced to almost one-eighth by a minus-th power value of 2.

Furthermore, by sharing the pixel correction address data of the second LUT unit 706 in units of three layers, three pixels, and three lines, the memory capacity required for the pixel correction address of the second LUT unit 706 is the first Compared with the memory capacity in the embodiment, a minus third power of 3 can be reduced to approximately 1/27.

(Eleventh embodiment)
(Stores unevenness correction data using run-length codes in multiple layers)
Next, as described in the second embodiment, for example, for the scan lines from 0 to 767, the horizontal unevenness correction data is sequentially set to the initial value of the line, and the horizontal unevenness correction data following this value data. Will be described with reference to a nonuniformity correction method in which, for example, run-length code data is encoded, which is obtained by encoding a value indicated by the number of pixels that changes by a predetermined value in the horizontal direction or a time in units of a plurality of pixels. The initial value from J to A of each scanning line of the unevenness correction data stored in the second LUT unit 706 is stored with initial value data addresses for all, for example, gradations from 0 to 255.

With respect to the data obtained by encoding the horizontal unevenness correction data following the initial value of each scanning line described above, the value indicated by the predetermined number of pixels changing in the horizontal direction or the time in units of a plurality of pixels, The correction value data address is stored as data common to multiple gradation units, and the initial value is reproduced for each gradation at the time of unevenness correction, and unevenness correction data for each scanning line is reproduced in multiple gradation units. By reproducing in common and performing unevenness correction, the memory capacity of the second LUT unit 706 can be reduced.

As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible.

For example, the numerical values given in the above embodiment are merely examples, and different numerical values may be used as necessary.

1 is a block diagram showing an entire circuit according to a first embodiment of the present invention. It is a basic diagram which shows the structure of the projection part of the 3 plate-type liquid crystal projector by 1st Embodiment of this invention. It is a block diagram which shows the gradation correction part by 1st Embodiment of this invention. FIG. 3 is a block diagram showing a configuration of a memory cell in a first LUT unit according to the first embodiment of the present invention. FIG. 6 is a diagram showing an address configuration of a memory cell in a second LUT unit according to the first embodiment of the present invention. It is a figure which shows the example of a characteristic of the gradation correction | amendment of one pixel. 6 is a timing chart showing the timing of reading from the memory cell of the second LUT unit according to the first embodiment of the present invention. It is a basic diagram which shows the structure of the gradation correction | amendment part by 2nd Embodiment of this invention. It is a figure which shows the structure of the data of the memory cell in the 2nd LUT part by 2nd Embodiment of this invention. It is a code | symbol table | surface in 2nd Embodiment of this invention. 6 is a timing chart showing the timing of reading from the memory cell of the second LUT unit according to the first embodiment of the present invention. It is a block diagram which shows the circuit structure of the decompression | decompression process part by 2nd Embodiment of this invention. It is a block diagram which shows the display apparatus by 3rd Embodiment of this invention. It is a circuit block diagram of the gradation correction | amendment part in 4th Embodiment of this invention. It is a figure which shows the address structure of the memory cell of the 2nd LUT part in 4th Embodiment of this invention. It is a figure which shows the address structure of the memory cell of the 2nd LUT part by 5th Embodiment of this invention. It is a read timing chart from the memory cell of the 2nd LUT part by a 5th embodiment of this invention. It is a figure which shows the address structure of the memory cell of the 2nd LUT part by 6th Embodiment of this invention. It is a figure which shows the address structure of the memory cell of the 2nd LUT part by 7th Embodiment of this invention. It is a figure which shows the 2nd LUT part by the 9th Embodiment of this invention, an initial value production | generation part, and a correction data reproduction | regeneration part. It is a figure which shows the address structure of the memory cell of the 2nd LUT part by 9th Embodiment of this invention. It is a timing chart which shows the timing of read-out of a memory cell and correction value reproduction by a 9th embodiment of this invention. It is a circuit block diagram of the display apparatus by a prior art. It is a basic diagram which shows the example of the screen division | segmentation in the display apparatus by a prior art.

Explanation of symbols

1, 2, 3 Image signal input terminals 4, 5, 6 AD conversion unit 7, 8, 9 Tone correction unit 10, 11, 12 DA conversion unit 13, 14, 15 Liquid crystal drive unit 16, 17, 18 Liquid crystal display unit 19 synchronization signal input terminal 20 timing signal generation unit 21 microcomputer unit 90 signal processing circuit 91 addition circuit 92 conversion circuit 93 drive circuit 94 memory 95 address counter 96 memory device 201 synchronization separation circuit 202 PLL circuit 203 timing signal generation circuit 701 image signal input Unit 702 first lookup table (LUT) unit 703 address decoding unit 704 first memory table unit 705 memory cell 706 second LUT unit 707 memory cell 709 initial value setting unit 710 correction data reproduction unit 711 decompression processing unit 712 Switching circuit 713 Addition / subtraction circuit (arithmetic unit)
714 Latch part 715, 723, 755, 761, 762, 763 Latch circuit 716 Image signal output terminal 717 Memory cell 756 Inverter 757 Changeover switch circuit 758 Decoder 759 Counter 760 0-value decoder 761 Data switch 764 Switch circuit part 767 Line address 1001 Light source 1002, 1003 Dichroic mirror 1004, 1005, 1006 Mirror 1007 Cross dichroic prism 1008 Projection lens 1009 Screen

Claims (9)

A correction apparatus of the image display apparatus for correcting the brightness or color variations in the display unit of the image display device,
A gradation correction unit that corrects the image signal of each pixel using correction data corresponding to the gradation value of the image signal, the pixel address in the horizontal direction, and the line address;
The gradation correction unit
Correction data for each gradation value can be stored, and when an image signal of one pixel is input, a first memory that outputs correction data corresponding to the gradation value of the input image signal;
A second memory that stores correction data for one line in a differential compression format for each line address;
According to the timing at which the image signal of each pixel is input to the first memory, correction data for all gradation values corresponding to the horizontal pixel address and line address of the input image signal are stored in the second memory. A correction data reproducing unit that reproduces the correction data in the differential compression format stored in the memory and writes correction data of all the reproduced gradation values in the first memory;
A correction device for an image display device, comprising: The correction data in the differential compression format includes an initial value corresponding to the correction data of the first pixel in the horizontal direction, and a difference from the correction data of the previous pixel as data for obtaining correction data of pixels other than the first pixel. Data consisting of values
The correction device for an image display device according to claim 1. The correction data in the differential compression format after the second line has a difference value with respect to the initial value of the previous line as the initial value.
The correction device for an image display device according to claim 2. One difference value is used to reproduce correction data of a plurality of pixels in the horizontal direction.
The correction device for an image display device according to claim 2, wherein the correction device is an image display device. One correction data in the differential compression format is used for reproducing correction data of a plurality of lines.
The correction apparatus for an image display apparatus according to claim 1, wherein the correction apparatus is an image display apparatus. The correction data in the differential compression format includes an initial value corresponding to the correction data of the first pixel in the horizontal direction, and the number of correction data having the same value as data for obtaining correction data of pixels other than the first pixel, Data that is encoded with a combination of the amount of change in the correction data value after a certain number of advances
The correction device for an image display device according to claim 1. The correction data in the differential compression format includes an initial value corresponding to correction data for the first pixel in the horizontal direction, and run-length encoded data as data for obtaining correction data for pixels other than the first pixel. Is composed data
The correction device for an image display device according to claim 1. A non-volatile third memory storing correction data in the differential compression format;
The second memory is a volatile random access memory;
When the correction device is started up, the correction data in the differential compression format is copied from the third memory to the second memory.
The correction apparatus for an image display apparatus according to claim 1, wherein the correction apparatus is an image display apparatus. A correction device for an image display device according to any one of claims 1 to 8,
A display unit that displays an image based on the image signal corrected by the gradation correction unit of the correction device;
An image display device comprising:

Images