JP2003043082A - Equipment and method for measuring jitter and tester for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an equipment and a method for measuring the jitters of a waveform to be measured in a short time with high precision, and a semiconductor integrated circuit tester. SOLUTION: A control circuit 20 outputs a start pulse ST for starting jitter measurement to an RS flip-flop 22. The RS flip-flop 22 outputs a signal S1 of 'H' level by the start pulse ST. By integrating this signal S1 by an integration circuit 23, the time having passed after the inputting of the start pulse ST to the RS flip-flop 22 is clocked. If a waveform WF to be measured exceeds a threshold value Vth , a stop pulse SP is outputted from a comparator 21, and the signal S1 becomes 'L' level. Accordingly, jitters are found by converting the integrated value of the integration circuit 23 into a digital data by an ADC circuit 25, and converting it into a time according to a table stored in a data map 27 after that.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter measuring apparatus and method, and a semiconductor integrated circuit testing apparatus called a so-called IC tester, and more particularly, to a jitter of a pulse signal having a short period of nano order of several nanoseconds. The present invention relates to a jitter measuring apparatus and method for measuring, and a semiconductor integrated circuit test apparatus for measuring jitter of a signal obtained by inputting a test pattern to a device under test.

[0002]

2. Description of the Related Art FIG. 6 is a diagram for explaining an example of a conventional jitter measuring method. The curve with the reference symbol DW in FIG. 6A indicates the measured waveform output from the device under measurement or the like. This measured waveform DW has, for example, a cycle T10 of about several nanoseconds, is sampled at a certain sampling cycle (this sampling cycle is sufficiently shorter than the cycle T10), and is converted into digital data. When measuring the jitter of the measured waveform DW, for example, as shown in FIG.
The rising portions d1, d2, d3, ... Of are overlapped.

FIG. 6B is a diagram showing a state in which the rising portions d1, d2, d3, ... Of the waveform DW to be measured are superimposed. As shown in FIG. 6B, the measured waveform DW
The rising edge of may be relative to the ideal rising time, may be earlier in time, or may be later in time. This rise time difference is the jitter. As described above, since the measured waveform DW is digital data, the measured waveform DW as shown in FIG.
W becomes discrete. Therefore, in order to measure the jitter of the discrete measured waveform DW, a threshold section having a certain width defined by the lower limit value V _t1 and the upper limit value V _t2 is set, and the data included in this threshold section is set. It is necessary to find the relationship (histogram) between the number and time.

Here, the reason why the threshold section having a certain width defined by the lower limit value V _t1 and the upper limit value V _t2 is set when the histogram is obtained is that the measured waveform DW is discrete digital data. is there. In other words, if a certain voltage value is set as the threshold value, there is a case where the threshold value is located between a certain voltage level of the measured waveform DW and another voltage level of the measured waveform DW that is adjacent in time. This is because, in such a relationship, the determination may not be made even though the voltage level of the waveform DW to be measured changes so as to pass the threshold value. Therefore, the threshold section is defined, and the rise of the measured waveform DW is determined when one or more of the discrete digital data of the measured waveform DW enters the threshold section.

FIG. 6C is a diagram showing an example of the obtained histogram. In the histogram shown in FIG. 6C, the horizontal axis represents time and the vertical axis represents the number of data included in the threshold section. When the histogram shown in FIG. 6C is obtained, the time interval of points at which the number of data is 1 / e (e is a natural logarithm) is centered around the time when the number of data is maximum from the distribution. Then, the time interval is used as the jitter.

[0006]

By the way, in the conventional method described with reference to FIG. 6, a certain finite value is used to measure the rising jitter of the digitized waveform DW to be measured as described above. It is necessary to set the threshold interval with. When the threshold section is set in this manner, if one rise of the measured waveform DW in the threshold section is focused on, the jitter is included also in the threshold section. For example, assuming that there are two pieces of digital data included in the threshold section at the rising edge, the digital data has different time and voltage levels, so that the rising edge has a temporal width. Since this time width causes an error in jitter measurement, it is desirable to define the width of the threshold section as small as possible in order to improve the jitter measurement accuracy.

However, when the threshold section is minutely defined, since the measured waveform DW is discrete digital data, the voltage level of the measured waveform DW and the measured waveform DW are temporally adjacent to each other. There is a risk that the threshold value may be located between other voltage levels that are set. In such a case, since the rising edge of the measured waveform DW is not detected,
There is a problem that inaccurate jitter is measured in the waveform of the noted period.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a jitter measuring apparatus and method and a semiconductor integrated circuit test apparatus capable of measuring the jitter of a waveform to be measured with high accuracy in a short time. To aim.

[0009]

In order to solve the above-mentioned problems, the jitter measuring apparatus of the present invention uses a jitter measurement start timing (t) for a measured waveform (WF) of an analog signal.
Setting means (20) for setting ₁ ) and the setting means (2)
(0) from the start timing (t ₁ ) until the measured waveform (WF) reaches a predetermined threshold value (V _th ), a time measuring means (21) for measuring a time (Δt, T1, T1 ′). To 27) are provided.
According to the present invention, the jitter measurement start timing is set for the measured waveform WF of the analog signal instead of measuring the jitter of the digital measured waveform as in the conventional case. Since the time until the measured waveform reaches a predetermined threshold value is measured,
The jitter of the signal under measurement can be measured with high accuracy.
The analog signal mentioned here is a signal that is not a sampled discrete signal. Therefore, a rectangular pulse having a sharp edge is not a discrete signal and is therefore included in the analog signal. The jitter measuring apparatus of the present invention is characterized in that the measured waveform (WF) has a period on the order of nanoseconds. Further, the jitter measuring device of the present invention is the time measuring means (21 to 27).
However, the jitter of the measured waveform (WF) is measured by measuring the time (Δt, T1, T1 ′) at each rising or falling of the measured waveform (WF). According to the present invention, the jitter is measured at each rising or falling of the waveform to be measured, and it is not necessary to obtain the jitter from the histogram as in the conventional case. Therefore, accurate data can be handled with a small amount of data. As a result, the jitter can be measured with high accuracy and the time required for the measurement can be shortened. Further, in the jitter measuring apparatus of the present invention, the setting means (20) outputs one of a pulse generated based on a preset setting value and a measurement reference clock (CK) input from the outside. Start timing (t
It is characterized by ₁ ). Further, in the jitter measuring apparatus of the present invention, it is preferable that the setting value and the threshold value (V _th ) can be changed based on setting data (D1) from the outside. Further, the jitter measuring device of the present invention,
The time measuring means (21 to 27) outputs the predetermined signal (S1) only from the start timing (t ₁ ) until the measured waveform (WF) reaches a predetermined threshold value (V _th ). A signal output unit (21, 22) and the predetermined signal (S1) output from the signal output unit (21, 22)
And a conversion section (27) for converting the signal (S2) integrated by the calculation section (23) into time according to a preset conversion table to obtain jitter. It has a feature. Further, in the jitter measuring apparatus of the present invention, it is preferable that the contents of the conversion table can be updated. Furthermore, it is preferable that the jitter measuring apparatus of the present invention further includes a storage unit (26) that stores the signal (S2) integrated by the calculation unit (23). In order to solve the above problems, the semiconductor integrated circuit test device of the present invention,
The reference clock (CK) is generated, and the device under test (50) is generated at the timing of the reference clock (CK).
Device (30) for generating a pattern (TP) to be given to
And the pattern (T
Setting means (2) for setting the reference clock (CK) to the start timing (t ₁ ) of the jitter measurement with respect to the measured waveform (WF) of the analog signal obtained when P) is given.
0) and the time (Δt, T) from the start timing (t ₁ ) set by the setting means (20) until the measured waveform (WF) reaches a predetermined threshold value (V _th ).
1 and T1 ′), and a jitter measuring device (10) provided with a clocking means (21 to 27). Further, the semiconductor integrated circuit testing device of the present invention is characterized in that the measured waveform (WF) has a cycle of nanosecond order. Further, in the semiconductor integrated circuit testing device of the present invention, the time measuring means (21 to 27) measures the time at each rise or fall of the measured waveform (WF) to obtain the measured waveform (WF). It is characterized by measuring the jitter of. In order to solve the above-mentioned problems, a jitter measuring method of the present invention comprises a setting step of setting a jitter measurement start timing (t ₁ ) for a measured waveform (WF) of an analog signal, and a setting step in the setting step. A time step of measuring a time (Δt, T1, T1 ′) from the started timing (t ₁ ) until the measured waveform (WF) reaches a predetermined threshold value (V _th ). I am trying. Further, in the jitter measuring method of the present invention, the timing step is performed only when the predetermined signal (from the start timing (t ₁ ) until the measured waveform (WF) reaches a predetermined threshold value (V _th ). S1) for outputting a signal, a calculation step for integrating the predetermined signal (S1), and a signal (S2) integrated in the calculation step is converted into time according to a preset conversion table to reduce jitter. It is characterized in that it includes a conversion step to be obtained.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A jitter measuring apparatus and method and a semiconductor integrated circuit testing apparatus according to an embodiment of the present invention will be described in detail below with reference to the drawings. First, the jitter measuring apparatus and method of the present invention and the principle of jitter measurement of the semiconductor integrated circuit test apparatus will be described. FIG. 1 is a diagram for explaining the principle of the jitter measuring apparatus and method and the semiconductor integrated circuit test apparatus of the present invention for measuring the jitter of a waveform under measurement. The present invention measures the jitter of the measured waveform WF itself of the analog signal instead of measuring the jitter of the measured waveform which is digitized as in the prior art. still,
The analog signal here means a signal that is not a sampled discrete signal. Therefore, a rectangular pulse with sharp edges is not a discrete signal,
Included in analog signal.

In the present invention, only one threshold value V _th for determining the rising of the waveform WF to be measured is set in FIG.
In addition, a highly accurate measurement reference clock that defines the jitter measurement start time is set for the measured waveform WF. In the example shown in FIG. 1, the measurement reference clock is input at time t ₁ , jitter measurement is started, the measured waveform WF rises, and the voltage level thereof exceeds the threshold value V _th (time t ₂ ). Finish the jitter measurement. Then, the jitter is measured by obtaining the time interval Δt between the time t ₁ at which the measurement reference clock is input and the time (time t ₂ ) at which the voltage level of the measured waveform WF exceeds the threshold value V _th .

As described above, in the present invention, the jitter is measured at each rising or falling of the waveform WF to be measured,
It is not necessary to obtain the jitter from the histogram as in the conventional case. If the measured waveform is digitally sampled as in the conventional case, histogram analysis must be performed based on many sample data. However, when the waveform to be measured is treated as analog as in the present invention, and the jitter value is obtained and analyzed for each period of the waveform,
Accurate data can be handled with a small amount of data. As a result, the jitter can be measured with high accuracy and the time required for the measurement can be shortened.

Next, a specific configuration for measuring jitter using the above principle will be described. FIG. 2 is a diagram showing a schematic front view of the jitter measuring apparatus according to the embodiment of the present invention. The external shape of the jitter measuring apparatus 10 shown in FIG. 2 is, for example, a shape of a conventional oscilloscope, and a waveform input end 11 to which a waveform to be measured is input and a clock to which a measurement reference clock is input are provided on the front surface thereof. An input terminal 12, a program data input terminal 13 for inputting program data for controlling the jitter measuring apparatus 10, an output terminal 14 for outputting a jitter measurement result, and a display 15 for displaying the measurement result in a graph format or a text format. Prepare

The measured waveform input from the measured waveform input terminal 11 is an analog signal having a nano-order period of, for example, about several nanoseconds. The above-mentioned measurement reference clock is input from the clock input terminal 12. The program data input from the program data input terminal 13 defines the operation of the jitter measuring apparatus 10, and includes data for setting the value of the threshold value V _th , for example. An example of the form of the program data will be described later.

Next, the internal structure of the jitter measuring apparatus of this embodiment will be described in detail. FIG. 3 is a block diagram showing the internal configuration of the jitter measuring apparatus according to the embodiment of the present invention. As shown in FIG. 3, the jitter measuring apparatus according to the present embodiment includes a control circuit 20, a comparator 21, an RS flip-flop 22, an integrating circuit 23, and a peak hold circuit 2.
4, analog / digital conversion circuit (hereinafter referred to as ADC circuit) 25, data memory 26, data map 27,
And a data display unit 28.

The control circuit 20 communicates with an external computer to receive the above-mentioned program data as the setting data D1, and transmits the data and signal designated by the setting data D1 to each block in the apparatus at the designated timing. . This program data is written in a certain language and can be edited by the user using a computer, for example.

The control performed by the control circuit 20 is specifically the control described below. That is, control for setting the threshold value V _th set in the program data to one input end of the comparator 21. Control for outputting a start pulse ST as a measurement reference clock to the RS flip-flop 22 at a predetermined timing based on the rate value set in the program data. Control for selecting whether to use the pulse generated based on the above rate value as the start pulse ST or to use the measurement reference clock CK input from the clock input terminal 12 (see FIG. 2) as the start pulse ST .

Control for outputting to the ADC circuit 25 a conversion start signal S12 defining the timing for converting the signal S3 output from the peak hold circuit 24 into a digital signal. Control for resetting the peak hold circuit 24 at a predetermined timing. Control for processing the data stored in the data memory 26 according to the program included in the setting data D1. Control for processing the contents of the data map 27 according to the program included in the setting data D1. Control for causing the data display unit 28 to display the content of the data stored in the data memory 26 or the content stored in the data map 27. The above control is controlled according to the program of the setting data D1.

The comparator 21 compares the voltage level between the threshold value V _th output from the control circuit 20 and the measured waveform WF input to the other input terminal. Waveform to be measured WF
If the threshold voltage V _th is higher than the voltage level of V, the signal that becomes the “L (low)” level is output, and conversely, if the voltage level of the measured waveform WF is higher than the threshold V _th , the voltage is “H”. (High) ”level signal is output. Comparator 21
The signal output from is used as a stop pulse SP for ending the jitter measurement described with reference to FIG.

The start pulse ST output from the control circuit 20 is input to the S input terminal of the RS flip-flop 22, and the stop pulse SP output from the comparator 21 is input to the R input terminal. That is, the measured waveform W
In one cycle of F, the RS flip-flop 22 is provided between the generation of the start pulse ST serving as a time measurement reference and the output of the stop pulse SP indicating that the rising of the measured waveform WF is detected. The signal S1 output from the output terminal becomes "H" level. In this embodiment, the signal S1 output from the RS flip-flop 22 is used.
Is integrated by the integrator circuit 23 and the time after the start pulse ST is input is measured. Therefore, the RS flip-flop 22 must output the signal S1 having a stable voltage value.

The integrating circuit 23 includes an RS flip-flop 2
The signal S1 output from 2 is integrated. That is, the control circuit 20 converts the start pulse ST to the analog voltage indicating the time from when the start pulse ST is output to when the measured waveform WF rises and the stop pulse SP is generated. The longer the RS flip-flop 22 outputs the signal S1 of "H" level, the longer the integration circuit 23.
The voltage value of the signal S2 output from is high. Incidentally, R
When the signal S1 output from the S flip-flop 22 is at “L” level, the signal S2 output from the integrating circuit 23 gradually decreases in signal level over time.

The peak hold circuit 24 is an integrating circuit 23.
It is a circuit that holds the maximum value of the signal S2 (analog voltage signal) output from. This peak hold circuit 24
A reset signal S10 is input from the control circuit 20, and when the level of the reset signal S10 becomes "H" level, the held maximum value is reset. In the present embodiment, in order to measure the jitter at each rising edge of the measured waveform WF, the peak hold circuit 24 is reset every cycle of the measured waveform WF. The reset timing is set by the setting data D1, but after the maximum value held by the peak hold circuit 24 is converted into a digital signal by the ADC circuit 25 and the signal is held in the data memory 26. The user previously programs the contents of the setting data D1 so that the peak hold circuit 24 is reset.

The ADC circuit 25 is the peak hold circuit 2
The signal S3 output from 4 is converted into a digital signal. The conversion timing of the ADC circuit 25 is determined by the control circuit 20.
Is defined by the timing signal S11 output from
When the timing signal S11 is output, the ADC circuit starts conversion. The conversion timing of the ADC circuit 25 is set by the setting data D1, but the peak hold circuit 2
The user preprograms the contents of the setting data D1 so that the ADC circuit 25 starts the conversion after the output of 4 becomes constant. Further, the ADC circuit 25 holds the current output until the next timing signal S11 is input.

The data memory 26 stores the data S4 (digital data) sequentially output from the ADC circuit 25 in the order of addresses. In the data memory 26, a signal defining the timing for writing the data S4 and the data memory 2
Signal S12 for erasing the data stored in 6
Is input from the control signal 20. Although the write timing is set by the setting data D1, the ADC circuit 25
In order for the data S4 to be written in the data memory 26 after the conversion processing in step S4 is completed, the user previously sets the setting data D.
Program the contents of 1.

The data map 27 stores a table showing the correspondence between the data stored in the data memory 26 (the data S5 output from the data memory 26) and the jitter. That is, the data stored in the data memory 26 is the digitally converted data obtained by integrating the “H” level signal S1 output from the RS flip-flop 22 by the integrating circuit 23.

As described above, the signal S2 output from the integrating circuit 23 is from the output of the start pulse ST from the control circuit 20 to the RS flip-flop 22 to the rise of the measured waveform WF and the generation of the stop pulse SP. The data map 2 is a table for obtaining the jitter (time) from this voltage value.
It is stored in 7.

A read signal S13 is output from the control circuit 20 to the data map 27, and the data map 27 is output.
Reads out the data of the address specified by the read signal S13 from the data memory 26, converts the value according to the table, and outputs the jitter measurement result S6.
The user can arbitrarily change the contents of the table. However, the change can be made only when the jitter measuring apparatus of the present embodiment is not measuring.

The control circuit 20 is constructed so that it can read the data stored in the data memory 26 and the data converted by the data map 27, and the read data is output to the data display unit 28. Has been
The user can visually see the contents of the data. The data display unit 28 has a configuration in which the user can arbitrarily switch the data display format, such as graph display or text display.

Next, the operation of the jitter measuring apparatus according to the embodiment of the present invention having the above-described configuration will be described. FIG. 4 is a timing chart for explaining the operation of the jitter measuring apparatus according to the embodiment of the present invention. In FIG. 4, the measured waveform WF and the threshold value V _th are shown on the same timeline. As described with reference to FIG. 1, in order to measure the jitter, the control circuit 20 outputs RS
This is the time from when the start pulse ST is output to the flip-flop 22 until the measured waveform WF exceeds the threshold value V _th . In the example shown in FIG. 4, it is necessary to measure the times T1, T1 ', ....

As described above, the control circuit 20 uses the pulse generated based on the rate value as the start pulse ST, or the clock input terminal 12 (see FIG. 2).
It is possible to select whether to use the measurement reference clock CK input from the control pulse 20 as the start pulse ST. However, in the following description, the case where the control circuit 20 uses the pulse generated based on the rate value as the start pulse ST will be described. An example will be described. Now, let the period of the pulse which the control circuit 20 produces | generates based on a rate value be T2. The period T2 needs to be set so as to match the period of the measured waveform WF.

Control circuit 20 to RS flip-flop 2
When the start pulse ST is output to 2, the level of the signal S1 output from the RS flip-flop 22 is "H".
Becomes The signal S1 is integrated in the integrating circuit 23, and the value of the signal S2 output from the integrating circuit 23 increases at a constant increase rate while the level of the signal S1 is "H".
As described above, the magnitude of the value of the signal S2 output from the integrating circuit 23 is proportional to the time when the RS flip-flop 22 outputs "H".

In FIG. 4, the measured waveform WF is the threshold value V _th.
When it exceeds, the stop pulse SP from the comparator 21
Is output and the RS flip-flop 22 is reset, the value of the signal S1 output from the integrating circuit 23 gradually decreases. Therefore, the maximum value of the value of the signal S2 (the integration circuit 23 at the time when the stop pulse SP is output)
The peak hold circuit 24 is used to hold the value of the signal S2 output from the.

Stop pulse SP from comparator 21
Is output and the peak hold circuit 24 holds the maximum value, the control circuit 20 outputs the ADC circuit 25.
On the other hand, the timing signal S11 is output and the analog signal S3 is converted into digital data. The timing (T3) for outputting the timing signal S11 is set based on the start pulse ST. The control circuit 20 outputs the signal S12 to the data memory 26 at the timing when the conversion processing in the ADC circuit 25 is completed, and the digital data converted at this timing is converted into the data memory 2
Write to 6. The timing of outputting the signal S12 (T
4) is set in consideration of the time relationship with the timing signal S11.

The digital data written in the data memory 26 is read by the read signal S13 output from the control circuit 20, output to the data map 27, converted into jitter based on the table, and the jitter measurement result S6.
Is output as. As the jitter measurement result S6, the same value is output until the timing signal S11 in the next cycle of the measured waveform WF is given. After the digital data is written in the data memory 26, the reset signal S10 is output from the control signal 20 to the peak hold circuit 24, and the peak hold circuit 24 is reset. This is to measure the next cycle of the measured waveform.
It should be noted that the timing at which the reset signal S10 is output (T
5) is set in consideration of the temporal relationship with the signal S12.

Next, a semiconductor integrated circuit testing device according to an embodiment of the present invention will be described. FIG. 5 is a block diagram showing a schematic configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention. As shown in FIG. 5, the semiconductor integrated circuit test apparatus of this embodiment includes an IC tester 30, a jitter measuring apparatus 10, and a host computer 40. The jitter measuring apparatus 10 described above can be used alone for the jitter measurement, and in combination with the IC tester and the host computer 40, the IC tester 3 can be used.
The function of 0 can be used in the expanded form.

The host computer 40 programs the measurement timing of the device under test 50 and displays the output result. The test program P1 transmitted by the host computer 40 includes setting data D1 for operating the jitter measuring apparatus 10, in addition to a program for operating the IC tester 30. The measurement result R1 received by the host computer 40 from the IC tester 20 includes the jitter measurement result S6 measured by the jitter measuring apparatus 10.
In addition, the measurement result obtained by performing measurement using other functions of the IC tester 30 is also included.

The IC tester 30 includes a reference clock generation circuit 31 for measuring the device under test 50 and a pattern generation circuit 32 for generating a pattern at the timing of the measurement reference clock CK output from the reference clock generation circuit 31. Pattern T output from the pattern generation circuit 32
P is supplied to the device under test 50 and the pattern TP
In response to, the signal output from the device under measurement 50 is supplied to the jitter measuring apparatus 10 as the measured waveform WF from the measured waveform input terminal 11. Further, since the pattern generation circuit 32 generates the pattern TP at the timing of the measurement reference clock CK, the measurement reference clock CK is also supplied to the jitter measuring apparatus 10 via the clock input terminal 12.

In the semiconductor integrated circuit testing device having the above-described structure according to the embodiment of the present invention, the host computer 4
When the test program P1 is output from 0, the setting data D1 included in this test program is transferred to the IC tester 3
It is output to the jitter measuring apparatus 10 via 0. The control circuit 20 (see FIG. 3) included in the jitter measuring apparatus 10 transmits data and signals to each block in the apparatus at designated timing based on the setting data D1.

Reference clock generation circuit 3 of IC tester 30
When the measurement reference clock CK is output from 1, it is supplied to the pattern generation circuit 32 and the jitter measuring apparatus 10. The pattern generation circuit 32 generates the pattern TP at the timing of the measurement reference clock 31 and supplies it to the device under test 50. The device under test 50 outputs a response signal in response to the pattern TP. This signal is supplied to the jitter measuring apparatus 10 as the measured waveform WF, and the above-described processing is performed to measure the jitter of the measured waveform WF.

The jitter measurement result S6 is the jitter measurement device 10
Is output from the output terminal 14 to the IC tester 30 and is further output to the host computer 40 as the measurement result R1. In this way, the semiconductor integrated circuit test apparatus of this embodiment measures the jitter of the signal output from the device under test 50 as one of the tests. Although the case where the jitter at the rising edge of the measured waveform WF is measured has been described above as an example, the same measurement can be performed when the jitter at the falling edge of the measured waveform WF is measured.

Next, an example of programming the setting data D1 will be described. The setting data D1 is written in a certain programming language, and by transmitting this setting data D1 to the control circuit 20 provided in the jitter measuring apparatus 10,
It is possible to measure the jitter of the measured waveform WF and manipulate the digital data in the data memory 26 (see FIG. 3) at any timing determined by the user. The following are examples of contents, points to be noted, and forms to be programmed.

The program items necessary for operating the jitter measuring apparatus are as follows.・ Setting of threshold value V _th・ Setting of rate value ・ Selection command of whether measurement reference clock input from outside as start pulse ST or clock generated at rate value is used ・ Peak hold circuit 24 is reset Timing • Timing of starting conversion in the ADC circuit 25 • Write timing of the data memory 26 • Operation command of the data memory 26 • Operation command of the data map 27

Details of each program item are as follows. -Threshold setting Defines which voltage level jitter is measured for the measured waveform. (Example) level = 2.5V

Setting of rate value A start pulse ST having a rate value as a cycle is generated with reference to the first clock of the measurement reference clock input from the outside. (Example) rate = 1.0us

Selection of whether to use a measurement reference clock input from the outside as the start pulse ST or to use a clock generated at a rate value Whether to use a start pulse according to the setting of the command rate value, or an external clock Set whether to use. (Example) start_pulse = rate or start_pulse = clk

Timing for resetting the peak hold circuit 24 A command for resetting the peak value held in the peak hold circuit 24. ADC reset timing
The data S4 output from the circuit 25 is stored in the data memory 26
After storing to. (Example) peak_rst = 65ns

A timing for starting conversion in the ADC circuit 25 A command for starting AD conversion. The timing for starting the conversion is preferably when the output of the peak hold circuit 24 becomes constant. (Example) adc_st = 50ns

Writing timing of the data memory 26 When the conversion in the ADC circuit 25 is completed, the digital data is stored in the data memory 26. Specify this timing. (Example) DataMemory = 60ns

Operation command of data memory 26 Writing, reading, and clearing of the data memory can be performed at any time. (Example) Write DataMemory (ADDRESS, DataIn, “writ
e ”) (Example) Read DataMemory (ADDRESS, DataOut,“ rea
d ") (Example) Clear DataMemory (ADDRESS, 0ns,“ clear ”)

Operation command of data map 27 Since this data map can be rewritten only in the background (that is, in the state where the jitter measuring device is not performing the measurement operation), there is no setting of the rewriting timing.
The following operations can be performed only in the background. (Example) Rewrite DataMap (DigitalData, JitterData,
“Write”) (Example) Read DataMap (DigitalData, DataOut, “rea
d ") (Example) Clear DataMap (DigitalData, 0ps," clear ")

[0051]

As described above, according to the present invention,
Rather than measuring the jitter of the waveform to be measured digitized as in the past, the start timing of the jitter measurement is set for the waveform to be measured WF of the analog signal, and the waveform to be measured is predetermined from this start timing). Since the time until the threshold is reached is measured, there is an effect that the jitter of the signal under measurement can be measured with high accuracy. Further, according to the present invention, the jitter is measured at each rising or falling edge of the waveform to be measured, and it is not necessary to calculate the jitter from the histogram as in the conventional case. Therefore, accurate data can be handled with a small amount of data. it can. As a result, there is an effect that the jitter can be measured with high accuracy and the time required for the measurement can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the jitter measuring apparatus and method and the semiconductor integrated circuit test apparatus of the present invention for measuring the jitter of a measured waveform.

FIG. 2 is a diagram showing a schematic front view of a jitter measuring apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram showing an internal configuration of a jitter measuring apparatus according to an embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the jitter measuring apparatus according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a semiconductor integrated circuit testing device according to an embodiment of the present invention.

FIG. 6 is a diagram for explaining an example of a conventional jitter measuring method.

[Explanation of symbols]

10 Jitter Measuring Device 20 Control Circuit (Setting Unit) 21 Comparator (Time Measuring Unit, Signal Output Unit) 22 RS Flip-Flop (Time Measuring Unit, Signal Output Unit) 23 Integrating Circuit (Time Measuring Unit, Calculation Unit) 24 Peak Hold Circuit (Time Measuring Unit) ) 25 ADC circuit (time measuring means) 26 data memory (storage section) 27 data map (time measuring means, conversion section) 30 test device 50 device under test CK measurement reference clock (reference clock) D1 setting data S1 signal (predetermined signal) S2 signal T1, T1 'time t ₁ hour (start timing) TP pattern V _th threshold value WF measured waveform Δt time interval (time)

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Koichiro Kurihara             2081-28 Tahara, Mashiki-machi, Kamimashiki-gun, Kumamoto             Kyushu Ando Electric Co., Ltd. F term (reference) 2G132 AD10 AG01 AL09 AL11

Claims (13)

[Claims] 1. A setting means for setting a start timing of jitter measurement with respect to a measured waveform of an analog signal, and from the start timing set by the setting means until the measured waveform reaches a predetermined threshold value. A jitter measuring apparatus comprising: a time measuring unit for measuring time. 2. The jitter measuring apparatus according to claim 1, wherein the waveform to be measured has a period on the order of nanoseconds. 3. The time measuring means measures the time at each rising or falling of the measured waveform,
The jitter measuring apparatus according to claim 1 or 2, wherein the jitter of the waveform to be measured is measured. 4. The setting means uses, as the start timing, one of a pulse generated based on a predetermined set value and a measurement reference clock input from the outside. The jitter measuring device according to any one of claims 1 to 3. 5. The jitter measuring apparatus according to claim 1, wherein the set value and the threshold can be changed based on setting data from the outside. 6. The signal output unit, which outputs a predetermined signal only from the start timing until the measured waveform reaches a predetermined threshold value, and the signal output unit outputs the signal. 3. The method according to claim 1, further comprising: an arithmetic unit that integrates a predetermined signal, and a converter that converts the signal integrated by the arithmetic unit into time according to a preset conversion table to obtain jitter. 5. The jitter measuring device according to any one of 5 above. 7. The jitter measuring apparatus according to claim 6, wherein the contents of the conversion table can be updated. 8. The jitter measuring apparatus according to claim 6, further comprising a storage unit that stores the signal integrated by the calculation unit. 9. A test apparatus for generating a reference clock and a pattern to be given to a device under test at the timing of the reference clock, and a measured analog signal obtained when the pattern is given to the device under test. Setting means for setting the reference clock to the start timing of jitter measurement for a waveform, and a timekeeping for measuring the time from the start timing set by the setting means until the measured waveform reaches a predetermined threshold value A semiconductor integrated circuit test apparatus, comprising: a jitter measuring apparatus including: 10. The semiconductor integrated circuit testing device according to claim 9, wherein the measured waveform has a period on the order of nanoseconds. 11. The method according to claim 9, wherein the time measuring means measures the jitter at each rising or falling of the measured waveform to measure the jitter of the measured waveform. Semiconductor integrated circuit test equipment. 12. With respect to a measured waveform of an analog signal,
It is characterized by comprising a setting step for setting the start timing of the jitter measurement, and a time counting step for measuring the time from the start timing set in the setting step until the measured waveform reaches a predetermined threshold value. Jitter measurement method. 13. The signal measuring step of outputting a predetermined signal only from the start timing until the measured waveform reaches a predetermined threshold value, and a calculation step of integrating the predetermined signal. 13. The jitter measuring method according to claim 12, further comprising: and a converting step of converting the signal integrated in the calculating step into time according to a conversion table set in advance to obtain jitter.