JP2003037128A - Method of manufacturing solder bump electrode - Google Patents
Method of manufacturing solder bump electrodeInfo
- Publication number
- JP2003037128A JP2003037128A JP2001224582A JP2001224582A JP2003037128A JP 2003037128 A JP2003037128 A JP 2003037128A JP 2001224582 A JP2001224582 A JP 2001224582A JP 2001224582 A JP2001224582 A JP 2001224582A JP 2003037128 A JP2003037128 A JP 2003037128A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- solder bump
- bump
- copper
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半田金属間化合物の
抑制に関し、具体的には、半導体装置上への半田バンプ電
極製造における脆弱な半田金属間化合物生成の抑制方法
と構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to suppression of solder intermetallic compounds, and more particularly, to a method and structure for suppressing generation of brittle solder intermetallic compounds in the production of solder bump electrodes on a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置の実装、接続技術である「フリ
ップチップ」は、はんだバンプを用いた実装、接続技術と
して知られている。従来、はんだバンプを形成する方法
として蒸着法とめっき法と印刷法が知られている。図２
に従来の印刷法による、はんだバンプを製造方法を示す。
半田バンプの印刷は、印刷前に電極下地部の形成を必要
とする。この電極下地部は半田を印刷させるために必要
である。2. Description of the Related Art "Flip chip", which is a mounting and connecting technique for semiconductor devices, is known as a mounting and connecting technique using solder bumps. Conventionally, vapor deposition, plating and printing are known as methods for forming solder bumps. Figure 2
A method of manufacturing solder bumps by a conventional printing method is shown in FIG.
Printing solder bumps requires the formation of an electrode underlayer prior to printing. This electrode base portion is necessary for printing solder.
【０００３】図２(ａ)は、下地金属膜２と金属導電層３
で表面が被覆された半導体基板１を示す。従来、下地金
属膜２としてＣｒやTi-Wが用いられてきた。またこの薄
膜は電極下地部４である銅バンプをめっきするための金
属導電層の一部分として機能する。FIG. 2A shows a base metal film 2 and a metal conductive layer 3.
A semiconductor substrate 1 whose surface is covered with is shown. Conventionally, Cr or Ti-W has been used as the base metal film 2. Further, this thin film functions as a part of the metal conductive layer for plating the copper bump which is the electrode base portion 4.
【０００４】金属導電層３が形成された後の第2ステッ
プはフォトリソグラフィによるめっきマスクの形成であ
る。 金属導電層上にフォトレジストを塗布し、露光、現像
する。フォトレジストはめっきマスクとして残る。フォト
レジストがめっきマスク４として図２(ａ)に示されてい
る。The second step after the metal conductive layer 3 is formed is to form a plating mask by photolithography. A photoresist is applied on the metal conductive layer, exposed and developed. The photoresist remains as a plating mask. The photoresist is shown in FIG. 2 (a) as the plating mask 4.
【０００５】第3ステップはめっきマスク開口部への銅
めっきである。電極下地部として銅バンプが形成された
後、このフォトレジストを除去する。この時点で半導体基
板は金属導電層と銅バンプとで覆われている。これは図
２(ｂ)に示されている。The third step is copper plating on the plating mask opening. After the copper bump is formed as the electrode base portion, the photoresist is removed. At this point, the semiconductor substrate is covered with the metal conductive layer and the copper bumps. This is shown in FIG. 2 (b).
【０００６】下地金属膜２および金属導電層３は銅バン
プ形成された後、銅バンプをマスクとして除去する。図２
(ｃ)は、下地金属膜２および金属導電層３が除去されて、
電気的には分離されているが機械的には半導体基板に固
定された銅バンプが残った状態を示す。After the base metal film 2 and the metal conductive layer 3 are formed with copper bumps, the copper bumps are removed by using the copper bumps as a mask. Figure 2
In (c), the base metal film 2 and the metal conductive layer 3 are removed,
The figure shows a state in which copper bumps that are electrically separated but mechanically fixed to the semiconductor substrate remain.
【０００７】図２(ｄ)はスクリーン印刷により半田ペー
ストを印刷後、リフローし半田バンプ５を形成する。こ
の時点で半田バンプが形成された半導体装置は実装を行
なうことができる。In FIG. 2D, after solder paste is printed by screen printing, reflow is performed to form solder bumps 5. At this point, the semiconductor device on which the solder bumps are formed can be mounted.
【０００８】従来の技術で電極下地部４の銅バンプ表面
に直接半田バンプ５を形成しているため電極下地部４と
半田バンプ５界面に半田金属間化合物７が形成された。
この金属間化合物は機械的に脆弱であるため、この半導
体装置は実装後信頼性試験において金属間化合物界面よ
り破壊する。Since the solder bumps 5 are directly formed on the surface of the copper bumps of the electrode base portion 4 by the conventional technique, the solder intermetallic compound 7 is formed at the interface between the electrode base portion 4 and the solder bump 5.
Since this intermetallic compound is mechanically weak, this semiconductor device is destroyed from the intermetallic compound interface in the reliability test after mounting.
【０００９】図２（e）は電極下地部４である銅バンプ
表面にニッケル(Ｎｉ)８をめっきしたものを示す。ニッ
ケルを銅バンプ表面を堆積させることで電極下地部であ
る銅バンプと半田バンプとの間に金属間化合物を形成し
ないため、従来よく用いられてきた。しかし、電極下地
部４の銅バンプ形成後にニッケル８をめっきさせる必要
があるため工程が長くなっていた。FIG. 2 (e) shows that the surface of the copper bump which is the electrode base portion 4 is plated with nickel (Ni) 8. Since nickel is not deposited on the surface of the copper bump to form an intermetallic compound between the copper bump which is the electrode base and the solder bump, it has been often used conventionally. However, since it is necessary to plate nickel 8 after forming the copper bumps of the electrode base portion 4, the process is long.
【００１０】[0010]
【発明が解決しようとする課題】したがって、本発明は、
電極下地部表面に下地金属の副生成物を形成し従来のニ
ッケルめっきを用いずに半田バンプとの界面に半田金属
間化合物を形成させずに半田バンプを製造する方法と構
造である。Therefore, the present invention is
It is a method and structure for manufacturing a solder bump by forming a by-product of a base metal on the surface of an electrode base and forming a solder intermetallic compound at the interface with the solder bump without using conventional nickel plating.
【００１１】[0011]
【課題を解決するための手段】前記課題を解決するため
に本発明は半田バンプを形成する前に下地金属膜をエッ
チングし、電極下地部表面にエッチング時に生成する下
地金属の副生成物を堆積させた後に半田バンプを形成す
る方法。この方法で製造された半田バンプは半田バンプ
と電極下地部の間に下地金属の副生成物があるため、半
田が電極下地部との界面に脆弱な半田金属間化合物層を
形成せず機械的に丈夫な半田バンプである。In order to solve the above problems, the present invention etches a base metal film before forming solder bumps, and deposits a base metal by-product generated during etching on the surface of an electrode base portion. A method of forming solder bumps after the above. Since the solder bumps produced by this method have a by-product of the base metal between the solder bumps and the electrode underlayer, the solder does not form a brittle solder intermetallic compound layer at the interface with the electrode underlayer and mechanically It is a durable solder bump.
【００１２】[0012]
【発明の実施の形態】本発明はＳｎ−Ａｇ半田を用いた
半田バンプにおいて、電極下地部表面のＣｕの存在下で
Ｔｉ−Ｗ膜を選択的にエッチングし、そのエッチング中
にTi-Wを含有する副生成物を電極下地部である銅バンプ
表面に体積させ脆弱な半田金属間化合物の生成を抑制す
る半田バンプの製造方法である。BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, in a solder bump using Sn-Ag solder, a Ti-W film is selectively etched in the presence of Cu on the surface of an electrode underlayer, and Ti-W is removed during the etching. It is a method for manufacturing a solder bump in which a contained by-product is deposited on the surface of a copper bump that is an electrode base portion to suppress the formation of a brittle solder intermetallic compound.
【００１３】本発明は半田と金属間化合物を形成する電
極下地部表面に半田と金属間化合物を形成しない物を下
地金属膜を用いて形成する半田バンプの製造方法とその
半田バンプ構造を対象とする。The present invention is directed to a solder bump manufacturing method and a solder bump structure thereof in which a material not forming solder and an intermetallic compound is formed on a surface of an electrode base portion forming a solder and an intermetallic compound by using a base metal film. To do.
【００１４】図１に本発明の実施例を示す。図１（a）は
本発明を用いた半田バンプの完成図である。実施例の製
造工程は半導体基板１１としてシリコン(Ｓｉ)ウエハ上
にシリコン酸化膜、Ａｌ−Ｓｉ，シリコン窒化膜からな
る。この基板に、下地金属として０．１５ミクロンのＴｉ
−Ｗ(図１(b)１２)と金属導電層の０．５ミクロンのＣ
ｕ(図１(b)１３)をスパッタリングし、めっきマスク(図
１(b)１４)を形成。この半導体基板にＣｕを２０ミクロ
ンをめっきし銅バンプ(図１(b)１５)を形成し電極下地
部とする。銅バンプ形成後めっきマスク１４であるフォ
トレジストを有機溶剤とレジストアッシングで除去し硫
酸＋過酸化水素水＋水からなるエッチング液で０．５ミ
クロンのＣｕ(図１(c)１３)を除去する。このとき銅バ
ンプ(図１(c)１５)下のCuは銅バンプがあるためエッチ
ングされずに残る。FIG. 1 shows an embodiment of the present invention. FIG. 1A is a completed view of a solder bump using the present invention. In the manufacturing process of the embodiment, a silicon oxide film, Al-Si, and a silicon nitride film are formed on a silicon (Si) wafer as the semiconductor substrate 11. 0.15 micron Ti is used as a base metal on this substrate.
-W (Fig. 1 (b) 12) and 0.5 micron C of metal conductive layer
u (FIG. 1 (b) 13) is sputtered to form a plating mask (FIG. 1 (b) 14). Cu of 20 μm is plated on this semiconductor substrate to form copper bumps (15 in FIG. 1 (b)), which are used as electrode bases. After forming the copper bumps, the photoresist which is the plating mask 14 is removed by an organic solvent and resist ashing, and Cu of 0.5 micron (FIG. 1 (c) 13) is removed by an etching solution composed of sulfuric acid + hydrogen peroxide solution + water. . At this time, Cu under the copper bump (15 in FIG. 1C) remains without being etched because there is a copper bump.
【００１５】次に、ハロゲン系ガス(４塩化炭素(ＣＣｌ
４)や６弗化硫黄(ＳＦ６)等)を用いたドライエッチング
を行い、下地金属であるTi-W(図１(c)１２)をエッチン
グしながら電極下地部の銅バンプ表面にTi-Wを含有する
副生成物(図１(c)１７)を堆積させる。Next, a halogen-based gas (carbon tetrachloride (CCl
4) and sulfur hexafluoride (SF6) etc.) are used for dry etching to etch Ti-W (Fig. 1 (c) 12), which is the base metal, on the surface of the copper bumps under the electrodes. A by-product (FIG. 1 (c) 17) containing a is deposited.
【００１６】その後、スクリーン印刷法により表面に副
生成物をもつ銅バンプの上に半田ペーストを形成させリ
フローを行い半田バンプを形成し完成する図１（a）。After that, a solder paste is formed on a copper bump having a by-product on the surface by screen printing and reflow is performed to form a solder bump, which is completed in FIG. 1 (a).
【００１７】[0017]
【発明の効果】本発明によって得られた半田バンプは半
田バンプと電極下地部の間に下地金属の副生成物がある
ため、半田が電極下地部との界面に脆弱な半田金属間化
合物を生成さずに機械的に丈夫な半田バンプを形成でき
る。また、半田金属間化合物を形成しないニッケルを電
極下地部の銅バンプにめっきせずに同等の機能を有する
ためニッケルめっきの工程分プロセスを短くできる。Since the solder bump obtained by the present invention has a by-product of the base metal between the solder bump and the electrode base, the solder forms a brittle solder intermetallic compound at the interface with the electrode base. Instead, mechanically strong solder bumps can be formed. Further, since nickel having no solder intermetallic compound is plated on the copper bumps of the electrode base portion and has the same function, the nickel plating process can be shortened.
【図１】本発明を用いた実施例の半田バンプの製造工程
を示す。FIG. 1 shows a manufacturing process of a solder bump according to an embodiment of the present invention.
【図２】従来技術の説明図FIG. 2 is an explanatory diagram of a conventional technique.
１、１１・・・・・・半導体基板 ２、１２・・・・・・下地金属膜 ３、１３・・・・・・金属導電層 ４、１４・・・・・・電極下地部 ５、１５・・・・・・めっきマスク ６、１６・・・・・・半田バンプ ７、１７・・・・・・金属間化合物 ８・・・・・・ニッケル 1, 11 ... Semiconductor substrate 2, 12 ... ・ Base metal film 3, 13 ... Metal conductive layer 4, 14 ... Electrode base 5, 15 ... Plating mask 6, 16 ... Solder bump 7, 17 ...- Intermetallic compounds 8: Nickel
Claims (7)
金属エッチング時に発生する下地金属の副生成物を堆積
させた構造の半田バンプ。1. A solder bump having a structure in which a by-product of a base metal generated during base metal etching is deposited between the solder bump and the surface of the electrode base portion.
を特徴とする請求項１記載の半田バンプ。2. The solder bump according to claim 1, wherein the solder bump contains lead solder.
ることを特徴とする請求項１記載の半田バンプ。3. The solder bump according to claim 1, wherein the solder bump contains lead and tin solder.
ステン、ニッケル、アルミニウム、シリコンおよび銅か
らなる群から選択された金属を含有することを特徴とす
る請求項１記載の半田バンプ。4. The solder bump according to claim 1, wherein the base metal contains a metal selected from the group consisting of chromium, titanium, tungsten, nickel, aluminum, silicon and copper.
ン、タングステン、ニッケル、アルミニウム、シリコン
および銅からなる群から選択された金属を含有すること
を特徴とする請求項１記載の半田バンプ。5. The solder bump according to claim 1, wherein the by-product of the base metal contains a metal selected from the group consisting of chromium, titanium, tungsten, nickel, aluminum, silicon and copper.
式である事を特徴とする請求項１記載の半田バンプ。。6. The solder bump according to claim 1, wherein the etching is a wet etching method. .
である事を特徴とする請求項１記載の半田バンプ。7. The solder bump according to claim 1, wherein the etching is a dry etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001224582A JP4688362B2 (en) | 2001-07-25 | 2001-07-25 | Solder bump electrode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001224582A JP4688362B2 (en) | 2001-07-25 | 2001-07-25 | Solder bump electrode and manufacturing method thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003037128A true JP2003037128A (en) | 2003-02-07 |
| JP2003037128A5 JP2003037128A5 (en) | 2008-07-03 |
| JP4688362B2 JP4688362B2 (en) | 2011-05-25 |
Family
ID=19057715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001224582A Expired - Fee Related JP4688362B2 (en) | 2001-07-25 | 2001-07-25 | Solder bump electrode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4688362B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322437A (en) * | 1989-06-19 | 1991-01-30 | Nec Corp | Manufacture of semiconductor device |
| JP2000049181A (en) * | 1998-07-29 | 2000-02-18 | Mitsubishi Electric Corp | Semiconductor device and production thereof |
-
2001
- 2001-07-25 JP JP2001224582A patent/JP4688362B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322437A (en) * | 1989-06-19 | 1991-01-30 | Nec Corp | Manufacture of semiconductor device |
| JP2000049181A (en) * | 1998-07-29 | 2000-02-18 | Mitsubishi Electric Corp | Semiconductor device and production thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4688362B2 (en) | 2011-05-25 |
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