JP2003037126A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having fine pads at fine intervals, and a method for manufacturing the same. SOLUTION: The method for manufacturing the semiconductor device comprises a process for forming an opening 2 in the interlayer insulation film 1 on a semiconductor substrate, a process for forming a metal film 6 in the opening 2, a process for forming passivation layers 7, 8 on the metal film 6 and the interlayer insulation film 1, a process for exposing the upper surface of the metal film 6 by arranging an opening 9 in the passivation layers 7, 8, a process for forming a low melting point metal film 10 on the exposed upper surface of the metal film 6 and the upper surface of the passivation layers 7, 8, and a process for agglutinating the low melting point metal film 10 on the metal film 6 by heating at a higher temperature than the melting point of the low melting point metal film 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having bumps, and more particularly to a semiconductor device having bumps having a minute size and intervals and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the high integration of ULSI, the number of terminals connected to the outside has dramatically increased. For this reason, the pitch of pads used as connection terminals is becoming narrower. A conventional method for forming bumps on a pad will be described below.

After forming an interlayer insulating film on a semiconductor substrate and further forming necessary wiring, an opening is formed to connect to this wiring, and a pad connecting to the wiring through this opening is made of aluminum or the like. To form.

Next, a passivation layer is formed on the entire surface, and the passivation layer in the bump formation planned region on the pad is opened.

Next, a barrier metal is formed on the entire surface by sputtering. As a barrier metal layer, Pd is 0.05
μm, Ni 0.3 μm, and Ti 0.15 μm thick. This barrier metal prevents the reaction between the pad and the bump.

A resin layer of polyimide or the like is formed on the entire surface as a negative resist with a thickness of 50 μm. Only the pad is opened by a lithography process to provide a bump formation region.

Next, a metal to be a bump is formed on the pad by plating, filling by printing, or the like. Here, the bump metal is a stack of Ag and Sn.

Next, the resin layer which is the negative resist around the bumps is removed.

Next, the barrier metal is etched using the bumps as a mask.

Next, heating is performed at 260 ° C., and a bump shape is formed by reflow so that the periphery has a rounded shape.

The conventional pad size thus formed is, for example, about 70 μm square, and the distance between the pads is about 10.
The bump size is about 58 μm square, and the pad opening size is about 30 μm.

[0012]

The conventional semiconductor device as described above has the following problems.

With the progress of large-scale integration of semiconductor devices,
If the pitch between bumps is further reduced in the future, high precision will be required for lithography and etching, and there is a concern that the cost of the bump forming process will further increase.

Particularly when bumps are formed with a narrow pitch,
It is difficult to remove the polyimide resin, which is the resist material, in the bump formation region with a fine width. Also,
Since there are multiple lithography and etching processes,
The number of processes has increased.

An object of the present invention is to solve the above problems of the prior art.

In particular, it is an object of the present invention to provide a semiconductor device having pads formed with a fine size and intervals and a method for manufacturing the same.

[0017]

To achieve the above object, the present invention is characterized by a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and a wiring formed in the interlayer insulating film. A plurality of layers, a plurality of metal pads connected to the wiring layer and formed in the interlayer insulating film, and a plurality of metal pads formed in the interlayer insulating film, the surfaces other than the upper surface being covered with the interlayer insulating film. A dummy metal pad, the plurality of metal pads, the plurality of dummy metal pads, a passivation layer formed on the interlayer insulating film, and a portion of the plurality of metal pads in the passivation layer. A plurality of low-melting-point metal bumps that are embedded in the openings provided on the metal pads and are directly formed on the plurality of metal pads;
A plurality of dummy low-melting-point metal bumps which are buried in openings provided on a part of the plurality of dummy metal pads in the passivation layer and are directly formed on the plurality of dummy metal pads. The low melting metal bumps or the dummy low melting metal bumps are arranged adjacent to all the low melting metal bumps.

Another feature of the present invention is that a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a wiring layer formed in the interlayer insulating film, and a layer connected to the wiring layer, A plurality of metal pads formed in the insulating film, a plurality of barrier metals formed on the plurality of metal pads, and a surface other than the upper surface formed in the interlayer insulating film A plurality of dummy metal pads covered with a film, a plurality of dummy barrier metals respectively formed on the plurality of dummy metal pads, the plurality of barrier metals, the plurality of dummy barrier metals,
And a passivation layer formed on the interlayer insulating film and an opening formed on a portion of the plurality of barrier metals in the passivation layer, and directly formed on the plurality of barrier metals. A plurality of low-melting-point metal bumps, and a plurality of low-melting-point metal bumps embedded in an opening provided on a part of the plurality of dummy barrier metals in the passivation layer and directly formed on the plurality of dummy barrier metals. A semiconductor device having individual dummy low melting point metal bumps, and the low melting point metal bumps or the dummy low melting point metal bumps are arranged adjacent to all the low melting point metal bumps.

Another feature of the present invention is the step of forming an opening in an interlayer insulating film on a semiconductor substrate, the step of forming a metal film to be an electrode in the opening, the metal film and the interlayer. A step of forming a passivation layer on the insulating film,
A step of forming an opening in the passivation layer to expose the upper surface of the metal film; a step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer; Heating at a temperature equal to or higher than the melting point, and aggregating the low melting point metal film on the metal film.

Another feature of the present invention is the step of forming a metal film to be an electrode on the interlayer insulating film on the semiconductor substrate, the step of forming a passivation layer on the metal film and the interlayer insulating film, and A step of exposing an upper surface of the metal film by providing an opening in the passivation layer; a step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer; A method of manufacturing a semiconductor device, comprising: heating at a temperature equal to or higher than a melting point to aggregate the low melting point metal film on the metal film.

Another feature of the present invention is the step of forming a first opening in the interlayer insulating film on the semiconductor substrate to connect with the wiring groove, and the wiring groove in the interlayer insulating film on the semiconductor substrate. A step of forming a second opening insulated from the metal film, a step of forming a metal film in the wiring groove, the first opening and the second opening, and a passivation layer on the metal film and the interlayer insulating film. A step of forming an opening in the passivation layer to expose the upper surface of the metal film, and a step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation film. And a step of heating at a temperature equal to or higher than the melting point of the low melting point metal film to aggregate the low melting point metal film on the metal film.

Another feature of the present invention is the first feature on a semiconductor substrate.
A step of forming a wiring layer on the interlayer insulating film; a step of forming a second interlayer insulating film on the wiring layer and the first interlayer insulating film; and a step of forming a metal film connected to the wiring layer via a via, Forming on the second interlayer insulating film, forming a passivation layer on the metal film and the second interlayer insulating film, and forming an opening in the passivation layer to expose the upper surface of the metal film. A step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer, and heating at a temperature equal to or higher than the melting point of the low melting point metal film to form the low melting point metal film And a step of aggregating on a film.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. After a semiconductor element such as a transistor and a passive element such as a resistor are formed in a semiconductor substrate (not shown) on a silicon substrate by a normal silicon process, an interlayer insulating film 1 is formed and a wiring layer (not shown) is formed. Form.

Next, as shown in FIG. 2A, a pad forming groove 2 for external connection is formed in the interlayer insulating film 1. Here, the pad forming groove 2 is, for example, 40 μm.
It is formed so as to have a pad forming portion having a thickness of 5 μm on all sides.

Next, as shown in FIG. 2B, a TaN film 3 is formed as a barrier metal with a thickness of, for example, 50 nm on the entire surface. Here, the barrier metal is provided before the Cu layer is formed in order to prevent Cu from diffusing into the interlayer insulating film and to ensure the adhesion between the Cu layer and the interlayer insulating film. .

Next, as shown in FIG. 2C, a Cu seed layer 4 as a plating seed layer is formed on the entire surface by, for example, 200 nm.
After being formed to a thickness of nm by the sputtering method, FIG.
As shown in (D), the pad forming groove 2 is filled with a plated Cu layer by electrolytic plating.

Here, in order to suppress the resistance increase even when the Ag—Sn bump layer is diffused in Cu, the thickness of the Cu pad is set to be thicker, for example, 5 μm.

Next, as shown in FIG. 2E, the Cu seed layer 4, the plated Cu layer 5 and the TaN film 3 other than the wiring portion are removed by using a chemical mechanical polishing (CMP) method. ,
A Cu film 6 is formed in the pad forming groove 2.

Next, the silicon nitride film 7 is formed to a thickness of 100 n, for example.
m thickness, and the plasma silicon oxide film 8 is formed thereon.
Is formed with a thickness of, for example, 600 nm, and this laminated film is used as a passivation layer.

Next, as shown in FIG. 1 (A), a 20 μm square opening 9 is provided in the bump formation region on the pad in the passivation layer by a normal lithography process.

Next, as shown in FIG. 1B, an Ag--Sn alloy film 10 is formed on the entire surface of the wafer by a vapor deposition method, for example, 1
It is formed with a thickness of 5 nm.

Here, the alloy film may be formed by any one of a sputtering method, a printing method and a coating method instead of the vapor deposition method. The plating method cannot be used because the base on which the alloy film is formed is a non-metallic material.

Next, as shown in FIG. 1C, heat treatment is performed at 260 ° C. on a hot plate (not shown),
Ag-Sn alloy film 10 is aggregated on Cu film 6 to form spherical bump 11. Here, since the Cu film 6 is used as the pad, the wettability with the low-melting point metal is good, the low-melting point metal aggregates on the pad, and the passivation layer and the low-melting point metal are present in the region where Cu does not exist. The low wettability of the metal prevents the low melting point metal from aggregating.

In place of the Ag-Sn alloy, at least one of Pb, Sn, In, Ga, Sb and Ag which are low melting point metals can be selected and used. Where P
When b is used, the heat treatment temperature on the hot plate is changed from 260 ° C. to about 180 ° C. because its melting point is low.

Such bumps 11 are semiconductor chips 14
The state of being formed on the surface of is shown in FIG. As shown in FIG. 3, when the bumps 11 are densely formed with a uniform density over the entire surface of the semiconductor chip 14, the structure shown in FIG. 1C is applied to each bump.

In the method of manufacturing the semiconductor device of the present embodiment, the surface tension of the solder is used in the bump formation without using lithography. Therefore, the bump can be formed on the pad in a self-aligned manner.

In the method of manufacturing the semiconductor device of the present embodiment, since there is no lithography step, the sum of the pad size and the distance between the pads is about 40 μm regardless of the above size.
It can be formed with a fine size.

Also, several hundreds of Cu pads can be manufactured at low cost.
It is possible to form a large number of bumps, one or more.

According to the method of manufacturing a semiconductor device of the present embodiment, it is possible to form bumps with a fine size and a small number of steps.

Further, in the method of manufacturing the semiconductor device of the present embodiment, no barrier metal is used between the Cu film 6 and the Ag—Sn alloy film 10, and the bumps are directly formed on the pads by self-alignment. Therefore, it is possible to form bumps with a minute size and intervals with a very small number of steps.

If bumps are formed sparsely or sparsely on the semiconductor chip, it is necessary to form dummy bumps as shown in FIG.

That is, as shown in FIG. 4, the interlayer insulating film 1 is formed on the semiconductor substrate 15, and the wiring layer 16 is formed in the interlayer insulating film 1. A normal bump is formed with the structure shown in FIG.
It is connected to the wiring layer 16 by a via 17 under the N layer 3.

However, although the dummy bump 18 has the same structure as a normal bump, it is not connected to the wiring layer at all and is in an insulating state. The TaN layer 3 and the Cu film 6 formed under the dummy bumps 18 and Ag
The size of the -Sn layer 8 can be different from that of the structure under the normal bump. Here, the size is smaller than that of a normal bump.

This is because it is necessary to provide a positioning margin for the size of a normal bump in order to make a connection with the via. Therefore, the size of the Cu film under the normal bumps is limited, but since there is no connection with the via in the dummy pad,
The size of the Cu film under the dummy pad can be made relatively small.

As described above, in the semiconductor device of this embodiment, as shown in FIG. 4, the interlayer insulating film 1 is formed on the semiconductor substrate 15. A wiring layer 16 is formed in the interlayer insulating film 1. Further, the metal pad, which is the Cu film 6 formed in the interlayer insulating film 1, is connected to the wiring layer 16.

A plurality of dummy metal pads made of the Cu film 6 are formed in the interlayer insulating film 1, and the surfaces other than the upper surface are covered with the interlayer insulating film 1.

Further, passivation layers 7 and 8 are formed on the plurality of metal pads, the Cu film 6 which is a plurality of dummy metal pads, and the interlayer insulating film 1.

The passivation layers 7 and 8 are buried in the opening 2 provided on a part of the Cu film 6 which is a plurality of metal pads, and a plurality of metal pads are provided on the plurality of metal pads.
A plurality of low melting point metal bumps 11 are directly formed.

Further, a plurality of dummy bumps 18 made of a plurality of low melting point metals are buried in the openings 2 provided on a part of the plurality of metal pads 6 in the passivation layers 7 and 8, and a plurality of dummy bumps 18 are formed. It is directly formed on the Cu film 6 which is a metal pad.

The semiconductor device having such a structure can have pads formed with fine sizes and intervals.

As an example of the pad arrangement of such a semiconductor device, in the center pad type pad shape as a first example as shown in FIG. 5, a normal bump 11 (here, dummy bump 18 and Squares for identification) are arranged, surround them, and a plurality of dummy bumps 18 are uniformly formed on the other surface of the semiconductor chip 14 at a uniform density.

Further, as a second example as shown in FIG. 6, the normal bump 11 is provided only around the surface of the semiconductor chip.
In the case where the dummy bumps 18 are shown here (in order to be distinguished from the dummy bumps 18), the dummy bumps 18 are formed with a uniform density on the inner and outer regions of the surface of the semiconductor chip 14.

Further, as a third example as shown in FIG. 7, in the case where normal bumps 11 (here, shown as squares for distinguishing from dummy bumps 18) are formed with a sparse distribution. The dummy bumps 18 are formed between the outermost periphery and the normal bumps 11 so as to have a dense distribution.

Thus, by forming the dummy pad which is not electrically connected to the wiring layer in the portion where the normal bump density is low, it is possible to prevent the bump forming layer from remaining on the passivation layer. That is, when the area of the portion having a low pad density is large, the low melting point metal may remain aggregated even if the wettability is low. In that case, the low melting point metal alloy layer having a larger protrusion than the normal bump is passivated. May form on layers.

Therefore, in order to prevent such a situation, dummy bumps are formed in the non-bump region at intervals where aggregation does not occur on the passivation layer. In this way, bumps or dummy bumps are arranged adjacent to all the bumps. The dummy bump is formed on the dummy pad, and the dummy pad is not connected to another wiring layer by the via. It is desirable that the dummy bumps have the same size as a normal bump.

When the portion where the pad does not exist is large, a dummy pad that is not electrically connected but that coagulates and absorbs the low melting point metal alloy is provided, so that the low melting point metal alloy is on the insulating film between the pads. It is possible to avoid the occurrence of a short circuit during the joining due to the remaining.

(Modification of First Embodiment) A method of manufacturing a semiconductor device of this modification will be described with reference to FIGS. First, a semiconductor element such as a transistor and a passive element such as a resistor are formed in a semiconductor substrate (not shown) by a normal silicon process on a silicon substrate, then an interlayer insulating film 1 is formed, and a wiring layer (not shown) is formed. ) Is formed.

Next, as shown in FIG. 8A, an Al layer 12 is formed on the interlayer insulating film 1 by the sputtering method.

Next, as shown in FIG. 8B, the Al layer 12 is etched by a normal lithography process and the RIE method so as to have a predetermined metal pad shape to form an Al pad 13. .

Next, as shown in FIG. 8C, a passivation layer 19 made of a silicon nitride film or a plasma silicon oxide film is formed on the Al pad 13 and the interlayer insulating film 1.

Next, as shown in FIG. 8D, a 20 μm square opening 9 is formed in the bump formation region on the pad in the passivation layer 19 by a normal lithography process.
To provide.

Next, as shown in FIG. 9 (A), an Ag--Sn alloy film 10 is formed on the entire surface of the wafer by a vapor deposition method, for example, 1
It is formed with a thickness of 5 nm.

Here, the alloy film may be formed by any one of the sputtering method, the printing method and the coating method instead of the vapor deposition method. The plating method cannot be used because the base on which the alloy film is formed is a non-metallic material.

Next, as shown in FIG. 9B, heat treatment is performed on a hot plate (not shown) at 260.degree.
Ag-Sn alloy film 10 is aggregated on Al pad 13 to form spherical bump 11. In this way, the interlayer insulating film 1
The Al pad 13 is formed on the Al pad 13
A passivation film 19 is formed around and partly on the upper surface and on the interlayer insulating film 1. The opening 9 is provided on the Al pad 13 of the passivation film 19. A bump 11 is formed on the passivation film 19 around the opening 9 and the Al pad 13.
Thus, the Cu of the semiconductor device according to the first embodiment is
Instead of the film 6, an Al pad 13 is formed to form a semiconductor device.

Here, since the Al pad 13 is used, the wettability with the low melting point metal is good, the low melting point metal aggregates on the pad, and in the region where Al does not exist, the passivation layer and the low melting point metal are formed. Since the wettability with is poor, aggregation of the low melting point metal is prevented.

In place of the Ag-Sn alloy, at least one of Pb, Sn, In, Ga, Sb and Ag which are low melting point metals can be selected and used. Where P
When b is used, the heat treatment temperature on the hot plate is changed from 260 ° C. to about 180 ° C. because its melting point is low.

Further, the semiconductor device according to the present modification shown in FIG. 9B can be applied as the semiconductor device shown in FIGS. 3 to 7 as in the first embodiment.

Also in this modification, the same effect as that of the first embodiment can be obtained.

(Second Embodiment) In the method of manufacturing a semiconductor device according to the present embodiment, FIG. 1, FIG. 2, and FIG.
Will be explained. The steps from FIG. 2A to FIG. 2E are the same as the method of manufacturing the semiconductor device according to the second embodiment. Further, in the step of FIG. 1A, the same is true up to the step of forming the opening 9 in the bump formation planned region on the pad in the passivation layer by a normal lithography step. However, unlike the first embodiment, the depth of the wiring groove formed in the step of FIG. 2A is 3 μm.

Here, the depth of the wiring groove in which Cu is formed is made shallower than that in the first embodiment because the barrier metal is formed on the Cu layer in the present embodiment.
Since the reaction between the Cu layer and the low melting point metal does not occur, C of that amount
This is because it is not necessary to provide a margin for the u layer.

Next, as shown in FIG. 10A, a titanium film having a thickness of 50 nm, a nickel film having a thickness of 300 nm, and a palladium film having a thickness of 50 nm are formed on the entire surface.
A barrier metal 20 made of is formed.

Next, as shown in FIG. 10B, the barrier metal 20 composed of the laminated film is left only above the pad by a normal lithography process.

Next, an Ag—Sn alloy film is formed on the entire surface of the wafer by vapor deposition to have a film thickness of 15 nm, for example.

Next, as shown in FIG. 10 (C), heat treatment is performed on a hot plate at 260 ° C., and Ag—S is added.
The n alloy film is aggregated above the pad to form a spherical bump 21.

Here, as the barrier metal, Ta, N
b, W, Mo, V, Cr, Zr, Ru, Ag, Au, T
At least one selected from i, Ni, Pd, and their nitrides, oxides, and borides, or a laminate can be appropriately selected and used. Here, the barrier metal is provided on the Cu layer in order to prevent a phenomenon in which the resistance of the pad increases due to the formation of a metal having a high resistance due to the reaction between the low melting point metal and the Cu film.

According to the method of manufacturing the semiconductor device of the present embodiment, the same effect as that of the method of manufacturing the semiconductor device of the first embodiment can be obtained although the number of steps is increased by several steps.

Further, according to the semiconductor device of the present embodiment, the same effect as that of the semiconductor device according to the first embodiment can be obtained, and the barrier metal 20 and the Cu film 6 are provided.
Since it is formed between the bump 21 and the bump 21,
It is possible to provide a semiconductor device in which resistance between the u film 6 and the u film 6 is suppressed low.

As in the first embodiment, as shown in FIG. 4, a semiconductor device having dummy bumps and ordinary bumps can be formed. Further, a semiconductor device having a bump structure having the arrangement as shown in FIGS. 5 to 7 can be formed.

(Third Embodiment) The structure of the semiconductor device of the present embodiment will be described with reference to FIGS. 2, 11, and 12.

The steps shown in FIGS. 2A to 2E are the same as those in the first embodiment. However, the depth of the wiring groove 2 is 3 μm as in the second embodiment.

Next, as shown in FIG. 11A, C
After oxidizing the upper surface of the u film 6 with hydrogen peroxide solution, the oxide film is removed with hydrochloric acid to etch the Cu film 6 by a thickness of, for example, 400 nm (recess etching).

Next, as shown in FIG. 11B, a barrier metal 25 having a titanium film with a thickness of 50 nm, a nickel film with a thickness of 300 nm, and a palladium film with a thickness of 50 nm is formed on the entire surface. .

Next, as shown in FIG. 11C, C
The barrier metal 25 made of this laminated film is left only on the Cu film 6 which is a pad by the MP method.

Next, as shown in FIG. 11D, a silicon nitride film 26 is formed to a film thickness of 100 nm,
Next, a plasma silicon oxide film 27 is formed thereon, for example, 60
It is formed with a film thickness of 0 nm.

Next, as shown in FIG. 12A, the plasma silicon oxide film 27 and the silicon nitride film 26 are formed only on the Cu film 6 to be the pad by the ordinary lithography process.
Make an opening inside.

Next, as shown in FIG. 12B, an Ag—Sn alloy film 28 is formed on the entire surface of the wafer by vapor deposition to have a film thickness of 15 nm, for example.

Next, as shown in FIG. 12 (C), heat treatment is performed on a hot plate at 260 ° C., and Ag—S is added.
The n-alloy film 28 is aggregated above the Cu film 6, which is a pad, to form a spherical bump 29.

In the method of manufacturing the semiconductor device of the present embodiment, the same effect as that of the method of manufacturing the semiconductor device of the first embodiment can be obtained although the number of steps is increased by several steps.

In this embodiment, the barrier metal 2
By forming 5 between the Cu film 6 and the bump 29, it is possible to provide a semiconductor device in which the resistance between the bump 29 and the Cu film 6 is suppressed low.

As in the case of the first embodiment, as shown in FIG. 4, a semiconductor device having dummy bumps and ordinary bumps can be formed.

That is, in the semiconductor device of this embodiment, the interlayer insulating film 1 is formed on the semiconductor substrate 15 in the region where the normal bumps are formed, and the wiring layer is formed in the interlayer insulating film 1. 16 are formed. A plurality of metal pads made of the Cu film 6 are formed in the interlayer insulating film 1 so as to be connected to the wiring layer 16. A plurality of barrier metals 25 are formed on the plurality of metal pads, respectively.

In addition, in the semiconductor device of the present embodiment, in the region where the dummy bumps are formed, a plurality of metal pads made of the Cu film 6 whose surfaces other than the upper surface are covered with the interlayer insulating film 1 are inter-layered. It is formed in the insulating film 1. Further, a plurality of barrier metals 2 are formed on the plurality of metal pads.
5 are formed respectively.

Further, passivation layers 26 and 27 are formed on the plurality of barrier metals 25 and the interlayer insulating film 1.

An opening 9 is provided on a part of the plurality of barrier metals 25 in the passivation layers 26 and 27.

In the area where normal bumps are formed,
A plurality of low melting point metal bumps 29 are directly formed on the plurality of barrier metals 25 by being embedded in the openings 9.

In the area where the dummy bumps are formed,
A plurality of low melting point metal bumps 29 embedded in the opening 9 are used as dummy bumps to form a plurality of barrier metal 2
It is formed directly on the surface 5.

Further, a semiconductor device having a bump structure arranged as shown in FIGS. 5 to 7 can be formed.

As described above, according to the semiconductor device of the present embodiment, the same effects as those of the semiconductor device of the second embodiment can be obtained.

In addition to the above, each of the embodiments is not limited to the above.
It can be implemented in combination.

[0100]

As described above, the present invention can provide a semiconductor device having a pad formed with a fine size and a space and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1A is a cross-sectional view showing a step of a method of manufacturing a semiconductor device according to a first embodiment of the present invention,
FIG. 3B is a cross-sectional view showing one step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 3C is the semiconductor device according to the first embodiment of the present invention. FIG.

FIG. 2A is a sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention,
FIG. 3B is a sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 3C is the sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 3D is a cross-sectional view showing a step of the manufacturing method, FIG. 3D is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. FIG. 7 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the first embodiment.

FIG. 3 is a perspective view showing the structure of the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a sectional view showing the structure of a semiconductor device having a dummy bump according to the first embodiment of the present invention.

FIG. 5 is a perspective view showing a first example of the structure of a semiconductor device having dummy bumps according to the first embodiment of the present invention.

FIG. 6 is a perspective view showing a second example of the structure of a semiconductor device having a dummy bump according to the first embodiment of the present invention.

FIG. 7 is a perspective view showing a third example of the structure of a semiconductor device having a dummy bump according to the first embodiment of the present invention.

FIG. 8A is a sectional view showing a step of the method for manufacturing the semiconductor device according to the modification of the first embodiment of the present invention, and FIG. 8B is the first embodiment of the present invention. 13C is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the modification of the exemplary embodiment, and FIG. 13C illustrates a step of the method for manufacturing the semiconductor device according to the modified example of the first embodiment of the present invention. FIG.
FIG. 7D is a sectional view illustrating a step of the method for manufacturing the semiconductor device according to the modification of the first embodiment of the present invention.

FIG. 9A is a sectional view showing a step of the method for manufacturing the semiconductor device according to the modification of the first embodiment of the present invention, and FIG. 9B is the first embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a semiconductor device according to a modified example of the form.

FIG. 10A is a sectional view showing a step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention,
(B) is sectional drawing showing 1 process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention, (C) shows the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG.

FIG. 11A is a sectional view showing a step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention,
(B) is sectional drawing showing 1 process of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention, (C) shows the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 6D is a cross-sectional view illustrating one step of a manufacturing method, and FIG. 7D is a cross-sectional view illustrating one step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 12A is a sectional view showing a step of the method of manufacturing the semiconductor device according to the third embodiment of the present invention,
(B) is sectional drawing showing 1 process of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention, (C) shows the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG.

[Explanation of symbols]

1 Interlayer Insulation Film 2 Pad Forming Groove 3 TaN Film 4 Cu Seed Layer 5 Plating Cu Layer 6 Cu Film 7, 26 Silicon Nitride Film (Passivation Layer) 8, 27 Plasma Silicon Oxide Film (Passivation Layer) 9 Opening 10 Ag- Sn alloy film 11, 21, 29 Bump 12 Al layer 13 Al pad 14 Semiconductor chip 15 Semiconductor substrate 16 Wiring layer 17 Via 18 Dummy bump 19 Passivation layer 20, 25 Barrier metal

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/88 M 21/92 602P (72) Inventor Naofumi Kaneko 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Formula Company Toshiba Yokohama Factory F-term (reference) QQ19 QQ48 QQ73 QQ89 RR04 RR06 SS15 VV01 VV07 XX03 XX14 XX28 XX33 XX34

Claims (12)

[Claims] 1. A semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a wiring layer formed in the interlayer insulating film, and a wiring layer connected to the wiring layer and formed in the interlayer insulating film. A plurality of metal pads, a plurality of dummy metal pads formed in the interlayer insulating film, the surfaces other than the upper surface being covered with the interlayer insulating film, the plurality of metal pads, the plurality of dummy pads A metal pad, a passivation layer formed on the interlayer insulating film, and embedded in an opening provided on a part of the plurality of metal pads in the passivation layer, and on the plurality of metal pads. A plurality of low-melting-point metal bumps directly formed, and a plurality of dummy metal bumps embedded in openings provided on a part of the plurality of dummy metal pads in the passivation layer. A plurality of dummy low-melting-point metal bumps directly formed on the pad, and the low-melting-point metal bumps or the dummy low-melting-point metal bumps are arranged adjacent to all the low-melting-point metal bumps. A semiconductor device characterized by: 2. A semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a wiring layer formed in the interlayer insulating film, and a wiring layer connected to the wiring layer and formed in the interlayer insulating film. A plurality of metal pads, a plurality of barrier metals respectively formed on the plurality of metal pads, and a plurality of layers formed in the interlayer insulating film, the surfaces other than the upper surface being covered with the interlayer insulating film. A plurality of dummy metal pads, a plurality of dummy barrier metals respectively formed on the plurality of dummy metal pads, a plurality of barrier metal layers, a plurality of dummy barrier metal layers, and an interlayer insulating film. The formed passivation layer and an opening provided on a part of the plurality of barrier metals in the passivation layer are embedded in the opening, and the passivation layer is directly formed on the plurality of barrier metals. A plurality of low melting point metal bumps made, is embedded in an opening provided on said plurality of dummy barrier metal portion of the passivation layer,
A plurality of dummy low melting point metal bumps directly formed on the plurality of dummy barrier metal, and adjacent to all the low melting point metal bumps, the low melting point metal bumps or the dummy low melting point metal bumps A semiconductor device in which is arranged. 3. A step of forming an opening in an interlayer insulating film on a semiconductor substrate, a step of forming a metal film serving as an electrode in the opening, and a passivation layer on the metal film and the interlayer insulating film. A step of forming an opening in the passivation layer to expose the upper surface of the metal film, and a step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer. And a step of heating at a temperature equal to or higher than a melting point of the low melting point metal film to aggregate the low melting point metal film on the metal film. 4. A step of forming a metal film to be an electrode on an interlayer insulating film on a semiconductor substrate, a step of forming a passivation layer on the metal film and the interlayer insulating film, and an opening in the passivation layer. Providing a step of exposing the upper surface of the metal film, a step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer, and heating at a temperature equal to or higher than the melting point of the low melting point metal film. And a step of aggregating the low melting point metal film on the metal film. 5. A step of forming a first opening connected to a wiring groove in an interlayer insulating film on a semiconductor substrate, and a second opening insulated from the wiring groove in the interlayer insulating film on the semiconductor substrate. A step of forming a portion, a step of forming a metal film in the wiring groove, the first opening and the second opening, and a step of forming a passivation layer on the metal film and the interlayer insulating film, Forming an opening in the passivation layer to expose the upper surface of the metal film; forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer; Heating at a temperature equal to or higher than the melting point, and aggregating the low melting point metal film on the metal film. 6. A step of forming a wiring layer on a first interlayer insulating film on a semiconductor substrate, a step of forming a second interlayer insulating film on the wiring layer and the first interlayer insulating film, and the wiring layer. Forming a metal film on the second interlayer insulating film to be connected via a via, forming a passivation layer on the metal film and the second interlayer insulating film, and forming an opening in the passivation layer. Providing a step of exposing the upper surface of the metal film, a step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer, and heating at a temperature not lower than the melting point of the low melting point metal film. And a step of aggregating the low melting point metal film on the metal film. 7. The method of manufacturing a semiconductor device according to claim 3, wherein the metal film is Cu. 8. The low melting point metal is Pb, Sn, In, G
8. The method for manufacturing a semiconductor device according to claim 3, further comprising at least one selected from a, Bi, Sb, and Ag. 9. The method for manufacturing a semiconductor device according to claim 3, wherein the low-melting-point metal film is formed by any one of a sputtering method, an evaporation method, a printing method, and a coating method. . 10. A step of forming a barrier metal on the exposed upper surface of the metal film before the step of forming the low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer. 4. The method according to claim 3, wherein
9. A method of manufacturing a semiconductor device according to any one of items 1 to 9. 11. A step of recess etching the exposed upper surface of the metal film before the step of forming a low melting point metal film on the exposed upper surface of the metal film and the upper surface of the passivation layer, and this recess etching. 10. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming a barrier metal on the upper surface of the metal film. 12. The barrier metal is Ta, Nb, W, M
o, V, Cr, Zr, Ru, Ag, Au, Ti, Ni,
12. The method of manufacturing a semiconductor device according to claim 10, comprising at least one selected from Pd and its nitride, oxide, and boride, or a laminated layer.