JP2003030931A - Signal detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal detection circuit in which making a circuit large size caused by external connection capacity is suppressed and whole circuit scale can be reduced, when a circuit is turned into an IC. SOLUTION: When a circuit is made IC, a signal S10 in which high-frequency band components are extracted from a TE signal by a high-pass filter 10 is made a binary signal S11 by a hysteresis comparator 11 and a level-setting circuit 12 to can be dispersed with the capacity of the outside of an IC, after that, setting very long time constant is not required by performing reshaping of a waveform by a mono-multi 13, and connection of capacity from IC pins and the outside of an IC is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal obtained by superposing a plurality of types of signals having different waveforms.

[0002]

2. Description of the Related Art In recent years, the amount of information handled by computer systems has rapidly increased, and in response to the increase in the amount of information, one of the optical recording media has a relatively large capacity. DVD-RAM discs and the like, which are easy to handle, have been widely used by general users.

In such a DVD-RAM disc or the like, a TE signal containing not only data but also address information forming an ID is recorded as the recording information, and from this TE signal, the address portion is recorded. In order to detect the ID of a signal, a composite signal in which a plurality of types of signals having different waveforms due to differences in amplitude, frequency, phase, etc., such as a TE signal, are overlapped, A signal detection circuit that detects a signal is used.

The conventional signal detecting circuit as described above will be described below. FIG. 11 is a block diagram showing the configuration of a conventional signal detection circuit. In FIG. 11, 1 is a high-pass filter, 2 is a full-wave rectifier circuit (FWR) connected to the output of the high-pass filter 1, and 3 is a full-wave rectifier circuit 2.
Is connected to the output of the low-pass filter 4, reference numeral 4 is a comparator connected to the output of the low-pass filter 3,
Is a low-pass filter connected to the output of the low-pass filter 3, 6 is a capacitor connected to the low-pass filter 5, and 7 is an offset circuit connected to the output of the low-pass filter 5 and the input of the comparator 4.

In the conventional signal detection circuit, the input signal TE is input to the full-wave rectification circuit 2 through the high pass filter 1. The output signal of the full-wave rectifier circuit 2 is connected to the + input terminal of the comparator 4 and the input terminal of the low-pass filter 5 via the low-pass filter 3. Low pass filter 5
Is grounded via a capacitor 6 for determining its time constant. Further, the output of the low-pass filter 5 is connected to the-side input terminal of the comparator 4 via the offset circuit 7, and it corresponds to the level difference of the input signal from the comparator 4 to the + side and-side input terminals. You are getting the output signal.

The operation of the signal detection circuit configured as described above will be described below with reference to FIGS. 11 and 12. FIG. 12 is a signal waveform diagram of each part showing the operation timing in the above-mentioned conventional signal detection circuit.

First, the input signal TE is high-pass filter 1
Applied to the input of. The signal S1 from which the low-frequency components have been removed by the high-pass filter 1 is then fed to the full-wave rectifier circuit 2
Entered in.

The signal S2 that is full-wave rectified by the full-wave rectifier circuit 2 is then input to the low-pass filter 3. Here, the signal S3 of the low frequency component is extracted from the signal S2. This signal S3 is input to the low-pass filter 5 having a time constant set by the capacitor 6, and a signal S4 having a low frequency component is further extracted from the signal S3.

After that, the signal S5 obtained by adding an offset to the signal S4 by the offset circuit 7 and the output signal S3 from the low-pass filter 3 are compared by the comparator 4 so that the TE signal which is a composite signal of a plurality of signals,
High when the potential of the signal S3 is higher than that of the signal S5
A signal indicating, for example, an ID is detected as an output signal having a (level) as an arbitrary signal for the purpose of detection.

[0010]

However, in the conventional signal detecting circuit as described above, in order to obtain the signal S4 having a lower frequency component than the signal S3, it is necessary to make the time constant of the low-pass filter 5 sufficiently long. However, when configuring such a low-pass filter having a very long time constant, the value of the capacitor 6 must be sufficiently large.

Therefore, when the circuit is integrated into an IC, the capacitor 6 cannot be built in the IC and must be connected to the outside of the IC, and the external connection capacitance increases the size of the circuit and the overall circuit scale. It had a problem that it became large.

The present invention solves the above-mentioned conventional problems. Even when the circuit is integrated into an IC, it is possible to suppress an increase in the size of the circuit due to an external connection capacitance and reduce the overall circuit scale. A detection circuit is provided.

[0013]

In order to solve the above problems, the signal detection circuit of the present invention detects an arbitrary signal having a predetermined purpose of use from a composite signal in which a plurality of types of signals having different waveforms are superimposed. A high-pass filter to which the composite signal is input as a detection target signal for detecting the arbitrary signal; a hysteresis comparator in which an output terminal of the high-pass filter is connected to a first input terminal; A level setting circuit in which a second input terminal of the hysteresis comparator is connected to an output terminal; and a mono-multi circuit in which an output terminal of the hysteresis comparator is connected to an input terminal and which outputs a detection signal from the composite signal, By the setting circuit, as an input signal from the output terminal to the second input terminal of the hysteresis comparator A hysteresis level width that is a comparison value with the input signal to the first input terminal in the hysteresis comparator is output, and the hysteresis comparator outputs the first input from the output terminal based on the hysteresis level width. It is configured such that a continuous pulse signal is output corresponding to an input signal to the terminal, and the monomulti outputs a signal that is turned on for a predetermined period from the starting point of the continuous pulse signal as the detection signal. And

From the above, in the conventional case, due to the circuit configuration,
A desired circuit can be configured without using a low-pass filter having a very long time constant, which was necessary to obtain a signal having a sufficiently low frequency component.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A signal detecting circuit according to claim 1 of the present invention is a signal detecting circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which a plurality of types of signals having different waveforms are superposed. In, a high-pass filter to which the composite signal is input as a detection target signal for detecting the arbitrary signal, a hysteresis comparator in which an output terminal of the high-pass filter is connected to a first input terminal, and a hysteresis comparator A level setting circuit in which two input terminals are connected to the output terminal; and a monomulti circuit in which the output terminal of the hysteresis comparator is connected to the input terminal and outputs a detection signal from the composite signal. As an input signal from the output terminal to the second input terminal of the hysteresis comparator,
A hysteresis level width that is a comparison value with the input signal to the first input terminal in the hysteresis comparator is output, and the hysteresis comparator outputs the first input from the output terminal based on the hysteresis level width. A continuous pulse signal is output corresponding to an input signal to the terminal, and the monomulti outputs a signal that is turned on for a predetermined period from the starting point of the continuous pulse signal as the detection signal.

A signal detection circuit according to a second aspect of the present invention is a signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which plural kinds of signals having different waveforms are superposed, and the arbitrary signal is detected. A high-pass filter to which the composite signal is input as a detection target signal, a full-wave rectifier circuit in which an output terminal of the high-pass filter is connected to an input terminal, and an output terminal of the full-wave rectifier circuit has a first input A comparator connected to the terminal, a level setting circuit in which the second input terminal of the comparator is connected to the output terminal, and a mono output circuit that outputs the detection signal from the composite signal by connecting the output terminal of the comparator to the input terminal. And a multi, and by the level setting circuit, from its output terminal,
As a signal input to the second input terminal of the comparator, a level comparison value with the signal input to the first input terminal of the comparator is output, and the comparator outputs the level comparison value to the level comparison value. Based on this, a continuous pulse signal is output corresponding to the input signal to the first input terminal, and the monomulti outputs a signal that is turned on for a predetermined period from the starting point of the continuous pulse signal as the detection signal. Configure to output.

A signal detection circuit according to a third aspect of the present invention is a signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which plural kinds of signals having different waveforms are superposed, and the arbitrary signal is detected. A high-pass filter to which the composite signal is input as a signal to be detected, first and second envelope detection circuits having output terminals of the high-pass filter connected to respective input terminals, and the first and second Each output terminal of the envelope detector circuit of
A subtraction circuit connected to each of the two input terminals; a comparator whose output terminal is connected to the first input terminal to output a detection signal from the composite signal; and a second input terminal of the comparator. A level setting circuit connected to the output terminal, the level setting circuit,
From the output terminal, a level comparison value with the input signal to the first input terminal of the comparator is output as an input signal to the second input terminal of the comparator,
The comparator is configured to output, as the detection signal, a signal that is turned on for a period corresponding to the input signal to the first input terminal based on the level comparison value.

A signal detection circuit according to a fourth aspect of the present invention is a signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which plural kinds of signals having different waveforms are superposed, and the arbitrary signal is detected. A first comparator in which the composite signal is input to a + side input terminal as a detection target signal, and a first level setting circuit in which a − side input terminal of the first comparator is connected to an output terminal, A first edge detection circuit in which an output terminal of the first comparator is connected to an input terminal, and a second edge detection circuit in which the composite signal is input to a-side input terminal as a detection target signal for detecting the arbitrary signal A comparator; a second level setting circuit in which the + side input terminal of the second comparator is connected to the output terminal; and a second level setting circuit in which the output terminal of the second comparator is connected to the input terminal. And edge detection circuit, the first and second
And a time measuring circuit for outputting a detection signal from the composite signal, wherein each output terminal of the edge detection circuit is connected to each of two input terminals, and by the first level setting circuit, As the input signal to the-side input terminal of the first comparator, a first level comparison value with the input signal to the + side input terminal of the first comparator is output, and the first level comparison value is output by the first comparator. From the output terminal, based on the first level comparison value,
A continuous pulse signal is output corresponding to the input signal to the + side input terminal, and the second level setting circuit outputs the pulse signal as an input signal from the output terminal to the + side input terminal of the second comparator. , A second level comparison value with the input signal to the-side input terminal of the second comparator is output, and the second comparator outputs the second level comparison value from the output terminal based on the second level comparison value. , The above-
A continuous pulse signal is output corresponding to the input signal to the side input terminal, and the first and second edge detection circuits output the output signals from the output terminals to the corresponding first and second comparators, respectively. A pulse signal that is turned on for a predetermined period from the starting point of each continuous pulse signal is output, and the time measurement circuit outputs the detection signal as the detection signal.
It is configured to output a signal that is turned on for twice as long as the period between the rising edge of the pulse signal from the first edge detecting circuit and the rising edge of the pulse signal from the second edge detecting circuit.

A signal detection circuit according to a fifth aspect of the present invention is a signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which plural kinds of signals having different waveforms are superposed, and the arbitrary signal is detected. And a first comparator to which the composite signal is input as a signal to be detected which is input to the + side input terminal, and a first side which is provided to the-side input terminal of the first comparator.
Based on the continuous pulse signal output from the first comparator by the comparison between the composite signal and the first level comparison value, the first level setting circuit supplying the level comparison value of A first mono-multi for outputting a first on signal for turning on for a predetermined period; a second comparator for receiving the composite signal as a detection target signal for detecting the arbitrary signal at a-side input terminal; A second level setting circuit that supplies a second level comparison value to the + side input terminal of the second comparator, and the second comparator outputs the composite signal by comparing the composite signal with the second level comparison value. Based on the continuous pulse signal, a second mono-multi that outputs a second ON signal that is turned on for a predetermined period from the starting point thereof and the first and second ON signals are 2
An OR circuit which is supplied to each of the two input terminals and outputs their OR signals, and the first and second ON signals are supplied to each of the two input terminals, and their AN
An AND circuit for outputting a D signal and an O from the OR circuit
The R output signal is used as a clock input, the AND output signal from the AND circuit is used as a reset input, and a signal that becomes High and a signal that becomes Low during the period from the rise of the OR output signal to the rise of the AND output signal are output. And a charge pump that charges and discharges the capacitance by the High signal and the Low signal from the flip-flop circuit,
A terminal voltage of a capacitor that changes according to charge and discharge of the charge pump is supplied to a first input terminal and outputs a detection signal from the composite signal, and a second comparator of the third comparator. And a third level setting circuit for supplying a third level comparison value to the input terminal of the third comparator, and the third comparator sets the terminal voltage of the capacitor and the third level comparison value as the detection signal. A signal that turns on for a predetermined period is output by comparison.

According to these configurations, a desired circuit is configured without using a low-pass filter having a very long time constant, which has been conventionally required to obtain a signal having a sufficiently low frequency component due to its circuit configuration. It is possible.

A signal detection circuit according to an embodiment of the present invention will be specifically described below with reference to the drawings. (Embodiment 1) A signal detection circuit according to Embodiment 1 of the present invention will be described.

FIG. 1 is a block diagram showing the configuration of the signal detection circuit according to the first embodiment. In FIG. 1, 10 is a high-pass filter, which has the same configuration as the conventional example. 11
Is a hysteresis comparator whose input is connected to the output of the high-pass filter 10, 12 is a level setting circuit connected to the hysteresis width setting input terminal of the hysteresis comparator 11, and 13 is the hysteresis comparator 11
It is a mono-multi with the output of as input.

The operation of the signal detection circuit configured as described above will be described below. FIG. 2 is a signal waveform diagram of each part showing the operation timing in the signal detection circuit of the first embodiment.

First, the input signal TE consisting of a low frequency signal component and a high frequency signal component passes through the high-pass filter 10, so that the low frequency signal component of the input signal TE is removed and a high frequency component signal S10 is output. Thereafter, the signal S11 binarized by the hysteresis comparator 11 is output based on the hysteresis width W1 set by the level setting circuit 12 in response to the signal S10.

As the signal S11 binarized by the hysteresis comparator 11, a plurality of pulses which are continuous for a certain period corresponding to the signal S10 of the high frequency component are output.
By passing the signal S11 through the monomulti 13, a continuous pulse having the starting point of the signal S11 as a base point is output.

As described above, according to this embodiment, since the low-pass filter having a large time constant as in the conventional case is not used, the capacitor connected to the outside of the IC is not required, and the circuit can be downsized. Further, since the circuit configuration is simpler than that of the conventional circuit, it is possible to reduce the number of IC elements when integrated into an IC.

Since the mono-multi 13 having a long time constant is used, the fall of the output signal may be delayed as compared with the conventional circuit, but there is no practical problem. (Embodiment 2) A signal detection circuit according to Embodiment 2 of the present invention will be described.

FIG. 3 is a block diagram showing the configuration of the signal detection circuit according to the second embodiment. In FIG. 3, 10 is a high-pass filter, 12 is a level setting circuit, 20 is a full-wave rectifier circuit, and 21 is a comparator, which has the same configuration as the conventional example. Reference numeral 13 is a mono-multi, which is the same as that in the first embodiment.

The operation of the signal detection circuit of the present embodiment having the above-described structure will be described below. Figure 4
FIG. 7 is a signal waveform diagram of each part showing the operation timing in the signal detection circuit of the second embodiment.

First, the input signal TE is high-pass filter 1
By passing 0, the low-frequency signal component of the input signal TE is removed and the high-frequency component signal S20 is output. Next, the full-wave rectifier circuit 20 turns the signal S20 into a full-wave rectified signal S21. After that, the signal S21 becomes the signal S23 which is binarized by the comparator 21 based on the threshold value S22 set by the level setting circuit 12.

The signal S2 binarized by the comparator 21
As 3, a plurality of continuous pulses corresponding to the signal S21 are output for a certain period of time. Therefore, by passing the signal S23 through the monomulti 13, a single continuous pulse whose starting point is the start point of the signal S23 is output.

As described above, according to the present embodiment, since a low-pass filter having a large time constant as in the prior art is not used, a capacitor connected to the outside of the IC becomes unnecessary, and therefore the circuit configuration can be downsized. It is possible.

Further, in the first embodiment, a period in which the threshold voltage is not crossed may occur for a long time in a portion where the DC component of the input signal TE largely changes. Since it needs to be taken for a long time, the detection sensitivity may be lowered. However, in the second embodiment, since the time interval across the threshold voltage in the comparator 21 is short, the time constant of the monomulti 13 can be shortened. Therefore, the detection sensitivity can be improved as compared with the first embodiment.

Since the circuit structure is simpler than that of the conventional circuit, the number of IC elements can be reduced. (Embodiment 3) A signal detection circuit according to Embodiment 3 of the present invention will be described.

FIG. 5 is a block diagram showing the configuration of the signal detection circuit according to the third embodiment. In FIG. 5, 10 is a high-pass filter, 12 is a level setting circuit, and 21 is a comparator, which has the same configuration as the conventional example. Further, 30 is an upper envelope detection circuit that receives the output signal of the high-pass filter 10, 31 is a lower envelope detection circuit that receives the output signal of the high-pass filter 10, and 32 is an output signal of the upper envelope detection circuit 30 that is + side. It is a subtraction circuit in which the output signal of the lower envelope detection circuit is connected to the negative input of the input.

The operation of the signal detection circuit of the present embodiment having the above-described structure will be described below. Figure 6
FIG. 9 is a signal waveform diagram of each part showing the operation timing in the signal detection circuit of the third embodiment.

First, the input signal TE is high-pass filter 1
By passing 0, the low-frequency signal component of the input signal TE is removed and the signal S30 of the high-frequency component is output. Then, the signal passes by passing through the upper envelope detecting circuit 30 and the lower envelope detecting circuit 31, For S30,
Signals S31 and S32 in which the upper and lower envelopes are detected are output, respectively.

By subtracting between these signals S31 and S32 by the subtraction circuit 32, only the portion of the signal S30 where the high frequency signal component is present, the signal S33 having a higher voltage level than the others is obtained. The signal S33 is binarized by the comparator 12 based on the voltage S34 set by the level setting circuit 12 to obtain an output signal.

As described above, according to the present embodiment, since a low-pass filter having a large time constant as in the prior art is not used, a capacitor connected to the outside of the IC is unnecessary, and therefore the circuit can be downsized. To do.

Further, since the circuit configuration is simpler than that of the conventional circuit, it is possible to reduce the number of IC elements when integrated into an IC. (Embodiment 4) A signal detection circuit according to Embodiment 4 of the present invention will be described.

FIG. 7 is a block diagram showing the configuration of the signal detection circuit according to the fourth embodiment. In FIG. 7, reference numeral 12 is a level setting circuit, and 21 is a comparator, which has the same structure as the conventional example. Reference numeral 40 is an edge detection circuit that receives the output of the comparator 21, and 41 is a time measurement circuit that receives the output of the edge detection circuit 40.

The operation of the signal detecting circuit of the present embodiment having the above-described structure will be described below. Figure 8
FIG. 9 is a signal waveform diagram of each part showing the operation timing in the signal detection circuit of the fourth embodiment.

First, the input signal TE is supplied to the level setting circuit 1
On the basis of the voltages S40 and S41 set by 2, each comparator 21 binarizes (voltages S40, S4
1 is, for example, the same level, and each comparator 2
1 is input to input terminals having different polarities), and a plurality of pulse signals S42 and S43 are continuous for a certain period.

By inputting a plurality of pulse signals S42 and S43 to the corresponding edge detection circuits 40, the output level is kept constant for a certain period of time after the first rising edge of each of the signals S42 and S43 is detected. Hig
The signals S44 and S45 that result in h are obtained.

The time measuring circuit 41 uses the signals S44 and S45.
Of the time period from the rising edge on the rising edge to the rising edge on the other side,
It outputs a signal that keeps the high level.

As described above, according to the present embodiment, since the low-pass filter having a large time constant as in the prior art is not used, the capacitor connected to the outside of the IC is unnecessary, and therefore the circuit structure can be downsized. And (Fifth Embodiment) A signal detection circuit according to a fifth embodiment of the present invention will be described.

FIG. 9 is a block diagram showing the configuration of the signal detection circuit of the fifth embodiment. In FIG. 9, reference numeral 12 is a level setting circuit, 13 is a mono-multi, and 21 is a comparator, which has the same configuration as the conventional example. Further, 50 is an OR circuit that receives the output of each monomulti 13, 13 is an AND circuit that receives the output of each monomulti 13, and 52 is the V terminal of the D terminal.
DD is a flip-flop circuit having a clock terminal connected to the output of the OR circuit 50 and a reset terminal connected to the output of the AND circuit 51, 53 is a charge pump controlled by the output of the flip-flop 52, and 55 is a charge pump 53.
The reference numeral 56 is a limiter circuit for limiting the voltage of the built-in capacitor 55.

The operation of the signal detection circuit of this embodiment having the above configuration will be described below. Figure 1
Reference numeral 0 is a signal waveform diagram of each part showing the operation timing in the signal detection circuit of the fifth embodiment.

First, the input signal TE is supplied to the level setting circuit 1
A plurality of pulse signals S52 and S53 which are binarized by the voltages S50 and S51 set by 2 and are continuous for a certain period.
Becomes

Next, a plurality of pulse signals S52, S53
Are input to the corresponding monomulti 13, and are converted into continuous single pulse signals S54 and S55. Next, the OR circuit 50 causes the pulse signal S5
The signal S56 is obtained by ORing 4, S55. Signal S
54 and the signal S55 may change in pulse order, and an OR is taken to obtain the signal S56 in order to detect an edge at which either the signal S54 or the signal S55 first rises.

Further, the AND circuit 51 generates the signal S57 by ANDing the pulse signals S54 and S55. The rising edge of the signal S57 is set so that it rises in exactly half the time expected for the pulse output. In the case of FIG. 10, the falling edge of the signal S54 lags behind the rising edge of the signal S55 due to the time constant of the monomulti 13, so that A
The output signal S57 of the ND circuit 51 becomes High level only from the rising edge of the signal S55 to the falling edge of the signal S54.

Therefore, from the rising of the signal S56,
Charge pump 5 controlled by signals S58 and S59
3 starts charging the built-in capacity 55. The voltage S60 of the built-in capacitor 55 starts to rise from the voltage that has been limited by the limiter circuit 56.

After that, when the signal S57 becomes High level, the flip-flop 52 is reset and the charge pump 5 controlled by the signals S58 and S59.
3, the voltage of the built-in capacitor 55 decreases to the voltage set by the limit circuit 56. The signal S60 that changes in voltage in this manner and the voltage S set by the level setting circuit 12
Based on 61 and, the final output is obtained by binarization by the comparator 21.

The reason why the signal S56 is not the final output is that the output sensitivity on the falling side is lowered due to the time constant of the monomulti 13. As described above, according to the present embodiment, since the conventional low-pass filter having a large time constant is not used, the capacitance connected to the outside of the IC is not required, and therefore the circuit configuration can be downsized.

[0055]

As described above, according to the present invention, without using a low-pass filter having a very long time constant, which was conventionally required to obtain a signal having a sufficiently low frequency component due to its circuit configuration. The desired circuit can be configured.

Therefore, even when the circuit is integrated into an IC, it is possible to eliminate the need for a capacitor that is connected to the outside of the IC to form a low-pass filter having a very long time constant in the conventional structure, and such an external circuit is required. It is possible to suppress an increase in the size of the circuit due to the connection capacitance and reduce the size of the entire circuit.

Further, in particular, according to the invention described in claim 1, the circuit configuration can be simplified as compared with the conventional one.
In the case of C conversion, the number of elements can be reduced,
The overall circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal detection circuit according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part showing the operation timing in the first embodiment.

FIG. 3 is a block diagram showing a configuration of a signal detection circuit according to a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram of each part showing the operation timing in the second embodiment.

FIG. 5 is a block diagram showing a configuration of a signal detection circuit according to a third embodiment of the present invention.

FIG. 6 is a signal waveform diagram of each part showing the operation timing in the third embodiment.

FIG. 7 is a block diagram showing a configuration of a signal detection circuit according to a fourth embodiment of the present invention.

FIG. 8 is a signal waveform diagram of each part showing the operation timing in the fourth embodiment.

FIG. 9 is a block diagram showing a configuration of a signal detection circuit according to a fifth embodiment of the present invention.

FIG. 10 is a signal waveform diagram of each part showing the operation timing in the fifth embodiment.

FIG. 11 is a block diagram showing a configuration of a conventional signal detection circuit.

FIG. 12 is a signal waveform diagram of each part showing the operation timing in the conventional example.

[Explanation of symbols]

1 High-pass filter 2 full-wave rectifier circuit 3 Low-pass filter 4 comparator 5 Low pass filter 6 External capacity 7 Offset circuit 10 high pass filter 11 Hysteresis comparator 12 level setting circuit 13 Mono Multi 20 full-wave rectifier circuit 21 Comparator 30 Upper envelope detection circuit 31 Lower envelope detection circuit 32 subtraction circuit 40 Edge detection circuit 41 hour measuring circuit 50 OR circuit 51 AND circuit 52 flip-flop circuit 53 Charge pump 55 Built-in capacity 56 limit circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5D044 BC04 CC04 FG18                 5D090 AA01 EE17                 5J039 DA12 DB08 DB12 FF10 FF13                       KK09 KK10 KK22                 5K029 AA18 AA20 HH08 LL01 LL08

Claims (5)

[Claims] 1. A signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal obtained by superposing a plurality of types of signals having different waveforms, wherein the composite signal is detected as the signal to be detected. A high-pass filter to which a signal is input, a hysteresis comparator having an output terminal of the high-pass filter connected to a first input terminal, and a level setting circuit having a second input terminal of the hysteresis comparator connected to an output terminal, The output terminal of the hysteresis comparator is connected to the input terminal and outputs a detection signal from the composite signal, and the level setting circuit allows the output terminal from the output terminal to the second input terminal of the hysteresis comparator. As an input signal, an input signal to the first input terminal of the hysteresis comparator Output a hysteresis level width as a comparison value with the signal, and the hysteresis comparator continuously outputs pulse signals from its output terminal in correspondence with the input signal to the first input terminal based on the hysteresis level width. And a signal detecting circuit configured to output, as the detection signal, a signal which is turned on for a predetermined period from the starting point of the continuous pulse signal, by the monomulti. 2. A signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which a plurality of kinds of signals having different waveforms are superposed, the composite signal being a detection target signal from which the arbitrary signal is detected. A high-pass filter into which a signal is input, a full-wave rectifier circuit in which the output terminal of the high-pass filter is connected to an input terminal, and a comparator in which the output terminal of the full-wave rectifier circuit is connected to a first input terminal,
The level setting circuit has a second input terminal of the comparator connected to the output terminal, and a monomulti circuit having the output terminal of the comparator connected to the input terminal to output a detection signal from the composite signal. Depending on the circuit
From the output terminal, a level comparison value with the input signal to the first input terminal of the comparator is output as an input signal to the second input terminal of the comparator,
The comparator outputs a continuous pulse signal from its output terminal corresponding to the input signal to the first input terminal based on the level comparison value, and the monomulti outputs the detection signal as the detection signal. A signal detection circuit configured to output a signal which is turned on for a predetermined period from a starting point of a continuous pulse signal. 3. A signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal obtained by superposing a plurality of types of signals having different waveforms, wherein the composite signal is detected as the signal to be detected. A high-pass filter to which a signal is input, first and second envelope detection circuits in which output terminals of the high-pass filter are connected to respective input terminals, and output terminals of the first and second envelope detection circuits are respectively provided. A subtraction circuit connected to each of the two input terminals, a comparator whose output terminal is connected to the first input terminal and outputs a detection signal from the composite signal, and a second input terminal of the comparator And a level setting circuit connected to the output terminal, the level setting circuit allows the output terminal to output a second input terminal of the comparator. A level comparison value with the input signal to the first input terminal of the comparator is output as an input signal to the child, and the comparator outputs the level comparison value as the detection signal based on the level comparison value.
A signal detection circuit configured to output a signal that is turned on for a period corresponding to an input signal to the input terminal of. 4. A signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal obtained by superposing a plurality of types of signals having different waveforms, wherein the composite signal is used as a detection target signal from which the arbitrary signal is detected. A first comparator to which a signal is input to a + side input terminal; a first level setting circuit to which a − side input terminal of the first comparator is connected to an output terminal; and an output terminal of the first comparator A first edge detection circuit connected to an input terminal; a second comparator in which the composite signal is input to a-side input terminal as a detection target signal for detecting the arbitrary signal;
Second level setting circuit in which the + side input terminal of the comparator is connected to the output terminal, a second edge detection circuit in which the output terminal of the second comparator is connected to the input terminal, and the first and the second Each of the output terminals of the edge detection circuit of No. 2 is connected to each of the two input terminals, and outputs a detection signal from the composite signal. As an input signal to the-side input terminal of the first comparator,
A first level comparison value with the input signal to the + side input terminal in the first comparator is output, and the first comparator outputs from the output terminal based on the first level comparison value, A continuous pulse signal is output corresponding to the input signal to the + side input terminal, and the second level setting circuit outputs the pulse signal as an input signal from the output terminal to the + side input terminal of the second comparator. , A second level comparison value with the input signal to the-side input terminal of the second comparator is output, and the second comparator outputs the second level comparison value from the output terminal based on the second level comparison value. , A continuous pulse signal corresponding to the input signal to the-side input terminal is output, and the first and second pulse signals are output.
The edge detection circuit outputs a pulse signal which is turned on for a predetermined period from each output terminal starting from the starting point of each continuous pulse signal from the corresponding first and second comparators, and the time measuring circuit Due to
A signal configured to output, as the detection signal, a signal that is turned on for a period twice as long as the period between the rising edge of the pulse signal from the first edge detecting circuit and the rising edge of the pulse signal from the second edge detecting circuit. Detection circuit. 5. A signal detection circuit for detecting an arbitrary signal having a predetermined purpose of use from a composite signal in which a plurality of types of signals having different waveforms are superposed, the composite signal being a detection target signal from which the arbitrary signal is detected. From the first comparator, a first comparator to which a signal is input to the + side input terminal, a first level setting circuit for supplying a first level comparison value to the-side input terminal of the first comparator, and the first comparator A first mono-multi that outputs a first ON signal that is turned on for a predetermined period from its starting point as a starting point based on a continuous pulse signal output by comparing the composite signal with a first level comparison value; A second comparator to which the composite signal is input to a-side input terminal as a detection target signal for detecting a signal and a second level comparison value to a + side input terminal of the second comparator are provided. A second level setting circuit for supplying,
A second ON signal, which is turned on for a predetermined period from its starting point as a starting point, is output based on the continuous pulse signal output from the comparison of the composite signal and the second level comparison value from the second comparator. A mono-multi circuit, an OR circuit that supplies the first and second ON signals to two input terminals, respectively, and outputs an OR signal of the two input terminals;
And an AND circuit that supplies the second ON signal to each of the two input terminals and outputs an AND signal thereof,
An OR output signal from the OR circuit is used as a clock input,
A flip-flop circuit that receives the AND output signal from the AND circuit as a reset input and outputs a signal that is High and a signal that is Low during the period from the rising of the OR output signal to the rising of the AND output signal;
High signal and L from the flip-flop circuit
A charge pump that charges and discharges a capacitance by an ow signal, and a terminal voltage of the capacitance that changes according to the charge and discharge of the charge pump are supplied to a first input terminal and output a detection signal from the composite signal. And a third level setting circuit that supplies a third level comparison value to a second input terminal of the third comparator, and the third comparator is used as the detection signal. A signal detection circuit configured to output a signal which is turned on for a predetermined period by comparing the terminal voltage of the above with the third level comparison value.