JP2003030163A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multiprocessor system capable of being operated to a common memory with a plurality of kinds of clocks. SOLUTION: Pseudo memories 3a to 3n as second memories are provided between first memories 1a to 1n and processors 4a to 4n to operate with a first frequency between the first memories 1a to 1n and the pseudo memories 3a to 3n and to operate with a second frequency synchronizing with frequencies F1 to Fn characteristic to the processors between the processors 4a to 4n and the pseudo memories 3a to 3n. The multiprocessor system operates with different frequencies between the first memories 1 and the pseudo memories 3 and between the processors 4 and the pseudo memories 3. Thus, the performance of the system can be improved flexibly and inexpensively compared with a conventional system. Furthermore, the system can be operated at higher speed similar to the processors like a cache memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of processors mounted therein.

[0002]

2. Description of the Related Art Conventionally, especially in recent years, clock-up of processors has been remarkably advanced. Further, the multiprocessor system is configured to have a shared memory, for example. In this configuration, most are due to technology shrink, and in many cases they are logically completely compatible. In addition, the memory and the network between the processor and the memory are improving only moderately as compared with the clock-up of the processor. Therefore, communication with the same clock is becoming difficult. Generally, conventional multiprocessor systems all use the same clock, or the network uses a divided frequency and operates at a speed of 1 / n.

Prior invention example 1 similar in technical field to the present invention
As an example, there is a "high-speed asynchronous communication system for memory access" in Japanese Patent Laid-Open No. 5-334171. In the invention example 1 of the prior application, as described in [Effects of the Invention] in paragraph 0029, by improving the high-speed execution of the CPU unit and the number of requests issued to the network unit, the network use efficiency is improved. There is.

[0004]

However, in the above prior art, in both the multiprocessor system and the network, the processors are operating at the same clock, and when the clocked up processors are applied, the Replacement and network,
And memory replacement, or network only 1
There was a problem that it was necessary to further increase the speed difference from / n to 1 / 2n.

An object of the present invention is to provide a multiprocessor system capable of operating a common memory with a plurality of types of clocks.

[0006]

In order to achieve the above object, the multiprocessor system of the present invention provides a pseudo memory as a second memory between the first memory and the processor, It operates at a first frequency synchronized with the pseudo memory, operates at a second frequency synchronized with the processor-specific frequency between the processor and the pseudo memory, and operates between the first memory and the pseudo memory. It is characterized by a multiprocessor configuration that operates at different frequencies between the processor and the pseudo memory.

Further, the above pseudo memory has a first buffer for input / output data which operates at a synchronous frequency with the network, and a second buffer which operates at a synchronous frequency with the processor. A synchronization circuit that operates the second buffer in synchronization with a clock input from the processor; a block (B1 to Bm) that arbitrates a request from the network and a request from the processor;
An arbitration circuit that determines at which frequency the blocks (B1 to Bm) are operated may be further included.

Further, the blocks (B1 to Bm) are divided into a predetermined size, and each of the divided blocks is a buffer whose frequency can be controlled. Synchronous communication is performed between the processor and the second buffer. Communication between the buffer or the second buffer and the blocks (B1 to Bm) is performed asynchronously, and the pseudo memory is a buffer operating at the synchronized frequency M, a buffer operating at frequencies F1 to Fn,
It is preferable to be configured by being divided into three blocks of blocks (B1 to Bm) which can be switched and operated at two frequencies of the frequency M and the frequencies F1 to Fn.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of a multiprocessor system according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIGS. 1 and 2, there is shown one embodiment of the multiprocessor system of the present invention.

FIG. 1 shows a configuration example of a multiprocessor system of the present invention in the case of a shared memory. The multiprocessor system of this embodiment shown in FIG.
a to 1n, crossbar switch 2, pseudo memories 3a to 3
n, and processors 4a to 4n. The processors 4a to 4n have different drive frequencies F1.
It is assumed that the driving is performed by ~ Fn.

The data paths 10 of the memories 1a to 1n are connected to the pseudo memories 3a to 3n via the crossbar switch 2. In each of the processors 4a to 4n, the data line 12 is connected to the pseudo memory 3 in a ratio of 1: 1. Further, the crossbar switch 2 and the pseudo memories 3a to 3n are connected by a data line 11.

FIG. 2 shows a configuration example of the pseudo memory 3. The pseudo memory 3 applied to this embodiment includes buffers 20 and 21, a synchronization circuit 22, an arbitration circuit 23, and blocks (B1 to Bm) 26.

Requests from the network 24, requests 25 from the processor, clocks M to the blocks (B1 to Bm) 26, clocks F1 to Fn to the synchronizing circuit 22,
Input / output data to / from the buffer 20 (first buffer) and input / output data to / from the buffer 21 (second buffer) are connected.

In the above connection relationship, the buffer 20 is
It is a buffer that operates at a frequency synchronized with the network. The buffer 21 is a buffer that operates at a frequency synchronized with the processor 4. The synchronization circuit 22 operates the buffer 21 in synchronization with the clock input from the processor 4. The arbitration circuit 23 receives a request 24 from the network and a request 25 from the processor 4.
Are arbitrated, and it is determined which of the requests the block (B1 to Bm) 26 should be operated at.
The blocks (B1 to Bm) 26 are blocks separated by a certain specific size, and each block (B1 to Bm)
m) 26 is a frequency controllable buffer.

(Explanation of Operation) As in the prior art, the communication 10 between the memory 1 and the crossbar switch 2 and the communication 11 between the crossbar switch 2 and the pseudo memory 3 are performed at the synchronized frequency M. . However, the communication 12 between the pseudo memory 3 and the processor 4 is performed at the frequencies F1 to Fn unique to the respective processors 4a to 4n. It is necessary for the user to set the peculiar frequency first after checking the characteristics of the LSI.

In the pseudo memory 3, which is sandwiched between the signals of two operating frequencies, the buffer 20 operating at the synchronized frequency M and the buffer 2 operating at the frequencies F1 to Fn.
1, a block (B1 to Bm) 26 that can be switched and operated at two frequencies M and F1 to Fn.

The network and the buffer 20, or the processor 4 and the buffer 21, perform conventional synchronous communication, but communication between the buffer 20 and the block (B1 to Bm) 26 or between the buffer 21 and the block (B1 to Bm) 26. Is performed by asynchronous communication such as shake hand. Therefore, when performing communication, it is necessary to first send a request to the arbitration circuit 23 to secure its own route.

The same block in the blocks (B1 to Bm) 26 may be used regardless of the direction of communication. Therefore, the arbitration circuit 23 needs to determine which request has priority. When the communication with the block (B1 to Bm) 26 is permitted by the arbitration, the block in the block (B1 to Bm) 26 is
The clock is tuned depending on whether the communication partner is the buffer 20 or the buffer 21 to prevent data from being lost.

According to the above-described embodiment, the buffer pseudo memory 3 is provided between the network and the processor, and the conventional synchronous communication is performed from both the network and the processor 4. The pseudo memory 3 does not need to have a large capacity like an ordinary memory, but can be a memory suitable for the amount of data to be transferred through the network, and is therefore small in size. Therefore, it can be expected to achieve the same speed as a processor like a cache memory. In this pseudo memory 3, there are functionally three types of buffers.

The first of the above three types of buffers is a buffer which is seen from the memory 1 and which is synchronized with the network.
The second is a buffer that is seen by the processor 4 and is synchronized with the processor. The third is a buffer that operates in these two frequency bands, and controls the frequencies that operate in each area of the buffer depending on the direction of communication. For example, in the case of communication from the memory 1 to the processor 4, the frequency is controlled in synchronization with the memory 1. When the processor 4 communicates with the memory 1, the processor 4 controls a buffer in the pseudo memory 3 with a clock synchronized with the processor. In this control, the 1st and 3rd or the 2nd and 3rd communicate asynchronously by shaking hands etc., and when the communication line is secured, the clock is set so that the 3rd buffer can communicate. To control.

According to the above-described embodiment, the pseudo memory 3 is provided between the memory 1 and the processor 4, the memory 1 and the pseudo memory 3 operate synchronously as usual, and the processor 4 and the pseudo memory 3 have the processor. It operates at a frequency that is synchronized with its own frequency. This allows a multiprocessor configuration with processors of different frequencies.

The above-described embodiment is an example of a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

[0023]

As is apparent from the above description, the multiprocessor system of the present invention operates at the first frequency in which the first memory and the pseudo memory are synchronized, and the multiprocessor system operates between the processor and the pseudo memory. Operates at a second frequency synchronized with the processor-specific frequency, between the first memory and the pseudo memory, and between the processor and the pseudo memory,
It has a multi-processor configuration that operates at different frequencies.

Therefore, since processors operating at different clocks can be operated by multiprocessors, only a certain processor is replaced with a faster one, or network and memory are replaced.
The performance of the system can be improved more flexibly and cheaply than ever before. In addition, the LSI produced in the early days was A
It is difficult to realize a multiprocessor by aligning processors operating at a certain clock at the evaluation stage because of variations in C characteristics, but this can be solved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an embodiment of a multiprocessor system of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration example of a pseudo memory.

[Explanation of symbols]

1 memory 2 crossbar switch 3 pseudo memory 4 processors 20, 21 buffer 22 Synchronous circuit 23 Arbitration circuit 26 blocks (B1-Bm)

Claims (6)

[Claims] 1. A second memory between the first memory and the processor.
A pseudo memory as a memory of the first memory, the first memory and the pseudo memory operate at a synchronized first frequency, and the processor and the pseudo memory operate at a frequency unique to the processor. A multiprocessor system that operates at a second frequency, and has a multiprocessor configuration that operates at different frequencies between the first memory and the pseudo memory and between the processor and the pseudo memory. . 2. The pseudo memory is configured to have a first buffer for input / output data that operates at a synchronization frequency with a network and a second buffer that operates at a synchronization frequency with the processor. The multiprocessor system according to claim 1, wherein 3. A synchronization circuit that operates the second buffer in synchronization with a clock input from the processor, a block (B1 to Bm) that arbitrates a request from the network and a request from the processor, and the block. 3. The multiprocessor system according to claim 2, further comprising an arbitration circuit that determines which frequency (B1 to Bm) should be operated. 4. The multiprocessor system according to claim 3, wherein the blocks (B1 to Bm) are divided into a predetermined size, and each of the divided blocks is a buffer capable of frequency control. 5. The synchronous communication is performed between the processor and the second buffer, and the asynchronous communication is performed between the first buffer or the second buffer and the blocks (B1 to Bm). A multiprocessor system according to claim 3 or 4, characterized in that 6. The pseudo memory includes a buffer that operates at a synchronized frequency M, a buffer that operates at frequencies F1 to Fn, and a block (B1 to Bm) that can operate by switching between two frequencies of a frequency M and frequencies F1 to Fn. ) Is divided into three blocks and is configured.
6. The multiprocessor system according to any one of 1 to 5.