JP2001318901A - Duplex multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize various systems from a large system up to a small system having the same constitution in a duplex multiprocessor system and to realize a system for finding out the high operational capacity of a processor, a system for finding out the large capacity of a file device, a system for finding out a high speed line interface, etc., in a unit in accordance with a request. SOLUTION: The slots of the unit are shared with a processor and an I/O device by unifying the backboard terminal of a processor card having an exclusive bus for confounding a memory with an I/O device card and a line interface card on the basis of basic constitution for connecting a confounding bus between processors by a crossbar switch for realizing a system bus for connecting multiprocessors and sharing the confounding bus with the crossbar switch.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplex system for a multiprocessor system or a processor system having an input / output device connected to a file device or a line interface, and more particularly to an improved duplex system of a duplex processor card. About.

[0002]

2. Description of the Related Art Conventionally, such a duplex system having a multiprocessor configuration generally uses a system bus for the multiprocessor configuration or a connection between a processor and an input / output device such as a crossbar switch or an ATM-HUB. It is realized by a serial link, and the memory confounding bus of the duplicated processor is constituted by a dedicated bus connecting the processors. Due to the explosive growth of networks in recent years, systems that require the same configuration from small to large systems due to the explosive growth of the system, and systems that require a powerful computing capability of the processor, systems that require large capacity file devices, There are demands for systems having various configurations depending on the situation, such as a system that requires a high-speed interface. In addition, it is required that the system can be easily added or removed after the system is constructed.

FIG. 5 shows an example of a duplex multiprocessor according to the prior art. The figure shows that there are confounding buses 81 and 82 as dedicated buses for confounding the memory connecting the duplicated processors.

[0004]

However, in the technique shown in FIG. 5, a dedicated connection pattern is provided on the backboard because the confounding part for connecting the memories of the dual processor card uses a dedicated bus. This requires the mounting position of the processor card to be fixed.

Further, when a processor card is added and the dedicated slot for the processor card on the unit is already closed, it is necessary to add the unit. Similarly, when an input / output device card and a line interface card are added, and when the slot is closed and only the processor card dedicated slot is vacant, there is a problem that the unit needs to be added.

It is a primary object of the present invention to provide a dual multiprocessor system with a processor card, an I / O card and a line interface card having a unitary backboard terminal arrangement to provide flexibility in increasing or decreasing each card. It is in.

[0007]

According to the present invention, there is provided a dual multiprocessor system comprising: a plurality of processors having a dedicated bus as a memory confounding bus connecting the duplicate processors; a plurality of input / output devices; In a duplexed multiprocessor system including a crossbar switch for connecting and exchanging a processor and a plurality of input / output devices, a crossbar switch is connected to a confounding portion connecting the duplexed processors by a part of the crossbar switch. .

The crossbar switch of the confounding section for connecting the duplicated processors is constituted by the same crossbar switch as a crossbar switch functioning as a system bus for communication between processors in a multiprocessor configuration.

In addition, when increasing or decreasing the number of processor cards on which a processor is mounted, or when increasing or decreasing the number of input / output device cards on which an input / output device is mounted, the number of cards is increased or decreased without being aware of the physical arrangement of the cards. Is possible.

The processor card has a circuit for multiplexing memory confounding access and input / output device or interprocessor communication access in the card.

Further, a system bus and a crossbar switch for communication between the processors are constituted by an ATM-HUB or a serial link.

More specifically, the dual processor system according to the present invention is characterized in that a dedicated bus of a confounding part connecting between the redundant processors of a multiprocessor system is deleted and a crossbar switch is provided. Since this crossbar switch can be realized with the same function as the crossbar switch functioning as a system bus for communication between processors in a multiprocessor configuration, the crossbar switch connecting the system bus is shared with the confounding section between the duplex processors. Is realized by the crossbar switch. The feature is that the number of crossbar switches becomes one and the interface of the processor card can be unified with the interface of the input / output device card.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, there is shown a dual multiprocessor according to an embodiment of the present invention. Book 2
The redundant processor system has a crossbar switch 21 for realizing memory confounding of the dual processor. Processors 11, 12, 13, and 14 are connected to input / output devices 31, 32, 41, and 42 via crossbar switches, respectively. Some of the input / output devices 31 and 32 connect file systems 51 and 52, and some of the input / output devices 41 and 42 connect line interfaces. The input / output devices 31, 32, 41, and 42 are connected to the crossbar switch 21 via a serial link 62. The processors 11 and 12 implement a duplex configuration (active system), and the processors 13 and 14 implement a duplex configuration (standby system).

Referring to FIG. 2, the processor 1 of FIG.
1, 12, 13, and 14 are configured as follows.
That is, the processor includes a microprocessor 1, a memory controller 2, a memory 3, and a bus adapter 4.
And a multiplexing circuit 5.

The crossbar switch and the input / output device shown in the figure are well-known in the art, and are not directly related to the present invention.

Next, the operation of this embodiment will be described with reference to FIG. First, the processors 11, 12, 13,
The operation of No. 14 will be described. The dual processor is 2
In the multiplexed state, the memory write of the processors 11 and 13 is reflected in the memories of the processors 12 and 14 of the other systems, so that the memory write access from the microprocessor 1 is written to the memory 3 from the memory controller 2. At the same time, the serial link 61 via the multiplexer 5
Output to The double write access to the other memory output to the serial link 61 is input to the other processors 12 and 14 from the serial link 61 via the crossbar switch 21. The double write access input to the serial link 61 is written from the memory controller 2 to the memory 3. By this operation, the contents of the memories 3 in the own processors 11 and 13 and the memories 3 in the processors 12 and 14 are made the same.

The processors 11, 12, 13, 14
In the case of access to the input / output devices 31, 32, 41, and 42, the access from the microprocessor 1 is output to the serial link 61 via the bus adapter 4 and the multiplexer 5. The access to the input / output device output to the serial link 61 is input to the input / output devices 31, 32, 41, and 42 from the serial link 62 via the crossbar switch 21.

Next, as a second embodiment of the present invention,
Although its basic configuration is the same as that of the first embodiment, it is further devised that the system bus does not affect the traffic involving memory confounding. FIG. 3 shows the configuration of the second embodiment. In the figure, a crossbar switch 21 and a processor 15, which connect between duplicated processors,
A serial link 64 is provided for connecting 16, 17, and 18 to the crossbar switch 22.

Therefore, the double writing operation to the other system memory using the dual multiprocessor system is performed by the processor 1.
The double writing accesses 5 and 17 are output from the serial link 64 and input from the serial link 64 to the other processors 16 and 18 via the crossbar switch 22. As described above, in the second embodiment, the processor 1
An effect is obtained that the multiplexing circuit 5 of 1, 12, 13, and 14 can be omitted.

Next, FIG. 4 shows a configuration diagram of the third embodiment. According to the figure, the serial link 64 of the second embodiment is connected to the crossbar switch 21 to constitute the third embodiment. In this case, in the unit, the processor card uses slots of two widths of the input / output device, so that the terminal arrangement on the backboard can be unified between the processor card and the input / output device card and can be configured with one crossbar switch. .

[0022]

As described above, according to the present invention,
In a duplexed multiprocessor system, a backboard terminal of a processor card is used as an input / output device card based on a basic configuration in which a confounding bus between processors is connected with a crossbar switch and shared with a crossbar switch that realizes a system bus connecting the multiprocessors. By unifying with the above, there is an effect that a free slot can be realized regardless of the physical configuration of the unit.

Therefore, according to the present invention, a small system to a large system can be realized with the same configuration.
It can be realized in the unit according to the demands such as a system that requires a powerful computing capability of the processor, a system that requires a large capacity of file device, and a system that requires a high-speed line interface. effective.

Further, according to the present invention, there is an effect that expansion and reduction after the system is constructed can be performed in the unit.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a duplex multiprocessor system as a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a processor used in a duplex multiprocessor system of the present invention.

FIG. 3 is a diagram showing a configuration of a duplex multiprocessor system as a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a duplex multiprocessor system as a third embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a duplex multiprocessor system as a conventional embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Microprocessor 2 Memory controller 3 Main memory 4 Bus adapter 5 Multiplexing circuit 11, 12 Duplex processor (active system) 13, 14 Duplex processor (standby system) 15, 16, 17, 18 Implementation The multiplexing devices of the duplex processors 11, 12, 13, and 14 in Examples 2 and 3 are omitted and two types of serial links are output. 21 Crossbar switch for system bus (duplex configuration) 22 Crossbar for memory confounding Switch (duplex configuration) 31, 32, 41, 42 Input / output device 51, 52 File device 61 Communication between serial link processors connecting processor card and crossbar switch, communication with input / output device, and memory confounding communication 62 Serial link connecting I / O device and crossbar switch 63 Processor card and link Performs communication between serial link processors connecting between sub-switches and communication with input / output devices. 64 Performs serial link memory confounding communication connecting between a processor card and a memory cross-over switch. 71, 72, 73, 74 Conventional 2 Weighted processor 81, 82 Confounding bus

Claims (6)

[Claims] 1. A plurality of processors each having a dedicated bus as a memory confounding bus for connecting redundant processors, a plurality of input / output devices, and a crossbar for connecting and exchanging the plurality of processors and the plurality of input / output devices. A duplex multiprocessor system comprising a switch, wherein a part of the crossbar switch is connected to a confounding part connecting the duplex processors with each other. 2. The crossbar switch of the confounding unit connecting between the duplicated processors comprises the same crossbar switch as a crossbar switch functioning as a system bus for communication between processors in a multiprocessor configuration. The dual multiprocessor system described in the above. 3. When increasing or decreasing the number of processor cards on which the processor is mounted, and increasing or decreasing the number of I / O device cards on which the input / output device is mounted, the number of cards is increased or decreased without being aware of the physical arrangement of the cards. The duplex multiprocessor system according to claim 1 or 2. 4. The dual multiprocessor system according to claim 1, wherein said processor card has a circuit for multiplexing a memory confounding access and an input / output device or an interprocessor communication access in said processor card. . 5. The dual multiprocessor system according to claim 1, wherein the system bus for the communication between the processors comprises an ATM-HUB or a serial link. 6. The dual multiprocessor system according to claim 1, wherein said crossbar switch is constituted by an ATM-HUB or a serial link.