JP2003023012A - Heterojunction bipolar transistor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a heterojunction bipolar transistor wherein etching anomalies of InGaP during the processing of a heterojunction bipolar transistor having stable emitter resistance and the emitter thereof are prevented, and the controllability of the emitter resistance can be improved. SOLUTION: A collector layer (3), a base layer (4), a lower emitter layer (5), an etching stop layer (10) and an upper emitter layer (11) are successively stacked on a GaAs substrate (1). The upper emitter layer has a higher impurity concentration at least in the neighborhood of the heterojunction interface between the etching stop layer (10) and the upper emitter layer (11) for cancelling the interfacial electric charge generated at the heterojunction interface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor using a compound semiconductor and a manufacturing method thereof, and more particularly to a structure for improving controllability of emitter resistance and a manufacturing method thereof.

[0002]

2. Description of the Related Art Gallium arsenide and AlGaAs or I
The heterojunction bipolar transistor using the nGaP heterojunction is an important semiconductor element applied to a high frequency amplifier of a mobile phone and a high frequency signal processing circuit of optical communication.

In this heterojunction bipolar transistor, a transistor structure is collectively formed on the semiconductor substrate by epitaxial growth, and the electrode formation surface of each layer is exposed by mesa etching to manufacture the transistor.

11 to 15 are process sectional views showing a general manufacturing process of this type of npn-type heterojunction bipolar transistor.

First, as shown in FIG. 11, a high specific resistance G
On an aAs substrate 101, an n-type GaAs subcollector layer 102 serving as a subcollector having an impurity concentration of 4 × 10 ¹⁸ cm ⁻³ and a layer thickness of 500 nm, an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a layer thickness of 700 nm. N-type GaAs collector layer 103 serving as a collector having p, a p-type GaAs base layer 104 serving as a base having an impurity concentration of 4 × 10 ¹⁹ cm ⁻³ and a layer thickness of 60 nm, and 3 × 10 ¹⁷ cm ^{−3 serving} as an n-type. N to be an emitter having an impurity concentration and a layer thickness of 30 nm
An InGaP emitter layer 105, an n-type GaAs contact layer 106 to be a contact having an impurity concentration of 4 × 10 ¹⁸ cm ⁻³ and a layer thickness of 100 nm is sequentially formed by MOCVD.

Next, as shown in FIG. 12, a photoresist mask indicated by a broken line is formed on the portion of the n-type GaAs contact layer 106 on the emitter formation region, and the n-type GaAs contact layer 106 is etched. . At this time, if an aqueous tartaric acid solution added with hydrogen peroxide is used as an etching solution for the n-type GaAs contact layer 106, the etching is performed with the n-type InGaP emitter layer 10.
Stop on 5.

Next, as shown in FIG. 13, the n-type Ga is
On the n-type InGaP emitter layer 105 including the As contact layer 106, a photoresist mask shown by a broken line, which is larger than a predetermined emitter formation region by a predetermined amount, is formed,
The type InGaP emitter layer 105 is etched. At this time, if hydrochloric acid is used as an etchant for the n-type InGaP emitter layer 105, the etching is performed using the p-type Ga.
Stop on As base layer 104.

Next, as shown in FIG. 14, the n-type Ga is
A photoresist mask for forming a collector region shown by a broken line is formed in a predetermined region including the As contact layer 106 and the n-type InGaP emitter layer 105, and the p-type GaA is formed.
s base layer 104 and the n-type GaAs collector layer 10
3 is etched until the n-type GaAs subcollector layer 102 is exposed.

Next, as shown in FIG. 15, the n-type Ga is
A collector electrode 107 on the As subcollector layer 102, a base electrode 108 on the p-type GaAs base layer 104,
An npn-type heterojunction bipolar transistor is completed by forming the emitter electrodes 109 on the n-type GaAs contact layer 106, respectively.

In this heterojunction bipolar transistor, the emitter layer below the GaAs contact layer 106 is a partial emitter layer 105a, and the In layer is formed on the base layer 104 at the outer periphery of the partial emitter layer 105a.
The GaP emitter layer is left and the guard ring layer 10 is formed.
5b, the guard ring layer 105b plays the most important role in putting the heterojunction bipolar transistor into practical use. That is, the guard ring layer 1 having a band gap larger than that of the GaAs base layer 104.
If 05b is left on the surface of the base layer 104, surface recombination of minority carriers injected from the partial emitter layer 105a into the base layer 104 is reduced. Therefore, the guard ring layer 105b is an essential requirement for ensuring the current gain and the element life.

By the way, in such a manufacturing method, a problem often occurs in the step of forming the guard ring layer 105b.

That is, as shown in FIG. 12, the n-type Ga is
After etching the As contact layer 106 to expose the InGaP emitter layer 105, the InGaP emitter layer 105 is formed to have a large area with respect to the n-type GaAs contact layer 106 in the process of FIG.
The etching of the guard ring layer 1
05b is formed, the InGaP emitter layer 1
In the case of No. 05, as oxidation proceeds, etching becomes difficult. Therefore, in the step shown in FIG. 13, there is a problem that the etching of the InGaP emitter layer 105 becomes impossible.

In order to solve such a problem, the above-mentioned I
In order to prevent the oxidation of the nGaP emitter layer 105, the above I
A technique for forming an etching stop layer on the nGaP emitter layer 105 (hereinafter referred to as a known technique) has been proposed (for example, JP-A-7-254612 and JP-A-9-36).
132).

The manufacturing method disclosed in these known techniques will be described with reference to the process sectional views of FIGS.

As shown in FIG. 16, high specific resistance GaAs
An impurity concentration of 4 × 10 ¹⁸ cm ⁻³ and 50
N-type GaAs as a subcollector having a layer thickness of 0 nm
Sub-collector layer 202, n-type Ga serving as a collector having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a layer thickness of 700 nm
As collector layer 203, p-type GaAs serving as a base having an impurity concentration of 4 × 10 ¹⁹ cm ⁻³ and a layer thickness of 60 nm
The base layer 204 is an n-type I serving as a lower emitter having an n-type impurity concentration of 3 × 10 ¹⁷ cm ⁻³ and a layer thickness of 30 nm.
nGaP lower emitter layer 205, n-type GaAs etching stop layer 210 having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ and a layer thickness of 10 nm, upper emitter layer having an impurity concentration of ³ × 10 ¹⁷ cm ⁻³ and a layer thickness of 30 nm N-type In
An n-type GaAs contact layer 206 to be a contact having a GaP upper emitter layer 211, an impurity concentration of 4 × 10 ¹⁸ cm ⁻³ , and a layer thickness of 100 nm is sequentially formed by MOCVD.

Next, as shown in FIG. 17, a photoresist mask shown by a broken line is formed on the portion of the GaAs contact layer 206 on the area where the emitter is to be formed.
The type GaAs contact layer 206 is etched, and then the InGaP upper emitter layer 211 is etched with hydrochloric acid. The GaAs contact layer 206 and the In
Since the GaP upper emitter layer 211 is etched using the same photoresist mask, the etching failure of the InGaP upper emitter layer 211 due to the oxidation, which has been a conventional problem, does not occur.

Next, a photoresist mask shown by a broken line, which is larger than the emitter region by a predetermined amount, is formed on the GaAs etching stopper layer 210 including the GaAs contact layer 206, and the GaAs etching stopper layer 21 is formed.
0 and the InGaP lower emitter layer 205 are etched. Also at this time, the GaAs etching stop layer 210 and the InGa layer are formed using the same photoresist mask.
Since the P lower emitter layer 205 is etched, the etching defect of the InGaP lower emitter layer 205 due to the oxidation, which has been a conventional problem, does not occur. As a result, the emitter layer 300 is the InGaP upper emitter layer 21.
1. The GaAs etching stop layer portion 21 thereunder
0a and the InGaP lower emitter layer portion 20 therebelow
On the other hand, a guard ring layer 350 composed of the InGaP lower emitter layer portion 205b and the GaAs etching stop layer portion 210b is formed on the outer peripheral portion of the InGaP lower emitter layer portion 205a.

Next, as shown in FIG.
A photoresist mask for forming a collector region shown by a broken line is formed in a predetermined region including the contact layer 206 and the GaAs etching stop layer 210, and the GaAs base layer 204 and the GaAs collector layer 203 are formed into the G
Etch until the aAs subcollector layer 202 is exposed.

Next, as shown in FIG.
The collector electrode 207 on the sub-collector layer 202, the G
a base electrode 208 on the aAs base layer 204, the Ga
By forming an emitter electrode 209 on the As contact layer 206 respectively, an np having a guard ring layer is formed.
The n-type heterojunction bipolar transistor is completed.

According to such a method, the InGaP
A thin etch stop layer 210 on the lower emitter layer 205.
Is inserted, the guard ring layer 350 can be easily formed on the outer peripheral portion of the InGaP lower emitter layer portion 205a.

However, in the heterojunction bipolar transistor obtained by this manufacturing method, the InGaP upper emitter layer 211 constituting the emitter layer 300 is formed.
The thin GaAs etching stop layer portion 210a is interposed between the InGaP lower emitter layer portion 205a and the InGaP lower emitter layer portion 205a, which causes a problem that the emitter resistance greatly varies.

This variation in emitter resistance is caused by GaAs
This is because interface charges are generated at the hetero interface when InGaP is grown thereon. InGaP on GaAs
Form a natural superlattice of InP and GaP depending on the growth conditions, and the interface charge at the heterointerface between GaAs and InGaP is said to be related to this natural superlattice and depends extremely sensitively on the growth conditions. And InG on GaAs
It is considered that the fixed charge at the hetero interface where aP is formed is negatively charged, and a potential barrier that inhibits the flow of electrons is formed at the interface.

A wafer having the structure shown in FIG. 16 was requested to be manufactured by a plurality of epitaxial wafer manufacturing companies (hereinafter, simply referred to as an epi-wafer company), and the results obtained by measuring the emitter resistance of a heterojunction bipolar transistor prototyped using the wafers were measured. It shows in Table 1.

[0024]

[Table 1]

As is clear from Table 1, there is a problem in that the value of the emitter resistance varies greatly depending on the epi-wafer company, and the value varies greatly, regardless of the same structure.

[0026]

As is apparent from the above, in the conventional manufacturing method, the InGaP emitter layer portion 105a is once exposed after the etching process of the GaAs contact layer 106, so that oxidation proceeds. There is a problem that etching becomes impossible.

Further, in the known technique, a thin GaAs etching stop layer portion 210a is interposed between the InGaP upper emitter layer 211 and the InGaP lower emitter layer portion 205 forming the emitter layer, and the value of the emitter resistance is reduced. There was the problem of large variations.

Therefore, when a plurality of npn type heterojunction bipolar transistors are formed on the same semiconductor substrate in a parallel connection structure, there is a problem that current is concentrated in the transistor having the smallest emitter resistance and is destroyed.

It is an object of the present invention to provide a heterojunction bipolar transistor having a stable emitter resistance.

Another object of the present invention is to provide a method of manufacturing a heterojunction bipolar transistor capable of preventing etching abnormality of InGaP during processing of an emitter and improving controllability of emitter resistance. .

[0031]

To achieve the above object, in a heterojunction bipolar transistor according to the first invention (claim 1), a collector layer is formed on a GaAs substrate,
In a heterojunction bipolar transistor in which a base layer, a lower emitter layer, an etching stop layer, and an upper emitter layer are sequentially stacked, the upper emitter layer has a heterojunction at least near a heterojunction interface between the etching stop layer and the upper emitter layer. It is characterized by having a high impurity concentration that cancels the interface charge generated at the interface.

According to the present invention, the upper emitter layer has a high impurity concentration at least in the vicinity of the heterojunction interface between the etching stopper layer and the upper emitter layer so as to cancel the interface charge generated at the heterojunction interface. Has been formed. Therefore, the potential barrier at the hetero interface is thin and has a low height, which facilitates the flow of electrons. Therefore, the emitter resistance component at the heterojunction interface is extremely small to a negligible level, and the emitter resistance of the transistor is determined by the sheet resistance of the emitter layer.

A heterojunction bipolar transistor according to a second invention (claim 2) is formed by stacking on a GaAs substrate and has a first compound semiconductor layer serving as a first conductivity type collector layer, and the first compound. A second compound semiconductor layer laminated on the semiconductor layer and serving as a base layer of the second conductivity type, laminated on the second compound semiconductor layer, and formed in a smaller area than the second compound semiconductor layer. A third compound semiconductor layer serving as a lower emitter layer of the first conductivity type, and a first conductivity type laminated on the third compound semiconductor layer and formed in substantially the same area as the third compound semiconductor layer. A fourth compound semiconductor layer serving as an etching stop layer of
A fifth compound semiconductor layer, which is laminated on the compound semiconductor layer and has an area smaller than that of the fourth compound semiconductor layer, and serves as an upper emitter layer of the first conductivity type, and is laminated on the fifth compound semiconductor layer. And a collector electrode, a base electrode, and an emitter electrode electrically connected to the first, second, and sixth compound semiconductor layers, respectively. The fifth compound semiconductor layer is characterized by having a high impurity concentration at least in the vicinity of the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer so as to cancel the interface charge generated at the heterojunction interface. There is.

According to the present invention, the fifth compound semiconductor layer cancels the interface charge generated at the heterojunction interface at least in the vicinity of the heterojunction interface between the fourth compound semiconductor layer and the fifth semiconductor layer. It is formed with a high impurity concentration. Therefore, the potential barrier at the hetero interface is thin and has a low height, which facilitates the flow of electrons. Therefore, the emitter resistance component at the heterojunction interface is extremely small to a negligible level, and the emitter resistance of the transistor is determined by the sheet resistance of the emitter layer.

The hetero according to the first and second inventions
In a junction bipolar transistor, the upper emitter
Or the fifth compound semiconductor layer is 2 × 10¹⁸
cm ^-3It is preferable to form a high impurity concentration of about a certain level or higher.
Yes.

In the second invention, the first, second, fourth and sixth compound semiconductor layers are made of GaAs, and the third and fifth compound semiconductor layers are made of InGaP.
Alternatively, it is preferably composed of AlGaAs.

Furthermore, a heterojunction bipolar transistor according to a third invention (claim 5) is formed by stacking on a GaAs substrate, and a first compound semiconductor layer serving as a first conductivity type collector layer, and the first compound. A second compound semiconductor layer laminated on the semiconductor layer and serving as a base layer of the second conductivity type, laminated on the second compound semiconductor layer, and formed in a smaller area than the second compound semiconductor layer. A third compound semiconductor layer serving as a lower emitter layer of the first conductivity type, and a first conductivity type laminated on the third compound semiconductor layer and formed in substantially the same area as the third compound semiconductor layer. A fourth compound semiconductor layer serving as an etching stop layer of
A fifth compound semiconductor layer, which is laminated on the compound semiconductor layer and has an area smaller than that of the fourth compound semiconductor layer, and serves as an upper emitter layer of the first conductivity type, and is laminated on the fifth compound semiconductor layer. A first conductive type seventh compound semiconductor layer serving as a ballast resistor, a first conductive type eighth compound semiconductor layer laminated on the seventh compound semiconductor layer, and an eighth compound semiconductor layer on the eighth compound semiconductor layer. A sixth compound semiconductor layer, which is formed in a stack and serves as a contact layer, and the first, second and eighth layers
The compound semiconductor layer includes a collector electrode, a base electrode, and an emitter electrode, which are electrically connected to each other, and the fifth compound semiconductor layer includes at least the fourth compound semiconductor layer and the fifth compound semiconductor layer. In the vicinity of the heterojunction interface, and in the vicinity of the heterojunction interface of at least the sixth compound semiconductor layer, the eighth compound semiconductor layer and the eighth compound semiconductor layer, the eighth compound semiconductor layer cancels the interface charge generated at the heterojunction interface. It is characterized by having a high impurity concentration.

According to this invention, the fifth compound semiconductor layer is near the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer, and the eighth compound semiconductor layer is the sixth compound semiconductor layer. In the vicinity of the heterojunction interface between the compound semiconductor layer and the eighth compound semiconductor layer, a high impurity concentration is set so as to cancel the interface charge generated at the heterojunction interface. Therefore, the potential barrier at the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer is improved so as to facilitate the flow of electrons, so that the emitter resistance is determined by the sheet resistance of the emitter layer and varies. It has a very small and stable value. Further, the potential barrier at the heterojunction interface between the eighth compound semiconductor layer and the sixth compound semiconductor layer is improved, and the interfacial charge at this heterojunction interface has little effect on the emitter resistance, so that the emitter resistance is reduced. Is maintained at a stable value with very little variation.

In the heterojunction bipolar transistor according to the third aspect of the present invention, each of the fifth and eighth compound semiconductor layers preferably has a high impurity concentration of about 2 × 10 ¹⁸ cm ^-3 or more.

The first, second, fourth and sixth compound semiconductor layers are composed of GaAs, and the third, fifth, and
The seventh and eighth compound semiconductor layers are InGaP or
It is preferably composed of AlGaAs.

Furthermore, in the method for manufacturing a heterojunction bipolar transistor according to the fourth aspect of the present invention (claim 8), a collector layer, a base layer, a lower emitter layer, an etching stop layer and an upper emitter layer are sequentially formed on a GaAs substrate. When forming the stacked layers, the upper emitter layer is formed at least near the heterojunction interface between the etching stopper layer and the upper emitter layer so as to have a high impurity concentration that cancels the interface charge generated at the heterojunction interface. And patterning the upper emitter layer with the etching stopper layer as an etching stopper, and then, using the base layer as an etching stopper, the etching stopper layer and the lower emitter layer with respect to the upper emitter layer. Patterning to have a large area, and after Collector layer, said base layer and said upper emitter layer to the collector electrode, a base electrode and emitter electrode, respectively, is characterized by comprising the step of electrically connecting.

According to the present invention, the upper emitter layer has a high impurity concentration at least near the heterojunction interface between the etching stopper layer and the upper emitter layer so as to cancel the interface charge generated at the heterojunction interface. Doping. Therefore, the potential barrier at the hetero interface is thin and has a low height, which facilitates the flow of electrons. Therefore, the emitter resistance component at the heterojunction interface can be made extremely small to a negligible level, the emitter resistance of the transistor can be determined by the sheet resistance of the emitter layer, and the controllability of the emitter resistance becomes easy.

In addition, since the lower emitter layer is covered with the etching stopper layer, the etching stopper layer and the lower emitter layer are sequentially etched.
There is no etching defect of the lower emitter layer due to oxidation, and the emitter layer can be easily processed.

Furthermore, a method for manufacturing a heterojunction bipolar transistor according to the fifth invention (claim 9) is
A first conductive type collector layer on a GaAs substrate
Compound semiconductor layer, second compound semiconductor layer serving as second conductivity type base layer, third compound semiconductor layer serving as first conductivity type lower emitter layer, and fourth compound semiconductor layer serving as first conductivity type etch stop layer And a fifth compound semiconductor layer serving as an upper emitter layer of the first conductivity type are laminated on the fourth compound semiconductor layer, the fifth compound semiconductor layer is formed of the fourth compound semiconductor layer. Forming a high impurity concentration near the heterojunction interface between the semiconductor layer and the fifth compound semiconductor layer so as to cancel the interface charge generated at the heterojunction interface; and forming a high impurity concentration on the fifth compound semiconductor layer. A step of stacking a sixth compound semiconductor layer to be an emitter contact layer, and then using the same mask,
And, the step of sequentially patterning the sixth and fifth compound semiconductor layers using the fourth compound semiconductor layer as an etching stopper, and then using the same mask, and the second compound semiconductor layer as an etching stopper.
A step of sequentially patterning the fourth and third compound semiconductor layers so as to have a larger area than the fifth compound semiconductor layer, and thereafter, the first, second and sixth compound semiconductor layers And the step of electrically connecting the collector electrode, the base electrode and the emitter electrode, respectively.

According to the present invention, in the fifth compound semiconductor layer, near the heterojunction interface between the fourth compound semiconductor layer and the fifth semiconductor layer, the interface charge generated at the heterojunction interface is offset. By doping to a high impurity concentration, the potential barrier at the hetero interface is
Since the thickness is thin and the height is low, electrons can easily flow. Therefore, the emitter resistance component at the heterojunction interface can be made extremely small to a negligible level, the emitter resistance of the transistor can be determined by the sheet resistance of the emitter layer, and the controllability of the emitter resistance becomes easy.

The fifth compound semiconductor layer serving as an upper emitter layer is patterned together with the sixth compound semiconductor layer serving as a contact by using the same mask, and the third compound semiconductor layer serving as a lower emitter layer. Are patterned together with the fourth compound semiconductor layer, which is an etching stop layer, using the same mask. Therefore, the fifth and third compound semiconductor layers to be the emitter layer do not have etching defects due to oxidation and can be easily processed.

Further, in the method for manufacturing a heterojunction bipolar transistor according to the sixth aspect of the present invention (claim 10), the first compound semiconductor layer serving as the first conductivity type collector layer and the second conductivity type are formed on the GaAs substrate. The second base layer of the mold
A step of sequentially laminating a compound semiconductor layer, a third compound semiconductor layer that will be a lower emitter layer of the first conductivity type, and a fourth compound semiconductor layer that will be an etching stop layer of the first conductivity type, and then the fourth compound When a fifth compound semiconductor layer to be an upper emitter layer of the first conductivity type is stacked on the semiconductor layer,
The fifth compound semiconductor layer is formed to have a high impurity concentration near the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer so as to cancel the interface charge generated at the heterojunction interface. And then
A first ballast resistor is formed on the fifth compound semiconductor layer.
A step of stacking a conductive type seventh compound semiconductor layer, and a step of stacking a first conductive type eighth compound semiconductor layer on the seventh compound semiconductor layer. A step of forming a high impurity concentration in the vicinity of the heterojunction interface between the seventh compound semiconductor layer and the eighth compound semiconductor layer so as to cancel the interface charge generated at the heterojunction interface, and A step of stacking a sixth compound semiconductor layer to be an emitter contact layer on the eighth compound semiconductor layer, and thereafter, using the same mask and using the fourth compound semiconductor layer as an etching stopper, The step of sequentially patterning the eighth, seventh and fifth compound semiconductor layers, and then using the same mask and using the second compound semiconductor layer as an etching stopper, A step of sequentially patterning the fourth and third compound semiconductor layers so as to have a large area with respect to the fifth compound semiconductor layer, and then forming the first, second and sixth compound semiconductor layers. , Collector electrode,
And a step of electrically connecting the base electrode and the emitter electrode, respectively.

According to the present invention, the fifth compound semiconductor layer is near the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer, and the eighth compound semiconductor layer is the seventh compound semiconductor layer. In the vicinity of the heterojunction interface between the compound semiconductor layer and the eighth compound semiconductor layer, a high impurity concentration is set so as to cancel the interface charge generated at the heterojunction interface. Therefore, since the potential barrier at the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer is improved so that electrons can easily flow, the emitter resistance can be determined by the sheet resistance of the emitter layer. The controllability of resistance becomes easy. Further, the potential barrier at the heterojunction interface between the seventh compound semiconductor layer and the sixth compound semiconductor layer is improved, and the interfacial charge at the heterojunction interface has almost no effect on the emitter resistance. Controllability of.

Further, the eighth compound semiconductor layer and the fifth compound semiconductor layer to be the upper emitter layer are patterned together with the sixth and seventh compound semiconductor layers using the same mask to form a lower emitter layer and a lower emitter layer. The third compound semiconductor layer to be formed is patterned together with the fourth compound semiconductor layer, which is an etching stop layer, using the same mask. Therefore, the eighth compound semiconductor layer and the fifth and third compound semiconductor layers to be the emitter layer do not have etching defects due to oxidation and can be easily processed.

[0050]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, the first embodiment of the present invention
The heterojunction bipolar transistor according to the embodiment will be described using its manufacturing method. 1 to 5 are process cross-sectional views showing the manufacturing process.

First, as shown in FIG. 1, Ga having a high specific resistance is used.
4x10 on the As substrate 1¹⁸cm^-3Impurity concentration and 5
N-type GaA serving as a subcollector having a film thickness of 00 nm
s subcollector layer 2, 1 × 10¹⁶cm^-3Impurity concentration and
And n-type GaA serving as a collector having a thickness of 700 nm
s collector layer (first compound is semiconductor layer) 3, 4 × 10 ¹⁹
cm^-3Impurity concentration and p-type that becomes the base layer of 60 nm
GaAs base layer (second compound semiconductor layer) 4, 3 × 10
¹⁷cm^-3With an impurity concentration of 25 nm and a film thickness of 25 nm
N-type InGaP lower emitter layer (third emitter layer)
Compound semiconductor layer) 5, 3 × 10¹⁸cm^-3Impurity concentration and
N-type G which is an etching stop layer having a thickness of 7 nm and
aAs etching stop layer (fourth compound semiconductor layer) 10,
2 x 10 ¹⁸cm^-3Has an impurity concentration of 20 nm and a film thickness of 20 nm.
N-type InGaP upper emitter serving as an upper emitter layer
Layer (fifth compound semiconductor layer) 11, 4 × 10¹⁸cm^-3No
A contact layer having a pure substance concentration and a film thickness of 100 nm;
N-type GaAs contact layer (sixth compound semiconductor layer)
6 is sequentially laminated by the well-known MOCVD method.
It

In the present embodiment, the formation of the n-type GaAs etching stop layer 10 is conventionally performed at 1 × 1.
The film has a high impurity concentration of 0 ¹⁸ cm ⁻³ and a film thickness of 10 nm, whereas the film has a high impurity concentration of 3 × 10 ¹⁸ cm ⁻³ and a film thickness of 7 nm.

Further, in forming the n-type InGaP upper emitter layer 11, in the conventional case, a low impurity concentration of 3 × 10 ¹⁷ cm ⁻³ and a film thickness of 30 nm are formed, while 2 × is formed. High impurity concentration of 10 ¹⁸ cm ^-3 and 20n
The film thickness is m.

Next, as shown in FIG. 2, a photoresist mask 20 is formed on the portion of the GaAs contact layer 6 on the emitter formation region, and the GaAs contact layer 6 is etched. The GaAs contact layer 6
Etching is stopped on the InGaP upper emitter layer 11 by using a tartaric acid aqueous solution to which hydrogen peroxide is added as the etching solution.

Subsequently, the InGaP upper emitter layer 11 is etched with hydrochloric acid. By using hydrochloric acid as an etchant for the InGaP upper emitter layer 11, etching is stopped on the GaAs etching stop layer 10.

The GaAs contact layer 6 and the InG
Since the etching of the aP upper emitter layer 11 is performed using the same photoresist mask 20, the etching failure of the InGaP upper emitter layer 11 due to the oxidation, which has been a conventional problem, does not occur.

Next, as shown in FIG. 3, a photoresist mask 21 larger than the emitter region by a predetermined amount is formed,
The GaAs etch stop layer 10 and the InGaP lower emitter layer 5 are etched. The GaAs etching stop layer 10 is etched with a tartaric acid aqueous solution containing hydrogen peroxide, and the InGaP lower emitter layer 5 is etched with hydrochloric acid.

At this time as well, since the GaAs etching stop layer 10 and the InGaP lower emitter layer 5 are etched using the same photoresist mask 21, the InGaP lower emitter layer 5 due to oxidation, which has been a problem in the prior art. No etching failure occurs.

As a result, the emitter layer 30 is formed of InG.
It is formed of the aP upper emitter layer 11, the GaAs etching stop layer portion 10a thereunder and the InGaP lower emitter layer portion 5a therebelow, while the InGa
InGaP is formed on the outer peripheral portion of the P lower emitter layer portion 5a.
A guard ring layer 35 composed of the lower emitter layer portion 5b and the GaAs etching stop layer portion 10b is formed.

Next, as shown in FIG. 4, a photo for forming a collector region is formed in a predetermined region including the GaAs contact layer 6, the InGaP upper emitter layer 11, the GaAs etching stop layer 10 and the InGaP lower emitter layer 5. A resist mask 22 is formed, and the GaAs base layer 4 and the GaAs collector layer 3 are sequentially etched until the GaAs subcollector layer 2 is exposed.

Next, as shown in FIG. 5, a collector electrode 7 is formed on the GaAs subcollector layer 2, a base electrode 8 is formed on the GaAs base layer 4, and a GaAs contact layer 6 is formed.
By forming the emitter electrodes 9 on each, an npn type heterojunction bipolar transistor having a guard ring layer is completed.

Heterojunction bipolar according to the above embodiment
In the transistor, the InGaP lower emitter layer portion
The GaAs etch stop layer portion 10a on the minute 5a,
And contact with the GaAs etching stop layer portion 10a
Of the donor in the InGaP upper emitter layer 11
Doping concentration (impurity concentration) is 2 × 10 ¹⁸
cm^-3Higher concentration than above. Therefore, the hetero interface
Half of the positive fixed charge is sufficient to compensate for the negative fixed charge of
Clamped on the conductor, stopping the GaAs etching
Between the layer portion 10 and the InGaP upper emitter layer 11;
The potential barrier at the terror junction interface is thin and
The height becomes low and electrons easily flow.

Therefore, the emitter resistance at the heterojunction interface becomes an extremely small value that can be ignored, and the emitter resistance of the transistor is determined by the sheet resistance of the emitter layer. Therefore, even if the amount of fixed charges at the interface fluctuates due to the deviation of the growth conditions, the emitter resistance is hardly affected, and the emitter resistance is stable.

Further, in the above manufacturing method, the InGaP
The upper emitter layer 11 is patterned together with the GaAs contact 6 using the same mask 20, and the InGaP lower emitter layer 5 is patterned together with the GaAs etch stop layer 10 using the same mask 21. . Therefore, the InGap upper emitter layer 11 and the InGaP lower emitter layer 5 have no etching defects due to oxidation and can be easily processed.

Furthermore, the InGaP lower emitter layer 5 is formed.
The GaAs etch stop layer 10 and the I
When the nGaP upper emitter layer 11 is sequentially laminated, the GaAs etching stopper layer 10 and the In layer are formed.
By setting the impurity concentration of the donor in the GaP upper emitter layer 11 to be as high as 2 × 10 ¹⁸ cm ⁻³ or more, the GaAs etching stop layer 10 and the In
The potential barrier at the heterojunction interface with the GaP upper emitter layer 11 is improved to facilitate the flow of electrons. Therefore, the emitter resistance can be determined by the sheet resistance of the emitter layer, and the controllability of the emitter resistance becomes easy. For example,
Table 2 shows the results of measuring the emitter resistance of a heterojunction bipolar transistor prototyped using a plurality of epiwafer manufacturing companies for the wafer having the structure shown in FIG. 1.

[0067]

[Table 2]

As is clear from this table, there was almost no difference between the epi-wafer companies, and a transistor with a stable emitter resistance could be manufactured with good reproducibility. (Second Embodiment) Next, a heterojunction bipolar transistor and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. 6 to 10 are process sectional views showing the manufacturing method.

The difference between this embodiment and the first embodiment is that in the first embodiment, the n-type InGaP is used.
Upper emitter layer 11 and the n-type GaAs contact layer 6
And an InGaP layer 62 having a low impurity concentration and an InGaP layer 63 having a high impurity concentration are provided therebetween. N
The type InGaP layer 62 has a large emitter resistance and functions as a ballast resistor necessary for a power amplifier or the like, and the InGaP layer 63 has the InGaP layer 63 and the InG.
This is to prevent the interface resistance at the heterojunction interface with the aP layer 62 from affecting the emitter resistance.

That is, as shown in FIG. 6, a high specific resistance Ga
4x10 on As substrate 51¹⁸cm^-3Impurity concentration and 5
N-type GaAs subcollector layer 5 having a film thickness of 00 nm
2, 1 x 10¹⁶cm^-3Impurity concentration and 700nm film
N-type GaAs collector layer serving as a collector layer having a thickness
(First compound semiconductor layer) 53, 4 × 10¹⁹cm^-3Impure
P-type as a base layer having a material concentration and a film thickness of 60 nm
GaAs base layer (second compound semiconductor layer) 54, 3 × 1
0¹⁷cm^-3With an impurity concentration of 25 nm and a film thickness of 25 nm
N-type InGaP lower emitter layer (first
3 compound semiconductor layer) 55, 3 × 10¹⁸cm^-3Concentration of impurities
To be an etching stop layer having a thickness of 7 nm and a thickness of 7 nm.
Type GaAs etching stop layer 60 (fourth compound semiconductor
Layer), 2 × 10¹⁸cm^-3Impurity concentration and 20 nm film
N-type InGaP upper layer to be a thick upper emitter layer
Mitter layer (fifth compound semiconductor layer) 61, 5 × 10¹⁶cm
^-3Ballast having an impurity concentration of 100 nm and a film thickness of 100 nm
N-type InGaP ballast which becomes a resistance and a resistance layer (seventh compound)
Semiconductor layer) 62, 2 × 10¹⁸cm^-3Impurity concentration and 2
N-type InGaP layer (8th compound half
Conductor layer) 63, 4 × 10 ¹⁸cm^-3Impurity concentration and 10
N-type GaAs contact layer serving as a 0 nm contact layer
The (sixth compound semiconductor layer) 56 is formed by the well-known MOCVD method.
Thus, the layers are sequentially formed.

In this embodiment, similarly to the first embodiment, when the n-type GaAs etching stop layer 60 is formed, a film having a high impurity concentration of 3 × 10 ¹⁸ cm ⁻³ and a film thickness of 7 nm is used. The n-type InGaP upper emitter layer 61 is formed to have a high impurity concentration of 2 × 10 ¹⁸ cm ⁻³ and a film thickness of 20 nm.

Furthermore, when the n-type InGaP layer 63 is laminated on the n-type InGaP layer 62, 2 ×
It is formed with a high impurity concentration of 10 ¹⁸ cm ⁻³ and a film thickness of 20 nm.

Then, as shown in FIG. 7, a photoresist mask 70 is formed on the portion of the GaAs contact layer 56 on the area where the emitter is to be formed, and the GaAs contact layer 56 is etched. By using a tartaric acid aqueous solution containing hydrogen peroxide as an etchant for the GaAs contact layer 56,
Stop on the aP layer 63.

Subsequently, the InGaP layers 63, 62 and 61 are etched with hydrochloric acid. The InGaP layer 6
By using hydrochloric acid as an etching solution for 3, 62 and 61, the etching is stopped on the GaAs etching stop layer 60.

The GaAs contact layer 56 and the In
Since the etching of the GaP layers 63, 62 and 61 is performed using the same photoresist mask 70, the InGaP layers 63, 62 and 61 due to oxidation, which has been a problem in the related art, are used.
No etching failure occurs.

Next, as shown in FIG. 8, a photoresist mask 71 larger than the emitter region by a predetermined amount is formed,
The GaAs etch stop layer 60 and the InGaP lower emitter layer 55 are etched. The GaAs etch stop layer 60 is formed of a tartaric acid aqueous solution containing hydrogen peroxide, and the InGaP lower emitter layer 55 is formed.
Perform etching with hydrochloric acid, respectively.

At this time as well, the same photoresist mask 71 is used to etch the GaAs etching stop layer 60 and the InGaP lower emitter layer 55, so that the InGaP emitter layer 55 due to oxidation, which has been a problem in the past, is removed. No etching defects occur.

As a result, the emitter layer 400 is formed of In
The GaP upper emitter layer 61, the GaAs etching stop layer portion 60a therebelow and the InGaP lower emitter layer portion 55a therebelow are formed.
On the outer peripheral portion of the GaP lower emitter layer portion 55a, the In
The guard ring layer 4 composed of the GaP lower emitter layer portion 55b and the GaAs etching stop layer portion 60b.
50 is formed.

Next, as shown in FIG. 9, the GaAs contact layer 56 and the InGaP layers 63, 62 and 6 are formed.
1. The GaAs etch stop layer 60 and the InG
A photoresist mask 72 for forming a collector region is formed on a predetermined region including the aP lower emitter layer 55, and the Ga
The As base layer 54 and the GaAs collector layer 53 are sequentially exposed until the GaAs subcollector layer 52 is exposed.
Etching.

Next, as shown in FIG.
On the sub-collector layer 52, the collector electrode 57, the GaA
An npn type heterojunction bipolar transistor having a guard ring layer is completed by forming a base electrode 58 on the s base layer 54 and an emitter electrode 59 on the GaAs contact layer 56, respectively.

The heterojunction bipolar of the second embodiment
According to the transistor, the same as in the first embodiment described above.
The GaAs etch stop layer 60 and the In
Impurity concentration of donor in GaP upper emitter layer 61
Is 2 × 10¹⁸cm ^-3Higher impurity concentration
Therefore, the GaAs etching stop layer 60 and the
InGaP lower emitter layer 61 has a heterojunction interface po
The thermal barrier has been improved to facilitate the flow of electrons,
Mitter resistance is determined by the sheet resistance of the emitter layer,
It becomes the set value.

In addition, an InGaP layer 63 having a high impurity concentration of 2 × 10 ¹⁸ cm ⁻³ or more is inserted between the GaAs contact layer 56 and the InGaP layer 62, and the G
The interface charge at the heterojunction interface between the aAs contact layer 56 and the InGaP layer 63 does not affect the ballast resistance. That is, the ballast resistance is determined by the sheet resistance of the InGaP layer 62 as the ballast resistance, that is, the two parameters of the thickness and the concentration, and has a stable value.

Therefore, the emitter resistance is the same as InGaP.
Since it is determined by the sheet resistance of the upper emitter layer 61 and the InGaP layer 62 serving as the ballast resistor, it has a stable and stable value.

Further, in the above manufacturing method, the InGap
Layers 63 and 62 and the InGaP upper emitter layer 61
Are patterned together with the GaAs contact layer 56 using the same mask 70, and the InGaP lower emitter layer 55 is patterned using the same mask 71.
Patterned with the s etch stop layer 60. Therefore, the InGaP layer 62, the InGaP upper emitter layer 61, and the InGaP lower emitter layer 5 are
No. 5 has no etching failure due to oxidation and can be easily processed.

Furthermore, the InGaP lower emitter layer 5 is formed.
When the GaAs etching stopper layer 10 and the InGaP upper emitter layer 11 are sequentially stacked on the substrate 5, the GaAs etching stopper layer 10 and the I
By setting the impurity concentration of the donor in the nGaP upper emitter layer 11 to be as high as 2 × 10 ¹⁸ cm ⁻³ or more, the GaAs etching stop layer 10 and the In
The potential barrier at the heterojunction interface with the GaP upper emitter layer 11 is improved to facilitate the flow of electrons. Therefore, the emitter resistance can be determined by the sheet resistance of the emitter layer.

Further, on the InGaP layer 62, the In
The InGaP layer 6 is formed when the GaP layer 63 is laminated.
By setting the impurity concentration of the donor in ^{3 to} a high concentration of 2 × 10 ¹⁸ cm ⁻³ or more, the interface charge at the heterojunction interface between the GaAs contact layer 56 and the InGaP layer 63 is improved so as not to affect the ballast resistance. The ballast resistance can be determined by the sheet resistance of the InGaP ballast resistance layer 62.

Therefore, the emitter resistance is set to the InGaP
The sheet resistance of the upper emitter layer 61 and the InGaP ballast resistance layer 62 can be determined, and the controllability of the emitter resistance becomes easy. For example, Table 3 shows the results of measuring the emitter resistance of a heterojunction bipolar transistor, which was manufactured by requesting a plurality of epi-wafer manufacturing companies to manufacture the wafer having the structure shown in FIG.

[0088]

[Table 3]

As is clear from this table, there was almost no difference between the epi-wafer companies, and a transistor with stable emitter resistance could be manufactured with good reproducibility.

Table 4 below shows the InGaP layer 62.
Shows the case where the thickness of each is 130 nm.

[0091]

[Table 4]

As is clear from this table, there is almost no difference between epiwafer companies, and it is well understood that a transistor having a stable emitter resistance can be manufactured with good reproducibility.

Although the contact layer is made of n-type GaAs in the above-mentioned embodiments, an n-type InGaAs layer may be provided on the n-type GaAs in order to further reduce the contact resistance.

In each of the above embodiments, GaAs is used.
And InGaP were combined, but GaAs and AlGa
Of course, a combination of As may be used.

[0095]

As described above, in the heterojunction bipolar transistor of the present invention, the variation is extremely small,
Has a stable emitter resistance.

Further, according to the method for manufacturing a heterojunction bipolar transistor of the present invention, the workability of the emitter and the controllability of the emitter resistance are improved, and a transistor having a stable emitter resistance can be manufactured with good reproducibility.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 4 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing a manufacturing process of the heterojunction bipolar transistor according to the first embodiment of the present invention.

FIG. 6 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the second embodiment of the invention.

FIG. 7 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the second embodiment of the invention.

FIG. 8 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the second embodiment of the invention.

FIG. 9 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the second embodiment of the invention.

FIG. 10 is a process cross-sectional view showing a manufacturing process of a heterojunction bipolar transistor according to the second embodiment of the invention.

FIG. 11 is a process sectional view showing a manufacturing process of a conventional heterojunction bipolar transistor.

FIG. 12 is a process sectional view showing a manufacturing process of a conventional heterojunction bipolar transistor.

FIG. 13 is a process cross-sectional view showing a manufacturing process of a conventional heterojunction bipolar transistor.

FIG. 14 is a process cross-sectional view showing a manufacturing process of a conventional heterojunction bipolar transistor.

FIG. 15 is a process cross-sectional view showing a manufacturing process of a conventional heterojunction bipolar transistor.

FIG. 16 is a process sectional view showing a process of manufacturing another conventional heterojunction bipolar transistor.

FIG. 17 is a process sectional view showing a process of manufacturing another conventional heterojunction bipolar transistor.

FIG. 18 is a process cross-sectional view showing the process of manufacturing another conventional heterojunction bipolar transistor.

FIG. 19 is a process sectional view showing a process of manufacturing another conventional heterojunction bipolar transistor.

FIG. 20 is a process cross-sectional view showing a process of manufacturing another conventional heterojunction bipolar transistor.

[Explanation of symbols]

1, 51, 101, 201 ... GaAs substrate 2, 52, 102, 202 ... n-type GaAs subcollector layer 3, 53, 103, 203 ... n-type GaAs collector layer 4, 54, 104, 204 ... p-type GaAs base layer 5, 55, 105, 205 ... N-type InGaP lower emitter layers 5a, 5b, 55a, 55b, 205a, 205b ...
Type InGaP lower emitter layer portions 6, 56, 106, 206 ... N type GaAs contact layers 7, 57, 107, 207 ... Collector electrodes 8, 58, 108, 208 ... Base electrodes 9, 59, 109, 209 ... Emitter electrode 10 , 60, 210 ... N-type GaAs etching stop layers 10a, 10b, 60a, 60b, 210a, 210b
... n-type GaAs etching stop layer portions 11, 61, 211 ... n-type InGaP upper emitter layers 20, 21, 22, 70, 71 ... photoresist masks 30, 300, 400 ... emitter layers 35, 105b, 350, 450 ... guards Ring layer 62 ... n-type InGaP ballast resistance layer 63 ... n-type InGaP layer 105 ... n-type InGaP emitter layer 105a ... partial emitter layer

Claims (10)

[Claims] 1. A collector layer, a base layer, and a GaAs substrate,
In a heterojunction bipolar transistor in which a lower emitter layer, an etching stop layer, and an upper emitter layer are sequentially stacked, the upper emitter layer occurs at a heterojunction interface at least near the heterojunction interface between the etching stop layer and the upper emitter layer. A heterojunction bipolar transistor having a high impurity concentration that cancels the interfacial charge that occurs. 2. A first compound semiconductor layer, which is laminated on a GaAs substrate and serves as a first conductivity type collector layer, and a laminate, which is laminated on the first compound semiconductor layer and serves as a second conductivity type base layer. A second compound semiconductor layer, and a second compound semiconductor layer laminated on the second compound semiconductor layer,
A third compound semiconductor layer, which has a smaller area than the compound semiconductor layer and serves as a lower emitter layer of the first conductivity type; and a third compound semiconductor layer stacked on the third compound semiconductor layer.
A fourth compound semiconductor layer serving as an etching stop layer of the first conductivity type formed in substantially the same area as the compound semiconductor layer; and a fourth compound semiconductor layer laminated on the fourth compound semiconductor layer, and
A fifth compound semiconductor layer, which has a smaller area than the compound semiconductor layer and serves as an upper emitter layer of the first conductivity type; and a sixth compound semiconductor layer, which is laminated on the fifth compound semiconductor layer and serves as a contact layer, The first, second, and sixth compound semiconductor layers each include a collector electrode, a base electrode, and an emitter electrode electrically connected, and the fifth compound semiconductor layer includes at least the fourth compound semiconductor layer. In the vicinity of the heterojunction interface between the fifth compound semiconductor layer and
A heterojunction bipolar transistor having a high impurity concentration that cancels the interface charge generated at the heterojunction interface. 3. The heterojunction bipolar transistor according to claim 2, wherein the upper emitter layer or the fifth compound semiconductor layer has a high impurity concentration of about 2 × 10 ¹⁸ cm ⁻³ . 4. The first, second, fourth and sixth compound semiconductor layers are made of GaAs, and the third and fifth compound semiconductor layers are made of InGaP or AlGaAs. The heterojunction bipolar transistor according to claim 2 or 3. 5. A first compound semiconductor layer laminated on a GaAs substrate to serve as a first conductive type collector layer, and laminated on the first compound semiconductor layer to form a second conductive type base layer. A second compound semiconductor layer, and a second compound semiconductor layer laminated on the second compound semiconductor layer,
A third compound semiconductor layer, which has a smaller area than the compound semiconductor layer and serves as a lower emitter layer of the first conductivity type; and a third compound semiconductor layer stacked on the third compound semiconductor layer.
A fourth compound semiconductor layer serving as an etching stop layer of the first conductivity type formed in substantially the same area as the compound semiconductor layer; and a fourth compound semiconductor layer laminated on the fourth compound semiconductor layer, and
A fifth compound semiconductor layer, which is formed in an area smaller than that of the compound semiconductor layer and serves as a first conductivity type upper emitter layer, and a first conductivity type seventh layer, which is laminated on the fifth compound semiconductor layer and serves as a ballast resistor. A compound semiconductor layer, an eighth compound semiconductor layer of the first conductivity type laminated on the seventh compound semiconductor layer, and a sixth compound semiconductor layer laminated on the eighth compound semiconductor layer to serve as a contact layer. And a collector electrode, a base electrode, and an emitter electrode electrically connected to the first, second, and eighth compound semiconductor layers, respectively, and the fifth compound semiconductor layer includes at least the fourth compound semiconductor. Near the heterojunction interface between the layer and the fifth compound semiconductor layer, and the eighth compound semiconductor layer is at least the heterojunction boundary between the sixth compound semiconductor layer and the eighth compound semiconductor layer. In the vicinity of each heterojunction bipolar transistor, characterized by having a high impurity concentration so as to cancel the surface charges generated at the heterojunction interface. 6. The heterojunction bipolar transistor according to claim 5, wherein each of the fifth and eighth compound semiconductor layers has a high impurity concentration of about 2 × 10 ¹⁸ cm ⁻³ . 7. The first, second, fourth and sixth compound semiconductor layers are made of GaAs, and the third, fifth, seventh and eighth compound semiconductor layers are made of InGaP or AlGa.
The heterojunction bipolar transistor according to claim 5 or 6, wherein the heterojunction bipolar transistor is composed of As. 8. A collector layer, a base layer, and a GaAs substrate,
When the lower emitter layer, the etching stopper layer, and the upper emitter layer are sequentially laminated, the upper emitter layer has an interfacial charge generated at the heterojunction interface at least in the vicinity of the heterojunction interface between the etching stopper layer and the upper emitter layer. And a step of patterning the upper emitter layer by using the etching stopper layer as an etching stopper, and a step of patterning the upper emitter layer by using the base layer as an etching stopper. Patterning the lower emitter layer so as to have a larger area than the upper emitter layer; and thereafter, forming a collector electrode, a base electrode and an emitter electrode on the collector layer, the base layer and the upper emitter layer, And a step of electrically connecting Method of manufacturing a heterojunction bipolar transistor according to symptoms. 9. A GaAs substrate on which a first compound semiconductor layer serving as a first conductivity type collector layer, a second compound semiconductor layer serving as a second conductivity type base layer, and a first conductivity type lower emitter layer are formed. A step of sequentially stacking a third compound semiconductor layer and a fourth compound semiconductor layer to be an etching stop layer of the first conductivity type, and a fifth step of forming an upper emitter layer of the first conductivity type on the fourth compound semiconductor layer. When the compound semiconductor layers are laminated, the fifth compound semiconductor layer is formed in the vicinity of the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer,
A step of forming so as to have a high impurity concentration that cancels an interface charge generated at the heterojunction interface, and a sixth step of forming a contact layer on the fifth compound semiconductor layer.
A step of stacking compound semiconductor layers, a step of sequentially patterning the sixth and fifth compound semiconductor layers using the same mask and using the fourth compound semiconductor layer as an etching stopper, Using the same mask and using the second compound semiconductor layer as an etching stopper, the fourth and third
A step of sequentially patterning the compound semiconductor layer so as to have a large area with respect to the fifth compound semiconductor layer, and thereafter, the first, second and sixth compound semiconductor layers are formed,
Collector electrode, base electrode and emitter electrode,
And a step of electrically connecting the heterojunction bipolar transistor. 10. A GaAs substrate, which is a first compound semiconductor layer serving as a first conductivity type collector layer, a second compound semiconductor layer serving as a second conductivity type base layer, and a first conductivity type lower emitter layer. A step of sequentially stacking and forming a third compound semiconductor layer and a fourth compound semiconductor layer serving as an etching stop layer of the first conductivity type, and then forming an upper emitter layer of the first conductivity type on the fourth compound semiconductor layer. When the fifth compound semiconductor layer is formed, the fifth compound semiconductor layer causes an interface charge generated at the heterojunction interface in the vicinity of the heterojunction interface between the fourth compound semiconductor layer and the fifth compound semiconductor layer. A step of forming so as to have a high impurity concentration that cancels out, and a step of laminating and forming a seventh compound semiconductor layer of the first conductivity type, which becomes a ballast resistance, on the fifth compound semiconductor layer, To The serial seventh compound semiconductor layer, the first conductive type eighth
When the compound semiconductor layers are laminated, the eighth compound semiconductor layer cancels the interface charge generated at the heterojunction interface in the vicinity of the heterojunction interface between the seventh compound semiconductor layer and the eighth compound semiconductor layer. And a step of forming a sixth compound semiconductor layer to serve as a contact layer on the eighth compound semiconductor layer, and then using the same mask, and A step of sequentially patterning the sixth, eighth, seventh, and fifth compound semiconductor layers using the fourth compound semiconductor layer as an etching stopper; and, using the same mask, and then forming the second compound semiconductor layer. As the etching stopper, the fourth and the third
A step of sequentially patterning the compound semiconductor layer so as to have a large area with respect to the fifth compound semiconductor layer, and thereafter, the first, second and sixth compound semiconductor layers are formed,
Collector electrode, base electrode and emitter electrode,
And a step of electrically connecting the heterojunction bipolar transistor.