JP2003022970A - METHOD OF FORMING SEMICONDUCTOR SUBSTRATE, FIELD TRANSISTOR, AND SiGe LAYER, AND METHOD OF FORMING DISTORTED Si LAYER AND METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR UTILIZING THE FORMING METHOD - Google Patents
METHOD OF FORMING SEMICONDUCTOR SUBSTRATE, FIELD TRANSISTOR, AND SiGe LAYER, AND METHOD OF FORMING DISTORTED Si LAYER AND METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR UTILIZING THE FORMING METHODInfo
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高速ＭＯＳＦＥＴ
等に用いられる半導体基板と電界効果型トランジスタ並
びに歪みＳｉ層等を形成するために好適なＳｉＧｅ層の
形成方法及びこれを用いた歪みＳｉ層の形成方法と電界
効果型トランジスタの製造方法に関する。TECHNICAL FIELD The present invention relates to a high speed MOSFET.
The present invention relates to a semiconductor substrate and a field effect transistor used for the above, a method for forming a SiGe layer suitable for forming a strained Si layer and the like, a method for forming a strained Si layer using the same and a method for manufacturing a field effect transistor.
【０００２】[0002]
【従来の技術】近年、Ｓｉ（シリコン）ウェーハ上にＳ
ｉＧｅ（シリコン・ゲルマニウム）層を介してエピタキ
シャル成長した歪みＳｉ層をチャネル領域に用いた高速
のＭＯＳＦＥＴ、ＭＯＤＦＥＴ、ＨＥＭＴが提案されて
いる。この歪みＳｉ−ＦＥＴでは、Ｓｉに比べて格子定
数の大きいＳｉＧｅによりＳｉ層に引っ張り歪みが生
じ、そのためＳｉのバンド構造が変化して縮退が解けて
キャリア移動度が高まる。したがって、この歪みＳｉ層
をチャネル領域として用いることにより、通常の１．３
〜８倍程度の高速化したＦＥＴが可能になるものであ
る。また、プロセスとしてＣＺ法による通常のＳｉ基板
を基板として使用できるため、従来のＣＭＯＳ工程で高
速ＣＭＯＳを実現可能にするものである。2. Description of the Related Art Recently, S on a Si (silicon) wafer
A high-speed MOSFET, MODFET, and HEMT using a strained Si layer epitaxially grown via an iGe (silicon germanium) layer in a channel region have been proposed. In this strained Si-FET, tensile strain occurs in the Si layer due to SiGe having a lattice constant larger than that of Si, so that the band structure of Si is changed, degeneracy is released, and carrier mobility is increased. Therefore, by using this strained Si layer as a channel region,
Up to 8 times faster FET is possible. Moreover, since a normal Si substrate by the CZ method can be used as a substrate as a process, a high-speed CMOS can be realized by a conventional CMOS process.
【０００３】しかしながら、ＦＥＴのチャネル領域とし
て要望される上記歪みＳｉ層をエピタキシャル成長する
には、Ｓｉ基板上に良質なＳｉＧｅ層をエピタキシャル
成長する必要があるが、ＳｉとＳｉＧｅとの格子定数の
違いから、転位等により結晶性に問題があった。このた
めに、従来、以下のような種々の提案が行われていた。However, in order to epitaxially grow the strained Si layer required as the channel region of the FET, it is necessary to epitaxially grow a high-quality SiGe layer on the Si substrate. However, due to the difference in lattice constant between Si and SiGe, There was a problem in crystallinity due to dislocations and the like. To this end, various proposals have been made in the past.
【０００４】例えば、ＳｉＧｅのＧｅ組成比を一定の緩
い傾斜で変化させたバッファ層を用いる方法、Ｇｅ（ゲ
ルマニウム）組成比をステップ状（階段状）に変化させ
たバッファ層を用いる方法、Ｇｅ組成比を超格子状に変
化させたバッファ層を用いる方法及びＳｉのオフカット
ウェーハを用いてＧｅ組成比を一定の傾斜で変化させた
バッファ層を用いる方法等が提案されている（U.S.Pate
nt 5,442,205、U.S.Patent 5,221,413、PCT WO98/0085
7、特開平6-252046号公報等）。現状では、歪みＳｉ−
ＦＥＴ用のＳｉ基板は、例えば、Ｓｉ（００１）基板上
に、ＳｉＧｅのＧｅ組成比を０から高濃度まで連続的に
変化させたＳｉＧｅバッファ層を成膜することにより、
高速ＦＥＴが実現可能となっている。For example, a method using a buffer layer in which the Ge composition ratio of SiGe is changed with a certain gentle slope, a method using a buffer layer in which the Ge (germanium) composition ratio is changed stepwise (stepwise), a Ge composition A method using a buffer layer whose ratio has been changed to a superlattice shape, a method using a buffer layer whose Ge composition ratio has been changed at a constant gradient using an Si off-cut wafer, and the like have been proposed (USPate
nt 5,442,205, USPatent 5,221,413, PCT WO98 / 0085
7, JP-A-6-252046, etc.). At present, strain Si-
The Si substrate for the FET is formed, for example, by forming a SiGe buffer layer in which the Ge composition ratio of SiGe is continuously changed from 0 to a high concentration on a Si (001) substrate.
High-speed FET has become feasible.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の技術では、以下のような課題が残されている。すな
わち、上記従来の技術を用いて成膜されたＳｉＧｅの結
晶性は、貫通転位密度がデバイスとして要望されるレベ
ルには及ばない悪い状態であった。また、実際にデバイ
スを作製する際に不良原因となる表面ラフネスについて
も転位密度が低い状態で良好なものを得ることが困難で
あった。この表面ラフネスは、内部の転位のために生じ
た凹凸が表面にまで影響を及ぼしたものである。However, the above-mentioned conventional techniques have the following problems. That is, the crystallinity of SiGe formed using the above-mentioned conventional technique was in a bad state in which the threading dislocation density did not reach the level required for a device. Further, it was difficult to obtain a good surface roughness that causes a defect when actually manufacturing a device in a state where the dislocation density is low. This surface roughness is that the unevenness caused by internal dislocations even affects the surface.
【０００６】例えば、Ｇｅ組成比を傾斜させたバッファ
層を用いる場合では、貫通転位密度を比較的低くするこ
とができるが、表面ラフネスが悪化してしまう不都合が
あり、逆にＧｅ組成比を階段状にしたバッファ層を用い
る場合では、表面ラフネスを比較的少なくすることがで
きるが、貫通転位密度が多くなってしまう不都合があっ
た。また、オフカットウェーハを用いる場合では、転位
が成膜方向ではなく横に抜け易くなるが、まだ十分な低
転位化を図ることができていない。したがって、貫通転
位によるＦＥＴの動作不良を防ぐためには、貫通転位密
度を低減する必要がある。For example, when a buffer layer having a graded Ge composition ratio is used, the threading dislocation density can be made relatively low, but there is a disadvantage that the surface roughness is deteriorated. In the case of using the buffer layer formed into a shape, the surface roughness can be relatively reduced, but there is a disadvantage that the threading dislocation density increases. Further, when an off-cut wafer is used, dislocations are likely to escape laterally instead of in the film formation direction, but a sufficient reduction of dislocations has not been achieved yet. Therefore, in order to prevent malfunction of the FET due to threading dislocations, it is necessary to reduce the threading dislocation density.
【０００７】本発明は、前述の課題に鑑みてなされたも
ので、貫通転位密度が低くかつ表面ラフネスも小さい半
導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の
形成方法及びこれを用いた歪みＳｉ層の形成方法と電界
効果型トランジスタの製造方法を提供することを目的と
する。The present invention has been made in view of the above-mentioned problems, and a semiconductor substrate having a low threading dislocation density and a small surface roughness, a field effect transistor, a method for forming a SiGe layer, and a strained Si layer using the same. It is an object to provide a forming method and a method for manufacturing a field effect transistor.
【０００８】[0008]
【課題を解決するための手段】本発明は、前記課題を解
決するために以下の構成を採用した。すなわち、本発明
の半導体基板は、Ｓｉ基板上に、Ｇｅ組成比が表面に向
けて漸次増加するＳｉＧｅの傾斜組成層を複数層積層状
態としたＳｉＧｅバッファ層を備え、これらの傾斜組成
層各々は、隣接する２つの傾斜組成層のうち上側の傾斜
組成層の下面側のＧｅ組成比は、下側の傾斜組成層の上
面側のＧｅ組成比より小であることを特徴とする。The present invention has the following features to attain the object mentioned above. That is, the semiconductor substrate of the present invention is provided with a SiGe buffer layer in which a plurality of SiGe gradient composition layers in which the Ge composition ratio gradually increases toward the surface are laminated on the Si substrate, and each of these gradient composition layers is formed. Of the two adjacent gradient composition layers, the Ge composition ratio on the lower surface side of the upper gradient composition layer is smaller than the Ge composition ratio on the upper surface side of the lower gradient composition layer.
【０００９】また、本発明のＳｉＧｅ層の形成方法は、
Ｓｉ基板上に、Ｇｅ組成比が表面に向けて漸次増加する
ＳｉＧｅの傾斜組成層を複数層積層状態としたＳｉＧｅ
バッファ層を成膜する方法であって、積層方向に隣接す
る２つの傾斜組成層の上側の傾斜組成層の下面側のＧｅ
組成比が下側の傾斜組成層の上面側のＧｅ組成比より小
であるように、前記ＳｉＧｅの傾斜組成層をエピタキシ
ャル成長する工程を複数回繰り返し、各々のＳｉＧｅの
傾斜組成層を成膜することを特徴とする。The method of forming the SiGe layer of the present invention is
SiGe in which a plurality of SiGe graded composition layers in which the Ge composition ratio gradually increases toward the surface is laminated on the Si substrate
A method for forming a buffer layer, comprising Ge on the lower surface side of the gradient composition layer above the two gradient composition layers adjacent to each other in the stacking direction.
The step of epitaxially growing the gradient composition layer of SiGe is repeated a plurality of times so that the composition ratio is smaller than the Ge composition ratio on the upper surface side of the lower gradient composition layer, and each gradient composition layer of SiGe is formed. Is characterized by.
【００１０】本発明者らは、ＳｉＧｅの成膜技術につい
て研究を行ってきた結果、結晶中の転位が以下のような
傾向を有することがわかった。すなわち、ＳｉＧｅ層を
成膜する際に、成膜中に発生する転位は成膜方向に対し
て斜め方向又は横方向（成膜方向に直交する方向：＜１
１０＞方向）のいずれかに走り易い特性を持っている。
また、転位は層の界面で横方向に走り易いが、組成が急
峻に変化する界面では、上記斜め方向に走り易くなると
共に多くの転位が高密度に発生すると考えられる。As a result of research on the SiGe film forming technique, the present inventors have found that dislocations in crystals have the following tendencies. That is, when forming a SiGe layer, dislocations generated during the film formation are oblique or lateral to the film formation direction (direction orthogonal to the film formation direction: <1
10> direction).
Further, it is considered that dislocations tend to run laterally at the interface of the layers, but tend to run diagonally at the interface where the composition changes abruptly and many dislocations occur at high density.
【００１１】したがって、Ｇｅ組成比を単純な階段状に
して成膜すると、急峻な組成変化となる界面部分で多く
の転位が高密度に生じると共に、転位が成膜方向の斜め
方向に走り易く、貫通転位となるおそれが高いと考えら
れる。また、Ｇｅ組成比を単純に緩く傾斜させて成膜す
ると、上記斜め方向に走った転位が横方向に逃げるきっ
かけとなる部分（界面等）が無く、表面にまで貫通して
しまうと考えられる。Therefore, if the Ge composition ratio is formed in a simple stepwise manner, many dislocations are generated at a high density at the interface portion where the composition changes abruptly, and the dislocations easily run in the oblique direction of the film formation direction. It is considered that threading dislocations are likely to occur. Further, it is considered that when the film is formed with the Ge composition ratio being simply and gently inclined, there is no portion (interface, etc.) that triggers the dislocations running in the oblique direction to escape in the lateral direction, and penetrates to the surface.
【００１２】これらに対し、本発明のＳｉＧｅ層の形成
方法では、上側の傾斜組成層の下面側のＧｅ組成比が、
下側の傾斜組成層の上面側のＧｅ組成比より小となるよ
うに、Ｇｅ組成比が表面に向けて漸次増加するＳｉＧｅ
の傾斜組成層をエピタキシャル成長する工程を複数回繰
り返し、各ＳｉＧｅの傾斜組成層を成膜し、また、本発
明の半導体基板では、Ｇｅ組成比が表面に向けて漸次増
加するＳｉＧｅの傾斜組成層各々が、隣接する２つの傾
斜組成層のうち上側の傾斜組成層の下面側のＧｅ組成比
を下側の傾斜組成層の上面側のＧｅ組成比より小とした
ＳｉＧｅバッファ層を備えているので、積層された各傾
斜組成層の界面がＧｅ組成比が不連続な面となり、転位
密度が小さくかつ表面ラフネスが小さいＳｉＧｅ層を形
成することができる。On the other hand, in the method of forming the SiGe layer of the present invention, the Ge composition ratio on the lower surface side of the upper gradient composition layer is
SiGe in which the Ge composition ratio gradually increases toward the surface so as to be smaller than the Ge composition ratio on the upper surface side of the lower graded composition layer
The step of epitaxially growing the graded composition layer is repeated a plurality of times to form each graded composition layer of SiGe, and in the semiconductor substrate of the present invention, each of the graded composition layers of SiGe whose Ge composition ratio gradually increases toward the surface. However, since it has a SiGe buffer layer in which the Ge composition ratio on the lower surface side of the upper gradient composition layer of two adjacent gradient composition layers is smaller than the Ge composition ratio on the upper surface side of the lower gradient composition layer, The interface between the stacked gradient composition layers becomes a surface having a discontinuous Ge composition ratio, so that a SiGe layer having a low dislocation density and a low surface roughness can be formed.
【００１３】すなわち、界面において転位が横方向に走
り易くなり、貫通転位が生じ難くなる。また、界面での
組成変化が小さいので、界面での転位発生が抑制され、
傾斜組成層の層内で転位が均等に発生して、表面ラフネ
スの悪化を抑制することができる。That is, dislocations easily run laterally at the interface, and threading dislocations hardly occur. Further, since the composition change at the interface is small, the generation of dislocations at the interface is suppressed,
Dislocations are uniformly generated in the layer of the graded composition layer, and the deterioration of the surface roughness can be suppressed.
【００１４】さらに、本発明のＳｉＧｅの傾斜組成層で
は、主に傾斜組成層において転位同士の絡み合いが起こ
り、傾斜組成層中の転位密度が減少するとともに、転位
が横方向に誘導されることにより表面領域における貫通
転位密度が減少する。この現象は、上記傾斜組成層の傾
斜組成が緩やかな傾斜であるほど顕著に表れる。また、
傾斜組成層は、その厚みが厚いほど効果的である。すな
わち、傾斜組成が続いている間、転位密度は傾斜組成層
の膜厚が所定の膜厚以下では顕著な低下は見られない
が、傾斜組成層の膜厚が所定の膜厚を超えると、傾斜組
成領域の膜厚が増加するにしたがって徐々に低下する。Furthermore, in the graded composition layer of SiGe of the present invention, dislocations are entangled mainly in the graded composition layer, the dislocation density in the graded composition layer is reduced, and the dislocations are induced in the lateral direction. The threading dislocation density in the surface region is reduced. This phenomenon is more remarkable as the gradient composition of the gradient composition layer has a gentler gradient. Also,
The thicker the gradient composition layer is, the more effective it is. That is, while the graded composition continues, the dislocation density does not significantly decrease when the thickness of the graded composition layer is equal to or less than the predetermined thickness, but when the thickness of the graded composition layer exceeds the predetermined thickness, It gradually decreases as the film thickness of the graded composition region increases.
【００１５】一方、表面領域のＧｅ組成比が高くなる
と、転位の発生が促進され、最終的な表面領域における
貫通転位密度が高くなってしまう。そこで、上記の傾斜
組成層においては、上側の層の界面近傍のＧｅ組成比を
下側の層の界面近傍のＧｅ組成比より小さくするステッ
プを導入することにより、表面領域における貫通転位密
度を低く抑えることができる。この構造によれば、表面
のＧｅ組成比が同一の構造を作製する場合に、傾斜組成
領域の合計膜厚がより厚い構造を容易に作製することが
できる。その結果、傾斜組成層中の転位密度をより効果
的に減少させることができ、表面領域における貫通転位
密度をより効果的に低減させることができる。On the other hand, when the Ge composition ratio in the surface region becomes high, the generation of dislocations is promoted, and the threading dislocation density in the final surface region becomes high. Therefore, in the above graded composition layer, by introducing a step of making the Ge composition ratio near the interface of the upper layer smaller than the Ge composition ratio near the interface of the lower layer, the threading dislocation density in the surface region is lowered. Can be suppressed. According to this structure, when a structure having the same Ge composition ratio on the surface is manufactured, a structure having a larger total film thickness in the gradient composition region can be easily manufactured. As a result, the dislocation density in the graded composition layer can be reduced more effectively, and the threading dislocation density in the surface region can be reduced more effectively.
【００１６】本発明の半導体基板は、Ｓｉ基板上にＳｉ
Ｇｅ層が形成された半導体基板であって、上述した本発
明のＳｉＧｅ層の形成方法により前記ＳｉＧｅ層が形成
されていることを特徴とする。すなわち、この半導体基
板では、上記本発明のＳｉＧｅ層の形成方法によりＳｉ
Ｇｅ層が形成されているので、転位密度が小さくかつ表
面ラフネスが小さい良質なＳｉＧｅ層が得られ、例えば
歪みＳｉ層をＳｉＧｅ層上に形成するための基板として
好適である。The semiconductor substrate of the present invention comprises a Si substrate and a Si substrate.
A semiconductor substrate having a Ge layer formed thereon, characterized in that the SiGe layer is formed by the method for forming a SiGe layer of the present invention described above. That is, in this semiconductor substrate, the SiGe layer forming method of the present invention is used to form Si.
Since the Ge layer is formed, a high-quality SiGe layer having a low dislocation density and a small surface roughness can be obtained, and for example, it is suitable as a substrate for forming a strained Si layer on the SiGe layer.
【００１７】本発明の半導体基板は、上記本発明の半導
体基板の前記ＳｉＧｅバッファ層上に直接又は他のＳｉ
Ｇｅ層を介して形成された歪みＳｉ層を備えていること
を特徴とする。また、本発明の歪みＳｉ層の形成方法
は、Ｓｉ基板上にＳｉＧｅ層を介して歪みＳｉ層を形成
する方法であって、前記Ｓｉ基板上に、上記本発明のＳ
ｉＧｅ層の形成方法によりＳｉＧｅバッファ層をエピタ
キシャル成長する工程と、該ＳｉＧｅバッファ層上に直
接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタキシ
ャル成長する工程とを有することを特徴とする。また、
本発明の半導体基板は、Ｓｉ基板上にＳｉＧｅ層を介し
て歪みＳｉ層が形成された半導体基板であって、上記本
発明の歪みＳｉ層の形成方法により前記歪みＳｉ層が形
成されていることを特徴とする。The semiconductor substrate of the present invention may be formed on the SiGe buffer layer of the semiconductor substrate of the present invention directly or on another Si.
It is characterized by including a strained Si layer formed via a Ge layer. The method of forming a strained Si layer of the present invention is a method of forming a strained Si layer on a Si substrate via a SiGe layer, and the method of forming the strained Si layer of the present invention on the Si substrate.
The method is characterized by comprising a step of epitaxially growing a SiGe buffer layer by a method of forming an iGe layer, and a step of epitaxially growing a strained Si layer on the SiGe buffer layer directly or via another SiGe layer. Also,
The semiconductor substrate of the present invention is a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer, and the strained Si layer is formed by the method of forming a strained Si layer of the present invention. Is characterized by.
【００１８】上記半導体基板では、上記本発明の半導体
基板のＳｉＧｅバッファ層上に直接又は他のＳｉＧｅ層
を介して形成された歪みＳｉ層を備え、また上記歪みＳ
ｉ層の形成方法では、上記本発明のＳｉＧｅ層の形成方
法によりエピタキシャル成長したＳｉＧｅバッファ層上
に直接又は他のＳｉＧｅ層を介して歪みＳｉ層をエピタ
キシャル成長し、また上記半導体基板では、上記本発明
の歪みＳｉ層の形成方法により歪みＳｉ層が形成されて
いるので、傾斜組成層中の転位密度が減少し、表面の貫
通転位密度がより効果的に低減される。また、表面状態
が良好なＳｉＧｅ層上に歪みＳｉ層を成膜することによ
り、良質な歪みＳｉ層を形成することができる。例えば
歪みＳｉ層をチャネル領域とするＭＯＳＦＥＴ等を用い
た集積回路用の基板として好適である。The semiconductor substrate has a strained Si layer formed directly or via another SiGe layer on the SiGe buffer layer of the semiconductor substrate of the present invention, and the strain S
In the method of forming the i layer, the strained Si layer is epitaxially grown directly or through another SiGe layer on the SiGe buffer layer epitaxially grown by the method of forming the SiGe layer of the present invention. Since the strained Si layer is formed by the method of forming the strained Si layer, the dislocation density in the graded composition layer is reduced, and the threading dislocation density on the surface is more effectively reduced. Further, by forming the strained Si layer on the SiGe layer having a good surface condition, a good strained Si layer can be formed. For example, it is suitable as a substrate for an integrated circuit using a MOSFET or the like having a strained Si layer as a channel region.
【００１９】本発明の電界効果型トランジスタは、Ｓｉ
Ｇｅ層上の歪みＳｉ層にチャネル領域を有する電界効果
型トランジスタであって、上記本発明の半導体基板の前
記歪みＳｉ層に前記チャネル領域を有することを特徴と
する。また、本発明の電界効果型トランジスタの製造方
法は、ＳｉＧｅ層上にエピタキシャル成長された歪みＳ
ｉ層にチャネル領域が形成される電界効果型トランジス
タの製造方法であって、上記本発明の歪みＳｉ層の形成
方法により前記歪みＳｉ層を形成することを特徴とす
る。また、本発明の電界効果型トランジスタは、ＳｉＧ
ｅ層上にエピタキシャル成長された歪みＳｉ層にチャネ
ル領域が形成される電界効果型トランジスタであって、
上記本発明の歪みＳｉ層の形成方法により前記歪みＳｉ
層が形成されていることを特徴とする。The field effect transistor of the present invention is made of Si
A field effect transistor having a channel region in a strained Si layer on a Ge layer, characterized in that the strained Si layer of the semiconductor substrate of the present invention has the channel region. In addition, the method for manufacturing a field effect transistor of the present invention is based on the strain S epitaxially grown on the SiGe layer.
A method of manufacturing a field effect transistor in which a channel region is formed in an i layer, characterized in that the strained Si layer is formed by the above-described strained Si layer forming method of the present invention. The field effect transistor of the present invention is made of SiG.
A field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on an e layer,
The strained Si layer is formed by the method for forming a strained Si layer according to the present invention.
It is characterized in that a layer is formed.
【００２０】これらの電界効果型トランジスタ及び電界
効果型トランジスタの製造方法では、上記本発明の半導
体基板の前記歪みＳｉ層にチャネル領域が形成され、又
は上記本発明の歪みＳｉ層の形成方法により、チャネル
領域が形成される歪みＳｉ層が形成されるので、良質な
歪みＳｉ層により高速動作可能等の高特性を有する電界
効果型トランジスタを高歩留まりで得ることができる。In the field effect transistor and the method for manufacturing the field effect transistor, a channel region is formed in the strained Si layer of the semiconductor substrate of the present invention, or by the method of forming the strained Si layer of the present invention, Since the strained Si layer in which the channel region is formed is formed, a field effect transistor having high characteristics such as high-speed operation can be obtained with a high yield due to the high-quality strained Si layer.
【００２１】[0021]
【発明の実施の形態】以下、本発明に係る各実施形態
を、図面を参照しながら説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００２２】図１は、本発明に係る一実施形態の半導体
ウェーハ（半導体基板）Ｗ０及び歪みＳｉ層を備えた半
導体ウェーハ（半導体基板）Ｗ１を示す断面図であり、
この半導体ウェーハの構造をその製造プロセスと合わせ
て説明すると、まず、ＣＺ法で引上成長して作製された
Ｓｉ基板１上に、Ｇｅ組成比ｘが０からｙ（例えばｙ＝
０．３）まで成膜方向に傾斜をもって不連続的に変化す
るＳｉ1-xＧｅxのステップ傾斜層（ＳｉＧｅバッファ
層）２を減圧ＣＶＤ法によりエピタキシャル成長する。
なお、上記減圧ＣＶＤ法による成膜は、キャリアガスと
してＨ2を用い、ソースガスとしてＳｉＨ4及びＧｅＨ4
を用いている。FIG. 1 is a sectional view showing a semiconductor wafer (semiconductor substrate) W0 and a semiconductor wafer (semiconductor substrate) W1 having a strained Si layer according to one embodiment of the present invention.
The structure of this semiconductor wafer will be described together with its manufacturing process. First, a Ge composition ratio x is 0 to y (for example y =
A step gradient layer (SiGe buffer layer) 2 of Si 1-x Ge x which changes discontinuously with a gradient in the film forming direction up to 0.3) is epitaxially grown by the low pressure CVD method.
In the film formation by the low pressure CVD method, H 2 is used as a carrier gas, and SiH 4 and GeH 4 are used as a source gas.
Is used.
【００２３】次に、ステップ傾斜層２上にＧｅ組成比ｚ
が一定（本実施形態ではｚ＝ｙ）であるＳｉ1-yＧｅyの
緩和層３をエピタキシャル成長して半導体ウェーハＷ０
を作製する。さらに、Ｓｉ1-zＧｅzの緩和層３上にＳｉ
をエピタキシャル成長して歪みＳｉ層４を形成すること
により、本実施形態の歪みＳｉ層を備えた半導体ウェー
ハＷ１が作製される。なお、各層の膜厚は、例えば、ス
テップ傾斜層２が１〜２μｍ、緩和層３が０．５〜１μ
ｍ、歪みＳｉ層４が１５〜２５ｎｍである。Next, a Ge composition ratio z is formed on the step gradient layer 2.
Is constant (z = y in this embodiment), and the relaxation layer 3 of Si 1-y Ge y is epitaxially grown to form the semiconductor wafer W0.
To make. Furthermore, Si is formed on the relaxation layer 3 of Si 1-z Ge z.
Is epitaxially grown to form the strained Si layer 4, the semiconductor wafer W1 including the strained Si layer of the present embodiment is manufactured. The thickness of each layer is, for example, 1 to 2 μm for the step gradient layer 2 and 0.5 to 1 μm for the relaxation layer 3.
m, the strained Si layer 4 is 15 to 25 nm.
【００２４】上記ステップ傾斜層２の成膜は、図２及び
図３に示すように、下地材料のＧｅ組成比からＧｅ組成
比を所定値まで漸次増加させたＳｉＧｅの傾斜組成層を
エピタキシャル成長する工程を複数回繰り返すことによ
り行われ、ここでは、４層のＳｉＧｅの傾斜組成層２ａ
〜２ｄが積層されたステップ傾斜層２が得られる。As shown in FIGS. 2 and 3, the step graded layer 2 is formed by epitaxially growing a graded composition layer of SiGe in which the Ge composition ratio of the base material is gradually increased to a predetermined value. Is repeated a plurality of times, and here, four gradient composition layers 2a of SiGe are formed.
The step gradient layer 2 in which ~ 2d are laminated is obtained.
【００２５】例えば、本実施形態では、１回のＳｉＧｅ
の傾斜組成層のエピタキシャル成長工程を１ステップと
すると、まず最初のステップとして、Ｓｉ基板１上に第
１の傾斜組成層２ａを、Ｇｅ組成比を０から０．１２ま
で漸次増加させて成長させる。次に、第２のステップと
して、第１の傾斜組成層２ａ上に第２の傾斜組成層２ｂ
を、Ｇｅ組成比を０．０６から０．１８まで漸次増加さ
せて成長させる。For example, in this embodiment, one SiGe
Assuming that the step of epitaxially growing the graded composition layer is one step, the first graded composition layer 2a is grown on the Si substrate 1 by gradually increasing the Ge composition ratio from 0 to 0.12. Next, as a second step, the second graded composition layer 2b is formed on the first graded composition layer 2a.
Are grown by gradually increasing the Ge composition ratio from 0.06 to 0.18.
【００２６】次に、第３のステップとして、第２の傾斜
組成層２ｂ上に第３の傾斜組成層２ｃを、Ｇｅ組成比を
０．１２から０．２４まで漸次増加させて成長させる。
次に、第４のステップとして、第３の傾斜組成層２ｃ上
に第４の傾斜組成層２ｄを、Ｇｅ組成比を０．１８から
０．３まで漸次増加させて成長させる。Next, as a third step, the third graded composition layer 2c is grown on the second graded composition layer 2b by gradually increasing the Ge composition ratio from 0.12 to 0.24.
Next, as a fourth step, the fourth graded composition layer 2d is grown on the third graded composition layer 2c by gradually increasing the Ge composition ratio from 0.18 to 0.3.
【００２７】ここでは、第１の傾斜組成層２ａ〜第４の
傾斜組成層２ｄそれぞれの膜厚は、いずれも同一になる
ように設定されている。すなわち、第１の傾斜組成層２
ａの膜厚をｌ1、第２の傾斜組成層２ｂの膜厚をｌ2、第
３の傾斜組成層２ｃの膜厚をｌ3、第４の傾斜組成層２
ｄの膜厚ａをｌ 4とすると、ｌ1＝ｌ2＝ｌ3＝ｌ4となる
ように積層されている。Here, the first graded composition layer 2a to the fourth graded composition layer 2a are used.
The film thickness of each of the gradient composition layers 2d is the same.
Is set. That is, the first graded composition layer 2
The film thickness of a is l1, The thickness of the second gradient composition layer 2b is2, First
3 of the gradient composition layer 2c3, Fourth graded composition layer 2
the film thickness a of d FourThen, l1= L2= L3= LFourBecomes
Are stacked so that
【００２８】このように、第１の傾斜組成層２ａ〜第４
の傾斜組成層２ｄ各々は、隣接する２つの傾斜組成層の
うち上側の傾斜組成層の下面側のＧｅ組成比は、下側の
傾斜組成層の上面側のＧｅ組成比より小であるとされて
いる。すなわち、第２の傾斜組成層２ｂの下面側のＧｅ
組成比は、第１の傾斜組成層２ａの上面側のＧｅ組成比
より小とされ、第１の傾斜組成層２ａと第２の傾斜組成
層２ｂとの界面におけるＧｅ組成比は不連続とされてい
る。As described above, the first graded composition layers 2a to 4th
In each of the gradient composition layers 2d, the Ge composition ratio on the lower surface side of the upper gradient composition layer of the two adjacent gradient composition layers is smaller than the Ge composition ratio on the upper surface side of the lower gradient composition layer. ing. That is, Ge on the lower surface side of the second gradient composition layer 2b
The composition ratio is smaller than the Ge composition ratio on the upper surface side of the first graded composition layer 2a, and the Ge composition ratio at the interface between the first graded composition layer 2a and the second graded composition layer 2b is discontinuous. ing.
【００２９】第３の傾斜組成層２ｃも同様に、その下面
側のＧｅ組成比は、第２の傾斜組成層２ｂの上面側のＧ
ｅ組成比より小とされ、この界面におけるＧｅ組成比は
不連続とされている。第４の傾斜組成層２ｄも同様に、
その下面側のＧｅ組成比は、第３の傾斜組成層２ｃの上
面側のＧｅ組成比より小とされ、この界面におけるＧｅ
組成比は不連続とされている。Similarly, the Ge composition ratio on the lower surface side of the third gradient composition layer 2c is G on the upper surface side of the second gradient composition layer 2b.
The composition ratio is smaller than the e composition ratio, and the Ge composition ratio at this interface is discontinuous. Similarly, the fourth graded composition layer 2d
The Ge composition ratio on the lower surface side is set to be smaller than the Ge composition ratio on the upper surface side of the third graded composition layer 2c, and Ge at this interface is formed.
The composition ratio is discontinuous.
【００３０】ここで、傾斜組成層のエピタキシャル成長
工程を４回（ステップ数４）繰り返し行い、第１の傾斜
組成層２ａ〜第４の傾斜組成層２ｄが積層されたステッ
プ傾斜層２としたのは、傾斜組成層中の転位密度を低く
するとともに、貫通転位密度及び表面ラフネスの両方を
低くすることができるからである。Here, the stepwise graded layer 2 in which the first graded composition layer 2a to the fourth graded composition layer 2d are laminated is performed by repeating the epitaxial growth step of the graded composition layer four times (the number of steps is 4). This is because both the dislocation density in the graded composition layer and the threading dislocation density and the surface roughness can be lowered.
【００３１】本実施形態の半導体ウェーハＷ０及び歪み
Ｓｉ層を備えた半導体ウェーハＷ１では、Ｓｉ基板１上
に、下地材料（成長する際の下地がＳｉ基板１の場合は
Ｓｉ、傾斜組成層２ａ〜２ｄの場合はＳｉＧｅ）のＧｅ
組成比からＧｅ組成比を漸次増加させたＳｉＧｅの傾斜
組成層をエピタキシャル成長する工程を複数回繰り返す
ことにより、傾斜組成層２ａ〜２ｄからなるステップ傾
斜層２を形成したので、傾斜組成層２ａ〜２ｄ各々の界
面におけるＧｅ組成比が膜厚方向に不連続かつ減少する
こととなり、上述したように転位密度が少なくかつ表面
ラフネスが少ないステップ傾斜層２を形成することがで
きる。In the semiconductor wafer W0 and the semiconductor wafer W1 provided with the strained Si layer of the present embodiment, the underlying material (Si when the underlying substrate during growth is the Si substrate 1, Si, the graded composition layers 2a ... Ge in 2Ge in case of 2d)
Since the step graded layer 2 including the graded composition layers 2a to 2d is formed by repeating the step of epitaxially growing the graded composition layer of SiGe in which the Ge composition ratio is gradually increased from the composition ratio, the graded composition layers 2a to 2d are formed. The Ge composition ratio at each interface is discontinuous and decreases in the film thickness direction, and as described above, it is possible to form the step-graded layer 2 having a small dislocation density and a small surface roughness.
【００３２】すなわち、本実施形態では、上記成膜方法
により、格子緩和に必要な転位を均等に発生させると共
に、転位をできるだけ横方向に走らせて表面上に貫通し
て出ないようにＳｉＧｅ層を成膜することができるの
で、このように良好な表面状態を得ることができる。That is, in the present embodiment, by the above-described film forming method, dislocations necessary for lattice relaxation are generated uniformly, and the SiGe layer is formed so that the dislocations run in the lateral direction as much as possible so as not to penetrate the surface. Since a film can be formed, a good surface condition can be obtained in this way.
【００３３】また、本実施形態では、複数層の傾斜組成
層において上側の層の界面近傍のＧｅ組成比を下側の層
の界面近傍のＧｅ組成比より小さくすることにより、傾
斜組成層中の転位密度をより効果的に減少させるととも
に、表面領域における貫通転位密度を低く抑えることが
できる。Further, in this embodiment, in a plurality of gradient composition layers, the Ge composition ratio in the vicinity of the interface of the upper layer is made smaller than the Ge composition ratio in the vicinity of the interface of the lower layer, so that The dislocation density can be reduced more effectively, and the threading dislocation density in the surface region can be suppressed low.
【００３４】また、本実施形態では、主に傾斜組成層に
おいて転位同士の絡み合いが起こり、傾斜組成層中の転
位密度を減少させるとともに、転位が横方向に誘導され
ることにより表面領域における貫通転位密度を減少させ
ることができる。これは、上記傾斜組成層の傾斜組成が
緩やかな傾斜であるほど顕著に表れ、傾斜組成層はその
厚みが厚いほど効果的となる。これにより、傾斜組成層
の膜厚が所定の膜厚を超えた場合には、傾斜組成領域の
膜厚が増加するにしたがって転位密度を徐々に低下させ
ることができる。In this embodiment, dislocations are entangled with each other mainly in the graded composition layer to reduce the dislocation density in the graded composition layer, and the dislocations are laterally induced to cause threading dislocations in the surface region. The density can be reduced. This is more remarkable as the gradient composition of the gradient composition layer has a gentler gradient, and the thicker the gradient composition layer is, the more effective it is. As a result, when the film thickness of the graded composition layer exceeds a predetermined film thickness, the dislocation density can be gradually reduced as the film thickness of the graded composition region increases.
【００３５】また、上記の傾斜組成層においては、上側
の層の界面近傍のＧｅ組成比を下側の層の界面近傍のＧ
ｅ組成比より小さくするステップを導入することによ
り、表面領域における貫通転位密度を低く抑えることが
できる。この構造によれば、表面のＧｅ組成比が同一の
構造を作製する場合に、傾斜組成領域の合計膜厚がより
厚い構造を容易に作製することができる。その結果、傾
斜組成層中の転位密度をより効果的に減少させることが
でき、表面領域における貫通転位密度をより効果的に低
減させることができる。In the above graded composition layer, the Ge composition ratio near the interface of the upper layer is set to the G composition ratio near the interface of the lower layer.
The threading dislocation density in the surface region can be suppressed low by introducing the step of making the composition ratio smaller than the e composition ratio. According to this structure, when a structure having the same Ge composition ratio on the surface is manufactured, a structure having a larger total film thickness in the gradient composition region can be easily manufactured. As a result, the dislocation density in the graded composition layer can be reduced more effectively, and the threading dislocation density in the surface region can be reduced more effectively.
【００３６】図４は、本発明のステップ傾斜層の変形例
を示す図であり、ステップ傾斜層の膜厚に対するＧｅ組
成比を示している。このステップ傾斜層は、上述したス
テップ傾斜層２の第４の傾斜組成層２ｄ上に、Ｇｅ組成
比が第４の傾斜組成層２ｄの最終的な組成比である上面
側のＧｅ組成比と同一とされ、かつＧｅ組成比が膜厚方
向で一定であるＳｉＧｅの一定組成層をエピタキシャル
成長している。FIG. 4 is a diagram showing a modification of the step gradient layer of the present invention, showing the Ge composition ratio with respect to the film thickness of the step gradient layer. This step graded layer has the same Ge composition ratio as the final composition ratio of the fourth graded composition layer 2d on the fourth graded composition layer 2d of the step graded layer 2 on the upper surface side. And a constant composition layer of SiGe having a constant Ge composition ratio in the film thickness direction is epitaxially grown.
【００３７】図５は、本発明のステップ傾斜層の他の変
形例を示す図である。このステップ傾斜層は、上述した
ステップ傾斜層２の第４の傾斜組成層２ｄ上に、Ｇｅ組
成比が第４の傾斜組成層２ｄの最終的な組成比である上
面側のＧｅ組成比より小とされ、かつＧｅ組成比が膜厚
方向で一定であるＳｉＧｅの一定組成層をエピタキシャ
ル成長している。FIG. 5 is a diagram showing another modification of the step gradient layer of the present invention. This step graded layer has a Ge composition ratio on the fourth graded composition layer 2d of the above step graded layer 2 smaller than the Ge composition ratio on the upper surface side which is the final composition ratio of the fourth graded composition layer 2d. And a constant composition layer of SiGe having a constant Ge composition ratio in the film thickness direction is epitaxially grown.
【００３８】図６は、本発明のステップ傾斜層のさらに
他の変形例を示す図である。このステップ傾斜層は、上
述したステップ傾斜層２の第１の傾斜組成層２ａ上に、
出発点のＧｅ組成比が第１の傾斜組成層２ａの上面側の
Ｇｅ組成比より小であり、かつ最終点のＧｅ組成比が第
１の傾斜組成層２ａの上面側のＧｅ組成比と一致する傾
斜組成層を複数層（ここでは３層）成長させ、第４の傾
斜組成層２ｄ上に、Ｇｅ組成比が第４の傾斜組成層２ｄ
の最終的な組成比である上面側のＧｅ組成比と同一とさ
れ、かつＧｅ組成比が膜厚方向で一定であるＳｉＧｅの
一定組成層をエピタキシャル成長している。FIG. 6 is a diagram showing still another modification of the step gradient layer of the present invention. This step graded layer is formed on the first graded composition layer 2a of the step graded layer 2 described above.
The Ge composition ratio at the starting point is smaller than the Ge composition ratio on the upper surface side of the first graded composition layer 2a, and the Ge composition ratio at the final point matches the Ge composition ratio on the upper surface side of the first graded composition layer 2a. A plurality of gradient composition layers (here, three layers) are grown, and the Ge composition ratio is the fourth gradient composition layer 2d on the fourth gradient composition layer 2d.
Of the same composition as the Ge composition ratio on the upper surface side, which is the final composition ratio, and a constant composition layer of SiGe having a constant Ge composition ratio in the film thickness direction is epitaxially grown.
【００３９】次に、本発明の上記歪みＳｉ層を備えた半
導体ウェーハＷ１を用いた電界効果型トランジスタ（Ｍ
ＯＳＦＥＴ）を、その製造プロセスと合わせて図面を参
照して説明する。図７は、本発明の電界効果型トランジ
スタの概略的な構造を示す断面図であり、この電界効果
型トランジスタを製造するには、上記の製造工程で作製
した歪みＳｉ層を備えた半導体ウェーハＷ１の表面の歪
みＳｉ層４上にＳｉＯ2のゲート酸化膜５及びゲートポ
リシリコン膜６を順次堆積する。そして、チャネル領域
となる部分の上のゲートポリシリコン膜６の上に、ゲー
ト電極（図示略）をパターニングして形成する。Next, a field effect transistor (M using the semiconductor wafer W1 having the strained Si layer of the present invention is used.
OSFET) will be described with reference to the drawings together with the manufacturing process thereof. FIG. 7 is a cross-sectional view showing a schematic structure of the field-effect transistor of the present invention. To manufacture this field-effect transistor, the semiconductor wafer W1 having the strained Si layer manufactured in the above manufacturing process is used. A gate oxide film 5 of SiO 2 and a gate polysilicon film 6 are sequentially deposited on the strained Si layer 4 on the surface of. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 6 on the portion to be the channel region.
【００４０】次に、ゲート酸化膜５もパターニングする
ことにより、ゲート電極下以外の部分を除去する。さら
に、ゲート電極をマスクに用いたイオン注入により、歪
みＳｉ層４及び緩和層３にｎ型あるいはｐ型のソース領
域Ｓ及びドレイン領域Ｄを自己整合的に形成する。次い
で、ソース領域Ｓ及びドレイン領域Ｄ上にソース電極及
びドレイン電極（図示略）をそれぞれ形成し、歪みＳｉ
層４がチャネル領域となるｎ型あるいはｐ型ＭＯＳＦＥ
Ｔが製造される。Next, the gate oxide film 5 is also patterned to remove a portion other than under the gate electrode. Further, the n-type or p-type source region S and drain region D are formed in the strained Si layer 4 and the relaxation layer 3 in a self-aligned manner by ion implantation using the gate electrode as a mask. Next, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively, and the strained Si
N-type or p-type MOSFE whose layer 4 serves as a channel region
T is manufactured.
【００４１】このＭＯＳＦＥＴでは、歪みＳｉ層を備え
た半導体ウェーハＷ１の歪みＳｉ層４にチャネル領域を
形成したので、良質な歪みＳｉ層４により高速動作可能
等の高特性を有するＭＯＳＦＥＴを高歩留まりで得るこ
とができる。In this MOSFET, since the channel region is formed in the strained Si layer 4 of the semiconductor wafer W1 having the strained Si layer, the MOSFET having high characteristics such as high-speed operation can be produced with high yield by the strained Si layer 4 of good quality. Obtainable.
【００４２】なお、本発明は上記実施形態に限定される
ものではなく、本発明の趣旨を逸脱しない範囲において
種々の変更を加えることが可能である。例えば、上記実
施形態の半導体ウェーハＷ１の歪みＳｉ層４上に、さら
にＳｉＧｅ層を備えた構成としてもよい。また、上記各
実施形態では、傾斜組成層のエピタキシャル成長工程を
繰り返す回数を４回（ステップ数４）としたが、４回に
限定することなく、貫通転位密度及び表面ラフネスの両
方を効果的に低下させることを条件に回数を設定しても
良い。The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the semiconductor wafer W1 of the above embodiment may have a structure in which a SiGe layer is further provided on the strained Si layer 4. Further, in each of the above-described embodiments, the number of times of repeating the epitaxial growth step of the graded composition layer is set to 4 (the number of steps is 4), but the number is not limited to 4 and both the threading dislocation density and the surface roughness are effectively reduced. The number of times may be set on the condition that it is performed.
【００４３】また、上記実施形態では、ＭＯＳＦＥＴ用
の基板として歪みＳｉ層を備えた半導体ウェーハＷ１を
作製したが、他の用途に適用する基板としても構わな
い。例えば、本発明のＳｉＧｅ層の形成方法及び半導体
基板を太陽電池用の基板に適用してもよい。すなわち、
上述した各実施形態のいずれかのシリコン基板上に最表
面で１００％ＧｅとなるようにＧｅ組成比を漸次増加さ
せた傾斜組成層のＳｉＧｅ層を成膜し、さらにこの上に
ＧａＡｓ（ガリウムヒ素）を成膜することで、太陽電池
用基板を作製してもよい。この場合、低転位密度で高特
性の太陽電池用基板が得られる。In the above embodiment, the semiconductor wafer W1 having the strained Si layer was manufactured as the substrate for the MOSFET, but the substrate may be applied to other uses. For example, the method for forming a SiGe layer and the semiconductor substrate of the present invention may be applied to a solar cell substrate. That is,
On the silicon substrate of any of the above-mentioned embodiments, a SiGe layer having a graded composition layer in which the Ge composition ratio is gradually increased so that the outermost surface is 100% Ge is formed, and GaAs (gallium arsenide) is further formed thereon. ) May be formed into a film to form a solar cell substrate. In this case, a solar cell substrate having a low dislocation density and high characteristics can be obtained.
【００４４】[0044]
【発明の効果】本発明によれば、以下の効果を奏する。
本発明の半導体基板によれば、Ｓｉ基板上に、Ｇｅ組成
比が表面に向けて漸次増加するＳｉＧｅの傾斜組成層を
複数層積層状態としたＳｉＧｅバッファ層を備え、これ
らの傾斜組成層各々は、隣接する２つの傾斜組成層のう
ち上側の傾斜組成層の下面側のＧｅ組成比は、下側の傾
斜組成層の上面側のＧｅ組成比より小としたので、転位
を横方向に走らせて表面上に貫通する転位を低減するこ
とができる。また、界面での組成変化が小さいので、界
面における転位の発生を抑制することができる。The present invention has the following effects.
According to the semiconductor substrate of the present invention, a SiGe buffer layer in which a plurality of SiGe gradient composition layers whose Ge composition ratio gradually increases toward the surface is laminated is provided on the Si substrate, and each of these gradient composition layers is formed. , The Ge composition ratio on the lower surface side of the upper gradient composition layer of the two adjacent gradient composition layers is set to be smaller than the Ge composition ratio on the upper surface side of the lower gradient composition layer. Dislocations penetrating on the surface can be reduced. Further, since the composition change at the interface is small, the generation of dislocations at the interface can be suppressed.
【００４５】また、傾斜組成層中の転位密度をより効果
的に減少させることができ、表面領域における貫通転位
密度をより効果的に低減させることができる。また、複
数の傾斜組成層の合計膜厚を厚くすることができ、した
がって、転位密度を効果的に減少させることができる。Further, the dislocation density in the graded composition layer can be more effectively reduced, and the threading dislocation density in the surface region can be more effectively reduced. Further, the total film thickness of the plurality of graded composition layers can be increased, and therefore the dislocation density can be effectively reduced.
【００４６】したがって、格子緩和に必要な転位を均等
に発生させて表面ラフネスを低減させると共に、転位を
できるだけ横方向に走らせて貫通転位を低減させて成膜
を施すことができ、貫通転位密度及び表面ラフネスの小
さい良質な結晶性を得ることができる。Therefore, dislocations necessary for lattice relaxation can be uniformly generated to reduce the surface roughness, and dislocations can be run in the lateral direction as much as possible to reduce threading dislocations so that film formation can be performed. It is possible to obtain good crystallinity with a small surface roughness.
【００４７】また、本発明のＳｉＧｅ層の形成方法によ
れば、積層方向に隣接する２つの傾斜組成層の上側の傾
斜組成層の下面側のＧｅ組成比が下側の傾斜組成層の上
面側のＧｅ組成比より小であるように、前記ＳｉＧｅの
傾斜組成層をエピタキシャル成長する工程を複数回繰り
返し、各々のＳｉＧｅの傾斜組成層を成膜するので、界
面での集中的な転位発生を抑制し、さらに転位を横方向
に走らせて表面上に貫通する転位を低減し、貫通転位密
度及び表面ラフネスの小さい良質な結晶性を有する半導
体基板を容易に製造することができる。また、傾斜組成
層中の転位密度を効果的に減少させ、かつ表面領域にお
ける貫通転位密度をより効果的に低減させた半導体基板
を容易に製造することができる。Further, according to the method of forming a SiGe layer of the present invention, the Ge composition ratio on the lower surface side of the upper gradient composition layer of the two gradient composition layers adjacent to each other in the stacking direction is the upper surface side of the lower gradient composition layer. The step of epitaxially growing the graded composition layer of SiGe is repeated a plurality of times so as to be smaller than the Ge composition ratio of, and each of the graded composition layers of SiGe is deposited, so that the occurrence of concentrated dislocations at the interface is suppressed. Further, it is possible to easily manufacture a semiconductor substrate having good crystallinity with a small threading dislocation density and a small surface roughness by causing dislocations to run laterally to reduce dislocations penetrating on the surface. Further, it is possible to easily manufacture a semiconductor substrate in which the dislocation density in the graded composition layer is effectively reduced and the threading dislocation density in the surface region is more effectively reduced.
【００４８】また、本発明の歪みＳｉ層を備えた半導体
基板によれば、本発明の半導体基板のＳｉＧｅバッファ
層上に直接又は他のＳｉＧｅ層を介して形成された歪み
Ｓｉ層を備えたので、表面状態が良好なＳｉＧｅ層上に
Ｓｉ層を成膜することができ、良質な歪みＳｉ層を形成
することができる。Further, according to the semiconductor substrate having the strained Si layer of the present invention, since the strained Si layer formed directly or via another SiGe layer is provided on the SiGe buffer layer of the semiconductor substrate of the present invention. A Si layer can be formed on the SiGe layer having a good surface condition, and a high-quality strained Si layer can be formed.
【００４９】また本発明の歪みＳｉ層の形成方法によれ
ば、本発明のＳｉＧｅ層の形成方法によりエピタキシャ
ル成長したＳｉＧｅバッファ層上に直接又は他のＳｉＧ
ｅ層を介して歪みＳｉ層をエピタキシャル成長するの
で、表面状態が良好なＳｉＧｅ層上にＳｉ層を成膜で
き、良質な歪みＳｉ層を形成することができる。Further, according to the method for forming a strained Si layer of the present invention, the SiGe buffer layer epitaxially grown by the method for forming a SiGe layer of the present invention is directly or another SiG.
Since the strained Si layer is epitaxially grown via the e layer, the Si layer can be formed on the SiGe layer having a good surface condition, and the strained Si layer with good quality can be formed.
【００５０】また、本発明の電界効果型トランジスタに
よれば、本発明の半導体基板の前記歪みＳｉ層にチャネ
ル領域が形成されているので、良質な歪みＳｉ層により
高速動作可能等の高特性を有するＭＯＳＦＥＴを得るこ
とができる。Further, according to the field effect transistor of the present invention, since the channel region is formed in the strained Si layer of the semiconductor substrate of the present invention, the high quality strained Si layer provides high characteristics such as high-speed operation. It is possible to obtain a MOSFET having the same.
【００５１】また、本発明の電界効果型トランジスタの
製造方法によれば、本発明の歪みＳｉ層の形成方法によ
りチャネル領域となる歪みＳｉ層が形成されているの
で、良質な歪みＳｉ層により高速動作可能等の高特性を
有するＭＯＳＦＥＴを高歩留まりで作製することができ
る。Further, according to the method for manufacturing a field effect transistor of the present invention, since the strained Si layer to be the channel region is formed by the method of forming the strained Si layer of the present invention, the strained Si layer of high quality can be formed at high speed. A MOSFET having high characteristics such as being operable can be manufactured with a high yield.
【図１】 本発明に係る一実施形態の半導体ウェーハを
示す断面図である。FIG. 1 is a sectional view showing a semiconductor wafer according to an embodiment of the present invention.
【図２】 本発明に係る一実施形態のステップ傾斜層を
示す断面図である。FIG. 2 is a cross-sectional view showing a step graded layer according to an embodiment of the present invention.
【図３】 本発明に係る一実施形態のステップ傾斜層の
膜厚に対するＧｅ組成比を示す図である。FIG. 3 is a diagram showing a Ge composition ratio with respect to a film thickness of a step graded layer according to an embodiment of the present invention.
【図４】 本発明に係る一実施形態のステップ傾斜層の
変形例を示す図である。FIG. 4 is a diagram showing a modification of the step gradient layer according to the embodiment of the present invention.
【図５】 本発明に係る一実施形態のステップ傾斜層の
他の変形例を示す図である。FIG. 5 is a diagram showing another modification of the step gradient layer according to the embodiment of the present invention.
【図６】 本発明に係る一実施形態のステップ傾斜層の
さらに他の変形例を示す図である。FIG. 6 is a view showing still another modified example of the step gradient layer according to the embodiment of the present invention.
【図７】 本発明に係る一実施形態のＭＯＳＦＥＴを示
す概略断面図である。FIG. 7 is a schematic cross-sectional view showing a MOSFET of one embodiment according to the present invention.
１ Ｓｉ基板
２ ステップ傾斜層（ＳｉＧｅバッファ層）
２ａ〜２ｄ 傾斜組成層
３ 緩和層
４ 歪みＳｉ層
５ ＳｉＯ2ゲート酸化膜
６ ゲートポリシリコン膜
Ｓ ソース領域
Ｄ ドレイン領域
Ｗ０ 半導体ウェーハ（半導体基板）
Ｗ１ 歪みＳｉ層を備えた半導体ウェーハ（半導体基
板）1 Si Substrate 2 Step Graded Layer (SiGe Buffer Layer) 2a to 2d Gradient Composition Layer 3 Relaxation Layer 4 Strained Si Layer 5 SiO 2 Gate Oxide Film 6 Gate Polysilicon Film S Source Region D Drain Region W0 Semiconductor Wafer (Semiconductor Substrate) W1 Semiconductor wafer (semiconductor substrate) with strained Si layer
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/812 (72)発明者 山口 健志 埼玉県さいたま市北袋町１丁目297番地 三菱マテリアル株式会社総合研究所内 (72)発明者 塩野 一郎 埼玉県さいたま市北袋町１丁目297番地 三菱マテリアル株式会社総合研究所内 Ｆターム(参考） 5F045 AA06 AB01 AB02 AC01 AF03 BB12 DA53 DA58 HA22 5F052 GC01 GC03 JA01 KA01 KA05 5F102 FA00 GD01 GJ03 GK02 GK08 GK09 HC01 5F140 AA01 AB03 AC28 BA05 BC12 BC19 BF01 BF04 BK13 Front page continuation (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/812 (72) Inventor Kenji Yamaguchi 1-297 Kitabukuro-cho, Saitama City, Saitama Mitsubishi Materials Corporation (72) ) Inventor Ichiro Shiono 1-297 Kitabukuro-cho, Saitama City, Saitama Prefecture F-term in the Research Institute of Mitsubishi Materials Corporation (reference) 5F045 AA06 AB01 AB02 AC01 AF03 BB12 DA53 DA58 HA22 5F052 GC01 GC03 JA01 KA01 KA05 5F102 FA00 GD01 GJ03 GK02 GK08 GK08 GK08 GK08 GK08 HC01 5F140 AA01 AB03 AC28 BA05 BC12 BC19 BF01 BF04 BK13
Claims (9)
て漸次増加するＳｉＧｅの傾斜組成層を複数層積層状態
としたＳｉＧｅバッファ層を備え、 これらの傾斜組成層各々は、隣接する２つの傾斜組成層
のうち上側の傾斜組成層の下面側のＧｅ組成比は、下側
の傾斜組成層の上面側のＧｅ組成比より小であることを
特徴とする半導体基板。1. A SiGe buffer layer is provided on a Si substrate in which a plurality of SiGe gradient composition layers whose Ge composition ratio gradually increases toward the surface are laminated, and each of these gradient composition layers is adjacent to two adjacent layers. A semiconductor substrate, wherein a Ge composition ratio on a lower surface side of an upper gradient composition layer of the two gradient composition layers is smaller than a Ge composition ratio on an upper surface side of a lower gradient composition layer.
介して形成された歪みＳｉ層を備えていることを特徴と
する半導体基板。2. The semiconductor substrate according to claim 1, further comprising a strained Si layer formed on the SiGe buffer layer directly or via another SiGe layer.
域を有する電界効果型トランジスタであって、 請求項２記載の半導体基板の前記歪みＳｉ層に前記チャ
ネル領域を有することを特徴とする電界効果型トランジ
スタ。3. A field effect transistor having a channel region in a strained Si layer on a SiGe layer, the field effect transistor having the channel region in the strained Si layer of a semiconductor substrate according to claim 2. Type transistor.
て漸次増加するＳｉＧｅの傾斜組成層を複数層積層状態
としたＳｉＧｅバッファ層を成膜する方法であって、 積層方向に隣接する２つの傾斜組成層の上側の傾斜組成
層の下面側のＧｅ組成比が下側の傾斜組成層の上面側の
Ｇｅ組成比より小であるように、前記ＳｉＧｅの傾斜組
成層をエピタキシャル成長する工程を複数回繰り返し、
各々のＳｉＧｅの傾斜組成層を成膜することを特徴とす
るＳｉＧｅ層の形成方法。4. A method of forming a SiGe buffer layer in which a plurality of SiGe gradient composition layers, each having a Ge composition ratio gradually increasing toward the surface, are laminated on a Si substrate, wherein the SiGe buffer layers are adjacent to each other in the laminating direction. A step of epitaxially growing the gradient composition layer of SiGe so that the Ge composition ratio on the lower surface side of the upper gradient composition layer of the two gradient composition layers is smaller than the Ge composition ratio on the upper surface side of the lower gradient composition layer; Repeated multiple times,
A method of forming a SiGe layer, which comprises forming a gradient composition layer of each SiGe.
ｉ層を形成する方法であって、 前記Ｓｉ基板上に、請求項４記載のＳｉＧｅ層の形成方
法によりＳｉＧｅバッファ層をエピタキシャル成長する
工程と、 該ＳｉＧｅバッファ層上に直接又は他のＳｉＧｅ層を介
して歪みＳｉ層をエピタキシャル成長する工程とを有す
ることを特徴とする歪みＳｉ層の形成方法。5. Strain S is formed on a Si substrate via a SiGe layer.
A method of forming an i layer, comprising the step of epitaxially growing a SiGe buffer layer on the Si substrate by the method of forming a SiGe layer according to claim 4, and directly or through another SiGe layer on the SiGe buffer layer. And epitaxially growing the strained Si layer, thereby forming the strained Si layer.
た歪みＳｉ層にチャネル領域が形成される電界効果型ト
ランジスタの製造方法であって、 請求項５記載の歪みＳｉ層の形成方法により前記歪みＳ
ｉ層を形成することを特徴とする電界効果型トランジス
タの製造方法。6. A method of manufacturing a field effect transistor, wherein a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strained S is formed by the method of forming the strained Si layer according to claim 5.
A method of manufacturing a field effect transistor, which comprises forming an i layer.
導体基板であって、 請求項４記載のＳｉＧｅ層の形成方法により前記ＳｉＧ
ｅ層が形成されていることを特徴とする半導体基板。7. A semiconductor substrate having a SiGe layer formed on a Si substrate, wherein the SiG layer is formed by the method of forming a SiGe layer according to claim 4.
A semiconductor substrate having an e layer formed thereon.
ｉ層が形成された半導体基板であって、 請求項５記載の歪みＳｉ層の形成方法により前記歪みＳ
ｉ層が形成されていることを特徴とする半導体基板。8. A strain S on a Si substrate via a SiGe layer.
A semiconductor substrate having an i layer formed thereon, wherein the strain S is formed by the method of forming a strained Si layer according to claim 5.
A semiconductor substrate having an i layer formed thereon.
た歪みＳｉ層にチャネル領域が形成される電界効果型ト
ランジスタであって、 請求項５記載の歪みＳｉ層の形成方法により前記歪みＳ
ｉ層が形成されていることを特徴とする電界効果型トラ
ンジスタ。9. A field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strain S is formed by the method of forming a strained Si layer according to claim 5.
A field-effect transistor having an i-layer formed.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004070800A1 (en) * | 2003-02-04 | 2004-08-19 | Sumitomo Mitsubishi Silicon Corporation | Semiconductor substrate, field-effect transistor, and their production methods |
| JP2005536876A (en) * | 2002-08-23 | 2005-12-02 | アンバーウェーブ システムズ コーポレイション | Semiconductor heterostructures with reduced dislocation pileup and related methods |
| CN100378906C (en) * | 2004-10-21 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Semiconductor device having a smooth EPI layer and a method for its manufacture |
| JP2008141206A (en) * | 2006-11-30 | 2008-06-19 | Soitec Silicon On Insulator Technologies | Method of manufacturing semiconductor heterostructure |
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| JP2005536876A (en) * | 2002-08-23 | 2005-12-02 | アンバーウェーブ システムズ コーポレイション | Semiconductor heterostructures with reduced dislocation pileup and related methods |
| US7829442B2 (en) | 2002-08-23 | 2010-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
| JP2011018946A (en) * | 2002-08-23 | 2011-01-27 | Taiwan Semiconductor Manufacturing Co Ltd | Semiconductor heterostructure having reduced dislocation pile-up, and related method |
| WO2004070800A1 (en) * | 2003-02-04 | 2004-08-19 | Sumitomo Mitsubishi Silicon Corporation | Semiconductor substrate, field-effect transistor, and their production methods |
| KR100778196B1 (en) * | 2003-02-04 | 2007-11-22 | 가부시키가이샤 섬코 | Semiconductor substrate, field-effect transistor, and their production methods |
| US7405142B2 (en) | 2003-02-04 | 2008-07-29 | Sumco Corporation | Semiconductor substrate and field-effect transistor, and manufacturing method for same |
| CN100378906C (en) * | 2004-10-21 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Semiconductor device having a smooth EPI layer and a method for its manufacture |
| JP2008141206A (en) * | 2006-11-30 | 2008-06-19 | Soitec Silicon On Insulator Technologies | Method of manufacturing semiconductor heterostructure |
| US8247842B2 (en) | 2009-03-26 | 2012-08-21 | Sanken Electric Co., Ltd. | Nitride semiconductor device having graded aluminum content |
| JP2012191202A (en) * | 2011-03-03 | 2012-10-04 | Internatl Rectifier Corp | Iii-nitride semiconductor structures with strain-absorbing interlayer transition modules |
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