JP2003016773A - Register, data storing method, and data read-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a register provided with a non-volatile data storing function. SOLUTION: This device comprises a data write-in block 12 comprising a non-volatile storage element, and a data restoring block 14 for reading out data stored in the non-volatile storage element. MTJ elements 16a, 16b are used as a non-volatile storage element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory element in a semiconductor chip, especially MRAM (Magnetic Ran).
MTJ (Magnetic Tu) used for dom access memory
register, a method of storing data and a method of reading data.

[0002]

2. Description of the Related Art A register block 20 is a circuit block for temporarily storing data. Register block 2
0 indicates the NAND circuits 40a and 40b as shown in FIG.
It is composed of Flip-Flops. Data of "0" or "1" is stored as a combination of signals input to the input lines S and R.

The register block 20 inputs a signal of "High" to the input line S and inputs a signal of "Low" to the input line R.
w) ”signal is input, Q2 becomes“ high ”and Q1
Becomes "low". When a "High" signal is input to the input line R and a "Low" signal is input to the input line S, Q1 becomes "high" and Q2 becomes "low". The level of the signal on the input lines S and R is determined by the data written in the register. Further, by inputting a “high” signal to the input lines S and R at the same time, the data input to the register block 20 is held. Generally, if the "low" signals are input to the input lines S and R at the same time, the state of the register block 20 becomes unpredictable. Therefore, it is not possible to input the "low" signals to the input lines S and R at the same time. Absent.

Conventionally, a latch circuit or a register incorporated in a logic chip stores data in a volatile storage element such as a capacitor, and therefore loses data when the power is turned off. Therefore, the use of a non-volatile storage element is not only a very useful function for many system applications, but also one of the elements that enhances the function of the system.

Although there are nonvolatile semiconductor memory chips such as a flash memory, a logic chip having a nonvolatile memory function has not been designed or developed.
The reason is that incorporating a non-volatile storage element such as a flash memory makes the structure more complicated than that of a conventional semiconductor logic chip. This is because it is impossible to incorporate a nonvolatile storage element such as a flash memory in the existing manufacturing process of the semiconductor chip. Therefore, existing computer system and application logic chips do not have such non-volatile data storage capability.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a register having a nonvolatile data storage function, a data storage method, and a data read method.

[0007]

The gist of a register of the present invention is a register block in which data is stored, a data writing block including a nonvolatile storage element for storing the data, and the data writing block. And a data recovery block for reading the data stored in.

The gist of the data storage method of the present invention is to output a high signal from one of the two logic circuits according to the data output from the register block, and a high signal. Turning on the two switches connected to the logic circuit that outputs
Writing data to the two storage elements.

The gist of the data reading method of the present invention is as follows.
The method includes activating the current mirror circuit, amplifying the differential signal generated by activating the current mirror circuit, and holding the amplified differential signal.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a register, a data storing method and a data reading method of the present invention will be described with reference to the drawings.

As shown in FIG. 1, the register 10 of the present invention.
In addition to the conventional register block 20, has a data writing block 12 for temporarily storing the data of the register block 20, and a data restoration block 14 for restoring the data stored in the data writing block 12.
In FIG. 1, the register 10 has a 1-bit register function or a 1-bit latch function, but a general multi-bit register has the same blocks as described above for each bit.

The data write block 12 has MTJ (Magnetic Tunnel Junction) elements 16a and 16b which are nonvolatile storage elements. MTJ elements 16a, 16b
Is a storage element used for a memory cell of an MRAM (Magnetic Random Access Memory).

As shown in FIG. 2, a general MTJ element 16a has a free layer 2 which is a ferromagnetic layer.
6, a tunneling barrier 28 and a pinned layer 30, which is a ferromagnetic layer, are stacked. The magnetization direction of the fixed layer 30 is constant, and the magnetization direction of the free layer 26 can be changed by the direction of the magnetic field from the outside. Fixed layer 30
According to the combination of the magnetization direction of 1 and the magnetization direction of the free layer 26, the stored data is discriminated whether it is “0” or “1”. For example, when the magnetization directions of the fixed layer 30 and the free layer 26 are the same, the resistance of the MTJ element is small and the data is “0”, and when the magnetization directions of the fixed layer 30 and the free layer 26 are the same, the resistance of the MTJ element is high and the data is “1”. Is.

The data write block 12 is an AND to which the data output from the register block 20 is input.
Circuit 22b and NOT for inverting the value of the data
A to which the outputs of the circuit 24a and the NOT circuit 24a are input
And an ND circuit 22a. NOT circuit 24a and A
When the ND circuit 22a is one logic circuit, the one logic circuit and the AND circuit 22b include two logic circuits. Further, the signals of the data write line (Data Write: DW) are input to the AND circuits 22a and 22b. As long as the "Low" signal is input to the data write line, the outputs of the AND circuits 22a and 22b are fixed to low.

The two MTJ elements 16a and 16b are connected via a switch T5. Two MTJ elements 16
The magnetization directions of the respective fixed layers of a and 16b are configured so as to be opposite to each other. For example, as shown by the arrow in the figure, the directions are opposite to each other via the switch T5.

A switch T is provided on the MTJ elements 16a and 16b.
1, T2, T3 and T4 are connected. Together with the switch T5 described above, it is used to form the electrical path of the data write block 12. For example, switch T
1, T3 and T5 are turned on, switches T1 to M
The TJ element 16a, the switch T5, the MTJ element 16b, and the switch T3 are connected in series to form an electric path. When the switches T2, T4, and T5 are turned on, the switch T2 moves to the MTJ element 16b and the switch T.
5, the MTJ element 16a and the switch T4 are connected in series to form an electric path. In FIG. 1, the switch T
When a current flows from left to right through 5, the MTJ element 16a has the magnetization directions of the fixed layer and the free layer in the same direction, and "0" data is written, and the MTJ element 16b has the magnetization directions of the fixed layer and the free layer. The direction is opposite and the data of "1" is written. On the contrary, when a current flows from right to left through the switch T5, the magnetization directions of the fixed layer and the free layer of the MTJ element 16b become the same direction, and the data of "0" is written, and the MTJ element 16a becomes the fixed layer. The magnetization direction of the free layer is opposite, and the data of "1" is written. MT in any case
Complement to J elements 16a and 16b is True.
(False) data is written.

When the output of the AND circuit 22a becomes "high", the switches T1 and T3 are turned on. AND circuit 2
When the output of 2b goes "high", switches T2 and T4
Turns on. The switch T5 is turned on by inputting a "high" signal to the data write line.

The data restoration block 14 includes the MTJ element 1
6c and 16d are included. The MTJ elements 16c and 16d are shown in FIG.
As shown in FIG. 5, it is a resistance portion of the MTJ element, and the MTJ element 16a or 16b and the MTJ element 16c or 16d
Is an integral structure.

A switch T8 to which a signal of a data restore line (Data Restore: DRS) is input, and a NOT circuit 24b.
And a switch T7 to which the output of the NOT circuit 24b is input.
Is provided. The switches T7 and T8 are turned on by inputting a "low" signal to the data restoration line. Further, the switches T6, T9, T10 which are automatically turned on when the switches T7 and T8 are turned on.
Is included. The switches T9 and T10 in the figure are current mirror circuits. When all the switches of the data restoration block 14 are turned on, a differential signal (difference in signal level between the node ML and the node MR) appears on the nodes of the pair of MTJ elements 16c and 16d. "0" or "1" is determined according to the value of the differential signal. An amplifier / latch circuit (AMP & Latch) 18 connected to the nodes ML and MR is a circuit for amplifying and holding a differential signal. CMOSFET for holding data determined by the differential signal
(Complementary MOSFET) is used. The circuit configuration for holding the data is as shown in FIG. 3, and the two CMOSFETs 32a and 32b hold the data.

Switches T1, T2, T used in the data writing block 12 and the data restoring block 14
3, T4, T5, T6 and T7 use n-type MOSFETs. The switches T8, T9, T10 are p-type MOSFE
Use T.

Data is input to the register block 20 through a register input / output (Register I / Os) line. The data write block 12 and the data restore block 14 operate by inputting a signal to the data write line and the data restore line.

The operation of the register 10 will be described. During the circuit operation of the register 10, the data write line and the data restore line are "Low" and "High", respectively.
The data write block 12 is transmitted by transmitting the signal of
Then, the circuit operation of the data restoration block 14 is turned off. In this state, the register 10 is
Data writing block 12 and data restoring block 1
Signals are transmitted and received without activating 4. The signal includes a clock signal that is timed when operating register 10. The data stored in the register block 20 always appears on RO in the figure, but when DW is fixed to "low", both the DL and DR in the figure become "low" by the AND circuits 22a and 22b. Fixed, switch T
1, T2, T3 and T4 are turned off.

A "high" signal is sent to DW to write the data and switch T5 is turned on. At the same time, D
Either L or DR goes "high" depending on the data being written. For example, if the output signal of the register block 20 is “high”, DR becomes “high”. If the output signal of the register block 20 is "low", DL becomes "high".

The arrows in FIG. 1 indicate the MTJ elements 16a and 16b.
The magnetization direction of the fixed layer 30 is shown. The magnetization directions of the fixed layers 30 of the MTJ elements 16a and 16b connected via the switch T5 are opposite to each other. The data writing block 12 has true (true, “1”) and false (co
mplement, data of "0") is converted to MTJ elements 16a, 16
Write to pair b. For example, when DL is "high", the switches T1, T3 and T5 are turned on. Therefore, the current flows from the switch T1 to the left MTJ element 16a and the switch T1.
5, to the right MTJ element 16b and further to the switch T3. The direction of the magnetic field due to the current is the same as that of the magnetization of the fixed layer 30 in the left MTJ element 16a, and the right MJ element 16a is in the same direction.
The TJ element 16b is in the opposite direction. In this case, MT on the left
The magnetization directions of the fixed layer 30 and the free layer 26 of the J element 16a are the same, and the right MTJ element 16b is in the opposite direction.
When the output of the register block 20 is "low", the left M
"0" data is written in the TJ element 16a, and the right M
Data of "1" is written in the TJ element 16b. DR
Is high, the switches T2, T4 and T5 are turned on, and the combination of magnetizations is the reverse of the above. The data stored in the data write block 12 differs depending on whether DL is set to “high” or DR is set to “high”. As described above, the pair of MTJ elements 16a and 16b can easily rewrite data, and since the data is non-volatile, the data is saved even when the power is turned off.

Since the conventional MRAM has a matrix structure, the address of the lattice is addressed by the currents of the write word line and the free layer, and therefore it is necessary to provide a switch for switching easier addressing. However, in the write operation of the register of the present invention, it is not necessary to have the write word line because the structure of the storage element is not the structure in which the write word line and the bit line are arranged in a matrix like the MRAM.

In a normal MRAM including an MTJ element,
The memory array is configured in a matrix as described above, MTJ elements are arranged at the intersections, and M of the intersections selected by the vertical bit lines and the horizontal word lines are selected.
Since the data is written only in the TJ element, the current is passed through the write word line as well as the bit line. However, the MTJ elements 16a and 16b as shown in FIG. 1 are connected in pairs via the switch T5, and the magnetization directions of the fixed layer 30 are directed in opposite directions to each other as shown in FIG. Facing in the direction of. Therefore, the MTJ of the present invention
Since the elements 16a and 16b do not have the same structure as the memory array of the above MRAM, it is not necessary to select the elements to be written at the vertical and horizontal intersections. In addition, M in the conventional MRAM
Since the reversal of the magnetization direction of the free layer of the TJ element can be performed only by the current flowing in the bit line, the memory element of the register of the present invention has a configuration in which the write word line of the MTJ element of the conventional MRAM is omitted. Through the above write operation, the register transfers data to a memory having a True / Complement pair as a basic structure that saves data without consuming power.

To facilitate understanding of the operation principle, the fixed layer 30 of the MTJ elements 16a and 16b is shown in the data write block 12, and the resistance portion representing the resistance of the MTJ elements 16c and 16d is shown in the data restoration block 14. Figure 2
16a and 16c, or 16b and 16
d is an integral structure. Data restoration block 1
The pair of MTJ elements 16c and 16d of No. 4 is used as a resistor for the current mirror circuit (the switch T9 and the switch T10 portion) in the present invention.

To read the non-volatile data from register 10, the DW signal remains "low". DRS
The signal is switched to a high level initially and then to a low level. Switching from “high” to “low” turns on switches T7 and T8. Furthermore, the switches T6, T9, and T10 also operate, and the current mirror circuit (cu
rrent mirror circuit) is now available and switch T
Currents of the same value flow in 9 and T10.

A differential signal appears on the nodes ML and MR of the MTJ element 16c and 16d pair. The differential signals appearing on the nodes ML and MR are amplified and held by the amplifier / latch circuit 18. In other words, the nodes ML and MR
The data determined by the potential difference is amplified and held by the amplifier / latch circuit 18. The potentials of the nodes ML and MR are determined by the resistance values of the MTJ elements 16c and 16d. That is, it is determined by the data written in the MTJ elements 16a and 16b.

Data is held in the circuit of FIG. The amplified potential of the node ML appears at the node ML ′, and the amplified potential of the node MR appears at the node MR ′.
By turning on the n-type MOSFETs 38a and 38b, the potentials of the nodes ML 'and MR' appear at the nodes CL and CR, respectively. CMOSFET
2 are used, and if the node CR is “high”, the node CR holds “low”. On the contrary, node CL
Is high, the node CR holds low.

Since data is input to the register 10, D
The register block 20 takes in the data held in the amplifier / latch circuit 18 by the signal of RS. The above steps complete the data restoration operation. After this, DRS returns from "low" to "high" and the current mirror circuit is turned off.

Table 1 shows the signal state of each node and the memory state of the MTJ element in the above series of steps.

[0033]

[Table 1]

The MTJ element can be mounted in the latter half stage of the metal layer in the semiconductor manufacturing process used for the logic chip. Therefore, in comparison with other existing non-volatile memory devices such as flash memory, which requires completely separate transistor design in addition to logic circuit design, this MT
The manufacturing process of J memory device is much simpler and the cost is very low. According to the present invention, the nonvolatile memory element can be easily mounted on the conventional logic chip.

The nonvolatile memory element can be used in various ways from one latch register to a multi-bit register. Saving data in registers without consuming power is very helpful in returning to the operating environment before powering down. The non-volatile memory function of the logic chip with electrical modification also has a very wide range of applications. The function can also be achieved by flexibly changing the logical function.

Although the register, the data storing method and the data reading method of the present invention have been described above, the present invention is not limited to these. For example, MTJ
It is also possible to use a GMR (Giant Magnetoresistive) element instead of the element.

The present invention can be carried out in a mode in which various improvements, modifications and variations are added based on the knowledge of those skilled in the art without departing from the spirit of the present invention.

[0038]

According to the present invention, the logic chip is configured to include the MTJ element which is a non-volatile memory element, which can be easily designed and manufactured, and the cost can be reduced. Moreover, since a non-volatile storage element is used,
Data can be stored without power consumption by turning off the power.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a register according to the present invention.

FIG. 2 is a diagram showing a structure of an MTJ element.

FIG. 3 is a diagram of a circuit for holding data using a CMOSFET.

FIG. 4 is a circuit diagram used for a general register block.

[Explanation of symbols]

10: Register 12: Data writing block 14: Data restoration block 16a, 16b, 16c, 16d: MTJ element 18: Amp / Latch circuit (Amp and Latch) 20: Register block 22a, 22b: AND circuit 24a, 24b: NOT circuit 26: Free layer 28: Tunnel barrier 30: Fixed layer 32a, 32b: CMOSFET 34a, 34b: p-type MOSFET 36a, 36b, 38a, 38b: n-type MOSFET 40a, 40b: NAND circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshio Sunaga             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Hisadamu Miyatake             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Tsuneji Kitamura             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Hideo Asano             1 Kirihara, Fujisawa City, Kanagawa Japan             -M Fuji Co., Ltd. (72) Inventor Hiroaki Noda             1 Kirihara, Fujisawa City, Kanagawa Japan             -M Fuji Co., Ltd. (72) Inventor Hiroshi Umezaki             1 Kirihara, Fujisawa City, Kanagawa Japan             -M Fuji Co., Ltd. F-term (reference) 5E049 BA06 CB01                 5F083 BS27 FZ10

Claims (16)

[Claims] 1. A register block in which data is stored, a data write block including a non-volatile storage element for storing data output from the register block, and data stored in the data write block. A data recovery block to read, and a register containing the block. 2. The storage element includes a fixed layer, which is a ferromagnetic layer whose magnetization direction is fixed, and a free layer, which is a ferromagnetic layer whose magnetization direction can be changed. Register described in. 3. The two storage elements, wherein the fixed layer and the free layer of one storage element have the same magnetization direction, and the fixed layer and the free layer of the other storage element have different magnetization directions. The register according to Item 3 or 4. 4. The register according to claim 3, wherein the two storage elements are connected via a switch. 5. The register according to claim 4, wherein the magnetization directions of the fixed layers of the two storage elements are the directions of the switches or the directions opposite to each other. 6. The register according to claim 1, wherein the data write block includes two logic circuits to which the data output from the register block is input and which outputs a high signal or a low signal. 7. The register according to claim 6, comprising a plurality of switches to which outputs of the two logic circuits are input. 8. The register according to claim 7, wherein among the plurality of switches, the number of switches to which the output of one logic circuit is input is two. 9. The two switches to which the output of the one logic circuit is input are connected via the two storage elements and a switch connecting the two storage elements.
Register described in. 10. The register according to claim 3, further comprising a current mirror circuit that generates a differential signal generated by resistance values of the two storage elements in the data restoration block. 11. The register according to claim 10, including a circuit that amplifies and holds the differential signal. 12. The register according to claim 11, wherein a circuit that amplifies and holds the differential signal includes a CMOSFET for holding the differential signal. 13. The register according to claim 12, wherein the number of the CMOSFETs is two. 14. The storage element is an MTJ (Magnetic T).
The register according to any one of claims 1 to 13, which is an unnel junction element. 15. The method of storing data in a register according to claim 9, wherein the two logic circuits are selected from among the two logic circuits according to data output from the register block.
Outputting a high signal from one of the logic circuits, turning on two switches connected to the logic circuit outputting the high signal, and writing data to the two storage elements. A method of storing data, including the step of writing. 16. A method of reading data from a register according to claim 11, wherein the differential signal generated by the step of operating the current mirror circuit and the step of operating the current mirror circuit is amplified. And a step of holding the amplified differential signal, the method of reading data.