JP2003013280A - Laminated chip component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a laminated chip component of high connection reliability, provided with plating on the terminal, which has adequate wettability for plating on the terminal of an outer surface of a surface mounting component, and has connection reliability while controlling growth of whisker. SOLUTION: The laminated chip component comprises two plated layers of Sn-Bi eutectic alloy plating on the outermost surface of an external electrode terminal, and Sn-based alloy plating for the undercoat.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type component for soldering mounting.

[0002]

2. Description of the Related Art In recent years, high integration of mounting on a printed wiring board has been realized by increasing the density on one plane (miniaturization of components, narrowing pitch, etc.) and the use of three-dimensional chips and multilayer substrates. The method by originalization is being advanced. Currently, there are three types of surface mounting methods (lead insertion method, surface mounting method, and bare chip mounting method). Among them, the current mainstream is the method of mounting high density by miniaturizing components. Is.

On the other hand, recently, there is an increasing demand for eliminating Pb of the solder used for mounting these surface mount components. In other words, the solder does not contain Pb,
It is in a state of rapidly progressing toward so-called lead-free, and the demand extends to external electrodes on the surface of components. The external electrode is Sn, SnCu, S
Sn alloy compositions such as n-Bi are being determined, and among them, as lead-free plating for surface-mounted components, it is becoming common to use Ni plating for the base and pure Sn plating for the surface.

[0004]

The Sn plating is concerned about whisker growth, which is a stress migration, and the Sn plating is a metal that is easily oxidized by nature. Is known to do. The means to solve these at once is to alloy pure Sn, and it was thought that this would solve all of them. The most promising candidate is Sn-Bi alloy plating. In this alloy, the greater the amount of Bi, the more remarkable the improvement in wettability. But,
It has also been found that as the wettability is improved, a brittle compound layer is generated at the soldering boundary portion, and the connection reliability is significantly deteriorated. Although there is a problem of whiskers and wettability after going through such a process, the fact is that Sn plating has settled down.

Therefore, as described above, the object of the present invention is to provide a terminal which has good wettability as terminal plating on the outer surface of a surface-mounted component, suppresses whisker growth, and also has connection reliability. An object of the present invention is to provide a layered chip component having high connection reliability with plating.

[0006]

According to the laminated chip component of the present invention, it is possible to obtain a laminated chip component which is free from whiskers and excellent in wettability (solderability) while ensuring connection reliability. . As described above, the point of the configuration of the present invention is obtained by making the Sn-Bi alloy plating the outermost surface of the Sn-based alloy into a two-layer plated state.

That is, the present invention is a laminated chip component in which the outermost surface of the external electrode terminal is a Sn-Bi eutectic alloy plating and the underlayer is a two-layer plating composed of a Sn-based alloy plating.

The present invention also provides a three-layer plating in which the outermost surface of the external electrode terminal is Sn-Bi eutectic alloy plating, the underlayer is Sn-based alloy plating, and the underlayer is Sn plating. It is a laminated chip component.

Further, according to the present invention, the outermost surface of the external electrode terminal is Sn-Bi eutectic alloy plating, the underlayer is Sn alloy plating, the underlayer is Sn plating, and the underlayer is Ni plating. It is a multilayer chip component that is formed by four-layer plating.

The present invention is also a laminated chip component in which the thickness of the Sn-Bi eutectic alloy plating is 2 μm or less.

[0011]

EXAMPLE A laminated chip component according to an example of the present invention will be described below.

(Embodiment 1) A laminated chip component according to Embodiment 1 of the present invention will be described below. First, a binder resin (for example, PVB resin) is added to the insulating magnetic powder.
5 wt%, organic solvent (for example, ethylene glycol ether type) 60 wt% and the like are added and mixed to form a slurry. This slurry is used to form a long green sheet of an insulating magnetic material having a film thickness of 200 to 600 μm using a doctor blade method and cut into a predetermined size.

Then, an inner conductor was printed on the obtained green sheet with Ag paste in a predetermined pattern by a screen printing method, dried by heating, and the insulating magnetic slurry was printed with a magnetic layer by a screen printing method. , Dry by heating. Next, the internal conductor is printed in a predetermined pattern so as to be connected to the connection portion of the internal conductor, and dried by heating. In the same manner, the layered printing is repeated a required number of times to form a spiral coil of the internal conductor, and both ends of the formed coil are exposed to the outside.

A green sheet as an upper insulating magnetic layer is pressure-bonded to the laminated body printed in this manner by hot pressing to form an unfired laminated body. After debinding the unbaked chips in the air, they are integrally baked in the air to chamfer the chips.
Barrel polishing is performed so that the side surface of the chip is coated with a dip such as Ag paste by dipping so as to be connected to the internal conductors exposed to the outside of both ends of the coil, and dried at a predetermined temperature and time, The outer electrode terminals are formed by baking in an air atmosphere at a temperature.

Next, a nickel-plated layer by electrolytic plating is applied to the electrode terminals, and thereafter, as a comparative material, a 3216 size multilayer chip inductor having electrolytic Sn plating of 5 μm is obtained, and the other is immediately dried, then, Immediately Sn the electrolytic Sn plating 3.5μm
A 3216 size multilayer chip inductor obtained by performing -10 wt% Bi plating for 1.5 μm was obtained.

1) The 3216 multilayer chip inductor thus obtained was first subjected to whisker evaluation (N = 10) under the following conditions. As for the whisker evaluation conditions, the above laminated chip component was left in a constant temperature and constant humidity tank under conditions of 50 ° C. and 85% RH for 5000 hours. As a result, conventional electrolysis S
Whiskers of the n-plated product grew 150 μm, but Sn-
Only about 10 μm was observed for the bi-layer plated product of Bi.

2) The wettability was evaluated by a rapid heating method with a solder wettability tester. The test conditions are Sn-3.0Ag-0.
A 5Cu composition was used, which was immersed for 10 seconds at a temperature of 240 ° C. and an immersion speed of 2 mm / second, and immediately cooled. As a result of comparatively evaluating the wettability (zero cross time) at that time, it was found that the zero cross time of the product of the present invention was 2.0 seconds and that of the comparative material was 3.1 seconds, and the product of the present invention wets faster.

(Embodiment 2) A laminated chip component according to Embodiment 2 of the present invention will be described below. First, in the same manner as in Example 1, a nickel plating layer formed by electrolytic plating was first applied to the electrode terminals on the outer electrode terminals formed, and then two-layer plating was performed. The condition is that the total thickness of the two-layer plating is fixed at 5 μm, and Sn on the outermost surface of the external terminal is used.
-10wt% Bi plating 0.5, 1.0, 1.5, 2.
A 3216 size multilayer chip inductor having a ground layer of Sn plated thereon was performed for 0, 2.5 and 3.0 μm.

The 3216 multilayer chip inductor thus obtained was first subjected to whisker evaluation (N = 10) under the following conditions.

The whisker evaluation conditions were such that the above laminated chip parts were placed in a thermo-hygrostat at 50 ° C. and 85% RH for 5000.
It was left for Hr. As a result, the conventional electrolytic Sn-plated product
Whiskers grew to 150 μm, but for Sn-Bi two-layer plated products, only those having a thickness of about 10 μm were observed.

Next, the wettability was evaluated by a rapid heating method with a solder wettability tester. The test conditions are Sn-3.0Ag- manufactured by Senju Metal Co., Ltd. as a solder paste.
0.5Cu composition, temperature 240 ℃, immersion speed 2mm
Immersion was performed for 10 seconds / second, followed by immediate cooling.

As a result of evaluating the wettability (zero cross time) at that time, the Sn-10 wt% Bi plating thickness was set to 0.
5, 1.0, 1.5, 2.0, 2.5, 3.0 μm and Sn-
Zero crossing time is 3. with increasing Bi plating thickness.
1 second, 2.0 seconds, 1.9 seconds, 2.0 seconds, 1.8 seconds, 1.8 seconds and even if the outer surface is 0.5 μm, it can be wetted quickly by the Sn-Bi double-layer structure. all right. However, as a result of analyzing the composition around the final solidified portion of the solder by EPMA for each sample of the cross-sectional structure of the soldered state after the wettability test, the Sn-Bi alloy plated layer was 2.5.
It was found that the precipitation of only Bi alone was observed together with the Sn-Bi eutectic composition only for those having a thickness of 3.0 μm, and the reliability at high temperature was poor. Therefore, Sn on the outermost surface
-By setting the Bi eutectic plating layer to at least 2.0 μm or less, highly reliable soldering can be obtained.

(Embodiment 3) A laminated chip component according to Embodiment 3 of the present invention will be described below. First, in the same manner as in Examples 1 and 2, the outer electrode terminal was formed, first, the electrode terminal was subjected to the nickel plating layer by electrolytic plating, and then the two-layer plating was performed. The condition was that the total thickness of the two-layer plating was fixed at 5 μm, Sn-Bi eutectic plating on the outermost surface of the external terminals was performed at 1.5 μm, and the underlying plating was Ni and Sn plated to obtain a 3216 size multilayer chip inductor. . 3 thus obtained
First, whisker evaluation (N = 10) was performed on the 216 layered chip inductor under the following conditions.

The whisker evaluation conditions were such that the above laminated chip parts were placed in a thermo-hygrostat at 50 ° C. and 85% RH for 5000.
It was left for Hr. As a result, in all cases, only those having a thickness of about 10 μm were observed. Next, regarding wettability evaluation,
It was performed by a rapid heating method with a solder wettability tester. The test conditions are Sn-3.
It was of a composition of 0Ag-0.5Cu and immersed at a temperature of 240 ° C. for 2 seconds at an immersion speed of 2 mm / sec for 10 seconds and then immediately cooled.

As a result of evaluating the wettability (zero crossing time) at that time, as for the base Ni, 2.6 seconds was compared with the base Sn.
It was 1.9 seconds, and it was found that it was fairly wet. Therefore, Sn in the outermost surface Sn-Bi eutectic plating layer
Only in the case of undercoating, highly reliable soldering becomes possible. It is considered that the underlayer may be a Sn alloy, but it is desirable that Cu or Ag other than Bi is used as the alloy element.

[0026]

As described above, according to the present invention, it is possible to provide a highly reliable laminated chip component free from defects such as ion migration growth and whisker growth and having good solder wettability. it can. Also, as a result,
Since the product yield is remarkably increased and the process is simple, the cost can be reduced.

Claims (4)

[Claims] 1. A multilayer chip component, wherein the outermost surface of an external electrode terminal is Sn-Bi eutectic alloy plating, and the underlayer is a two-layer plating composed of Sn-based alloy plating. 2. The outermost surface of the external electrode terminal is Sn-Bi eutectic alloy plating, and the base thereof is Sn-based alloy plating,
Furthermore, a multilayer chip component, characterized in that the base thereof is a three-layer plating having Sn plating. 3. The outermost surface of the external electrode terminal is Sn-Bi eutectic alloy plating, and the base thereof is Sn-based alloy plating,
A multilayer chip component, wherein the base is Sn plating and the base is 4-layer plating composed of Ni plating. 4. The multilayer chip component according to claim 1, wherein the thickness of the Sn—Bi eutectic alloy plating is 2 μm or less.