JP2003008542A - Orthogonal frequency-division signal demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an orthogonal frequency-division signal demodulator that can eliminate distortion even when a digital signal supplied from an analog/ digital converter circuit has the distortion. SOLUTION: First an amplitude detection circuit 12 detects the amplitude of an IF signal amplified by a voltage-controlled amplifier means 4 on the basis of a digital signal supplied from the analog/digital converter circuit 5. Then an amplitude control signal generating circuit 13 detects a difference between the amplitude and a prescribed amplitude and gives a DC voltage based on the difference to a VCA(Voltage Controlled Amplifier) circuit 4. The VCA circuit 4 amplifies the IF signal while varying the amplification factor on the basis of the received DC voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to orthogonal frequency division (OFDM).
xing) OFD applied to digital broadcasting, etc.
The present invention relates to an M demodulator.

[0002]

2. Description of the Related Art As a terrestrial digital broadcasting system, for example, a terrestrial digital radio broadcasting, a terrestrial digital television broadcasting, etc., a large number of AC carriers are used, and each carrier is phase modulated (PSK) or quadrature amplitude modulated (QAM). Orthogonal Frequency Division (OFDM) system which modulates a signal by the () system is proposed. The reason why the OFDM method is proposed is that the OFDM signal is less susceptible to multipath. For example, when the terrestrial digital broadcast is received in an area with many buildings such as an urban area, or when the mobile receiver receives the terrestrial digital broadcast, the OF
DM signals are less susceptible to multipath.

The modulation circuit and the demodulation circuit in the digital broadcasting have recently been actively implemented by digital circuits from the viewpoint of sophistication of functions, complexity, and improvement of stability. In such applications, especially in receivers,
It is necessary to convert the received modulated signal from an analog signal to a digital signal.

An analog-digital conversion circuit (hereinafter referred to as an A / D conversion circuit) is used to convert an analog signal into a digital signal. In the A / D conversion circuit, the minimum level and the maximum level of the supplied signal are defined in advance, and the difference between the minimum level and the maximum level is called the dynamic range. The A / D conversion circuit
The supplied signal is a digital signal within this dynamic range.

[0005]

By the way, when the amplitude of the signal supplied to the A / D conversion circuit is too large or too small, it becomes difficult for the demodulation device to accurately demodulate the received signal. .

For example, when the signal is modulated by the QAM method, the transmitting side maps the signal point to a predetermined position. At this time, when the amplitude of the signal supplied to the A / D conversion circuit is excessive, the intervals between the signal points are as shown in FIG. 7 (A) on the transmitting side shown in FIG. 7 (B). The demodulator cannot accurately demodulate the signal because it becomes large compared to the assumed constellation. On the other hand, when the amplitude of the signal supplied to the A / D conversion circuit is too small, the interval between the signal points is assumed to be the same as that shown in FIG. 7C on the transmission side shown in FIG. 7B. It becomes smaller than the constellation used, and the demodulation device cannot accurately demodulate the signal.

Furthermore, when the amplitude of the signal supplied to the A / D conversion circuit is excessive, the signal supplied by the A / D conversion circuit is clipped and distortion occurs. OF
The DM signal is a signal in which a large number of carrier waves are orthogonal to each other. However, when the clipping occurs, the energy of each carrier wave leaks to other carrier waves and the orthogonality is impaired. As a result, O
The quality of the FDM signal deteriorates, and a transmission error occurs. Further, when the amplitude of the signal supplied to the A / D conversion circuit is too small, the quantization noise becomes large. At this time as well, the quality of the OFDM signal deteriorates and a transmission error occurs.

Therefore, as shown in FIG. 8, an automatic level control (Automatic Level Co) is provided before the A / D conversion circuit 110.
The analog signal supplied to the A / D conversion circuit 110 has a constant amplitude at all times by including the control circuit 111. The ALC circuit 111 is the level detection circuit 1
12 and a voltage controlled amplification (VCA) circuit 113. The level detection circuit 112 detects the amplitude of the signal supplied from the VCA circuit 113, detects a difference from a predetermined amplitude, and supplies this difference to the VCA circuit 113 as a DC voltage. Then, the VCA circuit 113 controls the amplification factor on the basis of this DC voltage, and the A / D conversion circuit 112.
The level of the signal supplied to is always constant.

However, the ALC circuit 111 is
Although the amplitude of the signal before being supplied to the D conversion circuit 110 can be adjusted, when the signal supplied from the A / D conversion circuit 110 is distorted, this distortion cannot be eliminated. Therefore, for example, the A / D conversion circuit 110 has an unstable conversion characteristic, and therefore the A / D conversion circuit 110
When the signal supplied from the conversion circuit 110 is distorted, it becomes difficult for the demodulation device to accurately demodulate the signal.

The present invention has been devised in view of such a conventional situation, and provides an orthogonal frequency division signal demodulation device capable of eliminating distortion of a signal supplied from an A / D conversion circuit. The purpose is to do.

[0011]

A receiving apparatus according to the present invention is an orthogonal frequency division multiplex (OFDM).
A demodulation device for demodulating an OFDM signal modulated by an ancy division multiprexing) system, comprising:
Voltage control amplification means for amplifying the intermediate frequency signal obtained by converting the frequency of the DM signal by an amplification factor based on the amplitude control signal, and converting the intermediate frequency signal amplified by the voltage control amplification means from an analog signal to a digital signal Analog-to-digital conversion means, amplitude detection means for detecting the amplitude of the intermediate frequency signal amplified by the voltage-controlled amplification means based on the digital signal supplied from the analog-digital conversion means, and detection by the amplitude detection means. An amplitude control signal generation means for detecting the difference between the amplitude of the generated intermediate frequency signal and a predetermined amplitude, generating an amplitude control signal based on this difference, and providing the generated amplitude control signal to the voltage control amplification means. .

In the receiving apparatus according to the present invention, first, the amplitude detection circuit detects the amplitude of the intermediate frequency signal amplified by the voltage control amplification means based on the digital signal supplied from the analog-digital conversion means. Next, the control signal supply means detects the difference between the amplitude and the predetermined amplitude,
The control signal generated based on this difference is supplied to the voltage control amplification means. Then, the voltage control amplification means controls the amplification factor of the intermediate frequency signal supplied to the analog-digital conversion circuit based on the supplied control signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A demodulator to which the present invention is applied will be described in detail below with reference to the drawings.

First Embodiment First, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. Here, a demodulation device (OFDM demodulation device) for digital television broadcasting by the OFDM system will be described. FIG. 1 is a block diagram of the OFDM demodulator.

As shown in FIG. 1, the OFDM demodulator 1
Is an antenna 2, a tuner 3, and a voltage controlled amplifier (VC
A) circuit 4 and analog-digital (A / D) conversion circuit 5
, Digital quadrature demodulation circuit 6, and FFT (Fast Fourier
Transform) operation circuit 7, window synchronization circuit 8,
It includes an equalizer 9, a demapping circuit 10, an error correction circuit 11, an amplitude detection circuit 12, and an amplitude control signal generation circuit 13.

A broadcast wave of digital television broadcast broadcast from a broadcasting station is received by an antenna 2 of an OFDM demodulator 1 and supplied to a tuner 3 as a radio frequency (RF) signal. The RF signal received by the antenna 2 is frequency-converted into an intermediate frequency (IF) signal by the tuner 3 and supplied to the VCA circuit 4.

The VCA circuit 4 amplifies the IF signal supplied from the tuner 3 and supplies it to the A / D conversion circuit 5. V
The CA circuit 4 amplifies the IF signal while controlling the amplification factor according to the DC voltage supplied from the power supply circuit 13.

The A / D conversion circuit 5 converts the IF signal supplied from the VCA circuit 4 into a digital signal and supplies the digital signal to the digital quadrature demodulation circuit 6. The digital signal supplied from the A / D conversion circuit 5 is the amplitude detection circuit 12 described later.
Is also supplied to.

The digital quadrature demodulation circuit 6 quadrature demodulates the digitized IF signal using a carrier signal of a predetermined frequency (carrier frequency), and baseband OFD.
Supply the M signal. The baseband OFDM signal supplied from the digital quadrature demodulation circuit 6 is a so-called time domain signal before FFT calculation. Therefore, the baseband signal after digital quadrature demodulation and before FFT operation is called an OFDM time domain signal. As a result of quadrature demodulation, this OFDM time signal region becomes a composite signal including a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The OFDM time domain signal supplied by the digital quadrature demodulation circuit 6 is supplied to the FFT operation circuit 7 and the window synchronization circuit 8.

The FFT calculation circuit 7 performs FFT calculation on the OFDM time domain signal and extracts and supplies the data orthogonally modulated to each subcarrier. The signal supplied from the FFT operation circuit 7 is a so-called frequency domain signal after being FFT'd. From this, in the following, F
The signal after the FT calculation is called an OFDM frequency domain signal.

The FFT operation circuit 7 extracts a signal within a range of effective symbol length (for example, 2048 samples) from one OFDM symbol, that is, excludes a range corresponding to the guard interval from one OFDM symbol, and extracts the effective symbol length. Perform an FFT operation on the range OFDM time domain signal. Specifically, the calculation start position is O
It is any position from the boundary of the FDM symbol to the end position of the guard interval. This calculation range is called an FFT window.

In this way, the OFDM frequency domain signal supplied from the FFT operation circuit 7 is, similarly to the OFDM time domain signal, a decompression composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). It is an elementary signal. This composite signal is, for example, 16QAM or 64QAM.
It is a signal that is quadrature amplitude modulated by the AM method or the like. OFDM
The frequency domain signal is supplied to the equalizer 9.

The window synchronization circuit 8 receives the supplied OF.
By extending the DM time domain signal by the effective symbol period, the correlation between the guard interval portion and the signal which is the copy source of this guard interval is obtained, and the boundary position of the OFDM symbol is calculated based on this portion having high correlation, A window synchronization signal _Wsync indicating the boundary position is generated. The FFT window synchronization circuit 8 supplies the generated window synchronization signal W _sync to the FFT operation circuit 7.

The equalizer 9 carries out phase equalization and amplitude equalization of the OFDM frequency domain signal using the scattered pilot signal (SP signal). The OFDM frequency domain signal subjected to phase equalization and amplitude equalization is supplied to the demapping circuit 10.

The demapping circuit 10 demaps the OFDM frequency domain signal that has been equalized and phase equalized by the equalizer 9 according to, for example, the 16QAM method to decode the data. The data decoded by the demapping circuit 10 is supplied to the error correction circuit 11.

The error correction circuit 11 performs error correction on the supplied data using, for example, Viterbi decoding or Reed-Solomon code. The error-corrected data is supplied to, for example, an MPEG decoding circuit in the subsequent stage.

The amplitude detection circuit 12 detects the amplitude of the IF signal amplified by the VCA circuit 4 based on the digital signal supplied from the A / D conversion circuit 5, and outputs the detection result to the amplitude control signal generation circuit. Supply to 13.

The amplitude control signal generation circuit 13 detects the difference between the amplitude of the IF signal detected by the amplitude detection circuit 12 and a predetermined amplitude, converts this difference into a DC voltage, and VC
Supply to the A circuit 4. The DC voltage serves as an amplitude control signal that controls the amplification factor of the VCA circuit.

Next, the VCA circuit 4 and the amplitude detection circuit 1
2 and the method of adjusting the amplitude of the IF signal supplied to the A / D conversion circuit 5 by the amplitude control signal generation circuit 13 will be described.

In this embodiment, as shown in FIG. 2, the amplitude detection circuit 12 includes a square circuit 21 and a low-pass filter 22, and the amplitude control signal generation circuit 13 includes a subtraction circuit 23 and a cumulative addition circuit. 24 and a digital-analog (D / A) conversion circuit 25.

The operations of the amplitude detection circuit 12 and the amplitude control signal generation circuit 13 and the operation of the VCA circuit 4 are as described below.

In the amplitude detection circuit 12, first, the digital signal supplied from the A / D conversion circuit 5 is supplied to the squaring circuit 21. The squaring circuit 21 squares the signal supplied from the A / D conversion circuit 5. The signal squared by the squaring circuit 21 is supplied to the low-pass filter 22.

Next, the low pass filter 22 averages the signals supplied from the squaring circuit 21. The signal averaged by the low-pass filter 22 is the A / D conversion circuit 5
Represents the effective value of the signal passed through. The signal averaged by the low-pass filter 22 is supplied to the amplitude control signal generation circuit 13.

Here, in order to detect the amplitude, A
Although the digital signal supplied from the A / D conversion circuit 5 is squared, in order to obtain the amplitude, the digital signal supplied from the A / D conversion circuit 5 is multiplied by 2n (where n is a natural number) and then the low-pass signal is passed. It may be averaged by a filter.
The amplitude can also be obtained by taking the absolute value of the digital signal supplied from the A / D conversion circuit 5 and then averaging it by a low-pass filter.

In the amplitude control signal generation circuit 13, first, the subtraction circuit 23 obtains the difference X-Y between the amplitude X detected by the amplitude detection circuit 12 and the predetermined amplitude Y. The subtraction circuit 23 supplies a signal based on the difference XY to the cumulative addition circuit 24.

Next, the accumulative addition circuit 24 changes the subtraction circuit 23.
The difference X-Y is cumulatively added based on the signal supplied from. The cumulative addition circuit 24 supplies a signal based on the result of cumulative addition to the D / A conversion circuit 25.

Next, the D / A conversion circuit 25 converts the signal supplied from the cumulative addition circuit 24 into a DC voltage. D /
The A conversion circuit 25 supplies this DC voltage to the VCA circuit 4.

The VCA circuit 4 amplifies the IF signal supplied from the tuner 3 while controlling the amplification factor based on the DC voltage supplied from the amplitude control signal generation circuit 13, and the A / D conversion circuit 5 Supply to. In detail, VC
The A circuit 4 has a terminal to which the IF signal supplied from the tuner 3 is input and a control terminal to which the DC voltage supplied from the amplitude control signal generation circuit 13 is input. VC
The A circuit 4 amplifies the IF signal while controlling the amplification factor according to the DC voltage supplied from the control terminal so that the distortion of the digital signal supplied from the A / D conversion circuit 5 is eliminated. ing.

As described above, O to which the present invention is applied
The FDM demodulator 1 determines the amplification factor of the VCA circuit 4 based on the digital signal supplied from the A / D conversion circuit 5. Therefore, even when the signal supplied from the A / D conversion circuit 5 is distorted due to variations in the gain of the A / D conversion circuit 5, this distortion can be eliminated, and The conversion characteristics of the D conversion circuit 5 can be stabilized.

Further, the OFDM demodulation device 1 to which the present invention is applied feeds back the amplitude error to the VCA circuit 4 provided in the preceding stage of the A / D conversion circuit 5, thereby performing A / D conversion.
Since the distortion of the signal supplied from the conversion circuit 5 is eliminated, an OFDM signal having a wide dynamic range is
It is possible to eliminate the distortion that occurs when the D / D conversion is performed.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG.

The OFDM demodulation device described in the present embodiment is the same as the OFDM demodulation device 1 described in the first embodiment except for the amplitude control signal generation circuit 30, and therefore the description thereof will be used. . Here, the amplitude control signal generation circuit 30 will be described.

As shown in FIG. 3, the amplitude control signal generation circuit 30 includes a subtraction circuit 31, a cumulative addition circuit 32, and a pulse width modulation (PWM) circuit 33.
And a low pass filter 34.

The operation of the amplitude control signal generating circuit 30 and the operation of the VCA circuit 4 described above are as described below.

In the amplitude control signal generation circuit 30, the signal detected by the amplitude detection circuit 12 is first subtracted by the subtraction circuit 31.
Is supplied to.

The subtraction circuit 31 obtains a difference X-Y between the amplitude X detected by the amplitude detection circuit 12 and a predetermined amplitude Y. The subtraction circuit 31 supplies a signal based on the difference XY to the cumulative addition circuit 32.

Next, the cumulative addition circuit 32 is added to the subtraction circuit 31.
The difference X-Y is cumulatively added based on the signal supplied from. The cumulative addition circuit 32 supplies a signal based on the result of this cumulative addition to the PWM circuit 33.

The PWM circuit 33 generates a pulse duty signal based on the signal supplied from the cumulative addition circuit 32. The signal generated by the PWM circuit 33 is supplied to the low pass filter 34.

The low pass filter 34 includes a PWM circuit 33.
Averaging the signals provided by. Low pass filter 3
4 converts the averaged signal into a DC voltage to convert it to VCA.
Supply to the circuit 4.

Then, the VCA circuit 4 amplifies the IF signal supplied from the tuner 3 and controls the amplification factor based on the DC voltage supplied from the amplitude control signal generation circuit 30 to amplify the IF signal. Supply to. The VCA circuit 4 is
Depending on the DC voltage supplied from this control terminal, the A / D
The IF signal is amplified while controlling the amplification factor so that the distortion of the digital signal supplied from the conversion circuit 5 is eliminated.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG.

The OFDM demodulation device described in this embodiment is the same as the OFDM demodulation device 1 described in the first embodiment except for the amplitude control signal generation circuit 40, and therefore the description thereof is used. . Here, the amplitude control signal generation circuit 40 will be described.

As shown in FIG. 4, the amplitude control signal generation circuit 40 includes a digital comparison circuit 41 and a charge / discharge circuit 42.

The digital comparison circuit 41 is the amplitude detection circuit 1
The amplitude X supplied from 2 is compared with a predetermined amplitude Y. The digital comparison circuit 41 includes a first port 43 and a second port 43.
Port 44 of the. The first port 43 is X
When> Y, a flag is output. The second port 44 also outputs a flag when X <Y. When X = Y, neither port outputs a flag.

The charging / discharging circuit 42 includes a charging buffer 50.
A discharge buffer 51, first and second resistors 52,
53, a capacitor 54, and an input power supply 55. The charging buffer 50 and the discharging buffer 5
Reference numeral 1 is a so-called three-state buffer. The charging buffer 50 has an input connected to the input power supply 55, an output connected to the capacitor 54 via the first resistor 52, and a control input connected to the second port 44. When the flag from the second port 44 is input to the charging buffer 50, the capacitor 54 and the power supply 55 are connected via the first resistor 52. The discharge buffer 51 has an input grounded and an output second
Is connected to the capacitor 54 via the resistor 53, and the control input is connected to the first port 43. When the flag from the first port 43 is input to the discharging buffer 51, the capacitor 5 is connected via the second resistor 53.
4 is grounded.

The operations of the amplitude control signal generation circuit 40 and the VCA circuit 4 described above are as described below.

First, the digital comparison circuit 41 compares the amplitude X supplied from the amplitude detection circuit 12 with a predetermined amplitude Y.

Here, when X> Y, the first port 43 outputs a flag, and the flag is input to the control input of the discharge buffer 51. At this time, the second port 4
No. 4 outputs no flag, and the charging buffer 50 has high impedance. That is, the capacitor 54 is grounded via the second resistor 53. Therefore, the capacitor 5
The time constant determined by 4 and the second resistor 53 reduces the voltage stored in the capacitor 54. That is, the capacitor 54 is discharged. When the voltage accumulated in the capacitor 54 decreases, the DC voltage supplied from the charging / discharging circuit 42 to the VCA circuit 4 decreases.

On the other hand, when X <Y, the second port 44 outputs a flag, and the flag is input to the control input of the charging buffer 50. At this time, the first port 43
Does not output a flag, and the discharge buffer 51 has a high impedance. That is, the capacitor 54 is connected to the input power supply 55 via the first resistor 52. Therefore, the voltage is supplied from the input power supply 55 to the capacitor 54 via the first resistor 52, and the voltage accumulated in the capacitor 54 increases. That is, the capacitor 5
4 is charged. When the voltage accumulated in the capacitor 54 increases, the DC voltage supplied from the charge / discharge circuit 42 to the VCA circuit 4 increases.

The VCA circuit 4 amplifies the IF signal supplied from the tuner 3 while controlling the amplification factor based on the DC voltage supplied from the amplitude control signal generation circuit 40, and the A / D conversion circuit 5 Supply to. The VCA circuit 4 is
The IF signal is amplified while controlling the amplification factor according to the DC voltage supplied from the control terminal so that the distortion of the digital signal supplied from the A / D conversion circuit 5 is eliminated.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described with reference to FIG. OFDM described in the present embodiment
In the demodulator, parts other than the amplitude control signal generation circuit 60 are
Since it is the same as the OFDM demodulation device 1 described in the first embodiment, the description thereof will be applied. Here, the amplitude control signal generation circuit 60 will be described.

As shown in FIG. 5, the amplitude control signal generation circuit 60 includes a digital comparison circuit 61 and a charging / discharging circuit 62.

The digital comparison circuit 61 includes the amplitude detecting means 1
The amplitude X supplied from 2 is compared with a predetermined amplitude Y. The digital comparison circuit 61 includes a first port 63 and a second port 63.
Port 64 of the. The first port 63 is X
When = Y, a flag is output. Further, the second port 64 outputs a flag when X <Y. When X> Y, neither port outputs a flag.

The charging circuit 62 includes a buffer 70, a resistor 71, and a capacitor 72. Buffer 70
Is a so-called three-state buffer, which has a second input
, The output is connected to the capacitor 72 via the resistor 71, and the control input is connected to the first port 63. The buffer 70 becomes high impedance when a flag is input from the first port 63.

The operations of the amplitude control signal generation circuit 60 and the VCA circuit 4 described above are as described below.

First, the digital comparison circuit 61 compares the amplitude X supplied from the amplitude detection circuit 12 with a predetermined amplitude Y.

Here, when X> Y, neither the first port 63 nor the second port 64 outputs a flag. Since the flag is not output from the first port 63, the buffer 70 does not have high impedance.
Further, no voltage is supplied from the second port 64. Therefore, the voltage stored in the capacitor 72 decreases due to the time constant determined by the capacitor 72 and the resistor 71. That is, the capacitor 72 is discharged. When the voltage stored in the capacitor 72 decreases, the DC voltage supplied from the charge / discharge circuit 62 to the VCA circuit 4 decreases.

On the other hand, when X <Y, the second port 64 outputs a flag. Therefore, the buffer 70
The amount of voltage supplied from the capacitor 72 increases, the voltage is supplied to the capacitor 72 via the resistor 71, and the voltage accumulated in the capacitor 72 increases. That is, the capacitor 72
Is charged. When the voltage accumulated in the capacitor 72 increases, the DC voltage supplied from the charge / discharge circuit 62 to the VCA circuit 4 increases.

When X = Y, the first port 63 outputs a flag to bring the buffer 70 into a high impedance state. Since the buffer 70 has high impedance, the amount of voltage stored in the capacitor 72 does not increase or decrease. Therefore, the DC voltage supplied to the VCA circuit 4 is maintained.

The VCA circuit 4 amplifies the IF signal supplied from the tuner 3 while controlling the amplification factor based on the DC voltage supplied from the amplitude control signal generation circuit 60, and the A / D conversion circuit 5 Supply to. The VCA circuit 4 is
The IF signal is amplified while controlling the amplification factor according to the voltage input from the control terminal so that the distortion of the digital signal supplied from the A / D conversion circuit 5 is eliminated.

Fifth Embodiment Next, a fifth embodiment of the present invention will be described with reference to FIG.

The OFDM demodulation device described in the present embodiment is the same as the OFDM demodulation device 1 described in the first embodiment except for the amplitude control signal generation circuit 80, and therefore the description will be applied. . Here, the amplitude control signal generation circuit 80 will be described.

As shown in FIG. 6, the amplitude control signal generation circuit 80 includes a digital comparison circuit 81 and a charge / discharge circuit 82.

The digital comparison circuit 81 includes the amplitude detecting means 1
The amplitude X supplied from 2 is compared with a predetermined amplitude Y. The digital comparison circuit 81 includes the first to fourth ports 83.
~ 86. The first port 83 has XY> k
When (k is a threshold value, where k> 0), a flag is output. The second port 84 has k ≧ X−Y>
When it is 0, the flag is output. Third port 85
Outputs a flag when 0> X−Y ≧ −k.
The fourth port 86 outputs a flag when -k> XY. When XY = 0, neither port outputs a flag.

The charging / discharging circuit 82 has first and second charging buffers 90 and 91, first and second discharging buffers 92 and 93, first to fourth resistors 94 to 97, and an input. The power source 98 and the capacitor 99 are provided. The first and second charging buffers 90 and 91 and the first and second discharging buffers 92 and 93 are so-called three-state buffers. The first charging buffer 90 has an input connected to an input power supply 98 and an output connected to a first resistor 94.
Is connected to the capacitor 99 via a control input, and the control input is connected to the fourth port 86. The second charging buffer 91 has an input connected to the input power supply 98, an output connected to the capacitor 99 via the second resistor 95, and a control input connected to the third port 85. ing. First
The discharging buffer 92 has an input grounded, an output connected to the capacitor 99 through the third resistor 96, and a control input connected to the second port 84. Second
The discharging buffer 93 has an input grounded, an output connected to the capacitor 99 through the fourth resistor 97, and a control input connected to the first port 83.

The operations of the amplitude control signal generation circuit 80 and the VCA circuit 4 described above are as described below.

First, the digital comparison circuit 81 compares the amplitude X supplied from the amplitude detection circuit 12 with a predetermined amplitude Y.

Here, when XY> k, the first
Port 83 outputs the flag, and the flag is input to the second discharge buffer 93. At this time, none of the second to fourth ports 84 to 86 outputs a flag, and the first and second charging buffers 90 and 91 and the first discharging buffer 92 have high impedance. That is, the capacitor 99 is grounded via the fourth resistor 97. Therefore, the time constant determined by the capacitor 99 and the fourth resistor 97 reduces the voltage stored in the capacitor 99. That is, the capacitor 99 is discharged. When the voltage stored in the capacitor 99 decreases, the DC voltage supplied from the charging / discharging circuit 82 to the VCA circuit 4 decreases.

When k ≧ X−Y> 0, the second port 84 outputs a flag and the flag is input to the first discharge buffer 92. At this time, the first, third,
None of the fourth ports 83, 85, 86 outputs a flag, and the first and second charging buffers 90, 91, second
Each of the discharge buffers 93 has a high impedance. That is, the capacitor 99 is grounded via the third resistor 96. Therefore, the time constant determined by the capacitor 99 and the third resistor 96 reduces the voltage stored in the capacitor 99. That is, the capacitor 99
Discharges. When the voltage stored in the capacitor 99 decreases, the DC voltage supplied from the charging / discharging circuit 82 to the VCA circuit 4 decreases.

At this time, the voltage discharged from the capacitor 99 is larger when the capacitor 99 is grounded through the fourth resistor 97 than when it is grounded through the third resistor 96. Is set.

On the other hand, when 0> X−Y ≧ −k,
The third port 85 outputs the flag, and the flag is input to the second charging buffer 91. At this time, none of the first, second, and fourth ports 83, 84, 86 outputs a flag, and the first charging buffer 90 and the first and second discharging buffers 92, 93 are high, respectively. It becomes impedance. That is, the capacitor 99 has the second resistor 9
It connects with the power supply 98 for an input through 5. Therefore, the power supply for input 98 is connected to the capacitor 9 via the second resistor 95.
9 is supplied with voltage, and the voltage stored in the capacitor 99 increases. That is, the capacitor 99 is charged. When the voltage accumulated in the capacitor 99 increases, the DC voltage supplied from the charge / discharge circuit 82 to the VCA circuit 4 increases.

When XY <-k, the fourth
Port 86 outputs the flag, and the flag is input to the first charging buffer 90. At this time, none of the first to third ports 83 to 85 outputs a flag, and the second charging buffer 91, the first discharging buffer 92 and the second
Each of the discharge buffers 93 has a high impedance. That is, the capacitor 99 has the first resistor 94.
The input power source 98 is connected via. Therefore, the first
From the input power source 98 via the resistor 94 of
Is supplied to the capacitor 99, and the voltage accumulated in the capacitor 99 from the input power source 98 increases. That is, the capacitor 99 is charged. When the voltage accumulated in the capacitor 99 increases, the charging / discharging circuit 82 moves to the VCA circuit 4
The DC voltage supplied to it increases.

At this time, the voltage charged in the capacitor 99 is the voltage supplied to the capacitor 99 via the resistor 95.
8 is set to be larger when connected to the input power supply 98 via the resistor 94 than when connected to the input power supply 8.

The VCA circuit 4 amplifies the IF signal supplied from the tuner 3 while controlling the amplification factor based on the DC voltage supplied from the amplitude control signal generation circuit 80, and amplifies the IF signal. Supply to. The VCA circuit 4 is
The IF signal is amplified while controlling the amplification factor according to the DC voltage supplied from the control terminal so that the distortion of the digital signal output from the A / D conversion circuit 5 is eliminated.

In the charging / discharging circuit 82, the voltage discharged from the capacitor 99 is grounded via the fourth resistor 97 as compared with when the capacitor 99 is grounded via the third resistor 96. It is set to be more frequent when. Further, in the charge / discharge circuit 82, the voltage charged in the capacitor 99 is
It is set so that the number when connected to the input power source 98 via the resistor 94 is larger than that when connected to the input power source 98 via the resistor 5.

As a method of setting the charging / discharging circuit 82 as described above, for example, the first to fourth resistors 94 to 97 are used.
There is a method of changing the resistance value of each. The amount of voltage discharged from the capacitor 99 is the third
In order to set more resistance when grounded through the fourth resistor 97 than when grounded through the resistor 96, the resistance value of the third resistor 96 is set to the fourth resistance. 97
It should be smaller than the resistance value of. Also, the capacitor 9
In order to set the amount of voltage charged in 9 to be larger when the capacitor 99 is connected to the input power supply 98 than when the capacitor 99 is connected to the input power supply 98, The resistance value of the first resistor 94 may be smaller than the resistance value of the second resistor 95.

The amplitude control signal generation circuit 80 described above
Has a threshold value k set in the digital comparison circuit 81. By utilizing this threshold value k, the difference between X and Y is divided into stages, and a flag is output in accordance with each stage. The amount of voltage charged in the capacitor 99 or the amount of voltage discharged from the capacitor 99 is changed stepwise.
In the amplitude control signal generation circuit 80, the difference between XY is greater than k, greater than 0 and less than or equal to 0, 0, greater than or equal to -k and less than 0,
It is divided into 5 stages of less than -k. Here, when XY> k, a flag is output from the first port 83 and the discharge amount from the capacitor 99 is set to a predetermined amount. Further, when k ≧ X−Y> 0, a flag is output from the second port 84 so that the amount of discharge from the capacitor 99 is set to be smaller than that when XY> k. Furthermore, when -k <XY <0, a flag is output from the third port 85 so that the charge amount of the capacitor 99 is set to a predetermined amount. Furthermore, when X−Y ≦ −k, a flag is output from the fourth port 86 so that the charge amount of the capacitor 99 is −k <X−.
The number is set to be larger than that when Y <0.
When XY = 0, no flag is output from any port, and the capacitor 99 is neither charged nor discharged.

That is, the OFDM demodulation device provided with the amplitude control signal generation circuit 80 changes the amount of charge to the capacitor 99 and the amount of discharge from the capacitor 99 step by step according to the value of XY, and the capacitor 99 is changed. Is efficiently charged and discharged from the capacitor 99. Therefore,
The amplitude control signal generation circuit 80 can control the DC voltage supplied to the VCA circuit 4 at high speed, and can quickly eliminate the distortion of the digital signal supplied from the A / D conversion circuit 5.

[0089]

The OFDM demodulator to which the present invention is applied is
The amplification factor of the voltage controlled amplification means is determined based on the signal supplied from the analog-digital conversion means. Therefore, even if the signal supplied from the analog-to-digital conversion means is distorted due to the variation in gain due to the analog-to-digital conversion means, this distortion can be eliminated, and the conversion by the analog-to-digital conversion means can be performed. The characteristics are stable.

The OFDM demodulator to which the present invention is applied also feeds back the error of the amplitude to the voltage control amplifying means provided in the preceding stage of the analog-to-digital converting means, so that the signal supplied from the analog-to-digital converting means. Since the above distortion is eliminated, it is possible to eliminate the distortion generated when an OFDM signal having a wide dynamic range is converted into a digital signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an OFDM demodulation device to which the present invention is applied.

FIG. 2 shows the first embodiment of the OFDM demodulator, and is a block diagram showing the OFDM demodulator in which the amplitude control signal generation circuit includes a subtraction circuit, a cumulative addition circuit, and a D / A conversion circuit. .

FIG. 3 shows a second embodiment of the OFDM demodulation device, in which the amplitude control signal generation circuit is an OFD including a subtraction circuit, a cumulative addition circuit, a PWM circuit, and a low-pass filter.
It is a block diagram which shows an M demodulator.

FIG. 4 shows a third embodiment of the OFDM demodulator, and is a block diagram showing an OFDM demodulator in which an amplitude control signal generation circuit includes a digital comparison circuit and a charge / discharge circuit.

FIG. 5 shows a fourth embodiment of the OFDM demodulator, and is a block diagram showing another OFDM demodulator in which the amplitude control signal generation circuit includes a digital comparison circuit and a charge / discharge circuit.

FIG. 6 shows a fifth embodiment of the OFDM demodulator, and is a block diagram showing still another OFDM demodulator in which the amplitude control signal generation circuit includes a digital comparison circuit and a charge / discharge circuit.

FIG. 7 is a schematic diagram showing a state in which a received signal is demodulated when the amplitude of the IF signal supplied to the A / D conversion circuit is inappropriate.

FIG. 8 is a block diagram showing an amplitude control method in a conventional OFDM demodulation device.

[Explanation of symbols]

1 OFDM demodulation circuit, 2 antennas, 3 tuner,
4 VCA circuit, 5 A / D conversion circuit, 6 digital quadrature demodulation circuit, 7 FFT operation circuit, 8 window synchronization circuit, 9 equalizer, 10 demapping circuit, 11
Error correction circuit, 12 amplitude detection circuit, 13 amplitude control signal generation circuit

Claims (4)

[Claims] 1. Orthogonal frequency division multiplexing (OFDM)
A demodulator for demodulating an OFDM signal modulated by an onal Frequancy Division Multiprexing method, which is a voltage control amplification means for amplifying an intermediate frequency signal obtained by converting the frequency of the OFDM signal with an amplification factor based on an amplitude control signal. And an analog-to-digital conversion means for converting the intermediate frequency signal amplified by the voltage-controlled amplification means from an analog signal to a digital signal, and the voltage-controlled amplification means based on the digital signal supplied from the analog-to-digital conversion means. Amplitude detection means for detecting the amplitude of the intermediate frequency signal amplified by the amplitude detection means, and a difference between the amplitude of the intermediate frequency signal detected by the amplitude detection means and a predetermined amplitude is detected, and an amplitude control signal based on this difference is generated. And an amplitude control signal generating means for providing the voltage control amplifying means. Orthogonal frequency division signal demodulation device. 2. The amplitude control signal generation means detects a difference between the amplitude of the intermediate frequency signal and a predetermined amplitude, and subtracts the signal based on the difference, and the signal supplied from the subtraction means. Cumulative addition means for cumulatively adding the difference between the amplitude of the intermediate frequency signal and the predetermined amplitude based on the above, and for converting the signal supplied from the cumulative addition means into a DC voltage. 2. The orthogonal frequency division signal demodulation device according to claim 1, further comprising digital-analog conversion means for supplying the DC voltage to the voltage control amplification means. 3. The amplitude control signal generating means detects a difference between the amplitude of the intermediate frequency signal and a predetermined amplitude, and subtracts the signal based on the difference, and the signal supplied from the subtracting means. A cumulative addition means for cumulatively adding the difference between the amplitude of the intermediate frequency signal and a predetermined amplitude based on the above, and a pulse based on the signal supplied from the cumulative addition means for supplying a signal based on the result of the cumulative addition. And a low-pass filter for converting the signal supplied from the pulse width modulation means into a DC voltage and supplying the DC voltage to the voltage control amplification means. The orthogonal frequency division signal demodulation device according to claim 1. 4. The amplitude control signal generation means includes a comparison means for comparing the amplitude of the intermediate frequency signal with a predetermined amplitude and supplying a signal according to the comparison result, and a capacitor. Charging / discharging means for accumulating or discharging a voltage for the capacitor based on a signal supplied from the capacitor and supplying a DC voltage to the voltage control amplification means according to the voltage accumulated in the capacitor. The orthogonal frequency division signal demodulation device according to claim 1, which is characterized in that.