JP2000004264A - S/n estimating circuit and reception equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an S/N estimating circuit with which it is not necessary to discriminate the kind of a phase modulating system and the estimate of an S/N can be provided in a short time. SOLUTION: An S/N estimating circuit 250 has a square operating circuit 89 for operating a sum (I'2+Q'2) of the square of in-phase component and quadrature component provided from a signal, to which four-phase modulation is performed, to be modulated through phase detection, subtraction circuit 94 for subtracting a target value R2 from the operated result of the square operating circuit 89 and integration circuit 88 for integrating an absolute value |I'2+Q'2-R2| of the operated result at the subtraction circuit 94 by calculating that absolute value. A signal Se showing the integrated result from the integration circuit 88 is amplified by an amplifier circuit 87 and outputted to an output terminal T2 as an S/N estimate signal Sf.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a phase modulation (PS)
K: Estimated value of the S / N ratio of the phase-detected detected signal from the modulated signal subjected to Phase Shift Keying
The present invention relates to an N ratio estimation circuit and a receiving device.

[0002]

2. Description of the Related Art There is a phase modulation method for modulating a carrier wave according to a code (symbol) that is a modulation signal. In the phase modulation method, a carrier is phase-modulated according to a code to generate a modulated signal. This modulated signal is supplied to the phase demodulation circuit through the transmission path. Examples of the phase modulation include two-phase modulation (2PSK), four-phase modulation (4PSK), and eight-phase modulation (8PSK). Two-phase modulation is BPS
K (Binary Phase Shift Keying)
Four-phase modulation is QPSK (Quadrature Phase Shift Key)
ing).

[0003] Four-phase modulation is used for wireless communications such as cellular phones,
Often used for satellite communications and satellite broadcasting. The receiving device that inputs the modulated signal uses automatic gain control (AGC: Auto gain control).
matic gain control) circuit for gain adjustment. In the reception of satellite communication radio waves and satellite broadcasting radio waves,
Since the attenuation of radio waves is extremely large, when installing an antenna such as a parabolic antenna for reception, the direction of each antenna is set to a communication satellite (CS: Communication Satellite).
) And Broadcasting Satellite (BS)
It is necessary to exactly match the direction of.

[0004]

In a receiver for satellite communication or satellite broadcasting for transmitting an analog signal, the intensity of a received radio wave can be used when adjusting the direction of an antenna. It is difficult to increase the accuracy of aligning the directions. In a satellite communication or satellite broadcast receiving device for transmitting a digital signal, when adjusting the direction of an antenna, an error rate obtained by comparing data after phase demodulation with data obtained by correcting the error can be used. However, in this case, it takes time to adjust the direction of the antenna. For example, in the case of the QPSK method, the error rate in fine weather may be about 10 ^-5 to 10 ^{-6. To} display the error rate corresponding to the direction of the antenna with high accuracy, 1
Since it takes about a second or more, the response speed is slow and it takes time.

[0005] Since there is a correlation between the error rate and the SN ratio, the error rate can be estimated based on the SN ratio of the received radio wave. For the calculation method of the SN ratio, see "Modem of Digital Wireless Communication" (Yoichi Saito, IEICE, 199).
Published February, 2006), pages 24 to 25. According to this document, the noise n (t) of the carrier band is expressed by the following equation using the carrier frequency f and the time t. n (t) = x (t) cos2πft−y (t) sin2
The πft carrier band noise n (t) is converted into an in-phase component x (t) and a quadrature component y (t) by synchronous detection in the same manner as the modulation signal. The noise power (noise power) of the carrier band is represented by the square of the in-phase component x (t) of the noise and the quadrature component y of the noise.
It is calculated using the square of (t).

FIG. 1 is a schematic block diagram illustrating an example of a receiving apparatus capable of obtaining an estimated value of an SN ratio by inputting a phase-modulated signal. This receiving device 100
Is an antenna 1 such as a parabolic antenna and a converter 1
0, channel selection means 20, orthogonal detection means 30, digital demodulation means 40, identification means 50, SN ratio evaluation means 60, and gain control means 70. Antenna 1 is
A satellite broadcast wave or a satellite communication wave containing a high-frequency signal obtained by frequency-converting the modulated signal is received.
Converter 10 converts the frequency of received signal Srf of antenna 1 to generate intermediate frequency signal Sif.

The tuning means 20 receives the intermediate frequency signal Sif from a terminal T20, amplifies the intermediate frequency signal Sif, selects a modulated signal, and outputs the selected signal to a terminal 25. Orthogonal detection means 30
Transmits the modulated signal from the terminal 25 of the tuning means 20 to the terminal T
The signal is input from the terminal 30, and a detection signal of an in-phase component and a quadrature component is generated by phase detection such as synchronous detection using a quadrature carrier and output to a terminal T35.

The digital demodulation means 40 receives a detection signal from a terminal 35 of the quadrature detection means 30 from a terminal T40, generates digital detection signals I 'and Q', which are digital signals of the detection signal, and outputs the digital detection signals to a terminal T45. I do. The digital detection signals I ′ and Q ′ are sent to the identification unit 50 and the evaluation unit 6.
0 and the gain control means 70.

The identification means 50 comprises a digital demodulation means 40
The digital detection signals I ′ and Q ′ from the terminal T45 are input from a terminal T50, and a code that is a modulation signal (baseband signal) is restored based on the digital detection signals I ′ and Q ′ and output to a terminal T55. . The terminal T55 is connected to the output terminal T3 of the receiving device 100. Identification means 50
Generates reference digital detection signals I and Q, which are reference values of the in-phase and quadrature-component digital detection signals for the restored code, based on the input digital detection signals I ′ and Q ′, and outputs the reference digital detection signals to a terminal T59. Output.

The gain control means 70 receives the digital detection signals I 'and Q' from the terminal T45 of the digital demodulation means 40.
Is input from a terminal T70 to generate a control signal Sc for controlling the gain of an amplifier circuit described later and output it to a terminal T75. The tuning means 20 receives a control signal Sc from a terminal T29, and the gain of the intermediate frequency amplifier circuit in the tuning means 20 is controlled by the control signal Sc. The quadrature detection means 30 outputs the control signal Sc
From the terminal T39, and the gain of the variable gain type amplifier circuit in the quadrature detection means 30 is controlled by the control signal Sc.

The evaluation means 60 includes a digital demodulation means 40
, The digital detection signals I ′ and Q ′ from the terminal T45 are inputted from a terminal T60, and the reference digital detection signals I and Q from the terminal 59 of the identification means 50 are inputted from a terminal T69.
The signal Sm indicating the SN ratio is output to the terminal T65. Terminal T
65 is connected to the output terminal T2 of the receiving device 100. The evaluation means 60 calculates the difference between the in-phase component digital detection signal I ′ and the in-phase component reference digital detection signal I by two.
The power (I′−I) ² is calculated, and the square (Q′−Q) ² of the difference between the quadrature component digital detection signal Q ′ and the quadrature component reference digital detection signal Q is calculated. Add both values of.

FIG. 2 is a schematic block diagram illustrating gain control means, evaluation means, and identification means of receiving apparatus 100. Terminals T43 and T44 in the figure constitute a terminal T45. Terminals T51 and T52 constitute terminal T50, and terminal T50
57 and T58 constitute a terminal T59. Terminal T61, T
62 constitutes a terminal T60, and terminals T67 and T68 constitute a terminal T69. Terminals T71 and T72 constitute terminal T70.

The gain control means 70 includes an automatic gain control circuit 7
1 and a low-pass filter 72. The automatic gain control circuit 71 receives the digital detection signals I ′ and Q ′ from the terminals T71 and T72, generates a gain control signal Sa, and outputs it to the low-pass filter 72. The low-frequency component of the gain control signal Sa passes through the low-pass filter 72 and passes through the control signal Sc.
Is output to the terminal T75. In this way, the control signal Sc, which is a low-frequency component of the gain control signal Sa, is supplied to the tuning means 20 and the quadrature detection means 30, and the gain control signal S
The gain of the intermediate frequency amplifying circuit of the tuning means 20 and the gain of the variable gain type amplifying circuit of the quadrature detection means 30 are controlled based on a.

The evaluation means 60 includes subtraction circuits 61 and 62,
It has multiplication circuits 63 and 64, addition circuits 65 and 66, a delay circuit 67, and an amplification circuit 68. The evaluation means 60
From the terminals T61 and T62, digital detection signals I 'and Q'
And the reference digital detection signals I and Q are input from terminals T67 and T68, respectively. Subtraction circuit 61
Is the subtraction result (I′−) obtained by subtracting the in-phase component reference digital detection signal I from the in-phase component digital detection signal I ′.
A difference signal indicating I) is generated. The subtraction circuit 62 generates a difference signal indicating a subtraction result (Q'-Q) obtained by subtracting the in-phase component reference digital detection signal Q from the quadrature component digital detection signal Q '.

The multiplying circuit 63 generates a square signal indicating the operation result (I'-I) ² obtained by squaring the difference signal from the subtracting circuit 61. The multiplying circuit 64 generates a square signal indicating a calculation result (Q′−Q) ² obtained by squaring the difference signal from the subtracting circuit 62. The addition circuit 65 generates a signal indicating an addition result {(I′−I) ² + (Q′−Q) ² } obtained by adding the square signal from the multiplication circuit 63 and the square signal from the multiplication circuit 64. I do. The addition circuit 66 generates a signal obtained by adding the addition signal from the addition circuit 65 and the integration signal Sn from the delay circuit 67 and supplies the signal to the delay circuit 67. The integration signal Sn from the delay circuit 67 is supplied to the amplification circuit 68 and amplified, and
The signal is output to the terminal T65 as a signal Sm indicating the ratio. The terminal T65 is connected to the output terminal 2 of the receiving circuit 100.

The identification means 50 receives the digital detection signals I 'and Q' from the terminals T51 and T52, respectively. The identification means 50 restores the code which is a modulation signal based on the digital detection signals I 'and Q', and outputs the code to the terminal T55. The terminal T55 is connected to the output terminal T3 of the receiving device 100. An error correction circuit 15 is connected to the output terminal T3, and performs error correction of the code based on the code restored from the identification means 50. The identification means 50 generates reference digital detection signals I and Q of the in-phase component and the quadrature component for the restored code based on the digital detection signals I 'and Q', and outputs them to terminals T57 and T58, respectively. The reference digital detection signals I and Q correspond to individual codes and need to be generated for each individual code.

In the evaluation means 60 having such a configuration, since the reference digital detection signal is subtracted from the digital detection signal and the subtraction result is squared, the circuit size of the evaluation means 60 is large. Further, for the phase modulation method such as 2PSK, 4PSK, 8PSK, etc., it is necessary to determine the type of 2PSK, 4PSK, 8PSK or the like with respect to the inputted digital detection signal by the identification means 50, and generate a reference digital detection signal. Switching for that purpose is required by the identification means 50. Further, when the noise increases, it becomes difficult to determine the sign of the original modulation signal, and it becomes difficult for the identification unit 50 to generate an accurate reference digital detection signal.

An object of the present invention is to eliminate the necessity of discriminating the type of the phase modulation method when estimating the SN ratio.
An object of the present invention is to provide an SN ratio estimating circuit and a receiving device capable of obtaining an estimated value of a ratio in a short time.

[0019]

In the SN ratio estimating circuit of the present invention, the square of a detection signal of an in-phase component obtained by phase detection from a modulated signal subjected to phase modulation, and a quadrature component of a quadrature component orthogonal to the in-phase component are obtained. Calculate the sum of the square of the detected signal and 2
It has a multiplication circuit, a subtraction circuit that subtracts a target value from the calculation result of the square calculation circuit, and an integration circuit that calculates the absolute value of the calculation result of the subtraction circuit and integrates the absolute value.

In the SN ratio estimating circuit of the present invention, preferably,
The detection signals of the in-phase component and the quadrature component input to the squaring operation circuit are detection signals of the in-phase component and the quadrature component obtained by four-phase detection from the modulated signal subjected to the four-phase modulation. In the SN ratio estimation circuit of the present invention, preferably, the phase-modulated signal is a satellite communication radio wave or a satellite broadcast radio wave containing a high-frequency signal obtained by frequency-converting the modulated signal, using an antenna. This is a signal obtained by receiving and frequency-converting the received signal.

[0021] In the receiving apparatus of the present invention, a modulated signal whose carrier is phase-modulated according to a code is input, and a variable gain amplifier circuit for generating an amplified signal of the modulated signal is provided. A phase demodulation circuit that generates a detection signal of an in-phase component and a quadrature component, and an automatic gain control circuit that controls a gain of the variable gain amplifier circuit based on a detection signal of the phase demodulation circuit, An automatic gain control circuit for calculating a sum of a square of the detection signal of the in-phase component and a square of the detection signal of the quadrature component, and subtracting a target value from a calculation result of the square calculation circuit Subtraction circuit, an integration circuit for integrating the operation result of the subtraction circuit, and a signal generation circuit for generating a gain control signal for controlling the gain of the variable gain amplifier circuit based on the integration result of the integration circuit. It has bets, provided the absolute value integration circuit for integrating the absolute value calculates the absolute value of the calculation result of said subtraction circuit to the receiving device.

In the receiving apparatus of the present invention, preferably, a first analog / digital conversion circuit for converting the detection signal of the in-phase component from an analog signal to a digital signal, and the detection signal of the quadrature component is converted from an analog signal to a digital signal. A second analog / digital conversion circuit for converting the signals into signals, and digital signals output from both the analog / digital conversion circuits or interpolated signals of the digital signals, and remaining in each of the input signals. A carrier removing circuit for attenuating a carrier wave, wherein the square calculating circuit calculates a sum of squares of both output signals of the carrier removing circuit.

In the receiving apparatus of the present invention, preferably,
The detection signals of the in-phase component and the quadrature component input to the multiplication operation circuit are detection signals of the in-phase component and the quadrature component obtained by four-phase detection from the modulated signal subjected to the four-phase modulation.

In the receiving apparatus according to the present invention, preferably, the receiving apparatus includes: an antenna for receiving a satellite broadcast radio wave or a satellite communication radio wave containing a high-frequency signal obtained by frequency-converting the modulated signal; A converter that converts the frequency of the received signal to generate an intermediate frequency signal, an intermediate frequency amplifier that amplifies the intermediate frequency signal from the converter to generate an intermediate frequency amplified signal, and A signal selection circuit for selecting a modulation signal and supplying the selected signal to the variable gain type amplifier circuit, wherein the gain of the intermediate frequency amplifier circuit is controlled based on the gain control signal.

In the SN ratio estimating circuit of the present invention, the square operation circuit calculates the sum of the squares of the detection signals of the in-phase component and the quadrature component. Since the subtraction circuit subtracts the target value from the operation result of the square operation circuit, a difference between the sum of the squares of the detection signals of the in-phase component and the quadrature component and the target value of the sum is obtained. Since the integration circuit calculates the absolute value of the operation result of the subtraction circuit and integrates the absolute value, the operation result obtained by cumulatively adding the absolute value of the difference is obtained.

In the receiving apparatus according to the present invention, the variable gain type amplifier circuit generates an amplified signal of the modulated signal. The phase demodulation circuit generates a detection signal of an in-phase component and a quadrature component from the amplified signal of the modulated signal by phase detection. The automatic gain control circuit controls the gain of the variable gain type amplifier circuit based on the detection signal of the phase demodulation circuit. The automatic gain control circuit subtracts the target value of the sum from the sum of the square of the detection signal of the in-phase component and the square of the detection signal of the quadrature component, and integrates the subtraction result. Then, a gain control signal for controlling the gain of the variable gain amplifier circuit is generated based on the result of the integration. Since an absolute value integration circuit for calculating the absolute value of the subtraction result and integrating the absolute value is provided in the receiving device, a calculation result obtained by cumulatively adding the absolute values is obtained.

[0027]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 3 is a schematic block diagram illustrating an example of the receiving device according to the present invention. The receiving apparatus 200 inputs the modulated signal subjected to the phase modulation, and outputs an SN ratio estimation signal Sm indicating an estimated value of the SN ratio to an output terminal T2 of the receiving apparatus 200.

The receiving apparatus 200 includes an antenna 1 such as a parabolic antenna, a converter 10, a tuning unit 20, a quadrature detection unit 30, a digital demodulation unit 40, an identification unit 50, and an SN ratio evaluation unit 160. , Gain control means 1
70. The antenna 1 receives a satellite broadcast radio wave or a satellite communication radio wave containing a high-frequency signal obtained by frequency-converting the modulated signal. The frequency of the satellite broadcast radio wave or the satellite communication radio wave is, for example, about 12 GHz. Converter 10 frequency-converts reception signal Srf of antenna 1 to an intermediate frequency to generate intermediate frequency signal Sif. The frequency of the intermediate frequency signal Sif is, for example, about 1 GHz. As described above, the performance of the receiving device 200 can be improved by configuring the receiving device 200 with the superheterodyne system.

The tuning means 20 receives the intermediate frequency signal Sif from the terminal T20, amplifies the intermediate frequency signal Sif, selects a modulated signal, and outputs it to the terminal 25. Orthogonal detection means 30
Transmits the modulated signal from the terminal 25 of the tuning means 20 to the terminal T
The signal is input from the terminal 30, and a detection signal of an in-phase component and a quadrature component is generated by phase detection such as synchronous detection using a quadrature carrier and output to a terminal T35. The detection signals of the in-phase component and the quadrature component are, for example, detection signals of the in-phase component and the quadrature component obtained by four-phase detection from the modulated signal subjected to the four-phase modulation.

The digital demodulation means 40 receives the detection signal from the terminal 35 of the quadrature detection means 30 from a terminal T40, generates digital detection signals I 'and Q', which are digital signals of the detection signal, and outputs them to a terminal T45. I do. The digital detection signals I ′ and Q ′ are sent to the identification unit 50 and the evaluation unit 1.
60 and the gain control means 170.

The identification means 50 is a digital demodulation means 40
The digital detection signals I ′ and Q ′ from the terminal T45 are input from a terminal T50, and a code that is a modulation signal is restored based on the digital detection signals I ′ and Q ′ and output to a terminal T55. The terminal T55 is an output terminal T3 of the receiving device 200.
It is connected to the. An error correction circuit 15 is connected to the output terminal T3 of the receiving device 200, and performs error correction of the code based on the code recovered from the identification unit 50.

The gain control means 170 receives the digital detection signals I ',
Q ′ is input from a terminal T70, and a control signal Sc for controlling a gain of an amplifier circuit described later is generated and output to a terminal T75. The tuning means 20 receives a control signal Sc from a terminal T29, and the gain of the intermediate frequency amplifier circuit in the tuning means 20 is controlled by the control signal Sc. The quadrature detector 30 receives a control signal Sc from a terminal T39, and controls the gain of the variable gain amplifier circuit in the quadrature detector 30 by the control signal Sc.

The evaluation means 161 generates an S / N ratio estimation signal Sf obtained by estimating the S / N ratio of the modulated signal and outputs it to a terminal T65. The terminal T65 is an output terminal T2 of the receiving device 200.
And an SN ratio estimation signal Sf is output from an output terminal T2.
Is output to

FIG. 4 is a schematic block diagram for explaining the tuning means and the quadrature detection means. Terminals T33 and T34 in the figure
Constitutes the terminal T35. The tuning means 20 has an intermediate frequency amplification circuit 21 and a signal selection circuit 29B. The signal selection circuit 29B includes a multiplication circuit 22 and a SAW (Surface Ac
oustic Wave) filter 23 and PLL (Phase Locked)
Loop) circuit 28, frequency dividing circuit 29, and oscillating circuit 29A
And

The intermediate frequency signal Sif is supplied to a terminal T20 of the tuning circuit 20. The intermediate frequency amplification circuit 21 receives and amplifies the intermediate frequency signal Sif, and
Is generated and output to the multiplication circuit 22. The oscillation signal from the oscillation circuit 29A is output to the frequency dividing circuit 29. The frequency of the oscillation signal is, for example, 4 MHz. The frequency dividing circuit 29 receives the oscillation signal and generates a frequency-divided signal with the frequency of the oscillation signal reduced to 1 / M. Here, M is an integer of 2 or more.

The PLL circuit 28 includes a frequency dividing circuit 25, a phase comparing circuit 26, and a low-pass filter (LPF: Low Pass Filter).
Filter) 27 and a voltage controlled oscillator (VCO: Voltag)
e Controlled Oscillator) 24. The oscillation signal S28 from the voltage controlled oscillation circuit 24 is supplied to the multiplication circuit 22 and the frequency division circuit 25. The frequency dividing circuit 25 generates a frequency divided signal in which the frequency of the oscillation signal S28 from the voltage controlled oscillation circuit 24 is reduced to 1 / L. Here, L is an integer of 2 or more. The frequency-divided signal from the frequency-dividing circuit 25 is
Supplied to

The phase comparing circuit 26 includes frequency dividing circuits 25 and 29
And outputs a voltage signal corresponding to the phase difference to the low-pass filter 27. The low-pass filter 27 passes the low-frequency component of the voltage signal from the phase comparison circuit 26 and supplies the low-frequency component to the voltage-controlled oscillation circuit 24. The voltage control oscillation circuit 24 generates an oscillation signal S28 according to the signal from the low-pass filter 27.

The multiplying circuit 22 includes an intermediate frequency amplified signal S21
Is multiplied by the oscillation signal S28, and the signal indicating the multiplication result is represented by S
It is supplied to the AW filter 23. The multiplication circuit 22 is configured by, for example, a frequency mixing circuit (mixer). As the SAW filter 23, for example, the center frequency is 479.5M.
Hz and a pass band of 36 MHz. The SAW filter 23 receives the output signal of the multiplying circuit 22, extracts a signal having a frequency difference between the frequency of the intermediate frequency amplified signal S21 and the frequency of the oscillation signal S28, that is, a signal S23 having a so-called beat frequency, and outputs the signal to a terminal T25. I do. The tuning means 20 is set so that the signal S23 of this beat frequency becomes the modulated signal.
Is composed. The frequency dividing circuit 25 generates a frequency-divided signal obtained by reducing the frequency of the oscillation signal S28 to 1 / L. The beat frequency can be changed by changing the value of L with a switch or the like by an operator. The desired modulated signal S23 can be extracted from the intermediate frequency amplified signal S21 containing the modulated signal. The control signal Sc is supplied to the terminal T29, and the control signal is supplied to the control terminal of the intermediate frequency amplifier circuit 21 to control the gain of the intermediate frequency amplifier circuit 21. Terminal T2
5 is supplied to the terminal T30 of the quadrature detection means 30.

The quadrature detection means 30 has a variable gain type amplification circuit 31 and a phase demodulation circuit 38. The variable gain amplifying circuit 31 receives and amplifies the modulated signal S23 and outputs the amplified signal S31 to the phase demodulation circuit 38. Terminal T3
9 is supplied with a control signal Sc, which is supplied to a control terminal of the variable gain type amplifier circuit 31 to control the gain of the variable gain type amplifier circuit 31. The phase demodulation circuit 38 includes the multiplication circuit 3
3 and 34, a π / 2 phase shift circuit 32, low-pass filters 35 and 36, and an oscillation circuit 37.

The amplified signal S31 is supplied to multiplication circuits 33 and 34, respectively. The oscillation signal from the oscillation circuit 37 is
It is supplied to a π / 2 phase shift circuit 32 and a multiplication circuit 33. π
The / 2 phase shift circuit 32 converts the oscillation signal from the oscillation circuit 37 into π
A signal having a phase shifted by / 2 (90 °) is generated and supplied to the multiplying circuit. A signal obtained by shifting the phase of the oscillation signal from the oscillation circuit 37 by + π / 4 is supplied to the multiplication circuit 33.
A configuration may be adopted in which a signal obtained by shifting the phase of the oscillation signal from the oscillation circuit 37 by −π / 4 is supplied to the multiplication circuit 34. The frequency of the oscillation signal of the oscillation circuit 37 is, for example, 479.5.
MHz and a frequency equal to the carrier frequency. By supplying the output signal of the multiplying circuit 33 to the low-pass filter 35, the low-pass filter 35 outputs a detection signal AI ′ of the in-phase component to the terminal T33. By supplying the output signal of the multiplication circuit 34 to the low-pass filter 36, the detection signal AQ ′ of the orthogonal component is output from the low-pass filter 36 to the terminal T34. The phase demodulation circuit 38 is a configuration of a four-phase demodulation circuit that performs synchronous detection using orthogonal carriers. The oscillating circuit 37 may be constituted by a carrier recovery circuit for generating a carrier of an analog signal.

FIG. 5 is a schematic block diagram for explaining an example of the digital demodulation means. Terminals T41 and T42 in the figure
Constitutes a terminal T40, and terminals T43 and T44 constitute a terminal T4.
5 is constituted. From the terminal T33 of the quadrature detection means 30, a detection signal AI 'of the in-phase component of the analog signal is supplied to a terminal T41.
Is supplied. A terminal T42 receives a detection signal AQ ′ of the quadrature component of the analog signal from the terminal T34 of the quadrature detection means 30.
Is supplied.

The digital demodulation means 40 comprises analog / digital conversion circuits 41 and 42 and a timing detection circuit 4
7, a low-pass filter 48, and a voltage-controlled oscillation circuit 49.
And a carrier removal circuit 56. The carrier removal circuit 56 includes multiplication circuits 43 and 44, roll-off filters 45 and 46, a π / 2 phase shift circuit 54, and a carrier reproduction circuit 55.

The analog / digital conversion circuit 41 receives the in-phase component detection signal AI 'and generates a detection signal S41 of the in-phase component of the digital signal. The analog / digital conversion circuit 42 receives the quadrature component detection signal AQ 'and generates a quadrature component detection signal S42 of the digital signal. The multiplication circuit 43 receives the detection signal S41 and the digital carrier signal S55 from the carrier reproduction circuit 55, and outputs a signal indicating a result of multiplication of the signals to the roll-off filter 45. The multiplication circuit 44 receives the detection signal S42 and the digital signal from the π / 2 phase shift circuit 54, and outputs a signal indicating a result of multiplication of the signals to the roll-off filter 46.

The roll-off filter 45 includes a multiplication circuit 43
To generate a digital detection signal I ′ which is a digital signal in which intersymbol interference is reduced and which is a detection signal having an in-phase component. The roll-off filter 46 receives the output signal of the multiplying circuit 44 and generates a digital detection signal Q ′ which is a digital signal in which intersymbol interference is reduced and which is a detection signal of an orthogonal component. The roll-off filter (reception filter) may be constituted by a Nyquist filter. The digital detection signals I ′ and Q ′ are supplied to a carrier recovery circuit (carrier recovery circuit) 55 and a timing detection circuit 47.
And terminals T43 and T44.

The carrier recovery circuit 55 receives the digital detection signals I 'and Q' and inputs the digital detection signals I 'and Q'.
A digital carrier signal S55, which is a digital signal of a carrier remaining in Q ', is generated. Carrier regeneration circuit 5
Reference numeral 5 denotes a phase error detection circuit 51 for generating a phase error signal indicating a phase error between the digital carrier signal S55 and the digital detection signals I 'and Q'; a low-pass filter 52 for inputting the phase error signal; A numerically controlled oscillation circuit 53 that generates a digital carrier signal S55 based on a signal from the pass filter 52. The phase error detection circuit 51, the low-pass filter 52, the numerically controlled oscillation circuit 53, and the π / 2 phase shift circuit 54 may be constituted by circuits for inputting and outputting digital signals. The carrier reproducing circuit 55 may be constituted by a Costas type carrier reproducing circuit. The digital signal obtained by shifting the digital carrier signal S55 by + π / 4 may be supplied to the multiplication circuit 43, and the digital signal obtained by shifting the digital carrier signal S55 by −π / 4 may be supplied to the multiplication circuit 44. .

The timing detection circuit 47 detects the difference between the time interval of the analog / digital conversion by the analog / digital conversion circuits 41 and 42 and the code cycle and the digital detection signals I ′ and Q ′ output from the carrier removal circuit 56.
, And generates a shift detection signal S47 indicating the shift. The low-pass filter 48 outputs the shift detection signal S47
Enter The voltage control oscillation circuit 49 generates a timing signal S based on a signal supplied from the low-pass filter 47.
49 and the analog / digital conversion circuits 41 and 4
Feed to 2. Analog / digital conversion circuits 41, 4
2 is a detection signal A based on the timing signal S49.
Performs analog / digital conversion of I 'and AQ'.

FIG. 6 is a schematic block diagram for explaining the evaluation means, the gain control means, and the identification means. In the figure, terminal T4
3 and T44 constitute a terminal T45, and terminals T51 and T52
Constitutes a terminal T50, and terminals T71 and T72 constitute a terminal T7.
0. The digital detection signal I 'from the terminal T43 is supplied to terminals T71 and T51, and the digital detection signal Q' from the terminal T44 is supplied to terminals T72 and T52.

The identification means 50 receives the digital detection signals I 'and Q' from the terminals T51 and T52, respectively. The identification means 50 restores the code which is a modulation signal based on the digital detection signals I 'and Q', and outputs the code to the terminal T55. The terminal T55 is connected to the output terminal T3 of the receiving device 200.

The gain control means 170 has an automatic gain control circuit 171 and a low-pass filter 72. The automatic gain control circuit 171 includes a square operation circuit 89 and a subtraction circuit 94
, An integration circuit 99, an amplification circuit 97, and a pulse signal generation circuit 98. The square operation circuit 89 includes the multiplication circuit 9
1 and 92 and an adder circuit 93. Multiplication circuit 91
Outputs a signal obtained by squaring the digital detection signal I ′ from the terminal 71 to the addition circuit 93. The multiplying circuit 92 outputs a signal obtained by squaring the digital detection signal Q ′ from the terminal 72 to the adding circuit 93. The adder circuit 93 includes the multiplication circuit 9
The signals from the signals 1 and 92 are added, and a signal indicating the result of the addition is output to the subtraction circuit 94. The subtraction circuit 94 includes the addition circuit 9
3 from the signal indicating the addition result, the target value R of the addition result
A signal indicating the result of subtraction of ² (I ′ ² + Q ′ ² −R ² ) is output to the integration circuit 99 and the terminal T76. The target value R ² may be a value equal to the sum of the square of the detection signal I of the in-phase component and the square of the detection signal Q of the quadrature component when there is no transmission line noise.

The integrating circuit 99 has an adding circuit 95 and a delay circuit 96. The addition circuit 95 adds the signal from the subtraction circuit 94 and the signal from the delay circuit 96, and outputs a signal indicating the addition result to the delay circuit 96. The signal indicating the integration result from the delay circuit 96 is output to the amplifier circuit 97, and the amplifier circuit 97 outputs the integrated amplified signal S97 obtained by amplifying the signal from the delay circuit 96 to the pulse signal generation circuit 98.
The pulse signal generation circuit 98 generates a gain control signal Sa having a pulse width according to the integrated amplified signal S97, and outputs it to the low-pass filter 72. The signal from the low-pass filter 72 is output to the terminal T75 as a control signal Sc.

The result of subtraction (I ′ ² +
The signal indicating Q ′ ² −R ² ) is supplied to the terminal T 66 of the evaluation means 160 via the terminal T 76. Evaluation means 160
Has an absolute value integration circuit 88 and an amplification circuit 87.
The absolute value integration circuit 88 has an absolute value generation circuit 84, an addition circuit 85, and a delay circuit 86. Absolute value generation circuit 8
4 receives the signal from the subtraction circuit 94, calculates the absolute value of the subtraction result (I ′ ² + Q ′ ² −R ² ), generates an absolute value signal S84 indicating the absolute value, and Output to The adding circuit 85 outputs a signal obtained by adding the absolute value signal S84 from the absolute value generating circuit 84 and the integrated signal Se from the delay circuit 86 to the delay circuit 86. Delay circuit 86
Outputs an integration signal Se indicating an integration result of the absolute value signal S84 to the amplification circuit 87. The amplification circuit 87 outputs the integration signal S
e is amplified to generate an SN ratio estimation signal Sf,
Output to The SN ratio estimation signal Sf is supplied to the output terminal T2 of the receiving device 200 via the terminal T65.

A multiplication circuit for multiplying the signal from the subtraction circuit 94 by a constant coefficient may be provided between the subtraction circuit 94 and the addition circuit 95. The value of the coefficient is, for example, 0.1 to 0.00.
The value is in the range of 1. Target value R ² may be set in advance, the operator may be set by a switch or the like. In gain control means 171, a digital / analog conversion circuit for digital / analog conversion of integrated amplified signal S97 from amplification circuit 97 is provided instead of pulse signal generation circuit 98 and low pass filter 72, and this digital / analog conversion circuit is provided. May be used as the control signal Sc.

FIGS. 7 and 8 are signal space diagrams for explaining the distribution of the detection signal generated by the phase demodulation circuit. A complex plane is formed by the I axis and the Q axis. The distance from the origin O corresponds to the amplitude of the signal (detection signal), and the angle from the I axis corresponds to the phase of the signal (detection signal). When the code is transmitted using the QPSK method, the detection signal is located at the points A, B, C, and D in an ideal case where there is no noise on the transmission line. The position that should be located at point A may be shifted to point A ′. The coordinates of the point A 'are represented by A' (I ', Q') and correspond to the digital detection signals I ', Q'. The coordinates of the point A are represented by A (I, Q), Digital detection signals I and Q
It corresponds to.

The signal power can be obtained by calculating Σ (In ² + Qn ² ) when N codes are transmitted. When N codes are transmitted, the noise power is {(In-In ') ² + (Qn-Qn') ² }.
Can be calculated and obtained. Here, Σ indicates that the calculation result in parentheses is added for each of the N codes. The symbol n of In indicates a number assigned to the reference digital detection signal I of the in-phase component. Similarly, the code n of Qn indicates a number assigned to the reference digital detection signal Q of the orthogonal component. The symbol n of In ′ indicates a number assigned to the digital detection signal I ′ of the in-phase component. Similarly, the code n of Qn 'indicates a number given to the quadrature component digital detection signal Q'. Sign n
Takes each value of 1 to N, and N is an integer of 2 or more. S
The N ratio can be obtained by calculating (signal power) / (noise power). When using a common logarithm, 10 × log is used.
It can be obtained by calculating {(signal power) / (noise power)}.

In FIG. 8, a noise component (noise component) A
A ′ can be decomposed into a component Nr in a radial direction (r direction) and a component Nθ in a direction perpendicular to the direction (θ direction) using a component of polar coordinates. The line segment AE and the line segment EA 'are at right angles, the size of the line segment AE is Nr, and the size of the line segment EA' is Nθ. Therefore, when N codes are transmitted, the noise power can be obtained by calculating Σ (Nrn ² + Nθn ² ). The symbol n of Nrn indicates a number given to the noise component Nr in the r direction. Similarly,
The symbol n of Nθn indicates a number assigned to the noise component Nθ in the θ direction.

Gaussian noise is an ideal signal point A
The average value of Nr ^{2 and} the average value of Nθ ² become equal to each other, since points A to D are distributed around the center in the same manner in the amplitude direction and the phase direction. . If N is sufficiently large, approximately Σ (Nrn
² ) ≒ Σ (Nθn ² ), Σ (In × In ′) ≒ Σ (In ² ), and Σ (Qn ×
Qn ′) ≒ Σ (Qn ² ). Based on these, the noise power is represented by the following equation. {(In−In ′) ² + (Qn−Qn ′) ² } = {(In ² −2In × In ′ + In ′ ² ) + (Qn ² −2Qn × Qn ′ + Qn ′ ² )} {(In ′ ² + Qn ′ ² ) − (In ² + Qn ² )} = {(In ′ ² + Qn ′ ² ) −R ² } When the gain control means 170 operates ideally, In ² +
Qn ² = by setting the target value R ² such that R ^2, it is possible to accurately calculate the noise power. In each PSK method, since the reference signal serving point is located at a constant radius on the circumference in the constellation diagram, an In ²
The value of + Qn ² is constant.

FIGS. 9 to 11 show constellations (Constellations) in the QPSK system in satellite communication and satellite broadcasting.
llation) is a signal space diagram illustrating an example.
FIG. 9 shows a constellation in the case where there is almost no noise in the transmission path, and the SN ratio is about 36 dB. The signal points are concentrated on the four reference points with almost no deterioration of the detection signal due to noise. FIG. 10 is a constellation of CS digital broadcasting in fine weather, and the SN ratio is about 16 dB. Signal points are almost uniformly distributed around the four reference points due to noise. FIG. 11 shows a constellation of CS digital broadcasting during heavy rain, where the SN ratio is 6 dB.
It is about. Signal points are almost uniformly distributed around the four reference points due to noise. In FIG. 11, the signal points are spread and distributed more than in FIG.

FIG. 12 is a signal space diagram showing an example of a constellation in the BPSK system in satellite communication and satellite broadcasting. FIG. 12 shows a constellation of CS digital broadcasting in fine weather, where the SN ratio is 1
It is about 6 dB. Signal points are almost uniformly distributed around the two reference points due to noise.

FIG. 13 is a signal space diagram showing an example of a constellation in the 8PSK system in satellite communication and satellite broadcasting. FIG. 13 shows a constellation of CS digital broadcasting in fine weather, where the SN ratio is 1
It is about 6 dB. Signal points are almost uniformly distributed around the eight reference points due to noise.

From the constellations of FIGS. 9 to 12,
In the reception of satellite communication and satellite broadcasting, the noise superimposed on the signal can be regarded as almost Gaussian noise, so that the SN ratio in the phase modulation method can be estimated by the equation. In the receiving circuit 200, the carrier removing circuit 56
As a result, since the carrier components in the digital detection signals I ′ and Q ′ are attenuated, the detection accuracy of the SN ratio indicated by the SN ratio estimation signal Sf can be improved.

In the evaluation means 160 shown in FIG. 6, the addition result of the addition circuit 85 may be temporarily reset by a switch or the like, or the delay time of the delay circuit 86 may be temporarily reset by a switch or the like. Is also good.
Square operation circuit 89, subtraction circuit 94, and evaluation means 160
These form an SN ratio estimating circuit 250.

According to the SN ratio estimating circuit 250, when the SN ratio is estimated, the reference digital detection signals I and Q corresponding to the respective codes in the identification unit 50 are compared with the evaluation unit 60 shown in FIGS. Can be eliminated, the type of the phase modulation method need not be determined, and the SN ratio can be estimated even when the noise is large. According to the SN ratio estimating circuit 250, the SN ratio can be estimated in satellite communication or satellite broadcasting using the phase modulation method. Since it is not necessary to detect the error rate, when setting the direction of the antenna 1 of the receiving apparatus 200, the antenna 1 is determined based on the SN ratio estimation signal Sf obtained by amplifying the integrated signal Se.
The estimated value of the S / N ratio according to the angle can be obtained in a short time. Therefore, the adjustment time for adjusting the direction of the antenna 1 can be shortened.

The digital demodulation means 40A shown in FIG.
May be used in place of the digital demodulation means 40 in FIG. The digital demodulation means 40A is different from the digital demodulation means 40 of FIG. 5 in that an oscillation circuit 59 is used in place of the voltage controlled oscillation circuit 49, a timing detection circuit 47A is used in place of the timing detection circuit 47, and a low-pass filter is used. 48, a low-pass filter 48A is used, and a numerical control oscillation circuit 58 is provided.
, 42 and the carrier removing circuit 56
, And the configuration of the carrier removal circuit 56 is the same.

The timing detection circuit 47A has an analog /
A difference between the time at which the digital conversion circuits 41 and 42 perform analog / digital conversion and the time at which the code is switched is detected based on the output signals I 'and Q' of the carrier removal circuit 56, and a digital signal indicating the difference is detected. Is generated. The low-pass filter 48A is a low-pass filter for a digital signal to which the shift detection signal S47A is input, and the numerically controlled oscillation circuit 58 generates a digital signal oscillation signal S58 based on the signal from the low-pass filter 48A. . The interpolation circuit 57 receives the oscillation signal S58 and the digital signals S41 and S42, and uses the average value of the digital signals S41 and S42 to calculate the interpolation signals S41 and S42 of the digital signals S41 and S42.
41 'and S42' are generated. The interpolation circuit 57 is configured to perform linear interpolation.

The interpolation circuit 57 generates a digital signal S41,
An interpolation signal S of digital signals (sampling signals) S41 and S42 based on S42 and a deviation detection signal S47A.
41 'and S42' are generated for each code cycle. Oscillation circuit 5
Reference numeral 9 generates a timing signal S59 having a period of a multiple of the code period, for example, a half period of the code period, and supplies the timing signal S59 to both the analog / digital conversion circuits 41 and 42. The cycle of the timing signal may be 1/3 of the code cycle or 1/4 of the code cycle. Both the analog / digital conversion circuits 41 and 42 output the analog signals AI ′ and A ′ from the phase demodulation circuit 38 based on the timing signal S59.
Q ′ is subjected to analog / digital conversion. Interpolation signal S4 generated by interpolation circuit 57 by interpolation (Interpolation)
1 ′ and S42 ′ correspond to the multiplication circuit 4 of the carrier removal circuit 56.
The multiplication circuit 43 performs multiplication with the digital signal S55, and the multiplication circuit 44 performs multiplication with the digital signal obtained by shifting the digital signal S55 by 90 degrees.

The output signal S4 of the timing detection circuit 47A
A conversion circuit for converting 7A into an analog signal may be provided, and this conversion circuit and the timing detection circuit 47A may be used as the timing detection circuit 47 of the digital demodulation circuit 40. By the timing detection circuits 47 and 47A, an accurate symbol point in the code cycle can be estimated. In addition,
The above embodiment is an example of the present invention, and the present invention is not limited to the above embodiment.

[0067]

According to the SN ratio estimating circuit of the present invention, it is not necessary to determine the type of the phase modulation system, and the SN ratio can be estimated even when the noise is large.
Further, an estimated value of the SN ratio can be obtained in a short time in satellite communication or satellite broadcasting using a phase modulation method.

According to the receiving apparatus of the present invention, it is not necessary to determine the type of the phase modulation method, and the SN ratio can be estimated even when the noise is large. Further, an estimated value of the SN ratio can be obtained in a short time in satellite communication or satellite broadcasting using a phase modulation method. Therefore, the adjustment time for adjusting the direction of the antenna can be shortened.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating an example of a receiving device.

FIG. 2 is a schematic block diagram of a gain control unit, an evaluation unit, and an identification unit included in the receiving device of FIG.

FIG. 3 is a schematic block diagram illustrating an example of a receiving device of the present invention.

FIG. 4 is a schematic block diagram of a tuning unit and a quadrature detection unit included in the receiving apparatus of FIG. 3;

FIG. 5 is a schematic block diagram of an example of a digital demodulating means included in the receiving device of FIG. 3;

6 is a schematic block diagram of a gain control unit, an evaluation unit, and an identification unit included in the receiving device of FIG.

FIG. 7 is a signal space diagram of the QPSK system.

FIG. 8 is a signal space diagram of the QPSK method.

FIG. 9 is a signal space diagram illustrating an example of a constellation of the QPSK method when there is no noise on a transmission line.

FIG. 10 is a signal space diagram showing an example of a constellation of the QPSK method.

FIG. 11 is a signal space diagram showing an example of a constellation of the QPSK method.

FIG. 12 is a signal space diagram showing an example of a BPSK constellation.

FIG. 13 is a signal space diagram showing an example of an 8PSK constellation.

FIG. 14 is a schematic block diagram of an example of a digital demodulation unit included in the receiving device of FIG. 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Antenna, 10 ... Converter, 15 ... Error correction circuit, 20 ... Tuning means, 21 ... Intermediate frequency amplification circuit, 23 ...
SAW filter, 28: PLL circuit, 29B: signal selection circuit, 30: quadrature detection means, 31: variable gain type amplification circuit, 38: phase demodulation circuit, 40, 40A: digital demodulation means, 41, 42: analog / digital conversion circuit,
43, 44 multiplying circuits, 45, 46 roll-off filters, 47 timing detection circuits, 49 voltage controlled oscillation circuits (VCO), 50 identification means, 51 phase error detection circuits, 53, 58 numerical control oscillations Circuit (NCO), 54 ...
π / 2 phase shift circuit, 55: carrier recovery circuit (carrier recovery circuit), 56: carrier removal circuit, 57A: interpolation circuit,
59: oscillation circuit, 60, 160: evaluation means, 70, 17
0: gain control means, 71, 171: automatic gain control circuit (AGC circuit), 72: low-pass filter (LPF),
84 ... absolute value generation circuit, 88 ... absolute value integration circuit, 89 ...
Square operation circuit, 94 subtraction circuit, 98 pulse signal generation circuit, 99 integration circuit, 100, 200 reception device, 2
50: SN ratio estimating circuit, Sa: gain control signal, Sc: control signal, Sif: intermediate frequency signal, Sf: SN ratio estimating signal,
Se: integrated signal, Srf: received signal, I ': digital detection signal of in-phase component, Q': digital detection signal of quadrature component, T2, T3 ... output terminals.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/20 H04N 7/20 5K061 17/00 17/00 A F term (Reference) 5C061 BB03 CC05 5C064 DA01 DA14 5K004 AA05 FA02 FD05 FG02 FH01 FH04 FH07 5K020 AA05 BB06 CC03 DD25 EE05 FF06 NN01 5K042 AA05 BA08 CA02 CA12 CA18 DA04 DA13 EA02 EA15 FA11 JA01 LA06 5K061 AA14 BB06 BB10 CC25

Claims (14)

[Claims] A square for calculating a sum of a square of a detection signal of an in-phase component obtained by phase detection from a modulated signal subjected to phase modulation and a square of a detection signal of a quadrature component orthogonal to the in-phase component. An S / N ratio estimating circuit comprising: an arithmetic circuit; a subtraction circuit that subtracts a target value from the operation result of the square operation circuit; and an integration circuit that calculates an absolute value of the operation result of the subtraction circuit and integrates the absolute value. . 2. A detection signal of an in-phase component and a quadrature component input to the square operation circuit is a detection signal of an in-phase component and a quadrature component obtained by four-phase detection from a modulated signal subjected to four-phase modulation. 2. The SN ratio estimating circuit according to claim 1. 3. The phase-modulated modulated signal is obtained by receiving a satellite communication radio wave or a satellite broadcast radio wave containing a high-frequency signal obtained by frequency-converting the modulated signal with an antenna and frequency-converting the received signal. The signal-to-noise ratio estimating circuit according to claim 1, wherein the signal is a signal obtained by performing the following. 4. The SN according to claim 1, wherein the target value is equal to the sum of the square of the detection signal of the in-phase component and the square of the detection signal of the quadrature component when there is no transmission line noise.
Ratio estimation circuit. 5. A variable gain type amplifier circuit for receiving a modulated signal whose carrier is phase-modulated in accordance with a code and generating an amplified signal of the modulated signal, and an in-phase component and a quadrature component by phase detection from the amplified signal. A receiving device comprising: a phase demodulation circuit that generates a detection signal of the component; and an automatic gain control circuit that controls a gain of the variable gain amplifier circuit based on the detection signal of the phase demodulation circuit. A square operation circuit for calculating the sum of the square of the detection signal of the in-phase component and the square of the detection signal of the quadrature component; a subtraction circuit for subtracting a target value from the operation result of the square operation circuit; An integration circuit that integrates an operation result of the subtraction circuit; and a signal generation circuit that generates a gain control signal that controls a gain of the variable gain amplifier circuit based on the integration result of the integration circuit. The receiving device, wherein the receiving device includes an absolute value integration circuit that calculates an absolute value of an operation result of the subtraction circuit and integrates the absolute value. 6. A receiving apparatus, wherein: a first analog / digital conversion circuit for converting the in-phase component detection signal from an analog signal to a digital signal; and a converter for converting the quadrature component detection signal from an analog signal to a digital signal. A digital signal or an interpolation signal of each digital signal output from both the second analog / digital conversion circuit and the analog / digital conversion circuit is input, and the carrier wave remaining in each of the input signals is attenuated. The receiving device according to claim 5, further comprising a carrier removing circuit, wherein the square calculating circuit calculates a sum of squares of both output signals of the carrier removing circuit. 7. The signal generation circuit generates a gain control signal having a pulse width according to an integration result of the integration circuit, and supplies the gain control signal to the variable gain amplifier circuit via a low-pass filter. 6. The receiver according to claim 5, wherein the gain of the variable gain amplifier circuit is controlled. 8. A detection signal of an in-phase component and a quadrature component input to the square operation circuit is a detection signal of an in-phase component and a quadrature component obtained by four-phase detection from a modulated signal subjected to four-phase modulation. The receiving device according to claim 5. 9. The receiving apparatus, wherein both of the analog / digital conversion circuits are analog / digital converters.
A timing detection circuit that detects a difference between a time interval for digital conversion and a code cycle based on an output signal of the carrier removal circuit and generates an analog signal indicating the difference; and reduces the analog signal from the timing detection circuit to a low level. A voltage-controlled oscillating circuit that inputs the signal through a band-pass filter, generates a timing signal based on a signal from the low-pass filter, and supplies the timing signal to both the analog / digital conversion circuit; 7. The receiving device according to claim 6, wherein both the digital / digital conversion circuit performs an analog / digital conversion of the analog signal from the phase demodulation circuit based on the timing signal. 10. A multiplication circuit for multiplying a digital signal from the first analog / digital conversion circuit by a digital signal of the remaining carrier wave, and a first signal for inputting an output signal of the multiplication circuit. A multiplying circuit for multiplying the digital signal from the second analog / digital conversion circuit by a digital signal shifted by 90 degrees from the remaining digital signal of the carrier, and an output signal of the multiplying circuit A second roll-off filter, and a carrier recovery circuit that generates a digital signal of the remaining carrier based on signals from both of the roll-off filters, and a signal from both of the roll-off filters. Is the output signal of the carrier removal circuit. 11. A receiving apparatus comprising: an antenna for receiving a satellite broadcast radio wave or a satellite communication radio wave containing a high-frequency signal obtained by frequency-converting the modulated signal; A converter for generating a frequency signal; an intermediate frequency amplifier circuit for amplifying the intermediate frequency signal from the converter to generate an intermediate frequency amplified signal; and selecting the modulated signal from the intermediate frequency amplified signal and the variable gain. The receiving device according to claim 5, further comprising a signal selection circuit that supplies the intermediate frequency amplification circuit based on the gain control signal. 12. The receiving apparatus according to claim 5, wherein the target value is equal to a sum of a square of the detection signal of the in-phase component and a square of the detection signal of the quadrature component when there is no transmission line noise. . 13. The receiving apparatus, wherein both of the analog / digital conversion circuits are analog / digital converters.
A timing detection circuit for detecting a difference between a time at which the digital conversion is performed and the code switching time based on an output signal of the carrier removing circuit and generating a shift detection signal indicating the shift; An interpolation circuit that generates an interpolation signal of each digital signal for each code cycle based on each digital signal from both and the shift detection signal; and generates a timing signal having a cycle that is a multiple of the code cycle. An oscillation circuit that supplies the analog / digital conversion circuit to both the analog / digital conversion circuits, wherein both of the analog / digital conversion circuits perform analog / digital conversion of the analog signal from the phase demodulation circuit based on the timing signal. The receiving device according to claim 6. 14. A multiplication circuit for multiplying the remaining digital signal of the carrier by the interpolation signal of the digital signal output from the first analog / digital conversion circuit; A first roll-off filter for inputting an output signal, and a digital signal shifted by 90 degrees from the remaining digital signal of the carrier wave as the interpolation signal of the digital signal output from the second analog / digital conversion circuit. A multiplying circuit for multiplying, a second roll-off filter for inputting an output signal of the multiplying circuit, and a carrier recovery circuit for generating a digital signal of the remaining carrier based on signals from both of the roll-off filters. A signal from both the roll-off filter and an output signal of the carrier removal circuit. Receiver according to claim 13 wherein.