JP2003007866A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which the back bias effect of the semiconductor storage device comprising a charge accumulation layer and a control gate is reduced to improve integration degree, to raise the capacity ratio between a floating gate and a control gate with no increase of an occupied area, resulting in suppressed variation in cell characteristics, depending on manufacturing processes. SOLUTION: The semiconductor storage device comprises at least one memory cell composed of a semiconductor substrate, at least one island-like semiconductor layer, a charge accumulation layer formed at a part or the entire periphery of the side wall of the island-like semiconductor layer, and a control gate formed on the charge accumulation layer, and a gate electrode which is formed at least at one end of the memory cell, while arranged in series with the memory cell, to select the memory cell. A part of at least one of the charge accumulation layers is positioned in the recess formed on the side wall of the island-like semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a memory transistor having a charge storage layer and a control gate.

[0002]

2. Description of the Related Art As a memory cell of an EEPROM, a MOS transistor structure having a charge storage layer and a control gate in a gate portion and injecting charge into the charge storage layer and releasing charge from the charge storage layer by utilizing a tunnel current. Are known. In this memory cell, the difference in threshold voltage due to the difference in the charge storage state of the charge storage layer is regarded as data “0”,
It is stored as "1".

For example, in the case of an n-channel memory cell using a floating gate as a charge storage layer, in order to inject electrons into the floating gate, the source and drain diffusion layers and the substrate are grounded and a positive high voltage is applied to the control gate. Is applied. At this time, electrons are injected from the substrate side to the floating gate by the tunnel current. Due to this electron injection, the threshold voltage of the memory cell moves in the positive direction. To emit electrons from the floating gate, the control gate is grounded and a positive high voltage is applied to either the source, drain diffusion layer or the substrate. At this time, the electrons on the substrate side are emitted from the floating gate by the tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction.

In the above operation, the relationship of capacitive coupling among the floating gate, the control gate and the substrate is important in order to efficiently perform electron injection and emission, that is, writing and erasing. In other words, the larger the capacitance between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate, which facilitates writing and erasing.

However, due to recent advances in semiconductor technology, particularly advances in microfabrication technology, miniaturization and increase in capacity of EEPROM memory cells are rapidly advancing.

Therefore, how to secure a large capacity between the floating gate and the control gate while keeping the memory cell area small is an important issue.

In order to increase the capacitance between the floating gate and the control gate, the gate insulating film between them should be thinned or its permittivity should be increased, or the facing area between the floating gate and the control gate should be increased. It needs to be large.

However, thinning the gate insulating film is
There is a limit in reliability.

Increasing the dielectric constant of the gate insulating film may be achieved by using, for example, a silicon nitrogen film or the like instead of the silicon oxide film, but this is also not practical because it has a problem mainly in reliability.

Therefore, in order to secure a sufficient capacity, it is necessary to secure the overlap area between the floating gate and the control gate to be a certain value or more. This is an obstacle to achieving large capacity.

On the other hand, in the EEPROM disclosed in Japanese Patent No. 2877462, a memory transistor is formed by utilizing the side walls of a plurality of columnar semiconductor layers which are separated by lattice-striped grooves on a semiconductor substrate and arranged in a matrix. Composed. That is, the memory transistor includes a drain diffusion layer formed on the upper surface of each columnar semiconductor layer, a common source diffusion layer formed on the bottom of the groove, a charge storage layer surrounding the entire side wall of each columnar semiconductor layer, and a control gate. And the control gates are continuously arranged for a plurality of columnar semiconductor layers in one direction to form control gate lines. Also, a bit line connected to the drain diffusion layers of the plurality of memory transistors in a direction intersecting the control gate line is provided. The charge storage layer and the control gate of the memory transistor described above are formed below the columnar semiconductor layer. Also,
In the 1-transistor / 1-cell configuration, when the memory transistor is in the over-erased state, that is, when the read potential is 0 V and the threshold value is negative, the cell current flows even if it is not selected, which is inconvenient. . In order to prevent this reliably, a select gate transistor is provided which is stacked in series with the memory transistor and in which a gate electrode is formed so as to surround at least a part of the periphery of the columnar semiconductor layer. .

As a result, the conventional memory cell of the EEPROM has the charge storage layer and the control gate formed so as to surround the columnar semiconductor layer by utilizing the side wall of the columnar semiconductor layer. It is possible to secure a sufficiently large capacitance between the storage layer and the control gate. In addition, the drain diffusion layer connected to the bit line of each memory cell is
Each is formed on the upper surface of the columnar semiconductor layer and is completely electrically separated by the groove. Further, the element isolation region can be made small, and the memory cell size can be made small. Therefore, it is possible to obtain a large capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated.

FIG. 169 shows a conventional EEPROM having a columnar silicon layer 2 having a columnar shape. Also, FIG.
(A) and (b) are the EEPROM of FIG. 169, respectively.
FIG. 6 is a sectional view taken along line AA ′ and BB ′ of FIG. Note that FIG.
However, the select gate line in which the gate electrodes of the select gate transistors are continuously formed is not shown because it becomes complicated.

In this EEPROM, a p-type silicon substrate 1 is used, on which a plurality of columnar p ⁻ -type silicon layers 2 separated by lattice stripe grooves 3 are arranged in a matrix, and each of these columnar silicon layers 2 is a memory. It is a cell area. The drain diffusion layer 10 is formed on the upper surface of each silicon layer 2.
, A common source diffusion layer 9 is formed at the bottom of the groove 3, and an oxide film 4 having a predetermined thickness is buried in the bottom of the groove 3. Further, a floating gate 6 is formed below the pillar-shaped silicon layer 2 via a tunnel oxide film 5 so as to surround the circumference of the pillar-shaped silicon layer 2, and a control gate 8 is formed outside the floating gate 6 via an interlayer insulating film 7. Formed to form a memory transistor.

Here, as shown in FIGS. 169 and 170 (b), the control gate 8 is continuously arranged for a plurality of memory cells in one direction, and the control gate line, that is, the word line WL (WL1, WL2, ...). A gate electrode 32 is provided on the upper part of the pillar-shaped silicon layer 2 so as to surround the periphery thereof, similarly to the memory transistor, thereby forming a select gate transistor. Gate electrode 32 of this transistor
Are arranged continuously in the same direction as the control gate line to form the select gate line, like the control gate 8 of the memory cell.

In this way, the memory transistor and the select gate transistor are formed by being buried in the trench while being overlapped with each other. One end of the control gate line is left on the surface of the silicon layer as a contact portion 14, and the select gate line is also left a contact portion 15 on the silicon layer at the end opposite to the control gate. The Al wirings 13 and 16 to be the line CG are in contact with each other.

A common source diffusion layer 9 of the memory cell is formed on the bottom of the groove 3, and a drain diffusion layer 10 of each memory cell is formed on the upper surface of each columnar silicon layer 2.
The substrate of the memory cell thus formed is covered with a CVD oxide film 11, a contact hole is formed in the substrate, and a bit line commonly connecting the drain diffusion layers 10 of the memory cells in the direction intersecting the word line WL. BL (BL1, BL2,
.) Is provided.

When patterning the control gate line, a mask made of PEP is formed at the position of the columnar silicon layer at the end of the cell array, and the contact portion 14 made of a polycrystalline silicon film continuous with the control gate line is left on the surface of the mask. An Al film 13 which is formed at the same time as the bit line BL is brought into contact with the Al wiring 13 serving as a word line.

The above-mentioned EEPROM can be manufactured as follows.

First, a high impurity concentration p-type silicon substrate 1
A wafer in which a p ⁻ type silicon layer 2 having a low impurity concentration is epitaxially grown is used as a mask, a mask layer 21 is deposited on the surface of the wafer, and a photoresist pattern 22 is formed by a known PEP process. 21 is etched (FIG. 171 (a)).

Next, using the mask layer 21, the silicon layer 2 is etched by the reactive ion etching method to form the lattice-striped grooves 3 having a depth reaching the substrate 1.
As a result, the silicon layer 2 has a columnar shape and is separated into a plurality of islands. After that, the silicon oxide film 2 is formed by the CVD method.
3 is deposited and left on the side wall of each columnar silicon layer 2 by anisotropic etching. Then, by ion implantation of n-type impurities, the drain diffusion layers 10 are formed on the upper surfaces of the respective columnar silicon layers 2, and the common source diffusion layer 9 is formed on the bottom of the trench.
Are formed (FIG. 171 (b)).

After that, the oxide film 23 around each columnar silicon layer 2 is removed by isotropic etching, and then channel ion implantation is performed on the side wall of each silicon layer 2 by using oblique ion implantation if necessary. To do. Instead of the channel ion implantation, an oxide film containing boron may be deposited by the CVD method and boron diffusion from the oxide film may be used.

Then, a CVD silicon oxide film 4 is deposited, and this is etched by isotropic etching to fill the bottom of the groove 3 with a predetermined thickness. Then, a tunnel oxide film 5 having a thickness of, for example, about 10 nm is formed around each silicon layer 2 by thermal oxidation, and then a first-layer polycrystalline silicon film is deposited. This first-layer polycrystalline silicon film is etched by anisotropic etching to leave the lower sidewall of the columnar silicon layer 2 and form the floating gate 5 surrounding the silicon layer 2 (FIG. 172 (c)).

Next, an interlayer insulating film 7 is formed on the surface of the floating gate 6 formed around each columnar silicon layer 2. The interlayer insulating film 7 is, for example, an ONO film. And
The control gate 8 is also formed below the columnar silicon layer 2 by depositing the second-layer polycrystalline silicon film and etching by anisotropic etching (FIG. 172).
(D)). At this time, the control gate 8 sets the spacing between the pillar-shaped silicon layers 2 to a predetermined value or less in the vertical direction of FIG. 169 in advance, so that the control gate lines continuous in that direction can be obtained without using a mask process. Formed as. Then, after removing the unnecessary interlayer insulating film 7 and the tunnel oxide film 2 thereunder by etching, a CVD silicon oxide film 111 is deposited, and this is etched to the middle of the groove 3, that is, the floating gate 7 and control of the memory cell. The gate 8 is embedded until it is hidden (FIG. 173 (e)).

Then, a gate oxide film 31 of about 20 nm is formed on the exposed columnar silicon layer 2 by thermal oxidation, a third-layer polycrystalline silicon film is deposited, and this is etched by anisotropic etching to form a MOS. The gate electrode 32 of the transistor is formed (FIG. 173 (f)). This gate electrode 32 is also continuously patterned in the same direction as the control gate line to form a select gate line. The select gate line can be continuously formed by self-alignment, but it is more difficult than the case of the control gate 8 of the memory cell. Because
The memory transistor section has a two-layer gate,
Since the select gate transistor is a single-layer gate, the gate electrode spacing between adjacent cells is wider than the control gate spacing. Therefore, in order to ensure the continuity of the gate electrode 32, this is formed as a two-layer polycrystalline silicon structure, and the first polycrystalline silicon film is left only in the portion where the gate electrode is connected in the mask process, and the next polycrystalline silicon film is formed. On the other hand, the technique of leaving the side wall may be used.

A mask is formed during etching of the polycrystalline silicon film so that the contact portions 14 and 15 are formed on the upper surface of the columnar silicon layer at different ends of the control gate line and the select gate line.

Finally, a CVD silicon oxide film 112 is deposited and, if necessary, a flattening process is performed, a contact hole is opened, and Al is vapor-deposited and patterned to form an Al wiring 12 to be a bit line BL and a control gate. Al to be the line CG
The wiring 13 and the Al wiring 16 to be the word line WL are simultaneously formed (FIG. 175).

FIG. 175 shows a structure in which the cross-sectional structure of the main part of one memory cell of the EEPROM of this conventional example is replaced with a planar structure.
FIG. 175A shows an equivalent circuit, and FIG. 175B shows an equivalent circuit.

The operation of this EEPROM will be described below with reference to FIGS. 175 (a) and 175 (b).

First, in the case of using the hot carrier injection for writing, a sufficiently high positive potential is applied to the selected word line WL to select the selection control gate line CG and the selected bit line BL.
A given positive potential is applied to. As a result, a positive potential is applied to the memory transistor Q via the select gate transistor Qs.
It is transmitted to the drain of c, and a channel current is made to flow in the memory transistor Qc, hot carrier injection is performed,
The threshold value of the memory cell moves in the positive direction.

For erasing, the selection control gate CG is set to 0V,
By applying a high positive potential to the word line WL and the bit line BL,
The electrons of the floating gate are emitted to the drain side. In the case of batch erasing, a high positive potential can be applied to the common source to emit electrons to the source side. As a result, the threshold value of the memory cell moves in the negative direction.

In the read operation, the select gate transistor Qs is opened by the word line WL, the read potential of the control gate line CG is applied, and "0" or "1" is discriminated by the presence or absence of current. When using FN tunneling for electron injection, a high positive potential is applied to the selection control gate line CG and the selection word line WL, the selected bit line BL is set to 0 V, and electrons are injected from the substrate to the floating gate.

Since this EEPROM has the select gate transistor, it does not malfunction even in the overerased state.

By the way, in this conventional EEPROM, as shown in FIG. 175 (a), there is no diffusion layer between the select gate transistor Qs and the memory transistor Qc. This is because it is difficult to selectively form the diffusion layer on the side surface of the columnar silicon layer. Therefore,
In the structure of FIGS. 170A and 170B, it is desirable that the isolation oxide film between the gate portion of the memory transistor and the gate portion of the select gate transistor be as thin as possible. In particular, when using hot electron injection, sufficient "H" is applied to the drain part of the memory transistor.
In order to transmit the level potential, this isolation oxide film thickness is 30
It is necessary to be about 40 nm.

Such a minute interval is practically difficult only by burying the oxide film by the CVD method described in the previous manufacturing process. Therefore, the method of forming a thin oxide film on the exposed portions of the floating gate 6 and the control gate 8 at the same time in the step of gate oxidation for the select gate transistor is performed by burying the CVD oxide film with the floating gate 6 and the control gate 8 exposed. desirable.

Further, according to this conventional example, a columnar silicon layer is arranged with the bottom of the lattice-stripe-shaped groove as an isolation region, and a memory cell having a floating gate formed so as to surround the periphery of the columnar silicon layer is formed. Therefore, a highly integrated EEPROM having a small occupied area of memory cells can be obtained. Moreover, despite the small occupied area of the memory cell,
A sufficiently large capacitance between the floating gate and the control gate can be secured.

In the conventional example, the control gate of each memory cell is formed so as to be continuous in one direction without using a mask. This is possible only if the arrangement of the pillar-shaped silicon layers is not symmetrical. That is, by making the interval between the columnar silicon layers adjacent to each other in the word line direction smaller than that in the bit line direction, the control gate lines which are separated in the bit line direction and are connected to the word line direction are automatically obtained without a mask. . On the other hand, for example, when the columnar silicon layers are arranged symmetrically, the PEP process is required.

More specifically, the second-layer polycrystalline silicon film is deposited thickly, and after the PEP process, selective etching is performed so as to leave it in a portion to be continued as a control gate line. Then, a third-layer polycrystalline silicon film is deposited, and sidewall etching is performed in the same manner as described above.

Even if the columnar silicon layers are not arranged symmetrically, depending on the spacing of the arrangement, it may not be possible to automatically form a continuous control gate line as in the conventional example.

Even in such a case, the control gate line continuous in one direction may be formed by using the mask process as described above.

Further, in the conventional example, the memory cell having the floating gate structure is used, but the charge storage layer does not necessarily have to have the floating gate structure, and the charge storage layer is realized by trapping in the multilayer insulating film. For example, it is also effective in the case of the MNOS structure.

FIG. 176 shows a memory cell having such an MNOS structure. The memory cell of the MNOS structure of FIG. 176 corresponds to the memory cell of FIG. 170 (a).

The laminated insulating film 24 serving as a charge storage layer has a laminated structure of a tunnel oxide film and a silicon nitride film or a structure in which an oxide film is further formed on the surface of the nitride film.

In the above-mentioned MNOS, a conventional example in which a memory transistor and a select gate transistor are reversed, that is, a memory cell in which a select gate transistor is formed below the columnar silicon layer 2 and a memory transistor is formed above It is shown in FIG. 177.

This structure in which the select gate transistor is provided on the common source side can be adopted when the hot electron injection method is used as the writing method.

FIG. 178 shows a conventional example in which a plurality of memory cells are formed in one columnar silicon layer. The parts corresponding to those of the above-mentioned conventional example are denoted by the same reference numerals as those of the above-mentioned conventional example, and detailed description thereof is omitted. In this conventional example, a select gate transistor Qs1 is formed at the bottom of the pillar-shaped silicon layer 2, and three memory transistors Qc1, Qc2, Qc are formed thereon.
3 on top of it, and select gate transistor Q on top of it
s2 is formed. This structure is basically obtained by repeating the manufacturing process described above.

Also in the conventional example shown in FIGS. 177 and 178, the MNOS structure can be used as the memory transistor instead of the floating gate structure.

As described above, according to the above-mentioned conventional technique, a memory cell using a memory transistor having a charge storage layer and a control gate is formed by utilizing the side wall of the columnar semiconductor layer separated by the lattice stripe groove. By doing so, the capacitance between the control gate and the charge storage layer is sufficiently large, and the area occupied by the memory cell is reduced to achieve high integration.
EPROM can be obtained.

[0049]

In the above-mentioned conventional example, the charge storage layer and the control gate are formed in self-alignment with the columnar semiconductor layer, but the columnar semiconductor layer is the smallest when considering the capacity increase of the cell array. It is desirable to form with processing dimensions. Here, when a floating gate is used as the charge storage layer, the relationship of capacitive coupling among the floating gate, the control gate, and the substrate is as follows:
It is determined by the tunnel oxide film thickness that insulates the columnar semiconductor layer and the floating gate and the interlayer insulating film thickness that insulates the floating gate and the control gate.

In the conventional example, a side wall of the columnar semiconductor layer is used to have a charge storage layer and a control gate formed so as to surround the columnar semiconductor layer, and the capacitance between the charge storage layer and the control gate is small in an occupied area. However, when the columnar semiconductor layer is formed with the minimum processing size and the tunnel oxide film thickness and the interlayer insulating film thickness are fixed, the charge storage layer and the control gate are The capacitance of is simply determined by the area around the floating gate, that is, the film thickness of the floating gate. Therefore, it is difficult to increase the capacitance between the charge storage layer and the control gate without increasing the occupied area of the memory cell. In other words, it is difficult to increase the ratio of the capacitance of the floating gate and the control gate to the capacitance of the floating gate and the island-shaped semiconductor layer without increasing the occupied area of the memory cell.

Further, in the conventional example, the impurity diffusion layer is not formed between the memory cells included in one columnar semiconductor layer, but it is preferable to form the impurity diffusion layer.

Further, in the conventional example, when it is considered that a plurality of memory cells are connected in series to one columnar semiconductor layer and the threshold value of each memory cell is the same, the control gate line C
In a read operation in which a read potential is applied to G to determine “0” and “1” depending on the presence or absence of a current, in memory cells located at both ends connected in series, the threshold value fluctuates due to the back bias effect from the substrate. Becomes noticeable. As a result, the number of memory cells connected in series is limited on the device, which becomes a problem when the capacity is increased.

This is true not only in the case where a plurality of memory cells are connected in series to one columnar semiconductor layer but also in the in-plane direction when one memory cell is formed in one columnar semiconductor layer. There is also a problem that the threshold value of each memory cell varies due to variations in the back bias effect from the substrate.

When forming a transistor in the direction perpendicular to the substrate, the height of the columnar semiconductor layer increases as the number of steps increases, and a higher level trench etching process is performed to form the columnar semiconductor layer. Technology is required.

Further, in forming the columnar semiconductor layer by trench etching, for example, when the columnar semiconductor layer is formed into a columnar shape and the diameter thereof is equal to the distance between the columnar semiconductor layers, the aperture ratio is about 80.4%. Therefore, it becomes very difficult to process and form the columnar semiconductor layer in a shape closer to the vertical with respect to the semiconductor substrate. It is desirable to have a low aperture ratio when performing trench etching, but in the conventional example, the control gate line and select gate line are arranged so as to be continuous automatically, so that the capacitance between the charge storage layer and the control gate is secured. In addition, there is a limit in reducing the distance between the columnar semiconductor layers with respect to the diameter of the columnar semiconductor layer without increasing the occupied area of the memory cell, and it is difficult to reduce the aperture ratio.

Further, when the gate electrode of the transistor is formed in each stage, variations in the gate length due to process variations occur. For example, when the gate electrode is formed in a sidewall shape, the deposited electrode material film needs to be etched back to a level comparable to the height of the columnar semiconductor layer. That is, when the capacity is increased, the number of memory gates formed in the columnar semiconductor layer also increases, so that the height of the columnar semiconductor layer inevitably increases. Therefore, the amount of etch back also increases, and the process variation also increases. These influences become remarkable when the capacity of the cell array is increased.

When transistors are formed in the direction perpendicular to the substrate, if transistors are formed in each stage,
Variations in cell characteristics due to differences in tunnel film quality due to differences in thermal history between stages and differences in diffusion layer profiles occur.

The present invention has been made in view of these problems and has a structure in which the electric field transmitted from the control gate to the active region of the memory cell is increased instead of increasing the capacitance between the charge storage layer and the control gate. By obtaining high-speed device characteristics and reducing the influence of the back bias effect of a semiconductor memory device having a charge storage layer and a control gate, the degree of integration can be improved and the height of a columnar semiconductor layer can be reduced. By facilitating the processing during the trench etching of the columnar semiconductor layer and reducing the aperture ratio during the trench etching of the columnar semiconductor layer without increasing the occupied area of the memory cell, the shape closer to vertical to the semiconductor substrate can be obtained. To form a columnar semiconductor layer with
Another object of the present invention is to provide a semiconductor memory device capable of suppressing variations in characteristics of memory cells by minimizing the iterative history of thermal history of each memory cell transistor.

[0059]

According to the present invention, a semiconductor substrate, at least one island-shaped semiconductor layer, and a charge storage layer formed on all or part of the periphery of the sidewall of the island-shaped semiconductor layer are provided. And at least one memory cell composed of a control gate formed on the charge storage layer and at least one end of the memory cell, and being arranged in series with respect to the memory cell. A semiconductor memory device comprising a gate electrode for selecting a memory cell, wherein at least one of the charge storage layers is partially disposed inside a recess formed in a sidewall of the island-shaped semiconductor layer. A semiconductor memory device is provided.

That is, in the semiconductor device of the present invention, the side surface obtained by processing the semiconductor substrate or the semiconductor layer into a column having at least one depression is used as the active region surface, and the tunnel oxide film and the charge storage layer are arranged inside the depression. Become.

[0061]

BEST MODE FOR CARRYING OUT THE INVENTION In the semiconductor memory device of the present invention, the charge storage layer and the control gate may be formed over the entire periphery of the sidewall of the island-shaped semiconductor layer, or a part of the peripheral region may be formed. It may be formed in a region other than the above.

Further, only one memory cell may be formed in one island-shaped semiconductor layer, or two or more memory cells may be formed. When three or more memory cells are formed, a select gate is formed in the lower and / or upper part of the memory cell, and a select transistor including the select gate and the island-shaped semiconductor layer is formed. Is preferred.

In the semiconductor device of the present invention, "at least one of the memory cells is" electrically insulated "from the semiconductor substrate means that the semiconductor substrate and the island-shaped semiconductor layer are electrically insulated from each other. When two or more memory cells are formed, the memory cells located above the insulated location are electrically insulated from the semiconductor substrate by electrically insulating the memory cells from each other. May be electrically isolated from each other. Further, as will be described later, when a select gate (gate electrode) is optionally formed below the memory cell, a select transistor and a semiconductor formed by the select gate are formed. It may be electrically insulated from the substrate, and may be electrically insulated from the select transistor and the memory cell so that it is higher than the insulated region. Memory cells may be one that is electrically insulated from the semiconductor substrate located. In particular, when the select transistor is formed between the semiconductor substrate and the island-shaped semiconductor layer or under the memory cell,
It is preferable that the selection transistor and the semiconductor substrate are electrically insulated. The electrical insulation may be performed, for example, by forming an impurity diffusion layer having a conductivity type different from that of the semiconductor substrate over the entire region to be insulated, or by forming an impurity diffusion layer in a part of the region to be insulated. May be formed and the depletion layer at the junction may be utilized, or may be spaced so that it is not electrically conductive, resulting in electrical insulation. . Further, the semiconductor substrate and the cell or the selection transistor may be electrically insulated by an insulating film such as SiO ₂ . In addition, when a plurality of memory cells are formed, and when a select transistor is formed above and below the memory cell, a space between arbitrary memory cells and / or a space between the select transistor and the memory cells is arbitrarily formed. , May be electrically insulated. Embodiment in plan view of memory cell array In a memory cell array of a semiconductor memory device of the present invention described below, a plurality of memory cells having a charge storage layer and a third electrode to be a control gate are connected in series in a direction perpendicular to a semiconductor substrate surface. A plurality of memory cells are formed on the sidewalls of a semiconductor substrate and a plurality of island-shaped semiconductor layers arranged in a matrix on the semiconductor substrate and separated in a grid pattern, and the charge At least a part of the storage layer is provided inside the recess formed in the sidewall of the island-shaped semiconductor layer and has a source or drain of a memory cell which is an impurity diffusion layer arranged in the island-shaped semiconductor layer. A plurality of island-shaped semiconductor layers extending in the same direction and having a control gate line which is a third wiring continuously arranged in the horizontal direction with respect to the semiconductor substrate surface. It has a bit line which is a fourth wiring electrically connected to the impurity diffusion layer in the intersecting direction and arranged in the horizontal direction with respect to the semiconductor substrate surface, and further has a second wiring or a fifth wiring. And a source line which is a first wiring. In the present invention, the control gate line and the bit line orthogonal to the control gate line may be three-dimensionally formed in any direction.

Plan views of the memory cell array will be collectively described with reference to FIGS.

1 to 8 are plan views showing a memory cell array of an EEPROM having a floating gate as a charge storage layer. Note that FIGS. 1 to 8 show cross-sections in which the diameter of the island-shaped semiconductor layer 110 that forms the memory cell is small, that is, a dent portion.

In FIG. 1, the columnar island-shaped semiconductor portions forming the memory cells are arranged, for example, at the intersections of two kinds of parallel lines, and each memory cell is selected and controlled. The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer for achieving the above are memory cell arrays arranged in parallel to the substrate surface.

In addition, the AA 'direction which is the direction intersecting with the fourth wiring layer 840 and the BB' direction which is the direction of the fourth wiring layer 840.
By changing the arrangement interval of the island-shaped semiconductor parts depending on the direction,
The second conductive film, which is the control gate of each memory cell, is continuously formed in one direction, that is, in the AA ′ direction in FIG. 1, to form a third wiring layer. Similarly, the second conductive film which is the gate of the select gate transistor is continuously formed in one direction to form the second wiring layer.

Further, a terminal for electrically connecting to the first wiring layer arranged on the substrate side of the island-shaped semiconductor portion is
For example, A'of a memory cell connected in the AA 'direction in FIG.
A terminal for electrically connecting to the second wiring layer and the third wiring layer provided at the end portion on the side of the memory cell, for example, on the end portion on the A side of the memory cell connected in the AA 'direction in FIG. A fourth wiring layer 840 provided and arranged on the side of the island-shaped semiconductor portion opposite to the substrate.
Is electrically connected to each of the columnar island-shaped semiconductor portions forming the memory cell. For example, in FIG. 1, a fourth wiring is formed in a direction intersecting the second wiring layer and the third wiring layer. A layer 840 has been formed.

Further, the terminal for electrically connecting to the first wiring layer is formed of the island-shaped semiconductor portion, and is electrically connected to the second wiring layer and the third wiring layer. The terminal is formed of a second conductive film that covers the island-shaped semiconductor portion. Further, the terminals for electrically connecting to the first wiring layer, the second wiring layer, and the third wiring layer are the first contact portion 910, the second contact portions 921, 924, and the third contact portion, respectively. It is connected to the contact parts 932 and 933.

In FIG. 1, the first wiring layer 810 is drawn out to the upper surface of the semiconductor memory device via the first contact portion 910. Note that the columnar island-shaped semiconductor portions forming the memory cells do not have to be arranged as shown in FIG. 1, and if the positional relationship of the wiring layers and the electrical connection relationship are as described above,
The array of cylindrical island-shaped semiconductor portions forming the memory cell is not limited.

The island-shaped semiconductor portion connected to the first contact portion 910 is arranged at all end portions on the A'side of the memory cell connected in the AA 'direction in FIG. It may be arranged at a part or all of the end portion on the side, and any of the island-shaped semiconductor portions forming the memory cells connected in the AA ′ direction which is the direction intersecting with the fourth wiring layer 840. It may be placed in the crab. In addition, the island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 921 and 924 and the third contact portions 932 and 933 has an end on the side where the first contact portion 910 is not arranged. May be arranged in a portion, or may be continuously arranged at the end portion on the side where the first contact portion 910 is arranged, or may be a direction intersecting with the fourth wiring layer 840 AA ′.
May be arranged in any of the island-shaped semiconductor portions forming the memory cells connected in the direction, and the second contact portion 921
, 924, the third contact portion 932 and the like may be arranged separately.

In addition, the first wiring layer 810 and the fourth wiring layer 840
May have any width and shape as long as a desired wiring can be obtained. When the first wiring layer arranged on the substrate side of the island-shaped semiconductor portion is formed in self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film, The island-shaped semiconductor portion that serves as a terminal for electrically connecting to the wiring layer is electrically insulated from the second wiring layer and the third wiring layer formed of the second conductive film. , And are in contact with each other through the insulating film. For example, in FIG. 1, a first conductive film is formed on a part of the side surface of the island-shaped semiconductor portion to which the first contact portion 910 is connected via an insulating film, and the first conductive film forms a memory cell. The second conductive film is formed between the island-shaped semiconductor portion that is formed and the side surface of the first conductive film with an insulating film interposed therebetween. The second wiring layer and the third wiring layer, which are continuously formed, are connected to each other in the AA ′ direction which is a direction intersecting with the fourth wiring layer 840. The shapes of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion do not matter. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is set to, for example, the second The thickness of the conductive film may be twice or less, so that the first conductive film on the side surface of the island-shaped semiconductor portion that serves as a terminal for electrically connecting to the first wiring layer may be entirely removed.

In FIG. 1, the second and third contact portions are formed on the second wiring layers 821, 824, the third wiring layer 832, etc. formed so as to cover the tops of the island-shaped semiconductor portions. However, the shapes of the second and third wiring layers do not matter as long as they can be connected to each other. The selection gate transistor is omitted in FIG. 1 because it becomes complicated. In FIG. 1, cross sections used in the manufacturing process example, that is, AA ′ cross section, BB ′ cross section, CC ′ cross section, DD ′ cross section, EE ′ cross section, and F−
The F'section is also shown.

FIG. 2 shows an example in which a memory cell continuous in the AA ′ direction is divided into two as shown in FIG. 2 as compared with FIG. As shown in FIG. 2, all the memory cells continuous in the AA ′ direction may be divided, or
At least one of the memory cells continuous in the A ′ direction may be divided. Note that the positions where the first contacts 910 and the second contacts 921 to 924 are arranged are not limited as long as desired wiring can be drawn out.

In FIG. 2, the cross sections used in the manufacturing process example, that is, the AA 'cross section and the BB' cross section are shown together.

FIG. 3 shows an arrangement in which the columnar island-shaped semiconductor portions forming the memory cells are arranged, for example, at the intersections of two types of parallel lines that are not orthogonal to each other. The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer for selecting and controlling the memory cell array are parallel to the substrate surface.

A direction crossing the fourth wiring layer 840
By changing the arrangement interval of the island-shaped semiconductor portions in the −A ′ direction and the BB ′ direction in the figure, the second conductive film which is the control gate of each memory cell is unidirectional, and in FIG. The third wiring layer is formed continuously in the A'direction. Similarly, the second conductive film which is the gate of the select gate transistor is continuously formed in one direction to form the second wiring layer.

Further, a terminal for electrically connecting to the first wiring layer arranged on the substrate side of the island-shaped semiconductor portion is
For example, A'of a memory cell connected in the AA 'direction in FIG.
A terminal for electrically connecting to the second wiring layer and the third wiring layer provided at the end portion on the side of the memory cell, for example, on the end portion on the A side of the memory cell connected in the AA ′ direction in FIG. A fourth wiring layer 840 provided and arranged on the side of the island-shaped semiconductor portion opposite to the substrate.
Is electrically connected to each of the columnar island-shaped semiconductor portions forming the memory cell. For example, in FIG. 3, a fourth wiring is formed in a direction intersecting the second wiring layer and the third wiring layer. A layer 840 has been formed.

Further, the terminal for electrically connecting to the first wiring layer is formed of the island-shaped semiconductor portion, and is electrically connected to the second wiring layer and the third wiring layer. The terminal is formed of a second conductive film that covers the island-shaped semiconductor portion. The terminals for electrically connecting to the first wiring layer, the second wiring layer, and the third wiring layer are respectively the first contact portion 910, the second contact portions 921, 924, and the third contact portion. It is connected to 932 and 933.

In FIG. 3, the first wiring layer 810 is drawn out to the upper surface of the semiconductor memory device via the first contact portion 910.

The columnar island-shaped semiconductor portions forming the memory cells may not be arranged as shown in FIG.
The arrangement of the columnar island-shaped semiconductor portions forming the memory cell is not limited as long as the positional relationship and the electrical connection relationship of the wiring layers are as described above. In addition, the island-shaped semiconductor portion connected to the first contact portion 910 is arranged at all end portions on the A ′ side of the memory cell connected in the AA ′ direction in FIG. May be placed on part or all of the end of
It may be arranged in any of the island-shaped semiconductor portions forming the memory cells connected in the AA ′ direction which is the direction intersecting with the fourth wiring layer 840. The island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 921 and 924 and the third contact portions 932 and 933 is the first contact portion 91.
It may be arranged at the end on the side where 0 is not arranged, may be arranged continuously at the end on the side where the first contact portion 910 is arranged, or intersects with the fourth wiring layer 840. A- which is the direction
It may be arranged in any of the island-shaped semiconductor portions forming the memory cells connected in the A ′ direction, or the second contact portions 921, 924, the third contact portion 932, etc. may be divided and arranged. May be. The first wiring layer 810 and the fourth wiring layer 840 may have any width and shape as long as desired wiring can be obtained.

When the first wiring layer formed on the substrate side of the island-shaped semiconductor portion is formed in self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film , The island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer is electrically insulated from the second wiring layer and the third wiring layer formed of the second conductive film. However, they may be in contact with each other through the insulating film. For example, in FIG.
A first conductive film is formed on a part of the side surface of the island-shaped semiconductor portion to which the first contact portion 910 is connected via an insulating film, and the first conductive film forms a memory cell. A second conductive film is formed between the island-shaped semiconductor portion and a side surface of the first conductive film via an insulating film, and the second conductive film is a fourth wiring layer. A that intersects with 840
In the −A ′ direction, the second wiring layer and the third wiring layer, which are continuously formed, are connected. The shapes of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion do not matter.

Further, the distance between the island-shaped semiconductor portion serving as a terminal for electrically connecting to the first wiring layer and the first conductive film in the island-shaped semiconductor portion in which the memory cell is formed is set to, for example, By making the thickness of the second conductive film less than or equal to twice the thickness of the second conductive film, all the first conductive film on the side surface of the island-shaped semiconductor portion, which serves as a terminal for electrically connecting to the first wiring layer, is removed. Good. In FIG. 3, the second and third contact portions are the second wiring layer 82 formed so as to cover the tops of the island-shaped semiconductor portions.
Although it is formed on the first, 824, and third wiring layers 832, etc., the shapes of the second and third wiring layers do not matter as long as they can be connected to each other.

In FIG. 3, the select gate transistor is omitted because it is complicated. Further, the cross sections used in the manufacturing process examples, that is, the AA ′ cross section and the BB ′ cross section are also shown.

4 and 5 are different from FIGS. 1 and 3 in that the island-shaped semiconductor portion forming the memory cell has a quadrangular cross-sectional shape. Examples of different directions are shown. The sectional shape of the island-shaped semiconductor portion is not limited to a circle or a quadrangle. For example, it may be oval, hexagonal or octagonal. However, if the size of the island-shaped semiconductor part is near the processing limit, even if it has a corner such as a square, hexagon, or octagon at the time of design, the corner will be rounded due to the photo process or etching process. The cross-sectional shape of the island-shaped semiconductor portion approaches a circle or an ellipse. The selection gate transistor is omitted in FIGS. 4 and 5 because it becomes complicated.

In contrast to FIG. 1, FIG. 6 shows an example in which the number of memory cells formed in series in the island-shaped semiconductor portion forming the memory cells is two and no select gate transistor is formed. In FIG. 6, the cross section used for the manufacturing process example, that is, the AA ′ cross section and the BB ′ cross section are shown together.

FIG. 7 is different from FIG. 1 in that the cross section of the island-shaped semiconductor portion forming the memory cell is not a circle but an ellipse, and the major axis of the ellipse is in the BB ′ direction. An example of the case is shown. FIG. 8 shows a case in which the direction of the major axis of the ellipse is the AA ′ direction with respect to FIG. 7. The direction of the major axis of this ellipse is not limited to the AA 'direction and the BB' direction, but may be any direction. The selection gate transistor is omitted in FIGS. 7 and 8 because it becomes complicated.

The plan view of the semiconductor memory device having the floating gate as the charge storage layer has been described above.
The arrangement and structure of FIG. 8 may be used in various combinations. Embodiment in Cross Section of Memory Cell Array FIGS. 9 to 22 are cross sectional views of a semiconductor memory device having a floating gate as a charge storage layer. 9 to 22.
In the cross-sectional view of FIG.
FIG. 3 is a sectional view taken along the line A ′, and the even numbered drawings are BB ′ in FIG. 1.
FIG.

In these embodiments, a plurality of columnar island-shaped semiconductor layers 110 having, for example, at least one depression are arranged in a matrix on the p-type silicon substrate 100.
Transistors having a second electrode or a fifth electrode serving as a selection gate are arranged above and below each of the island-shaped semiconductor layers 110, and a plurality of memory transistors are sandwiched between the selection gate transistors, as shown in FIGS. In FIG. 22, for example, two transistors are arranged and each transistor is connected in series along the island-shaped semiconductor layer. That is, the silicon oxide film 460, which is an eighth insulating film having a predetermined thickness, is arranged at the bottom of the groove between the island-shaped semiconductor layers, and the gate insulating film thickness is formed on the sidewalls of the island-shaped semiconductor layer so as to surround the periphery of the island-shaped semiconductor layer 110. A second electrode 500 serving as a selection gate is arranged via the above to form a selection gate transistor, and a tunnel oxide film is formed inside the depression formed above the selection gate transistor so as to surround the periphery of the island-shaped semiconductor layer 110. The floating gate 510 is disposed via the control gate 420, and the control gate 5 is provided outside the floating gate 510 via the interlayer insulating film 610 made of a multilayer film.
20 is arranged to form a memory transistor.

Further, a transistor having a fifth electrode 500 serving as a selection gate is arranged above the memory transistors similarly arranged as above.

In addition, the selection gate 500 and the control gate 5
As shown in FIGS. 1 and 10, reference numeral 20 is a control gate that is continuously arranged for a plurality of transistors in one direction and is a selection gate line that is a second wiring or a fifth wiring and a third wiring. It is a gate line.

On the surface of the semiconductor substrate, the source diffusion layer 710 of the memory cell is arranged, and further, the diffusion layer 720 is arranged between the memory cells and between the select gate transistor and the memory cell to form each island shape. A drain diffusion layer 725 for each memory cell is arranged on the upper surface of the semiconductor layer 110. Note that, instead of arranging the source diffusion layer 710 of the memory cell so that the active region of the memory cell is in a floating state with respect to the semiconductor substrate, an insulating film is inserted below the surface of the semiconductor substrate, For example, an SOI substrate may be used. An oxide film 460, which is an eighth insulating film, is arranged between the memory cells arranged in this way so that the upper part of the drain diffusion layer 725 is exposed, and the drain diffusion of the memory cell in the direction intersecting the control gate line is formed. Layer 725
An Al wiring 840 which serves as a bit line for commonly connecting is provided.

The impurity concentration distribution of the diffusion layer 720 is not uniform, but, for example, impurities are introduced into the island-shaped semiconductor layer 110 and a thermal diffusion process is performed to perform the island-shaped semiconductor layer 110.
It is preferable that the distribution be such that the concentration gradually decreases from the surface to the inside. This improves the junction breakdown voltage between the diffusion layer 720 and the island-shaped semiconductor layer 110, and also reduces the parasitic capacitance. Similarly, the source diffusion layer 710
Regarding the impurity concentration distribution of, it is preferable that the impurity concentration distribution is such that the concentration gradually decreases from the surface of the semiconductor substrate 100 toward the inside of the semiconductor substrate. This improves the junction breakdown voltage between the source diffusion layer 710 and the semiconductor substrate 100, and also reduces the parasitic capacitance in the first wiring layer.

9 and 10 show an example in which the outer periphery of the floating gate is equal (flush) to the outer periphery of the island-shaped semiconductor layer 110.

11 and 12 show an example in which the diffusion layer 720 is not arranged between the respective transistors.

In FIG. 13 and FIG. 14, the diffusion layer 720 is not provided and the memory transistor and the select gate.
Transistor gate electrodes 500, 510, 520
And a polycrystalline silicon film 53 which is a third electrode arranged between
An example in which 0 is formed is shown. The polycrystalline silicon film 530, which is the third electrode, is omitted in FIG. 1 because it is complicated.

15 and 16 show an example of the case where the interlayer insulating film 610 is formed of a single layer film.

FIGS. 17 and 18 show an example in which the material of one gate is different from the material of the other gate, in which the control gate 520 and the floating gate 510 of the memory cell are different.

19 and 20 show an example in which the outer circumference of the floating gate is smaller than the outer circumference of the island-shaped semiconductor layer 110, as compared with FIGS. 9 and 10.

21 and 22 show an example in which the outer periphery of the floating gate is larger than the outer periphery of the island-shaped semiconductor layer 110, as compared with FIGS. 9 and 10. Embodiment in Operation Principle of Memory Cell Array The above-mentioned semiconductor memory device has a memory function depending on the state of charges accumulated in the charge accumulation layer. The operation principle of reading, writing, and erasing will be described below by taking a memory cell having a floating gate as a charge storage layer as an example. An array structure of a semiconductor memory device of the present invention has a transistor including a second electrode as a gate electrode and a transistor including a fifth electrode as a gate electrode as a select gate transistor, and between the select gate transistors. A plurality of memory cells having a third electrode as a control gate electrode having a charge storage layer, for example L (L is a positive integer),
It has island-shaped semiconductor layers connected in series, and includes a plurality of the island-shaped semiconductor layers, for example, M × N (M and N are positive integers). In this memory cell array, a plurality of, for example, M, fourth wirings arranged in parallel to the semiconductor substrate are connected to one end of each of the island-shaped semiconductor layers, and the other end is connected to the other end. The first wiring is connected. Further, a plurality of, for example, N ×, arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring.
The L third wirings are connected to the third electrodes of the memory cells, and the first wirings are arranged in parallel to the third wirings. FIG. 23 shows an equivalent circuit of the above memory cell array structure. Note that the definition of writing in the memory cell is, for example, a threshold of the memory cell is 0.5 V or more, and the definition of erasing is, for example, the threshold of the memory cell is −0.5 V or less. First, as an example of a reading method, FIG. 28 illustrates an example of timing of potentials applied to each electrode in reading. First, the first wiring (1-1 ~ 1-
N), the second wiring (2-1 to 2-N), the third wiring (3-1-1 to 3-NL), the
4 wiring (4-1 to 4-M), 5th wiring (5-1 to 5-N),
For example, from a state where 0V is applied, for example, 3V is applied to the fourth wiring (4-i), then 3V is applied to the second wiring (2-j), and the fifth wiring (5-j) is applied. ) To the third wiring (≠ 3-jh) other than the third wiring (3-jh).
Give V. Thereby, “0” or “1” is determined by the current flowing through the fourth wiring (4-i) or the current flowing through the first wiring (1-j).

After that, the third wiring (≠ 3-jh) other than the third wiring (3-jh) is returned to, for example, 0V, and the second wiring (≠ 2-j) is returned.
And the fifth wiring (≠ 5-j) is returned to, for example, 0 V, and the fourth wiring
(4-i) is returned to 0V, for example. At this time, the timings at which the potentials are applied to the respective wirings may be changed or may be the same.

Further, in the above description, the reading method when the memory cell having the third wiring (3-jh) as the gate electrode is the selected cell has been described, but the reading method other than the third wiring (3-jh) is described. 3
The same applies when a memory cell having one of the wirings as a gate electrode is a selected cell. 3rd wiring (3-jL) to 3rd
The wiring (3-j-1) may be read continuously, or in the reverse order or randomly. Furthermore, reading of a plurality or all of the memory cells connected to the third wiring (3-jh) may be performed simultaneously. By arranging the select gates above and below the plurality of memory cell portions in this way, when the memory cell transistor is in the over-erased state, that is, when the threshold value is in the negative state, the non-selected cells are For example, it is possible to prevent a phenomenon in which a cell current flows at a read gate voltage of 0V.

As an example of the writing method, FIG. 29 shows an example of the timing of the potential applied to each electrode in writing. First the first wiring (1-1 ~ 1-N), the second wiring (2-1 ~ 2-N),
0V is applied to the third wiring (3-1-1 to 3-NL), the fourth wiring (4-1 to 4-M), and the fifth wiring (5-1 to 5-N), respectively. 3V to the fourth wiring (≠ 4-i) other than the fourth wiring (4-i), and then to the fifth wiring (5-j), for example, 1V
And the third wire (≠ 3-j-) other than the third wire (3-jh)
For example, 3V is applied to h) and the second wiring (3-jh) is connected to, for example, 2V.
Give 0V. By holding this state for a desired time, a high potential is applied only between the channel section and control gate of the selected cell, and the Fowler-Nordheim tunneling phenomenon (hereinafter referred to as FN tunneling phenomenon) accumulates charge from the channel section. Electrons are injected into the layer. It is to be noted that the fourth wiring (≠ 4-i) excluding the fourth wiring (4-i) is provided with a fifth electrode in the island-shaped semiconductor layer not including the selected cell by applying, for example, 3V. The gate transistor is cut off and no writing is done. After that, for example, the third wiring (3-jh) is returned to, for example, 0 V, and then the second wiring (2-j) and the fifth wiring (5-j) are set to 0 V, for example.
After returning to V, the third wiring (≠ 3-jh) other than the third wiring (3-jh) is returned to 0V, for example, and the fourth wiring (4-i) is returned to 0V, for example. At this time, the timings at which the potentials are applied to the respective wirings may be changed or may be the same. Also,
The applied potential may be any combination of potentials as long as it satisfies the condition for storing a certain amount or more of negative charges in the charge storage layer of a desired cell. In the above, the writing method when the memory cell having the third wiring (3-jh) as the gate electrode is the selected cell has been described, but one of the third wirings other than the third wiring (3-jh) is described. The same is applied to the writing method when the memory cell having one of them as the gate electrode is the selected cell.

Also, from the third wiring (3-jL) to the third wiring (3-jL)
You can write continuously up to -1), or in the reverse order,
It may be random. Further, writing to a plurality or all of the memory cells connected to the third wiring (3-jh) may be performed at the same time. FIG. 34 shows an example of the timing of the potential applied to each electrode as a case where writing is performed without cutting off the select gate transistor including the fifth electrode in the island-shaped semiconductor layer that does not include the selected cell.

First, the first wiring (1-1 to 1-N) and the second wiring (2-
1 to 2-N), 3rd wiring (3-1-1 to 3-NL), 4th wiring (4-1 to 4-N)
M) and the fifth wiring (5-1 to 5-N), for example, from the state where 0 V is applied, the fourth wiring (≠ 4−) other than the fourth wiring (4-i)
i), for example, 7V, then, to the fifth wiring (5-j), for example, 20V, the third wiring other than the third wiring (3-jh)
For example, 3V is applied to (≠ 3-jh), and 20V is applied to the third wiring (3-jh). By maintaining this state for a desired period of time, it is possible to reduce the gap between the channel portion of the selected cell and the control gate.
A potential difference of about 0 V is generated, and electrons are injected from the channel portion into the charge storage layer by the FN tunneling phenomenon to perform writing. A potential difference of about 13V occurs between the control gate and the channel portion of the non-selected cell connected to the third wiring (3-jh), but the threshold value of this cell is changed within the write time of the selected cell. Sufficient electron injection to cause this is not possible, and thus writing of this cell is not realized. After that, for example, the third wiring (3-jh) is returned to, for example, 0 V, and then the fifth wiring (5-j) is returned to, for example, 0 V, and the third wiring (3
The third wiring (≠ 3-jh) other than -jh) is returned to 0V, for example, and the fourth wiring (≠ 4-i) is returned to 0V, for example. At this time, the timing of applying a potential to each wiring may be before or after or at the same time. Further, the applied potential may be any combination of potentials as long as it satisfies the condition for storing a certain amount or more of negative charges in the charge storage layer of a desired cell.

In the above description, the writing method in the case where the memory cell using the third wiring (3-jh) as the gate electrode is the selected cell has been described, but the third programming method other than the third wiring (3-jh) is described. The writing method when the memory cell having one of the wirings as the gate electrode as the selected cell is similarly performed.

Also, from the third wiring (3-jL) to the third wiring (3-jL)
You can write continuously up to -1), or in the reverse order,
It may be random. Further, writing to a plurality or all of the memory cells connected to the third wiring (3-jh) may be performed simultaneously. As an example of the erasing method, FIG. 30 shows an example of the timing of the potential applied to each electrode in the erasing.
The erase unit is one block or a batch of chips as in the selection range shown in FIG.

First, the first wiring (1-1 to 1-N), the second wiring
(2-j), third wiring (3-1-1 to 3-NL), fourth wiring (4-1 to 4-M),
For example, from the state where 0V is applied to each of the fifth wires (5-j), 20V is applied to the fourth wires (4-1 to 4-M), and the first wires (1-j) are applied. , For example, give 20V, then the second wiring (2-j)
To the fifth wiring (5-j), for example, 20V. By holding this state for a desired time, the electrons in the charge storage layer of the selected cell are extracted by the FN tunneling phenomenon and erased. After that, the second wiring (2-j) and the fifth wiring (5-j) are returned to 0 V, for example, and the fourth wiring (4-1
.About.4-M) is returned to, for example, 0V, and the first wiring (1-j) is returned to, for example, 0V. At this time, the timing of applying a potential to each wiring may be before or after or at the same time. The potentials to be applied may be any combination of potentials as long as they satisfy the condition for lowering the threshold value of a desired cell.

Further, in the above, the third wiring (3-j-1 to 3
-jL) has been described as the erasing method when the memory cell with the gate electrode is the selected cell, the third wiring (3-j-1 ~ 3-
The erasing method when the memory cell having one of the third wirings other than jL) as the gate electrode is the selected cell is similarly performed.

All memory cells connected to the third wiring (3-j-1 to 3-jL) may be erased at the same time, or the third wiring (3-1-1 to 3-jL). It is also possible to erase a plurality or all of the memory cells connected to (NL) simultaneously.

Further, the operation principle of reading, writing and erasing in another array structure of the semiconductor memory device of the present invention will be described.

The semiconductor memory device in this case has an island-shaped semiconductor layer having a charge storage layer and two memory cells each having a third electrode as a control gate electrode connected in series. , For example M × N (M and N are positive integers). Further, a plurality of elements arranged in parallel to the semiconductor substrate, for example M
The fourth wiring of the book is connected to one end of each of the island-shaped semiconductor layers, and the first wiring is connected to the other end. Furthermore, a plurality of, for example N × 2, third wirings arranged parallel to the semiconductor substrate and in a direction intersecting the fourth wiring are connected to the third electrode of the memory cell. Wiring is the third
Are arranged in parallel to the wiring.

FIG. 24 shows an equivalent circuit of the above memory cell array structure. Note that the definition of writing to the memory cell will be described, for example, when the threshold of the memory cell is 4 V or more, and the definition of erasing is when the threshold of the memory cell is 0.5 V or more and 3 V or less.

As an example of the reading method, FIG. 31 shows an example of the timing of the potential applied to each electrode in the reading. First, the first wiring (1-1 to 1-N), the third wiring (3-j-1, 3-j)
-2), 3rd wiring (≠ 3-j-1, ≠ 3-j-2), 4th wiring (4-1 to 4-
M), for example, from the state of applying 0V, 4th wiring (4
-i), for example, give 1V, then the third wiring (3-j-2)
For example, by applying 5V, the current flowing in the fourth wiring (4-i) or the current flowing in the first wiring (1-j) (j is a positive integer of 1 ≦ j ≦ N) causes “0”. "," 1 "is judged.

After that, the third wiring (3-j-2) is returned to 0V, for example, and the fourth wiring (4-i) is returned to 0V, for example. At this time, the timing of applying a potential to each wiring may be before or after or at the same time.

In the above description, the read method in the case where the memory cell having the third wiring (3-j-1) as the gate electrode is the selected cell has been described, but the third wiring (3-j- The reading method when the memory cell having one of the third wirings other than 1) as the gate electrode is the selected cell is similarly performed.

Reading from the third wiring (3-j-2) to the third wiring (3-j-1) may be continuously performed, or the order may be reversed or random. Further, reading of a plurality or all of the memory cells connected to the third wiring (3-j-1) may be performed simultaneously.

As an example of the writing method, FIG. 32 shows an example of the timing of the potential applied to each electrode in writing. First, the first wiring (1-1 to 1-N), the third wiring (3-1-1 to 3-N-
2), the fourth wiring (4-1 to 4-M), for example, from the state of applying 0V, the fourth wiring other than the fourth wiring (4-i) (≠ 4-
i) to an open state, and then to the fourth wiring (4-i), for example
By applying 6V, for example, 6V to the third wiring (3-j-2), and for example, 12V to the third wiring (3-j-1), and holding this state for a desired time The channel hot electrons are generated near the high potential side diffusion layer of the selected cell, and the third hot electron is generated.
Writing is performed by injecting the generated electrons into the charge storage layer of the selected cell by the high potential applied to the wiring (3-j-1).

After that, for example, the third wiring (3-j-1) is returned to, for example, 0V, and then the third wiring (3-j-2) is returned to, for example, 0V, and the fourth wiring (4 -i) is returned to 0V, for example, and the fourth wiring (≠ 4-
i) is returned to 0V, for example. At this time, the timing of applying a potential to each wiring may be before or after or at the same time. Further, the potentials to be applied may be any combination of potentials as long as they satisfy the conditions for accumulating negative charges in a desired amount or more in the charge accumulation layer of a desired cell.

In the above description, the writing method has been described in the case where the memory cell having the third wiring (3-j-1) as the gate electrode is the selected cell, but the third wiring (3-j- The writing method when a memory cell having one of the third wirings other than 1) as a gate electrode is a selected cell is similarly performed.

Writing may be performed in the order of the third wiring (3-j-2) and the third wiring (3-j-1), or in the reverse order. Furthermore
Writing to a plurality of or all of the memory cells connected to the wiring (3-j-1) of 3 may be performed at the same time.

As an example of the erasing method, FIG. 33 shows an example of the timing of the potential applied to each electrode in the erasing.
The erase unit is a block unit, and is performed only in the upper stage or in the lower stage of one word line or block.

First, the first wiring (1-1 to 1-N), the third wiring
(3-1-1 to 3-N-2) and the fourth wiring (4-1 to 4-M), for example, from the state where 0V is applied, the fourth wiring (4-1 to 4-M) ) Is opened, 5 V is applied to the first wiring (1-j), and the third wiring (3
-j-2) is applied with, for example, 5V, and the third wiring (3-j-1) is applied with, for example, -10V, and this state is maintained for a desired time to keep electrons in the charge storage layer of the selected cell. Is erased by FN tunneling phenomenon.

After that, the third wiring (3-j-1) is returned to, for example, 0 V, and then the third wiring (3-j-2) is returned to, for example, 0 V, and the first wiring (1-j ) To, for example, 0 V, and set the fourth wiring (4-1 to 4-M) to 0
Return to V. At this time, the timing of applying a potential to each wiring may be before or after or at the same time. Further, the applied potential may be any combination of potentials as long as it satisfies the condition for lowering the threshold value of a desired cell.

In the above description, the erasing method in the case where the memory cell having the third wiring (3-j-1) as the gate electrode is the selected cell has been described, but the third wiring (3-j-1) The same erasing method is performed when a memory cell having one of the third wirings other than the above) as a gate electrode is a selected cell.

A plurality of or all memory cells connected to the third wiring (3-j-1 to 3-j-2) may be erased at the same time, or the third wiring (3-1- It is also possible to erase a plurality or all of the memory cells connected to 1 to 3-N-2) at the same time.

In the above operating principle, the polarities of all the electrodes may be exchanged, as in the case of the island-shaped semiconductor layer formed of the N-type semiconductor. The magnitude relationship of the potentials is opposite to that described above.

Further, in each of the above read, write and erase operation examples, the first wiring is arranged in parallel with the third wiring, but the first wiring is arranged in parallel with the fourth wiring. Even when they are arranged and when the first wiring is common to the entire array, it is possible to operate by applying a potential corresponding to each. 1st wiring to 4th
If it is arranged in parallel with the wiring, it is possible to erase in block units or bit line units.

FIGS. 26 and 27 show an embodiment shown in FIGS. 13 and 14, in which the diffusion layer 720 is not disposed between the transistors and the gate electrodes of the memory transistor and the select gate transistor are 500. , 510, 520 is an equivalent circuit diagram showing a part of a memory cell array in the case where a polycrystalline silicon film 530 which is a third conductive film is formed between them.

FIG. 26 shows a polycrystalline silicon film 530 which is a third conductive film arranged between the gate electrodes of each memory transistor and select gate transistor as a structure arranged in one island-shaped semiconductor layer 110. FIG. 10 is an equivalent circuit diagram of the memory cell array when the memory cells are formed.

FIG. 27 shows an equivalent circuit when a plurality of island-shaped semiconductor layers 110 are arranged.

The equivalent circuit shown in FIG. 26 will be described below.

This memory cell array has a transistor having a thirty-second electrode 32 as a gate electrode and a transistor having a thirty-fifth electrode 35 as a gate electrode as select gate transistors, and charge accumulation is performed between the select gate transistors. 33rd electrode having a layer as a control gate electrode
(33-h) (h is a positive integer of 1 ≤ h ≤ L, L is a positive integer), a plurality of memory cells, for example L, are arranged in series, and as a gate electrode between each transistor. It has an island-shaped semiconductor layer 110 in which a transistor having a 36th electrode is arranged.
A 34th electrode 34 is connected to one end of each of the island-shaped semiconductor layers 110, a 31st electrode 31 is connected to the other end, and a plurality of 36 electrodes are all connected to one. Then, the island-shaped semiconductor layer 110 is provided as the 36th electrode 36.

Next, the equivalent circuit shown in FIG. 27 will be described.

In the memory cell array in which a plurality of island-shaped semiconductor layers 110 are arranged, the connection relation between the electrodes of the circuit elements arranged in each island-shaped semiconductor layer 110 shown in FIG. 26 and the wirings is shown.

This memory cell array has an island-shaped semiconductor layer 1
A plurality of 10, for example M × N (M and N are positive integers, and i is 1
≦ i ≦ M positive integer, j is 1 ≦ j ≦ N positive integer). A plurality of, for example, M thirty-fourth wirings arranged in parallel to the semiconductor substrate are connected to the above-mentioned thirty-fourth electrodes 34 provided in each island-shaped semiconductor layer 110. Parallel to the semiconductor substrate,
And a plurality of wires arranged in a direction intersecting with the 34th wiring 34,
For example, the N × L thirty-third wiring is connected to the above-mentioned thirty-third electrode (33-h) of each memory cell. A plurality of, for example N, thirty-first wirings arranged in a direction intersecting with the thirty-fourth wiring are connected to the above-mentioned thirty-first electrode 31 provided in each island-shaped semiconductor layer 110, and the thirty-first wiring Are arranged in parallel with the 33rd wiring.
In addition, a plurality of parallel to the semiconductor substrate, and arranged in a direction intersecting the 34th wiring 34, for example, N th 32nd wiring is connected to the above-mentioned 32nd electrode 32 of each memory cell, Further, similarly, a plurality of, for example, N th 35th wirings arranged in a direction parallel to the semiconductor substrate and intersecting with the 34th wiring 34 are connected to the above-mentioned 35th electrode 35 of each memory cell. To do. The above-mentioned 36th electrodes 36 provided in each island-shaped semiconductor layer 110 are all connected to one by a 36th wiring.

The 36th electrode 36 provided in each island-shaped semiconductor layer 110 does not have to be connected to one by the 36th wiring, and two or more memory cell arrays are provided by the 36th wiring. You may divide and connect to. That is, the 36th electrode may be connected to each block, for example.

Further, the select gate transistor, the memory cell adjacent to the select gate transistor, and the adjacent memory cells are not connected via the impurity diffusion layer. Instead, the distance between the select transistor and the memory cell and the memory cells is not changed. However, the operation principle of the memory cell array having a structure of approximately 30 nm or less and having a structure very close to that in the case where the select transistor and the memory cell and the memory cells are connected to each other through the impurity diffusion layer will be described.

When adjacent elements are sufficiently close to each other, the channel formed by the potential applied to the gate of the select gate transistor or the control gate of the memory cell, which is higher than the threshold value, is connected to the channel of the adjacent element, and When a potential equal to or higher than the threshold is applied to the gates of the elements, channels are connected to all the elements. This state is almost equivalent to the case where the select transistor is connected to the memory cell or the memory cell via the impurity diffusion layer. Therefore, the operating principle is that the select transistor is connected to the memory cell or the memory cell via the impurity diffusion layer. It is the same as when

Also, the select gate transistor and the memory cell are not connected via the impurity diffusion layer, and instead the third conductive film is arranged between the select transistor and the memory cell or the gate electrode of the memory cell. The operation principle of the memory cell array having the above will be described.

The third conductive film is located between the respective elements and is connected to the island-shaped semiconductor layer via an insulating film, for example, a silicon oxide film. That is, the third conductive film, the insulating film, and the island-shaped semiconductor layer form a MIS capacitor. A channel is formed by applying a potential such that an inversion layer is formed at the interface between the island-shaped semiconductor layer and the insulating film to the third conductive film. The formed channel has the same function as that of the impurity diffusion layer that connects the respective elements to the adjacent elements. Therefore, when a potential capable of forming a channel is applied to the third conductive film, the same operation as in the case where the select gate transistor or the memory cell is connected through the impurity diffusion layer is performed.

Even when a potential for forming a channel is not applied to the third conductive film, for example, when the island-shaped semiconductor layer is a P-type semiconductor, when electrons are extracted from the charge storage layer,
The operation is the same as when the select gate transistor and the memory cell are connected via the impurity diffusion layer. Embodiments in Manufacturing Method of Memory Cell Array Embodiments of a manufacturing method of a semiconductor memory device of the present invention and a semiconductor memory device formed by this method will be described with reference to the drawings.

In contrast to the conventional example, a semiconductor memory in which a columnar processed semiconductor substrate or semiconductor layer having at least one depression is formed, and a tunnel oxide film and a floating gate as a charge storage layer are formed inside each depression. An embodiment of the device will be described.

The steps or modes performed in the following production examples can be applied in various combinations with the steps or modes performed in another production example. Manufacturing Example 1 A semiconductor memory device in this manufacturing example includes a semiconductor substrate,
For example, it is processed into a columnar island-shaped semiconductor layer having at least one depression, and the side surface of the island-shaped semiconductor layer is used as an active region surface,
A floating gate is formed as a tunnel oxide film and a charge storage layer inside each recess, and select gate transistors are arranged above and below the island-shaped semiconductor layer. A plurality of memory transistors are sandwiched between the select gate transistors. For example, two transistors are arranged, each transistor is connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor. The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

35 to 60 and 61 to 86.
1A and 1B are cross-sectional views taken along lines AA 'and BB' in FIG. 1, which are plan views showing a memory cell array of an EEPROM, respectively.

In this manufacturing example, a silicon nitride film 310, for example, is formed on the surface of a p-type silicon substrate 100, which is a semiconductor substrate, as a first insulating film, which is a mask layer.
The silicon nitride film 310, which is the first insulating film, is etched by reactive ion etching using a resist R1 deposited to a thickness of ˜2000 nm and patterned by a known photolithography technique as a mask (FIGS. 35 and 61). Then, the silicon nitride film 310 that is the first insulating film
Is used as a mask, and the p-type silicon substrate 100, which is a semiconductor substrate, is subjected to reactive ion etching to 2000 to 20000 nm.
Etching is performed to form the first groove portions 210 having a grid pattern (FIGS. 36 and 62). As a result, the semiconductor substrate p
The silicon substrate 100 has a columnar shape and is separated into a plurality of island-shaped semiconductor layers 110.

Thereafter, if necessary, the island-shaped semiconductor layer 110 is formed.
The surface of is oxidized to form a second insulating film, for example, a thermal oxide film 410 having a thickness of 10 nm to 100 nm. Island semiconductor layer 11
When 0 is formed with the minimum processing size, the thermal oxide film 41
The formation of 0 reduces the size of the island-shaped semiconductor layer 110. In other words, it is formed with the minimum processing dimension or less.

Next, the thermal oxide film 410, which is the second insulating film around each island-shaped semiconductor layer 110, is removed by etching, for example, by isotropic etching, and if necessary, oblique ion implantation is used to remove each island. Ion implantation is performed on the sidewall of the semiconductor layer 110. For example, from a direction inclined by 5 to 45 °
Implantation energy of 5 to 100 keV, boron 1 × 10 ¹¹ to 1 × 1
The dose is about 0 ¹³ / cm ² . During the channel ion implantation, it is preferable to implant the island-shaped semiconductor layer 110 from multiple directions because the surface impurity concentration can be made uniform. Alternatively, instead of the channel ion implantation, an oxide film containing boron may be deposited by the CVD method and boron diffusion from the oxide film may be used. Note that the impurity introduction from the surface of the island-shaped semiconductor layer 110 may be performed before the surface of the island-shaped semiconductor layer 110 is covered with the thermal oxide film 410 that is the second insulating film, or may be performed. The introduction may be completed before forming 110, or may be introduced immediately before forming the gate oxide film. The method is not limited as long as the island-shaped semiconductor layer 110 has the same impurity concentration distribution.

Subsequently, a silicon oxide film 431 is deposited to a thickness of 10 to 100 nm as a fifth insulating film, and a silicon nitride film 321 is deposited to a thickness of 10 to 100 nm as a fourth insulating film.
Deposit (FIGS. 37 and 63).

Thereafter, as a sixth insulating film, for example, a silicon oxide film 441 is deposited to a thickness of 50 to 500 nm, and isotropically etched back to a desired height, for example, to form a silicon oxide film 441 which is the sixth insulating film. Is embedded in the first groove 210 (FIGS. 38 and 64).

Silicon oxide film 441 which is the sixth insulating film
Is used as a mask to remove the exposed portion of the silicon nitride film 321 which is the fourth insulating film by, for example, isotropic etching.
(FIGS. 39 and 65).

Subsequently, a silicon oxide film 471, which is an eleventh insulating film, is deposited to a thickness of 50 to 500 nm (FIGS. 40 and 66), and is etched back to a desired height by, for example, isotropic etching. The silicon oxide film 471, which is an insulating film, is embedded in the first groove 210 (FIGS. 41 and 6).
7).

A silicon oxide film 432 is deposited to a thickness of 10 to 100 nm as a fifth insulating film, and a silicon nitride film 322 is deposited to a thickness of 10 to 100 nm as a fourth insulating film.
After that, for example, by anisotropic etching, the silicon nitride film 322 which is the fourth insulating film is arranged on the side wall of the island-shaped semiconductor layer 110 in a sidewall shape with the silicon oxide film 432 which is the fifth insulating film interposed therebetween.

As the sixth insulating film, for example, a silicon oxide film 442 is deposited to a thickness of 50 to 500 nm and is etched back to a desired height by, for example, isotropic etching to form the silicon oxide film 442 as the sixth insulating film. One groove 21
Embedded in 0.

Subsequently, the exposed portion of the silicon nitride film 322 which is the fourth insulating film is removed by, for example, isotropic etching using the silicon oxide film 442 which is the sixth insulating film as a mask.

Silicon oxide film 47 which is the eleventh insulating film
2 is deposited to a desired height by, for example, isotropic etching, and then the silicon oxide film 472 which is the eleventh insulating film is formed on the first groove 2
10 (FIGS. 42 and 68).

Then, a silicon oxide film 433 is deposited to a thickness of 10 to 100 nm as a fifth insulating film, and a silicon nitride film 323 is deposited to a thickness of 10 to 100 nm as a fourth insulating film.
accumulate. After that, the silicon nitride film 323, which is the fourth insulating film, is formed on the island-shaped semiconductor layer 1 by anisotropic etching, for example.
A silicon oxide film 433 which is a fifth insulating film is formed on the sidewall of
Arranged in the shape of a sidewall through (see FIGS. 43 and 6).
9).

After that, the silicon oxide film is selectively removed by isotropic etching (FIGS. 44 and 70), and the exposed island-shaped semiconductor layer 110 is subjected to, for example, a thermal oxidation method to form a seventh oxide film. As the insulating film, for example, a silicon oxide film 450 is grown to a thickness of about 30 nm to 300 nm (FIGS. 45 and 7).
1).

Subsequently, isotropic etching is performed in this order on the silicon oxide film, the silicon nitride film, and the silicon oxide film to form the fifth insulating films, that is, the silicon oxide films 431 to 43.
3, silicon nitride films 321 to 32, which are fourth insulating films
3. The silicon oxide film 450, which is the seventh insulating film, is removed (FIGS. 46 and 72). Note that, in order to obtain the shape of the island-shaped semiconductor layer 110 in FIGS. 46 and 72, for example, isotropic etching is performed instead of forming the silicon oxide film 450 that is the seventh insulating film by a thermal oxidation method. A depression having a depth of about 30 nm to 300 nm may be formed on the sidewall of the island-shaped semiconductor layer 110, and the thermal oxidation method and the isotropic etching may be used together. The method is not limited as long as the desired shape is obtained.

Then, for example, a silicon oxide film 4 is formed around each island-shaped semiconductor layer 110 by using, for example, a thermal oxidation method as a third insulating film to be a tunnel oxide film of about 10 nm.
Form 20. At this time, the tunnel oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or an oxynitride film.

Subsequently, for example, a polycrystalline silicon film 510 to be the first conductive film is deposited to a thickness of about 50 nm to 200 nm (FIGS. 47 and 73), and anisotropic etching is performed to form the island-shaped semiconductor layer 110. A polycrystalline silicon film 510, which is a first conductive film, is buried in the depressions formed on the sidewalls via a silicon oxide film 420, which is a third insulating film, and the polycrystalline silicon film 512 is a first conductive film. 513
Are formed separately (FIGS. 48 and 74). Instead of performing anisotropic etching to form the polycrystalline silicon films 512 and 513, which are the first conductive film, isotropic etching is used to etch back until the recesses are not reached. It may be performed by anisotropic etching or isotropic etching.

As the sixth insulating film, for example, a silicon oxide film 440 is deposited to a thickness of 50 to 500 nm, and is etched back to a desired depth to be embedded (FIGS. 49 and 75).

Silicon oxide film 431 which is the fifth insulating film
Is deposited to a thickness of 10 to 100 nm, and then a silicon nitride film 321 which is a fourth insulating film is deposited to a thickness of 10 to 100 nm. Then, as the sixth insulating film, for example, a silicon oxide film 441 is formed in a thickness of 50 to 500n.
The silicon oxide film 441, which is the sixth insulating film, is buried in the first groove 210 by depositing m and etching back to a desired height by, for example, isotropic etching. Then, the exposed portion of the silicon nitride film 321 which is the fourth insulating film is removed by, for example, isotropic etching using the silicon oxide film 441 which is the sixth insulating film as a mask (FIG. 50).
And FIG. 76).

By repeating the above steps, the silicon nitride film 3 as the fourth insulating film is formed on the sidewall of the island-shaped semiconductor layer 110.
21 and 322 are arranged through the fifth insulating films, that is, the silicon oxide films 431 and 432, respectively (see FIGS. 51 and 7).
7), the silicon oxide film is selectively removed by isotropic etching.

After that, the island-shaped semiconductor layer 110 and the semiconductor substrate are formed.
Impurities are introduced into the plate 100 to form the N-type impurity diffusion layer 7
10 to 724 are formed (FIGS. 52 and 78). For example, 0
Injection energy of 5 to 100 keV from a direction inclined by ~ 7 °
ー, Arsenic or Phosphorus 1 × 10 ¹²~ 1 x 10¹⁵/cm²degree
The dose is. Here, the N-type impurity diffusion layer 710
Ion implantation to form ~ 724
It may be done around 110, in one direction or
Injection from several directions may be sufficient. That is, N-type impurity diffusion
The layers 721 to 724 surround the island-shaped semiconductor layer 110.
It does not need to be formed. It is also the first wiring layer
The timing for forming the impurity diffusion layer 710 is an N-type semiconductor.
It does not have to be the same as the formation of the layers 721 to 724.

Then, the silicon oxide films 431 and 432 which are the fifth insulating films and the silicon nitride films 321 and 322 which are the fourth insulating films are removed, and a silicon oxide film 461 is formed as an eighth insulating film. Deposit 50 to 500 nm, etch back to the desired depth and embed. Then, for example, a silicon oxide film 481 is formed around the island-shaped semiconductor layer 110 by using, for example, a thermal oxidation method as a thirteenth insulating film to be a gate oxide film of about 10 nm. On this occasion,
The gate oxide film is not limited to the thermal oxide film, but may be a CVD oxide film or an oxynitride film. The magnitude relation between the gate oxide film thickness and the tunnel oxide film thickness is not limited, but it is desirable that the gate oxide film thickness is larger than the tunnel oxide film thickness.

Next, for example, a polycrystalline silicon film 521 to be the second conductive film is deposited to a thickness of 15 nm to 150 nm and is formed in a sidewall shape by anisotropic etching to form a select gate. At that time, the distance between the island-shaped semiconductor layers 110 is set to A in FIG.
By setting the value in the −A ′ direction to a predetermined value or less in advance, the wiring layer is formed as the second wiring layer which becomes the select gate line continuous in the direction without using a mask process.

Thereafter, as shown in FIG. 79, the second groove 220 is formed in the p-type silicon substrate 100 which is a semiconductor substrate in a self-alignment with the polycrystalline silicon film 521 which is a second conductive film, and the impurity diffusion layer 710 is formed. (Figs. 53 and 7)
9). That is, the isolation portion of the first wiring layer is formed in self-alignment with the isolation portion of the second conductive film.

Subsequently, a silicon oxide film 462 which is an eighth insulating film is deposited to a thickness of 50 nm to 500 nm, and anisotropic etching and isotropic etching are performed on the side portions of the polycrystalline silicon film 521 which is the second conductive film and A silicon oxide film 462, which is an eighth insulating film, is buried so as to fill the upper portion (FIGS. 54 and 80).

After that, the interlayer insulating film 612 is formed on the exposed surfaces of the polycrystalline silicon films 512 and 513 which are the first conductive films.
To form. The interlayer insulating film 612 is, eg, an ONO film. Specifically, a 5-10 nm silicon oxide film is formed on the surface of the polycrystalline silicon film by the thermal oxidation method and a 5-10 nm film by the CVD method.
And a silicon oxide film of 5 to 10 nm are sequentially deposited.

Subsequently, similarly, a polycrystalline silicon film 522 to be the second conductive film is deposited in a thickness of 15 nm to 150 nm and etched back, so that the polycrystalline silicon film 51 to be the first conductive film is formed.
A polycrystalline silicon film 522, which is a second conductive film, is arranged on the second side with an interlayer insulating film 612 interposed therebetween. At this time, by setting the value to a predetermined value or less in the AA ′ direction in FIG. 1 in advance, it is formed as a third wiring layer which becomes a control gate line continuous in that direction without using a mask process. It

After that, a silicon oxide film 463, which is an eighth insulating film, is deposited to a thickness of 50 nm to 500 nm, and the side and upper portions of the polycrystalline silicon film 522, which is a second conductive film, are anisotropically and isotropically etched. The oxide film 463, which is the eighth insulating film, is embedded so as to bury (FIGS. 55 and 8).
1).

By repeating this in the same manner, the polycrystalline silicon film 523 which is the second conductive film is arranged on the side of the polycrystalline silicon film 513 which is the first conductive film with the interlayer insulating film 613 interposed therebetween, and the second conductive film is formed. A silicon oxide film 464, which is an eighth insulating film, is buried so as to fill the side and upper portions of the polycrystalline silicon film 523, which is a conductive film (FIGS. 56 and 82).

Subsequently, a polycrystalline silicon film 524 which is a second conductive film is deposited to a thickness of 15 nm to 150 nm and is formed in a sidewall shape by anisotropic etching (FIGS. 57 and 83).

Polycrystalline silicon film 52 which is the second conductive film
A tenth insulating film, for example, a silicon oxide film 465 having a thickness of 100 nm to 500 nm is deposited on the upper layer of No.
The upper part of the island-shaped semiconductor layer 110 including the impurity diffusion layer 724 is exposed by the P method or the like (FIGS. 58 and 84).

If necessary, the impurity concentration is adjusted with respect to the upper portion of the island-shaped semiconductor layer 110 by, for example, an ion implantation method, and the fourth wiring layer 840 crosses the direction of the second or third wiring layer. It is connected to the upper part of the island-shaped semiconductor layer 110.

After that, an interlayer insulating film is formed by a known technique, and a contact hole and a metal wiring are formed. As a result, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as the floating gate (FIGS. 59 and 85).

59 and 85 show the case where the fourth wiring layer 840 is misaligned with respect to the island-shaped semiconductor layer 110. However, as shown in FIGS. It is preferable to form without deviation.

In this manufacturing example, the lattice island-shaped first groove portion 210 is formed on the p-type semiconductor substrate, but the p-type impurity diffusion layer or the p-type silicon substrate formed in the n-type semiconductor substrate is formed. A lattice island-shaped first groove portion 210 may be formed in the p-type impurity diffusion layer formed in the n-type impurity diffusion layer formed therein. The conductivity type of each impurity diffusion layer may be the opposite conductivity type.

The film formed on the surface of the semiconductor substrate or the polycrystalline silicon film such as the silicon nitride film 310 which is the first insulating film is a multi-layer film of silicon oxide film / silicon nitride film from the silicon surface side. May be The silicon oxide film used for embedding the silicon oxide film is not limited to the CVD method, and for example, a silicon oxide film may be formed by spin coating.

In this manufacturing example, the control gate of each memory cell is formed continuously in one direction without using a mask. This is possible only if the island-shaped semiconductor layers are not arranged symmetrically. That is, by making the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction smaller than that in the fourth wiring layer direction, the second wiring layer is separated in the fourth wiring layer direction, A wiring layer connected to the third wiring layer direction is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography.

Further, by disposing the select gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is negative. Therefore, it is possible to prevent the cell current from flowing even in a non-selected cell. Manufacture Example 2 In this Manufacture Example, in a semiconductor memory device, a semiconductor substrate is processed into, for example, a pillar-shaped island-shaped semiconductor layer having at least one depression, and a side surface of the island-shaped semiconductor layer is used as an active region surface,
A floating gate is formed inside each recess as a tunnel oxide film and a charge storage layer. Select gate transistors are arranged above and below the island-shaped semiconductor layer, and are sandwiched between the select gate transistors to form a memory transistor. A plurality of, for example two, transistors are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor. The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

In the semiconductor memory device formed in this manufacturing example, as shown in FIGS. 87 and 88, the shape of at least one recess formed in the island-shaped semiconductor layer 110 is not a simple concave shape. More specifically, when the silicon oxide film 450 that is the seventh insulating film is formed by the thermal oxidation method,
The oxidizer enters from the end portion of the silicon nitride film 322 which is the fourth insulating film, and the silicon nitride film 322 which is the fourth insulating film.
A part of the island-shaped semiconductor layer 110 on the inside is oxidized to generate such a shape of the depression. The shape of the depression is not particularly limited as long as the diameter of a part of the sidewall of the island-shaped semiconductor layer 110 processed into a column shape is small.

Further, as shown in FIGS. 89 and 90,
The floating gate and the control gate may be arranged in the same recess. The arrangement relationship between the floating gate and the control gate inside the depression is not particularly limited. Manufacture Example 3 In this Manufacture Example, in a semiconductor memory device, a semiconductor substrate is processed into, for example, a pillar-shaped island-shaped semiconductor layer having at least one depression, and the side surface of the island-shaped semiconductor layer serves as an active region surface.
A floating gate is formed inside each recess as a tunnel oxide film and a charge storage layer. Select gate transistors are arranged above and below the island-shaped semiconductor layer, and are sandwiched between the select gate transistors to form a memory transistor. Are arranged in plurality, for example, two transistors are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor. The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

91 and 92 show an EEPROM.
2 is a plan view showing the memory cell array of FIG.
FIG. 4 is a sectional view taken along line BB ′ and line BB ′.

In the semiconductor memory device formed in this manufacturing example, the island-shaped semiconductor layer continuous in the AA 'direction is anisotropically etched until at least the impurity diffusion layer 710 is separated using a patterned mask. And embedding, for example, a silicon oxide film 490 as the fifteenth insulating film. As a result, the performance as an element is expected to be inferior to that of Production Example 1, but
A semiconductor memory device having an equivalent function can be obtained with double the element capacitance.

The fifteenth insulating film may be a silicon nitride film instead of the silicon oxide film, and is not limited as long as it is an insulating film. Manufacture Example 4 In this Manufacture Example, in a semiconductor memory device, a semiconductor substrate in which an oxide film is inserted, for example, a semiconductor portion on the oxide film of an SOI substrate is processed into, for example, a columnar island-shaped semiconductor layer having at least one depression. The side surface of the island-shaped semiconductor layer is used as an active region surface, a floating gate is formed as a tunnel oxide film and a charge storage layer inside each depression, and select gate transistors are arranged above and below the island-shaped semiconductor layer. A plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors, and the transistors are connected in series along the island-shaped semiconductor layer. -It is larger than the gate insulation film thickness of the transistor. The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

Incidentally, FIGS. 93 and 94, 95 and 9
6 is a cross-sectional view taken along the line AA ′ and the line BB ′ in FIG. 1, which is a plan view showing the memory cell array of the EEPROM.

Also in this manufacturing example, the same effect as in manufacturing example 1 can be obtained. Further, the impurity diffusion layer 7 which becomes the first wiring layer
The junction capacitance of 10 is suppressed or eliminated.

When the SOI substrate is used, the impurity diffusion layer 710 which is the first wiring layer may reach the oxide film of the SOI substrate (FIGS. 93 and 94) or may not reach it.
(FIGS. 95 and 96).

Note that the groove for separating and forming the first wiring layer may or may not reach the oxide film of the SOI substrate, and it may be deeply formed until it penetrates the oxide film of the SOI substrate. The impurity diffusion layer 710 is not limited as long as it is separated.

S in which an oxide film is inserted into the substrate as an insulating film
Although the OI substrate is used, the insulating film may be a silicon nitride film, and the type of the insulating film is not limited. Manufacture Example 5 In this Manufacture Example, in a semiconductor memory device, a semiconductor substrate is processed into, for example, a columnar island-shaped semiconductor layer having at least one depression, and the side surface of the island-shaped semiconductor layer is used as an active region surface.
A floating gate is formed as a tunnel oxide film and a charge storage layer inside each of the recesses, and a plurality of memory transistors, for example, two memory transistors are arranged in the island-shaped semiconductor layer, and the transistors are arranged in series along the island-shaped semiconductor layer. Be connected to.
The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

97 and 98 show the EEPROM
2 is a plan view showing the memory cell array of FIG.
FIG. 4 is a sectional view taken along line BB ′ and line BB ′.

In the semiconductor memory device formed in this manufacturing example, the polycrystalline silicon film 510 as the first conductive film is formed in the recess formed in the sidewall of the island-shaped semiconductor layer 110, and the silicon oxide as the third insulating film is formed. The polycrystalline silicon films 512 and 513, which are the first conductive films, are buried through the film 420.
Are formed separately (see FIGS. 48 and 74). As it is, impurities are introduced into the island-shaped semiconductor layer 110 and the semiconductor substrate 100 to form an N-type impurity diffusion layer. After that, the same operation as in Manufacturing Example 1 is performed except that the step of forming the select gate transistor is omitted (FIGS. 97 and 98).

Although the floating gate is used as the charge storage layer in this manufacturing example, the charge storage layer may have another form. Manufacture Example 6 In this Manufacture Example, in a semiconductor memory device, a semiconductor substrate is processed into, for example, a columnar island-shaped semiconductor layer having at least one depression, and the side surface of the island-shaped semiconductor layer is used as an active region surface.
A floating gate is formed as a tunnel oxide film and a charge storage layer inside each recess, and select gate transistors are arranged above and below the island-shaped semiconductor layer, and a plurality of memory transistors are sandwiched between the select gate transistors. Individual,
For example, two transistors are arranged, each transistor is connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor. The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

99 and 100 show the EEPRO
2 is a plan view showing the memory cell array of M in FIG.
It is an A'line and BB 'sectional view.

The semiconductor memory device formed in this manufacturing example has an element-to-element distance of 20 between each memory transistor and select gate transistor arranged in the island-shaped semiconductor layer 110.
It is realized by keeping the thickness of nm to 40 nm and not introducing the inter-element diffusion layers 721 to 723 (FIGS. 99 and 10).
0).

According to this manufacturing example, the same effects as in manufacturing example 1 (FIGS. 35 to 53 and FIGS. 61 to 79) can be obtained.

At the time of reading, as shown in FIG. 99, the impurity diffusion layers 710 are formed by electrically connecting the depletion layers and the inversion layers D1 to D4 to the respective gate electrodes 521, 522, 523 and 524. And 725 can set a path through which a current can flow. In this state, the charge storage layer 5
The gates 521, 522, and 5 so that it is possible to select whether or not the inversion layer is formed in D2 and D3 according to the states of 12, 513.
If the applied voltages of 23 and 524 are set, the information of the memory cell can be read.

The distribution of D2 and D3 is preferably a complete depletion type as shown in FIG. 101. In this case, the back bias effect in the memory cell is expected to be suppressed, and the effect of reducing variations in element performance and the like are expected. can get.

The diffusion of the impurity diffusion layers 710 to 724 can be suppressed by adjusting the impurity introduction amount or the heat treatment.
The distance in the height direction of the island-shaped semiconductor layer 110 can be set short, which enables cost reduction and process variation suppression. Manufacture Example 7 In this Manufacture Example, the case where the direction of the first wiring layer and the direction of the fourth wiring layer are parallel to each other will be described.

102 and 103 show the EEPR.
FIG. 2A is a plan view showing the memory cell array of the OM;
It is an A'line and BB 'sectional view.

In the semiconductor memory device described in Manufacturing Example 1, the first wiring continuous in the AA 'line direction is anisotropically etched by using, for example, a patterned resist to form an eighth insulating film. For example, the silicon oxide film 4
This is performed after the polycrystalline silicon film 521 which is the second conductive film is formed into a sidewall shape so that the first wiring is not separated in the BB ′ line direction by embedding 60. The step of separating the impurity diffusion layer 710 by self-alignment is omitted. As a result, a semiconductor memory having a memory function according to a charge state accumulated in a charge storage layer having a floating gate of a polycrystalline silicon film serving as a first conductive film in which the first wiring layer and the fourth wiring layer are parallel to each other. This is realized by the device (FIGS. 102 and 103). Manufacture Example 8 This Manufacture Example describes a case where the first wiring layer is electrically common to the memory array.

Incidentally, FIG. 104 and FIG. 105 show EEPR.
FIG. 2A is a plan view showing the memory cell array of the OM;
It is an A'line and BB 'sectional view.

In the semiconductor memory device described in Manufacturing Example 1, the second groove portion 220 is not formed in the semiconductor substrate 100, and the manufacturing example 1 (FIGS. 35 to 59 and FIGS. 61 to 85) relates to this. By omitting the step, at least the first wiring layer in the array becomes common without being divided,
A semiconductor memory device having a memory function is realized by a charge state accumulated in a charge accumulation layer having a polycrystalline silicon film serving as a first conductive film as a floating gate (FIGS. 104 and 1).
05). Manufacture Example 9 This Manufacture Example describes a case where the gate lengths of the memory transistor and the select gate transistor are different in the vertical direction.

Incidentally, FIGS. 106 and 107, FIGS. 108 and 109 are plan views showing the memory cell array of the EEPROM, respectively, and are lines AA 'and BB' in FIG.
It is a line sectional view.

Polycrystalline silicon films 511 to 51 which are first conductive films to be gates or select gates of memory cells.
4 is the length in the direction perpendicular to the semiconductor substrate 100 of FIG.
06 and 107, even if the gate lengths of the memory cells of the polycrystalline silicon films 512 and 513 which are the first conductive films are different, as shown in FIGS. Even if the select gate lengths of certain polycrystalline silicon films 521 and 524 are different, the lengths in the vertical direction of the polycrystalline silicon films 521 to 524 which are the second conductive films may not be the same. Rather, when reading the memory cells connected in series in the island-shaped semiconductor layer 110, the gate length of each transistor is changed in consideration of the decrease in the threshold value due to the back bias effect from the substrate. Is preferable. At this time, since the height of the first and second conductive films, which is the gate length, can be controlled for each layer, the control of each memory cell can be easily performed. Production Example 10 A case where the island-shaped semiconductor layer 110 is brought into an electrically floating state by the impurity diffusion layer 710 will be described.

Incidentally, FIGS. 110 and 111, FIGS. 112 and 113 are plan views showing the memory cell array of the EEPROM, respectively, and are lines AA 'and BB' in FIG.
It is a line sectional view.

In this manufacturing example, the impurity diffusion layers 710 and 7 are used.
It is realized by changing the arrangement of 21 to 723.

As shown in FIGS. 110 and 111,
The impurity diffusion layer 710 may be arranged so that the semiconductor substrate 100 and the island-shaped semiconductor layer 110 are not electrically connected, or as shown in FIGS. 112 and 113, the impurity-diffused layer 710 is arranged in the island-shaped semiconductor layer 110. The impurity diffusion layers 721 to 723 may be arranged so that the active regions of the memory cells and select gate transistors are also electrically insulated,
The impurity diffusion layers 710 and 721 to 723 may be arranged so that the same effect can be obtained in the depletion layer that spreads by the potential applied during reading, erasing, or writing.

According to this manufacturing example, the same effect as that of the manufacturing example 1 can be obtained. Further, since the impurity diffusion layer is arranged so that the active region of each memory cell is in a floating state with respect to the substrate, back bias from the substrate is obtained. The effect is lost, and variations in the characteristics of the memory cells due to the decrease in the threshold value of each memory cell during reading are suppressed. Further, it is desirable that each memory cell and select gate transistor be of a full depletion type. Manufacturing Example 11 In this manufacturing example, the case where the shape of the bottom of the island-shaped semiconductor layer 110 is not a simple columnar shape will be described.

114 and 115, FIG. 116 and FIG. 117 are plan views showing the memory cell array of the EEPROM, respectively, and are lines AA 'and BB' in FIG.
It is a line sectional view.

The bottom of the lattice-striped first groove 210 may have a partially or entirely rounded inclined structure as shown in FIGS. 114 and 115. Further, the lower end portion of the polycrystalline silicon film 521 to be the second conductive film may or may not reach the inclined portion of the bottom portion of the first groove portion 210.

Similarly, the bottom of the lattice-striped first groove 210 may have an inclined structure as shown in FIGS. 116 and 117, and the polycrystalline silicon film 5 to be the second conductive film is formed.
The lower end of 21 may or may not reach the slope of the bottom of the first groove 210. Manufacturing Example 12 In this manufacturing example, a case where the shape of the island-shaped semiconductor layer 110 is not a simple columnar shape will be described.

118 and 119, and FIGS. 120 and 121 are plan views showing the memory cell array of the EEPROM, respectively, and are lines AA 'and BB' in FIG.
It is a line sectional view.

When the first groove portion 210 is formed by reactive ion etching, the horizontal positions of the upper end portion and the lower end portion of the island-shaped semiconductor layer 110 may be displaced as shown in FIGS. 118 and 119. As shown in FIGS. 120 and 121, the outer shapes of the upper end portion and the lower end portion of the island-shaped semiconductor layer 110 may be different.

For example, when the island-shaped semiconductor layer 110 has a circular shape as shown in FIG.
In FIG. 19, an oblique cylinder is presented, and FIGS.
Then, the structure has a conical shape. The shape of the island-shaped semiconductor layer 110 is not particularly limited as long as the memory cells can be arranged in series in the direction perpendicular to the semiconductor substrate 100. Manufacture Example 13 In this Manufacture Example, in a semiconductor memory device, a region of at least one depression formed on a side surface of a columnar island-shaped semiconductor layer is defined in advance by a laminated film including a plurality of layers, and is opened by a photoresist mask. An island-shaped semiconductor layer is formed in a columnar shape in the formed hole-shaped groove by selective epitaxial silicon growth, the side surface of this island-shaped semiconductor layer is used as an active region surface, and a floating gate is formed as a tunnel oxide film and a charge storage layer inside each depression. And a select gate transistor is arranged on the upper and lower parts of the island-shaped semiconductor layer, and a plurality of memory transistors, for example, two memory transistors are arranged between the select gate transistors. Connected in series along the line, and the gate insulating film thickness of the select gate transistor is larger than that of the memory transistor. . The tunnel oxide film and the floating gate of each memory transistor are collectively formed.

122 to 130 and 131 to 131.
FIG. 139 is a cross-sectional view taken along the line AA ′ and the line BB ′ of FIG. 1, which is a plan view showing the memory cell array of the EEPROM.

In this manufacturing example, the p-type silicon substrate 100 is used.
A silicon oxide film 431 of 50 to 500 nm, for example, is deposited on the surface of the substrate as a fifth insulating film by, for example, a CVD method, and then a silicon nitride film 321 of 10 nm is formed as a fourth insulating film.
nm to 100 nm deposition, as a fifth insulating film, for example, a silicon oxide film 432 is deposited to 50 to 500 nm, as a fourth insulating film,
For example, a silicon nitride film 322 is deposited to a thickness of 10 to 100 nm, and a silicon oxide film 433 is deposited to a thickness of 50 to 50 as a fifth insulating film.
0 nm deposition, for example, a silicon nitride film 323 is deposited to 100 nm to 5000 nm as a fourth insulating film. Note that the deposited film thickness of the silicon oxide films 432 and 433 which are the fifth insulating films is set to be the height of the floating gate of the memory cell.

Then, using the resist R2 patterned by a known photolithography technique as a mask (FIGS. 122 and 131), the silicon nitride film 32 which is the fourth insulating film is formed by, for example, reactive ion etching.
3 and a silicon oxide film 433 which is a fifth insulating film, a silicon nitride film 322 which is a fourth insulating film, a silicon oxide film 432 which is a fifth insulating film, a silicon nitride film 321 which is a fourth insulating film, Silicon oxide film 4 which is the fifth insulating film
31 is sequentially etched to form the third groove 230 and the resist R2 is removed (FIGS. 123 and 132).

Next, as the fifteenth insulating film, for example, a silicon oxide film 491 is deposited to a thickness of 20 nm to 200 nm, and anisotropic etching is performed to a film thickness of about the third groove 23.
Silicon oxide film 491 which is a fifteenth insulating film on the inner wall of 0
Are arranged in a sidewall shape (see FIGS. 124 and 13).
3).

Then, the island-shaped semiconductor layer 1 is formed in the third groove portion 230 with the silicon oxide film 491 as the fifteenth insulating film interposed therebetween.
Embed 10. For example, a semiconductor layer is selectively epitaxially grown from the p-type silicon substrate 100 located at the bottom of the third groove 230 (FIGS. 125 and 134).

Further, the island-shaped semiconductor layer 110 is planarized with respect to the silicon nitride film 323 which is the fourth insulating film. At this time, an etch back using isotropic etching, an etch back using anisotropic etching, a planarization embedding using CMP may be used, and various combinations may be used, and any means may be used.

After that, for example, a silicon nitride film 310 of about 100 nm to 1000 nm is deposited as a first insulating film, and a resist R3 patterned by a known photolithography technique is used as a mask (FIGS. 126 and 13).
5), for example, by reactive ion etching, a silicon nitride film 310 that is a first insulating film, a silicon nitride film 323 that is a fourth insulating film, a silicon oxide film 433 that is a fifth insulating film, and a fourth insulating film. A silicon nitride film 322,
The silicon oxide film 432 which is the fifth insulating film is sequentially etched to expose the silicon oxide film 432 which is the fifth insulating film. At this time, the silicon oxide film 432 which is the fifth insulating film may be etched until the silicon nitride film 321 which is the fourth insulating film is exposed.

Then, the resist R3 is removed (see FIG. 127).
And FIG. 136), the silicon oxide film is entirely removed by isotropic etching (FIGS. 128 and 137), and the exposed island-shaped semiconductor layer 110 is formed into a seventh insulating film by using, for example, a thermal oxidation method. , For example, a silicon oxide film 45
0 (FIGS. 129 and 138).

Thereafter, according to Manufacturing Example 1, a semiconductor memory device having a memory function is realized by the charge state accumulated in the charge accumulation layer having the polycrystalline silicon film serving as the first conductive film as the floating gate ( 130 and 13
9).

As a result, the same effect as in Manufacturing Example 1 can be obtained, and the region of at least one depression formed on the side surface of the pillar-shaped island-shaped semiconductor layer can be accurately defined by the laminated film composed of multiple layers. Therefore, there is an advantage that variation in element performance can be reduced. Manufacture Example 14 In this Manufacture Example, in a semiconductor memory device, a semiconductor substrate is processed into, for example, a pillar-shaped island-shaped semiconductor layer having at least one depression, and the side surface of the island-shaped semiconductor layer serves as an active region surface.
A floating gate is formed as a tunnel oxide film and a charge storage layer inside each recess, and select gate transistors are arranged above and below the island-shaped semiconductor layer, and a plurality of memory transistors are sandwiched between the select gate transistors. Individual,
For example, two transistors are arranged, each transistor is connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor. The tunnel oxide film and the floating gate of each memory transistor are collectively formed, and the transmission gate is arranged between the respective transistors in order to transmit the potential to the active region of each memory transistor.

Note that FIGS. 140 and 141, and FIGS. 142 and 143 are plan views showing the memory cell array of the EEPROM, respectively, and are lines AA 'and BB' in FIG.
It is a line sectional view.

In this manufacturing example, the impurity diffusion layers 721 to 7 are formed.
A step of forming a second conductive film of polycrystalline silicon films 521, 522, 523, 524 without introducing 23 and then forming a gate electrode of, for example, a polycrystalline silicon film 530 as a third conductive film. It is realized by performing in the same manner as in Manufacturing Example 1 except that is added (FIGS. 140 and 141).

At the time of reading, as shown in FIG. 140,
Each gate electrode 521, 522, 523, 524, 5
By electrically connecting the depletion layer and the inversion layer indicated by D1 to D7 to 30, a path through which a current can flow can be set between the impurity diffusion layers 710 and 725. In this state, it is possible to select whether or not the inversion layer is formed in D2 and D3 depending on the states of the charge storage layers 512 and 513.
If the applied voltages of 1, 522, 523, 524, and 530 are set, the information of the memory cell can be read.

The distribution of D2 and D3 is preferably a complete depletion type as shown in FIG. 142. In this case, the back bias effect in the memory cell is expected to be suppressed, and the effect of reducing variations in device performance can be obtained. To be

Also in this manufacturing example, the same effect as in manufacturing example 1 can be obtained. In addition, the number of manufacturing steps is reduced, the required height of the island-shaped semiconductor layer 110 can be reduced, and process variations can be suppressed.

The upper and lower positions of the polycrystalline silicon film 530 which is the third conductive film may be the positions shown in FIG. 141, and the upper end is at least the polycrystalline silicon film which is the second conductive film. The upper end of 524 may be located above the lower end of the polycrystalline silicon film 521 that is the second conductive film, and the upper end may be located above the lower end of the 524. Manufacturing Example 15 In this Manufacturing Example, the silicon oxide film 4 which is the eighth insulating film is used.
A case where the embedding of 61 to 465 is not complete will be described.

143 and 144, 145 and 146 are plan views showing the memory cell array of the EEPROM, respectively, and are lines AA 'and BB' in FIG. 1, respectively.
It is a line sectional view.

In Manufacturing Example 1, the second groove 220 was formed by self-alignment by reactive ion etching using the polycrystalline silicon film 521 which is the second conductive film as a mask. The polycrystalline silicon film 522 which is the second conductive film, the polycrystalline silicon film 523 which is the second conductive film, or the polycrystalline silicon film 524 which is the second conductive film may be used. Alternatively, the resist may be separately formed by using a resist patterned by a known photolithography technique.

When the second groove portion 220 is formed by self-alignment by using the polycrystalline silicon film 524 which is the second conductive film as a mask, the formed second groove portion 220 is formed.
143 and FIG. 14 cannot be completely embedded when the silicon oxide film 465 that is the eighth insulating film is embedded in FIG.
Even if a hollow is formed as shown in 4,
It suffices that the hollow be an air gap as long as it can realize insulation between each control gate line and select gate line.

Also, as shown in FIGS. 145 and 146, the silicon oxide film may be selectively removed before the second trench 220 is filled with the silicon oxide film 465 which is the eighth insulating film.

By thus providing the hollow, a low dielectric constant is realized, and high-speed device characteristics with suppressed parasitic capacitance are expected. Manufacturing Example 16 In this manufacturing example, the outer periphery of the floating gate is the island-shaped semiconductor layer 11
The case where the outer circumference is different from 0 is shown.

147 to 148 and 149 to 149.
150 is a cross-sectional view taken along the line AA ′ and the line BB ′ of FIG. 1, which are plan views showing the memory cell array of the EEPROM.

In this manufacturing example, the polycrystalline silicon films 512 and 513 which are the first conductive films are buried in the depressions formed in the side surfaces of the island-shaped semiconductor layer 110 in the manufacturing example 1 and then the sixth insulating film is used. When burying a certain silicon oxide film 440,
The silicon oxide film 4 which is the third insulating film in a portion which is not embedded in the recess formed on the side surface of the island-shaped semiconductor layer 110.
20 is removed, and as shown in FIGS. 147 and 149,
The polycrystalline silicon films 512 and 51, which are the first conductive films, are formed by the thickness of the silicon oxide film 420, which is the third insulating film.
The outer circumference of 3 is larger than the outer circumference of the island-shaped semiconductor layer 110.

The outer periphery of the floating gate is the island-shaped semiconductor layer 110.
It may be larger or smaller than the outer circumference, and the size relationship does not matter.

148 and 150 are semiconductor memory device completion diagrams in which the outer periphery of the floating gate is larger than the outer periphery of the island-shaped semiconductor layer 110. Manufacturing Example 17 In this Manufacturing Example, the silicon oxide film 4 which is the sixth insulating film is used.
A case where a resist is used instead of 41 to 442 will be described.

Note that FIGS. 151-155 and 156-
FIG. 160 is a cross-sectional view taken along the line AA ′ and the line BB ′ in FIG. 1, which is a plan view showing the memory cell array of the EEPROM.

In this manufacturing example, the silicon oxide film 321 which is the fifth insulating film in the manufacturing example 1 is deposited, and the silicon oxide film 441 which is the fourth insulating film is further deposited. Approximately 25000 nm is applied (FIGS. 151 and 156). To expose to the desired depth,
For example, light light1 is irradiated to perform exposure (FIGS. 152 and 153). The step of exposing to a desired depth may be controlled by the exposure time, the exposure amount, or the exposure time and the exposure amount may be used in combination to control the exposure time. The control method including the developing step is not limited.

Then, development is carried out by a known technique to selectively remove the resist R5 which is the exposed region of the resist R4 and to embed the resist R4 (FIGS. 153 and 158). As described above, the resist etchback can be performed with good control by the exposure, and the effect of suppressing the variation in the device performance is expected. However, even if the resist R4 is etched back by, for example, ashing instead of the exposure. Good. Alternatively, burying may be performed without etching back so as to have a desired depth at the time of resist application. In this case, it is desirable to use a resist having low viscosity. These methods may be used in various combinations.

It is desirable that the coating surface of the resist R4 be hydrophilic, for example, coating on a silicon oxide film.

Then, using the resist R4 as a mask, the exposed portion of the silicon nitride film 321 which is the fourth insulating film is removed by, for example, isotropic etching (FIGS. 154 and 1).
59).

After removing the resist R4, the same semiconductor memory device is realized by performing the same operation as in Manufacturing Example 1.
(FIGS. 155 and 160).

As described above, by using the resist instead of using the silicon oxide films 441 to 442 which are the sixth insulating films, the thermal history given to the tunnel oxide film and the like is reduced, and the rework can be easily performed. Manufacture Example 18 In this Manufacture Example, when the island-shaped semiconductor layer 110 is formed by processing the p-type silicon substrate 100 using the resist R1 patterned by a known photolithography technique,
A case will be described in which the diameter of the island-shaped semiconductor layer 110 defined during the patterning of the resist R1 is further increased to be processed and formed.

161-163 and 164-.
FIG. 166 is a cross-sectional view taken along the line AA ′ and the line BB ′ in FIG. 1, which is a plan view showing the memory cell array of the EEPROM.

In Manufacturing Example 1, the space between the island-shaped semiconductor layers in the memory cell array can be made larger by providing the floating gate inside the island-shaped semiconductor layer 110.
Therefore, the diameter of the island-shaped semiconductor layer 110 may be increased without changing the arrangement interval of the island-shaped semiconductor layers 110.
However, for example, in the case where the diameter of the island-shaped semiconductor layer 110 and the space between the island-shaped semiconductor layers are formed with the minimum processing dimension, the space between the island-shaped semiconductor layers cannot be formed below the minimum processing dimension. Island semiconductor layer 1
Only the diameter of 10 is increased, and the island-shaped semiconductor layer 1
The arrangement interval of 10 increases and the device capacitance decreases.

A specific example of the manufacturing process for increasing the diameter of the island-shaped semiconductor layer 110 without increasing the arrangement interval of the island-shaped semiconductor layers 110 is shown below.

According to the process of Manufacturing Example 1, for example, a silicon nitride film 310 of 200 to 2000 nm is formed as a first insulating film serving as a mask layer on the surface of the p-type silicon substrate 100.
Using the resist R1 that has been deposited and patterned by a known photolithography technique as a mask, the silicon nitride film 310 that is the first insulating film is etched by reactive ion etching, and as the first insulating film, for example, silicon is used. A nitride film 311 is deposited to a thickness of 50 to 500 nm, and anisotropic etching is performed to a thickness of about 50 nm to form a silicon nitride film 311 which is the first insulating film on the sidewall of the silicon nitride film 310 which is the first insulating film. Place in a sidewall shape
(FIGS. 161 and 164).

Silicon nitride film 310 which is the first insulating film
Using the silicon nitride film 311 which is the first insulating film as a mask, the p-type silicon substrate 100 which is the semiconductor substrate is etched by 2000 to 20000 nm by reactive ion etching to form the lattice-striped first groove portions 210. by doing,
The diameter of the island-shaped semiconductor layer 110 defined during the patterning of the resist R1 is further increased to be processed (FIG. 1).
62 and FIG. 165).

By following the steps of Manufacturing Example 1 in the subsequent steps, a semiconductor memory device having a memory function is realized by the charge state accumulated in the charge accumulation layer having the floating gate of the polycrystalline silicon film serving as the first conductive film. (FIG. 163 and FIG.
66).

As a result, the same effect as in Manufacturing Example 1 can be obtained, and the diameter of the island-shaped semiconductor layer 110 is further increased, whereby the resistance at the upper and lower portions of the island-shaped semiconductor layer 110, that is, the resistance of the source and the drain is lowered. , The drive current is increased and the cell characteristics are improved. In addition, the reduction of the source resistance is expected to reduce the back bias. In addition, the island-shaped semiconductor layer 1
Since the aperture ratio is reduced in the processing of 10, the processing at the time of trench etching is facilitated, and further, the reaction gas used at the time of etching can be reduced, and the manufacturing cost can be reduced.

Manufacture Example 19 In this Manufacture Example, as shown in FIGS. 167 and 168, the select gate is formed in the depression of the island-shaped semiconductor layer 110, similarly to the charge storage layer. It has a structure substantially similar to that of No. 1 and can be produced according to Production Example 1.

In the present invention, the charge storage layers and control gates of the memory cell transistors described in Manufacturing Examples 1 to 19 and the structure of the select gates of the select gate transistors may be in any combination.

[0259]

According to the semiconductor memory device of the present invention, by forming the memory transistor in the island-shaped semiconductor layer, it is possible to increase the capacity of the memory transistor, reduce the cell area per bit, and reduce the chip size. Can be reduced and the cost can be reduced. Particularly, when the island-shaped semiconductor layer including the memory transistor is formed to have a diameter (length) of the minimum processing dimension, and the shortest distance of the space width between the semiconductor substrate pillars is formed by the minimum processing dimension. If the number of memory transistor stages per island semiconductor layer is two,
The capacity twice that of the conventional one can be obtained. Therefore, it is possible to increase the capacity by as many as the number of memory transistor stages per island semiconductor layer. Moreover, the vertical direction, which is the direction that determines the device performance, does not depend on the minimum processing dimension, and the device performance can be maintained.

Further, according to the semiconductor memory device of the present invention, variations in characteristics of memory cells are suppressed, variations in device performance are suppressed, control is facilitated, and cost reduction is realized. That is, since the charge storage layer is embedded in the island-shaped semiconductor layer, a space can be provided between the island-shaped semiconductor layers in the memory cell array, so that the hard mask for processing the semiconductor substrate cylinder becomes, for example, a sidewall. By forming the insulating film on the side wall of the mask and performing the trench etching, it is possible to form the semiconductor substrate cylinder with a large diameter without changing the arrangement intervals of the columnarly processed semiconductor substrate cylinders even in the minimum processing dimension. Become.
At that time, the resistances at the top and bottom of the semiconductor substrate cylinder, that is, the resistances of the source and drain, decrease, the drive current increases, and the cell characteristics improve. In addition, the reduction of the source resistance is expected to reduce the back bias.

Further, since the aperture ratio is reduced in the processing of the semiconductor substrate cylinder, the processing at the time of trench etching becomes easy. Furthermore, instead of increasing the diameter of the semiconductor substrate cylinder, if it is possible to reduce the arrangement interval of the semiconductor substrate cylinders in the minimum processing size, further increase in capacity is realized, and the cell area per bit is reduced. The size of the chip can be reduced and the cost can be reduced.

Further, when the charge storage layer is built in the semiconductor substrate cylinder, the transistor of the peripheral circuit can be built in with the same structure, and the transistor can be formed at the same time when the gate electrode of the select gate transistor is formed. A conformable integrated circuit that can be formed is realized. Further, since the memory cell portion is filled with polycrystalline silicon, it becomes easy to perform channel ion implantation only in the channel portion of the select gate transistor.

By forming the impurity diffusion layer so that the active region of each memory cell is in a floating state with respect to the substrate, the back bias effect from the substrate is eliminated, and the threshold value of each memory cell is lowered during reading. Variations in the characteristics of the memory cells do not occur, the number of cells connected in series between the bit line and the source line can be increased, and the capacity can be increased.

Further, the charge storage layer is buried inside the recess formed on the side surface of the semiconductor substrate cylinder through the tunnel oxide film, and anisotropic etching is performed along the side surface processed into a columnar shape, thereby forming the floating gate. Processing can be done in a batch.
That is, the tunnel oxide film and the charge storage layer are of the same quality for each memory cell.

Moreover, in order to process the semiconductor substrate into a column having at least one recess, a mask made of an insulating film is formed on the side surface of the semiconductor substrate column, and only the place where the recess is formed is opened. Thermal oxidation or a combination of isotropic etching and thermal oxidation to remove damages, defects and irregularities on the substrate surface can be used as a good active region surface. In particular, when the depressions are surrounded by using a circular pattern, local electric field concentration can be avoided from occurring on the active region surface, and electrical control can be easily performed. Further, the driving current and the S value are increased by disposing the transistor on the columnar semiconductor substrate so as to surround the gate electrode of the transistor. The effect of improving the drive current and increasing the S value is due to the reduction of the column diameter in the active region of the memory cell, which is controlled by the thermal oxide film thickness when forming the depression or the isotropic etching amount and the thermal oxide film thickness. The electric field concentration effect is increased, and the active region of the memory cell is further curved due to the three-dimensional electric field concentration effect due to the curvature in the height direction of the semiconductor substrate cylinder, and a faster device characteristic is realized during writing.

By bending the active region of the memory cell, the active region per unit height forming the memory cell can be formed longer, and the gate length along the semiconductor substrate cylinder, that is, from the lower end to the upper end of the gate, is correspondingly increased. The height difference can be set small, and the height of the semiconductor substrate cylinder is reduced. This facilitates formation of the semiconductor substrate cylinder by anisotropic etching, reduces the reaction gas used for etching, and reduces the manufacturing cost. Further, since the active region of the memory cell is curved, the end of the impurity diffusion layer is located closer to the gate electrode than the active region surface of the memory cell.
The current path due to punch through runs along the surface of the active area,
Control by the gate electrode voltage becomes easy, and the punch-through breakdown voltage improves.

[Brief description of drawings]

FIG. 1 is a plan view showing a memory cell array of an EEPROM having a floating gate as a charge storage layer in a semiconductor memory device of the present invention.

FIG. 2 EEP having a floating gate as a charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 3 EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 4 EEP having a floating gate as a charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 5: EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 6 EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 7: EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 8: EEP with floating gate as charge storage layer
It is a top view which shows another memory cell array of ROM.

FIG. 9 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer in the semiconductor memory device of the present invention.

10 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.

11 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.

FIG. 12 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 13 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 14 is a cross-sectional view corresponding to the BB ′ cross-sectional view in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 15 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of the semiconductor memory device having a floating gate as a charge storage layer.

16 is a cross-sectional view corresponding to the cross-sectional view taken along the line BB ′ in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

17 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 18 is a cross-sectional view corresponding to the cross-sectional view taken along the line BB ′ in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 19 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.

20 is a cross-sectional view corresponding to the cross-sectional view taken along the line BB ′ in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 21 is a cross-sectional view corresponding to the AA ′ cross-sectional view in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

22 is a cross-sectional view corresponding to the cross-sectional view taken along the line BB ′ in FIG. 1 of the semiconductor memory device having the floating gate as the charge storage layer.

FIG. 23 is an equivalent circuit diagram of the semiconductor memory device of the present invention.

FIG. 24 is an equivalent circuit diagram of the semiconductor memory device of the present invention.

FIG. 25 is an equivalent circuit diagram of the semiconductor memory device of the present invention.

FIG. 26 is an equivalent circuit diagram of the semiconductor memory device of the present invention.

FIG. 27 is an equivalent circuit diagram of the semiconductor memory device of the present invention.

FIG. 28 is a diagram showing an example of a timing chart at the time of reading of the semiconductor memory device of the present invention.

FIG. 29 is a diagram showing an example of a timing chart at the time of writing in the semiconductor memory device of the present invention.

FIG. 30 is a diagram showing an example of a timing chart at the time of erasing of the semiconductor memory device of the present invention.

FIG. 31 is a diagram showing an example of a timing chart at the time of another reading of the semiconductor memory device of the present invention.

FIG. 32 is a diagram showing an example of a timing chart at the time of another writing of the semiconductor memory device of the present invention.

FIG. 33 is a diagram showing an example of another timing chart at the time of erasing of the semiconductor memory device of the present invention.

FIG. 34 is a diagram showing an example of a timing chart at the time of another writing of the semiconductor memory device of the present invention.

FIG. 35 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 36 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 37 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 38 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 39 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 40 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

41 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

FIG. 42 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 43 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 44 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 45 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 46 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 47 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 48 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 1 of the semiconductor memory device of the present invention.

FIG. 49 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a first manufacturing example of the semiconductor memory device of the present invention.

FIG. 50 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 51 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 52 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 1 of the semiconductor memory device of the present invention.

FIG. 53 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 54 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 55 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 56 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 57 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 58 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 59 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 60 is a sectional (AA ′ line in FIG. 1) process drawing showing a first manufacturing example of the semiconductor memory device of the present invention.

FIG. 61 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 62 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 63 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 64 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 65 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 66 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 67 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 68 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 69 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 70 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

71 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.

72 is a sectional (BB ′ line in FIG. 1) process drawing showing a first manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 73 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 74 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 75 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 76 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

77 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

78 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

FIG. 79 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 80 is a sectional (BB ′ line in FIG. 1) process drawing showing a first manufacturing example of the semiconductor memory device of the present invention.

81 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.

FIG. 82 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention.

FIG. 83 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 84 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

FIG. 85 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 1 of the semiconductor memory device of the present invention.

86 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Manufacturing Example 1 of the semiconductor memory device of the present invention. FIG.

87 is a cross-sectional (AA 'line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

88 is a sectional (BB ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention; FIG.

89 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a second manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 90 is a sectional (BB ′ line in FIG. 1) process diagram showing a second manufacturing example of the semiconductor memory device of the present invention.

FIG. 91 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 3 of the semiconductor memory device of the present invention.

FIG. 92 is a sectional (BB ′ line in FIG. 1) process drawing showing a third manufacturing example of the semiconductor memory device of the present invention.

93 is a cross-sectional (AA 'line in FIG. 1) process drawing showing a fourth example of manufacturing the semiconductor memory device of the present invention. FIG.

FIG. 94 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 4 of the semiconductor memory device of the present invention.

FIG. 95 is a cross-sectional (AA ′ line in FIG. 1) process diagram showing a fourth manufacturing example of the semiconductor memory device of the present invention.

96 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 4 of the semiconductor memory device of the present invention. FIG.

97 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Manufacturing Example 5 of the semiconductor memory device of the present invention. FIG.

98 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a fifth example of manufacturing the semiconductor memory device of the present invention. FIG.

99 is a section (AA 'line in FIG. 1) process drawing showing a sixth example of manufacturing a semiconductor memory device of the present invention. FIG.

FIG. 100 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a sixth manufacturing example of the semiconductor memory device of the present invention.

101 is a diagram for explaining the position of a depletion layer in FIG. 99. FIG.

102 is a sectional (AA ′ line in FIG. 1) process drawing showing a seventh manufacturing example of the semiconductor memory device of the present invention. FIG.

103 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a seventh manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 104 is a sectional (AA ′ line in FIG. 1) process diagram showing a manufacturing example 8 of the semiconductor memory device of the present invention.

FIG. 105 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 8 of the semiconductor memory device of the present invention.

FIG. 106 is a sectional (AA ′ line in FIG. 1) process drawing showing a ninth example of manufacturing the semiconductor memory device of the present invention.

FIG. 107 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a ninth manufacturing example of the semiconductor memory device of the present invention.

FIG. 108 is a sectional (AA ′ line in FIG. 1) process drawing showing a ninth example of manufacturing the semiconductor memory device of the present invention.

FIG. 109 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a ninth manufacturing example of the semiconductor memory device of the present invention.

110 is a sectional (AA 'line in FIG. 1) process drawing showing a manufacturing example 10 of the semiconductor memory device of the present invention. FIG.

111 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 10 of the semiconductor memory device of the present invention. FIG.

112 is a sectional (AA 'line in FIG. 1) process drawing showing a manufacturing example 10 of the semiconductor memory device of the present invention. FIG.

113 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 10 of the semiconductor memory device of the present invention. FIG.

FIG. 114 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 11 of the semiconductor memory device of the present invention.

115 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 11 of the semiconductor memory device of the present invention. FIG.

FIG. 116 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 11 of the semiconductor memory device of the present invention.

117 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 11 of the semiconductor memory device of the present invention. FIG.

118 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 12 of the semiconductor memory device of the present invention. FIG.

FIG. 119 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 12 of the semiconductor memory device of the present invention.

FIG. 120 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 12 of the semiconductor memory device of the present invention.

121 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 12 of the semiconductor memory device of the present invention. FIG.

FIG. 122 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 123 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 124 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 125 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

126 is a cross-sectional (AA 'line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention. FIG.

127 is a cross-sectional (AA 'line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention. FIG.

FIG. 128 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 13 of the semiconductor memory device of the present invention.

FIG. 129 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 130 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

131 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention. FIG.

132 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention. FIG.

133 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 13 of the semiconductor memory device of the present invention. FIG.

FIG. 134 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 135 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 136 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

137 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention. FIG.

FIG. 138 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 139 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing Production Example 13 of the semiconductor memory device of the present invention.

FIG. 140 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing Production Example 14 of the semiconductor memory device of the present invention.

141 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 14 of the semiconductor memory device of the present invention; FIG.

142 is a diagram for explaining a depletion layer in FIG. 140. FIG.

FIG. 143 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention.

144 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention. FIG.

FIG. 145 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention.

146 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 15 of the semiconductor memory device of the present invention. FIG.

FIG. 147 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a sixteenth manufacturing example of the semiconductor memory device of the present invention.

FIG. 148 is a sectional (BB ′ line in FIG. 1) process drawing showing a sixteenth manufacturing example of the semiconductor memory device of the present invention.

FIG. 149 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 16 of the semiconductor memory device of the present invention.

150 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a sixteenth manufacturing example of the semiconductor memory device of the present invention. FIG.

151 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

152 is a sectional (AA 'line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention. FIG.

153 is a sectional (AA ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention; FIG.

FIG. 154 is a sectional (AA ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention.

FIG. 155 is a sectional (AA ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention.

156 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 17 of the semiconductor memory device of the present invention. FIG.

157 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention. FIG.

158 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention. FIG.

159 is a sectional (BB ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention. FIG.

FIG. 160 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a seventeenth manufacturing example of the semiconductor memory device of the present invention.

FIG. 161 is a cross-sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention.

162 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention. FIG.

FIG. 163 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention.

FIG. 164 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention.

FIG. 165 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention.

FIG. 166 is a cross-sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 18 of the semiconductor memory device of the present invention.

FIG. 167 is a sectional (AA ′ line in FIG. 1) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention.

FIG. 168 is a sectional (BB ′ line in FIG. 1) process drawing showing a manufacturing example 19 of the semiconductor memory device of the present invention.

FIG. 169 is a plan view showing a conventional EEPROM.

170 is a cross-sectional view taken along the line AA ′ and the line BB ′ of FIG. 800. FIG.

FIG. 171 is a step sectional view showing the method of manufacturing the conventional EEPROM.

172 is a step cross-sectional view showing the method of manufacturing the conventional EEPROM. FIG.

FIG. 173 is a process sectional view showing the method of manufacturing the conventional EEPROM.

FIG. 174 is a step sectional view showing the method of manufacturing the conventional EEPROM.

FIG. 175 is a plan view of a conventional EEPROM and a corresponding equivalent circuit diagram.

FIG. 176 is a cross-sectional view of a memory cell having a conventional MNOS structure.

FIG. 177 is a cross-sectional view of another conventional MNOS structure memory cell.

FIG. 178 is a cross-sectional view of a semiconductor device in which a plurality of memory cells are formed in one columnar silicon layer.

[Explanation of symbols]

100 P-type semiconductor substrate 101 P-type SOI semiconductor substrate layer 110 Island-shaped semiconductor layers 210, 220, 250 Groove portions 400, 410, 420, 431, 432, 433, 440, 441, 442, 450,
460, 461, 462, 463, 464, 465, 471, 472, 481, 484,
490 Silicon oxide film 310, 311, 321, 322, 323 Silicon nitride film 500, 510, 512, 513, 520, 521, 522, 523, 524, 530
Polycrystalline silicon film 612, 613 Interlayer insulation film 622, 623 Multilayer insulation film 710, 720, 721, 722, 723, 724 Impurity diffusion layer 810, 821, 824, 832, 833, 840 Wiring layer 910, 921, 932, 933 , 924 Contact R1, R2, R3, R4, R5 Resist light1 Light

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Taku Tanigami             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company (72) Inventor Kei Yokoyama             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company (72) Inventor Noboru Takeuchi             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F term (reference) 5F083 EP03 EP22 EP33 EP34 EP49                       EP55 EP76 ER03 ER09 ER14                       ER22 ER23 ER30 GA09 HA02                       JA04 JA36 LA12 LA16 NA01                       NA08 PR07 PR37 PR39 PR40                 5F101 BA12 BA13 BA29 BA36 BB02                       BC02 BC11 BD34 BE05 BE06

Claims (22)

[Claims] 1. A semiconductor substrate, at least one island-shaped semiconductor layer, a charge storage layer formed on all or part of the periphery of the side wall of the island-shaped semiconductor layer, and formed on the charge storage layer. A semiconductor memory device including at least one memory cell including a control gate, and at least one of the charge storage layers has a part thereof inside a recess formed in a sidewall of the island-shaped semiconductor layer. A semiconductor memory device characterized by being arranged. 2. The gate electrode for selecting the memory cell, which is formed at at least one end of the memory cell and is arranged in series with respect to the memory cell. Semiconductor memory device. 3. The control gate is formed on all or part of the periphery of the side wall of the charge storage layer, and the gate electrode is formed so as to surround part of or the periphery of the side wall of the island-shaped semiconductor layer. Item 3. The semiconductor memory device according to item 1 or 2. 4. The control gate is formed on all or part of the periphery of the side wall of the charge storage layer, and the gate electrode is partly arranged inside the recess formed on the side wall of the island-shaped semiconductor layer. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has the same deviation. 5. A semiconductor device in which a memory cell is formed of an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed in a semiconductor substrate or an island-shaped semiconductor layer, or formed in the semiconductor substrate or the island-shaped semiconductor layer. 5. The semiconductor substrate is electrically insulated from the semiconductor substrate by an impurity diffusion layer having a conductivity type opposite to that of the substrate and an impurity diffusion layer having the same conductivity type as the semiconductor substrate formed in the impurity diffusion layer. The semiconductor memory device according to any one of claims. 6. A plurality of memory cells are formed, and at least one of the plurality of memory cells is formed from another memory cell by an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed in the island-shaped semiconductor layer or the island. Electrically insulated by an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed in the semiconductor layer and an impurity diffusion layer having the same conductivity type as the semiconductor substrate formed in the impurity diffusion layer. The semiconductor memory device according to claim 1. 7. The semiconductor substrate according to claim 1, which is electrically insulated from the semiconductor substrate by an impurity diffusion layer and a depletion layer formed at a junction between the semiconductor substrate or the island-shaped semiconductor layer. The semiconductor memory device described. 8. A plurality of memory cells are formed, at least one of the plurality of memory cells is formed from another memory cell, and an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed in the island-shaped semiconductor layer, and the impurities. 8. The semiconductor memory device according to claim 1, which is electrically insulated from the semiconductor substrate by a depletion layer formed at a junction between the diffusion layer and the semiconductor substrate or the island-shaped semiconductor layer. . 9. The semiconductor memory device according to claim 1, wherein the impurity diffusion layer formed on the semiconductor substrate is a common wiring for at least one memory cell. 10. The semiconductor memory device according to claim 1, wherein a plurality of memory cells are formed for one island-shaped semiconductor layer, and these memory cells are arranged in series. 11. A plurality of island-shaped semiconductor layers are arranged in a matrix, a wiring for reading out a charge storage state of a memory cell is formed in the island-shaped semiconductor layer, and a plurality of control gates are continuous in one direction. 11. The control gate line is arranged in a pattern to form a control gate line, and a plurality of wirings in a direction intersecting with the control gate line are connected to form a bit line.
The semiconductor storage device according to item 1. 12. The island-shaped semiconductor layer facing the gate electrode is electrically formed from a semiconductor substrate or a memory cell by an impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate surface or the semiconductor substrate formed on the island-shaped semiconductor layer. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is insulated. 13. A semiconductor substrate, which has a conductivity type opposite to that of a semiconductor substrate, is self-aligned with a charge storage layer and partially or entirely around a sidewall of an island-shaped semiconductor layer so that channel layers of memory cells are electrically connected to each other. 12. An impurity diffusion layer or an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate and an impurity diffusion layer having the same conductivity type as the semiconductor substrate formed in the impurity diffusion layer are formed. 1. The semiconductor storage device according to one. 14. The island-shaped semiconductor layer is self-aligned with the charge storage layer and the gate electrode so that the channel layer arranged in the island-shaped semiconductor layer facing the gate electrode is electrically connected to the channel layer of the memory cell. An impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate, or an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate, and the same conductivity as the semiconductor substrate formed in the impurity diffusion layer, on a part or all of the periphery of the sidewall of the semiconductor substrate. 12. The semiconductor memory device according to claim 1, wherein a semiconductor type impurity diffusion layer is formed. 15. The semiconductor memory device according to claim 1, wherein the control gates are arranged close to each other so that the channel layers of the memory cells are electrically connected to each other. 16. The control gate and the gate electrode are arranged close to each other so that the channel layer arranged in the island-shaped semiconductor layer facing the gate electrode is electrically connected to the channel layer of the memory cell. 12. The semiconductor memory device according to any one of items 1 to 11. 17. The semiconductor memory device according to claim 1, further comprising an electrode between the control gates for electrically connecting the channel layers of the memory cells. 18. An electrode is further provided between the control gate and the gate electrode for electrically connecting the channel layer arranged in the island-shaped semiconductor layer facing the gate electrode and the channel layer of the memory cell. The semiconductor memory device according to claim 1. 19. The semiconductor memory device according to claim 1, wherein the control gate and all or part of the gate electrode are formed of the same material. 20. The semiconductor memory device according to claim 1, wherein the charge storage layer and the gate electrode are formed of the same material. 21. A plurality of island-shaped semiconductor layers are arranged in a matrix, and the width in one direction of the island-shaped semiconductor layers is larger than the distance between adjacent island-shaped semiconductor layers in the same direction. 1. The semiconductor memory device according to one. 22. A plurality of island-shaped semiconductor layers are arranged in a matrix, and the distance between the island-shaped semiconductor layers in one direction is smaller than the distance between the island-shaped semiconductor layers in different directions. The semiconductor storage device according to item 1.