JP3963677B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a semiconductor memory device including a memory transistor having a charge storage layer and a control gate and a manufacturing method thereof.
[0002]
[Prior art]
As a memory cell of an EEPROM, a device having a MOS transistor structure having a charge storage layer and a control gate in a gate portion and injecting a charge into the charge storage layer using a tunnel current and discharging a charge from the charge storage layer Are known. In this memory cell, the difference in threshold voltage due to the difference in charge storage state of the charge storage layer is stored as data “0” and “1”. For example, in the case of an n-channel memory cell using a floating gate as a charge storage layer, in order to inject electrons into the floating gate, the source and drain diffusion layers and the substrate are grounded and a positive high voltage is applied to the control gate. . At this time, electrons are injected from the substrate side into the floating gate by a tunnel current. By this electron injection, the threshold voltage of the memory cell moves in the positive direction. In order to discharge the electrons of the floating gate, the control gate is grounded and a positive high voltage is applied to any of the source, drain diffusion layer, and substrate. At this time, electrons on the substrate side are emitted from the floating gate by a tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction.
[0003]
In the above operation, in order to efficiently perform electron injection and emission, that is, writing and erasing, the relationship of capacitive coupling between the floating gate and the control gate and between the floating gate and the substrate is important. That is, as the capacitance between the floating gate and the control gate increases, the potential of the control gate can be effectively transmitted to the floating gate, and writing and erasing are facilitated.
However, due to advances in semiconductor technology in recent years, particularly advances in microfabrication technology, the size and capacity of EEPROM memory cells are rapidly increasing. Therefore, the memory cell area is small, and how to secure a large capacity between the floating gate and the control gate is an important problem.
In order to increase the capacitance between the floating gate and the control gate, the gate insulating film between them is thinned, the dielectric constant is increased, or the opposing area of the floating gate and the control gate is increased. is required.
[0004]
However, thinning the gate insulating film has a limit in reliability. In order to increase the dielectric constant of the gate insulating film, for example, it is conceivable to use a silicon nitrogen film or the like instead of the silicon oxide film, but this also has a problem mainly in reliability and is not practical.
Therefore, in order to secure a sufficient capacity, it is necessary to secure an overlap area of the floating gate and the control gate at a certain value or more. This becomes an obstacle to reducing the memory cell area and increasing the capacity of the EEPROM.
[0005]
On the other hand, in the EEPROM described in Japanese Patent No. 2877462, a memory transistor is configured by using the side walls of a plurality of columnar semiconductor layers that are separated from each other by a grid stripe-like groove on a semiconductor substrate. That is, the memory transistor has a drain diffusion layer formed on the top surface of each columnar semiconductor layer, a common source diffusion layer formed on the bottom of the groove, a charge storage layer surrounding the entire periphery of the side wall of each columnar semiconductor layer, and a control gate. The control gate is continuously arranged for a plurality of columnar semiconductor layers in one direction to form a control gate line. In addition, a bit line connected to the drain diffusion layer of the plurality of memory transistors in a direction intersecting with the control gate line is provided, and the charge storage layer and the control gate of the memory transistor described above are formed below the columnar semiconductor layer. The In the 1-transistor / 1-cell configuration, when the memory transistor is in an over-erased state, that is, when the read potential is 0 V and the threshold value is in a negative state, the cell current flows even if it is not selected. It is. In order to prevent this reliably, a selection gate transistor having a gate electrode formed so as to surround at least a part of the periphery of the columnar semiconductor layer is provided over the columnar semiconductor layer.
[0006]
Thus, the memory cell of the conventional EEPROM has a charge storage layer and a control gate formed so as to surround the columnar semiconductor layer using the side wall of the columnar semiconductor layer. A sufficiently large capacity between the control gates can be secured. Also, the drain diffusion layer connected to the bit line of each memory cell is formed on the upper surface of the columnar semiconductor layer, and is completely electrically separated by the groove. Further, the element isolation region can be reduced, and the memory cell size is reduced. Therefore, it is possible to obtain a large capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated.
[0007]
FIG. 344 shows a case where the columnar silicon layer 2 is cylindrical, that is, the upper surface is circular. The outer shape of the columnar silicon layer may not be cylindrical. A conventional example will be described below with reference to the drawings.
FIG. 344 is a plan view of a conventional EEPROM, and FIG. 345 is a cross-sectional view taken along lines A-A ′ and B-B ′ of FIG. 344. In FIG. 344, the selection gate line in which the gate electrodes of the selection gate and the transistor are continuously formed is not shown because it becomes complicated.
[0008]
In the conventional example, a plurality of columnar p-type silicon layers 2 separated by latticed grooves 3 are arranged in a matrix on a p-type silicon substrate 1, and each of these columnar silicon layers 2 is a memory cell region. A drain diffusion layer 10 is formed on the upper surface of each silicon layer 2, a common source diffusion layer 9 is formed at the bottom of the groove 3, and an oxide film 4 having a predetermined thickness is embedded in the bottom of the groove 3. Further, a floating gate 6 is formed below the columnar silicon layer 2 via a tunnel oxide film 5 so as to surround the columnar silicon layer 2, and a control gate 8 is formed outside the columnar silicon layer 2 via an interlayer insulating film 7. The memory transistor is formed. Here, as shown in FIG. 344 and FIG. 345 (b), the control gate 8 is continuously arranged for a plurality of memory cells in one direction, and the control gate line, that is, the word line WL (WL1, WL2,. ). Then, a gate electrode 32 is disposed on the upper part of the columnar silicon layer 2 via a gate oxide film 31 so as to surround the periphery of the column like the memory transistor, thereby forming a selection gate transistor. Similar to the control gate 8 of the memory cell, the gate electrode 32 of this transistor is continuously arranged in the same direction as the control gate line to become a selection gate line.
[0009]
As described above, the memory transistor and the select gate transistor are embedded in a state of being stacked inside the trench. One end portion of the control gate line is left as a contact portion 14 on the surface of the silicon layer, and the selection gate line is also left in the silicon layer at the opposite end to the control gate, and the word line WL and the control gate are respectively provided. Al wirings 13 and 16 to be lines CG are in contact.
A common source diffusion layer 9 of the memory cells is formed at the bottom of the trench 3, and a drain diffusion layer 10 for each memory cell is formed on the upper surface of each columnar silicon layer 2. The substrate of the memory cell thus formed is covered with a CVD oxide film 11, a contact hole is opened in this, and a bit line commonly connecting the drain diffusion layers 10 of the memory cells in a direction intersecting the word line WL Al wiring 12 to be BL (BL1, BL2,...) Is provided. When patterning the control gate line, a PEP mask is formed at the columnar silicon layer at the end of the cell array, and a contact portion 14 made of a polycrystalline silicon film continuous with the control gate line is left on the surface. In addition, an Al wiring 13 serving as a word line is contacted by an Al film formed simultaneously with the bit line BL.
[0010]
A specific manufacturing process example for obtaining the structure corresponding to FIG. 345 (a) will be described with reference to FIGS. 346 (a) to 349 (g).
[0011]
Using a wafer obtained by epitaxially growing a low impurity concentration p-type silicon layer 2 on a high impurity concentration p type silicon substrate 1, a mask layer 21 is deposited on the surface, and a photoresist pattern 22 is formed by a known PEP process. Then, the mask layer 21 is etched using this (FIG. 346 (a)).
[0012]
Then, using the mask layer 21, the silicon layer 2 is etched by a reactive ion etching method to form a lattice-like groove 3 having a depth reaching the substrate 1. Thereby, the silicon layer 2 is separated into a plurality of islands in a columnar shape. Thereafter, a silicon oxide film 23 is deposited by the CVD method, and this is left on the side wall of each columnar silicon layer 2 by anisotropic etching. Then, the drain diffusion layer 10 is formed on the upper surface of each columnar silicon layer 2 by ion implantation of n-type impurities, and the common source diffusion layer 9 is formed at the bottom of the groove (FIG. 346 (b)).
Thereafter, the oxide film 23 is etched away around each columnar silicon layer 2 by isotropic etching, and then channel ion implantation is performed on the sidewalls of each silicon layer 2 using oblique ion implantation as necessary. Instead of channel ion implantation, an oxide film containing boron may be deposited by a CVD method, and boron diffusion from the oxide film may be used. Then, a CVD silicon oxide film 4 is deposited and etched by isotropic etching to bury an oxide film having a predetermined thickness at the bottom of the groove 3.
[0013]
Next, a tunnel oxide film 5 of about 10 nm, for example, is formed around each silicon layer 2 by thermal oxidation, and then a first-layer polycrystalline silicon film is deposited. This first layer polycrystalline silicon film is etched by anisotropic etching to leave the lower side wall of the columnar silicon layer 2 to form a floating gate 6 surrounding the silicon layer 2 (FIG. 347 (c)).
Subsequently, an interlayer insulating film 7 is formed on the surface of the floating gate 6 formed around each columnar silicon layer 2. The interlayer insulating film 7 is, for example, an ONO film. Specifically, after oxidizing the surface of the floating gate 6 to a predetermined thickness, a silicon nitride film is deposited by plasma CVD, and the surface is thermally oxidized to form an ONO film. Then, a second-layer polycrystalline silicon film is deposited and etched by anisotropic etching, thereby forming the control gate 8 below the columnar silicon layer 2 (FIG. 347 (d)). At this time, the control gate 8 sets the interval between the columnar silicon layers 2 to a predetermined value or less in advance in the vertical direction of FIG. 344, so that a control gate line continuous in that direction can be used without using a mask process. It is formed. Then, the unnecessary interlayer insulating film 7 and the tunnel oxide film 2 thereunder are removed by etching, and then a CVD silicon oxide film 111 is deposited and etched to the middle of the groove 3, that is, the floating gate 7 and the control of the memory cell. It is buried until the gate 8 is hidden (FIG. 348 (e)).
[0014]
Thereafter, a gate oxide film 31 of about 20 nm is formed on the exposed columnar silicon layer 2 by thermal oxidation, and then a third-layer polycrystalline silicon film is deposited and etched by anisotropic etching to form a MOS transistor. The gate electrode 32 is formed (FIG. 348 (f)). The gate electrode 32 is also continuously patterned in the same direction as the control gate line to become a selection gate line. Although the selection gate lines can also be formed continuously by self-alignment, it is more difficult than the control gate 8 of the memory cell. This is because the memory transistor portion is a two-layer gate, whereas the select gate transistor is a single-layer gate, so that the gate electrode interval between adjacent cells is wider than the control gate interval. Therefore, in order to ensure that the gate electrode 32 continues, this is made into a two-layer polycrystalline silicon structure, and the first polycrystalline silicon film is left only in the portion where the gate electrode is connected in the mask process, and the next polycrystalline silicon film is formed. On the other hand, the technique of leaving the side wall may be used.
Note that a mask is formed in the etching of the polycrystalline silicon film so that the contact portions 14 and 15 are formed on the upper surface of the columnar silicon layer at different end portions of the control gate line and the selection gate line.
[0015]
Finally, a CVD silicon oxide film 112 is deposited, and if necessary flattened, then contact holes are opened, and Al wirings 12 and control gate lines CG that become bit lines BL are formed by vapor deposition and patterning of Al. The Al wiring 13 and the Al wiring 16 that becomes the word line WL are simultaneously formed (FIG. 349 (g)).
[0016]
FIG. 350 (a) shows a cross-sectional structure of the main part of one memory cell of this conventional EEPROM, and FIG. 275 (b) shows an equivalent circuit.
The operation of the conventional EEPROM will be briefly described with reference to FIGS. 350 (a) and 350 (b).
[0017]
First, in the case of using hot carrier injection for writing, a sufficiently high positive potential is applied to the selected word line WL, and a predetermined positive potential is applied to the selection control gate line CG and the selected bit line BL. As a result, a positive potential is transmitted to the drain of the memory transistor Qc through the selection gate transistor Qs, and a channel current is caused to flow through the memory transistor Qc to perform hot carrier injection. As a result, the threshold value of the memory cell moves in the positive direction.
[0018]
In erasing, the selection control gate CG is set to 0 V, a high positive potential is applied to the word line WL and the bit line BL, and electrons of the floating gate are emitted to the drain side. In the case of batch erasing, a high positive potential can be applied to the common source to emit electrons to the source side. As a result, the threshold value of the memory cell moves in the negative direction.
[0019]
In the read operation, the selection gate transistor Qs is opened by the word line WL, the read potential of the control gate line CG is applied, and “0” or “1” is discriminated by the presence or absence of current. When FN tunneling is used for electron injection, a high positive potential is applied to the selected control gate line CG and the selected word line WL, the selected bit line BL is set to 0 V, and electrons are injected from the substrate to the floating gate.
In addition, according to this conventional example, since there is a select gate transistor, an EEPROM which does not malfunction even in an overerased state can be obtained.
[0020]
By the way, in this conventional example, as shown in FIG. 350A, there is no diffusion layer between the select gate transistor Qs and the memory transistor Qc. This is because it is difficult to selectively form a diffusion layer on the side surface of the columnar silicon layer. Therefore, in the structure of FIGS. 345 (a) and 345 (b), it is desirable that the isolation oxide film between the gate portion of the memory transistor and the gate portion of the select gate transistor is as thin as possible. In particular, when hot electron injection is used, the isolation oxide film thickness needs to be about 30 to 40 nm in order to transmit a sufficient “H” level potential to the drain of the memory transistor.
Such a minute interval is practically difficult only by filling the oxide film by the CVD method described in the previous manufacturing process. Therefore, the filling with the CVD oxide film exposes the floating gate 6 and the control gate 8, and simultaneously forms a thin oxide film on the exposed portions of the floating gate 6 and the control gate 8 in the gate oxidation process for the select gate transistor. The method is desirable.
[0021]
Further, according to the conventional example, a columnar silicon layer is arranged with the lattice-shaped groove bottom as an isolation region, and a memory cell having a floating gate formed so as to surround the columnar silicon layer is configured. A highly integrated EEPROM with a small area occupied by memory cells can be obtained. In addition, although the memory cell occupation area is small, a sufficiently large capacitance between the floating gate and the control gate can be secured.
In the conventional example, the control gate of each memory cell is formed continuously in one direction without using a mask. This is only possible if the columnar silicon layers are not symmetrically arranged. That is, by making the interval between the columnar silicon layers in the word line direction smaller than that in the bit line direction, control gate lines that are separated in the bit line direction and connected in the word line direction are automatically obtained without a mask. .
[0022]
On the other hand, for example, when the columnar silicon layers are arranged symmetrically, a PEP process is required.
More specifically, the second-layer polycrystalline silicon film is deposited thick and is selectively etched through the PEP process so as to leave it in a portion to be continued as a control gate line.
Next, a third-layer polycrystalline silicon film is deposited, and etching of the remaining sidewall is performed in the same manner as described in the conventional example. Further, even when the arrangement of the columnar silicon layers is not symmetric, depending on the arrangement interval, it may not be possible to form a continuous control gate line automatically as in the conventional example.
Even in such a case, a control gate line continuous in one direction may be formed by using the mask process as described above.
[0023]
In the conventional example, a memory cell having a floating gate structure is used. However, the charge storage layer does not necessarily have a floating gate structure, and the charge storage layer is realized by trapping in a multilayer insulating film. It is also effective in some cases.
FIG. 351 is a cross-sectional view corresponding to FIG. 345 (a) in the case where a memory cell having an MNOS structure is used. The laminated insulating film 24 serving as a charge storage layer has a laminated structure of a tunnel oxide film and a silicon nitride film, or a structure in which an oxide film is further formed on the nitride film surface.
FIG. 352 shows an example in which the memory transistor and the selection gate transistor are reversed in the conventional example, that is, the selection gate transistor is formed below the columnar silicon layer 2 and the memory transistor is formed above. It is sectional drawing corresponding to (a). This structure in which a select gate transistor is provided on the common source side can be employed when a hot electron injection method is used as a writing method.
FIG. 353 shows a conventional example in which a plurality of memory cells are formed in one columnar silicon layer. Portions corresponding to the previous conventional example are denoted by the same reference numerals as those of the previous conventional example, and detailed description thereof is omitted. In this conventional example, a select gate transistor Qs1 is formed at the bottom of the columnar silicon layer 2, three memory transistors Qc1, Qc2, and Q3c are stacked thereon, and a select gate transistor Qs2 is formed thereon. is doing. This structure is basically obtained by repeating the manufacturing process described above.
In the conventional example described with reference to FIGS. 352 and 353, the MNOS structure can be used as the memory transistor instead of the floating gate structure.
[0024]
As described above, according to the prior art, by using the side walls of the columnar semiconductor layers separated by the lattice-like grooves, by configuring a memory cell using a memory transistor having a charge storage layer and a control gate, An EEPROM can be obtained in which a sufficiently large capacity is ensured between the control gate and the charge storage layer and the area occupied by the memory cells is reduced to achieve high integration.
[0025]
[Problems to be solved by the invention]
However, when a plurality of memory cells are connected in series to one columnar semiconductor layer and the threshold value of each memory cell is considered to be the same, a read potential is applied to the control gate line CG and the presence or absence of current is determined. In the read operation for discriminating “0” or “1”, in the memory cells located at both ends connected in series, the fluctuation of the threshold becomes remarkable due to the back bias effect from the substrate. As a result, the number of memory cells connected in series is restricted on the device, which causes a problem when the capacity is increased.
Also, when forming a transistor in a direction perpendicular to the substrate, if the transistor is formed for each stage, it depends on the difference in the tunnel film quality due to the difference in thermal history and the difference in the profile of the diffusion layer at each stage. Variations in cell characteristics occur.
[0026]
The present invention has been made in view of the above problems, and improves the degree of integration by reducing the influence of the back bias effect of a semiconductor memory device having a charge storage layer and a control gate without increasing the occupied area of the memory cell. In addition, the capacitance ratio between the charge storage layer and the control gate is further increased, and the memory history of each memory cell transistor due to the manufacturing process is minimized, thereby minimizing variations in memory cell characteristics. An object is to provide a method for manufacturing a device.
[0027]
[Means for Solving the Problems]
According to the present invention, a step of forming a first insulating film on a semiconductor substrate;
Patterning the first insulating film to form island-shaped insulating films separated from each other;
Forming a charge storage layer comprising a first conductive film on the sidewall of the island-like insulating film in a sidewall shape;
Forming a control gate made of a second conductive film on the side wall of the charge storage layer through an interlayer capacitance film in a sidewall shape;
Patterning the island-like insulating film to expose a part of the surface of the semiconductor substrate and the side walls of the first conductive film;
Forming a tunnel insulating film on the exposed sidewall of the first conductive film;
Forming an island-shaped semiconductor layer by epitaxial growth so as to be in contact with the tunnel insulating film;
A step of introducing an impurity into a region of the island-shaped semiconductor layer facing the first conductive film,
A semiconductor substrate, and at least one island-like semiconductor layer, at least one memory cell including a charge storage layer formed on all or part of the periphery of the sidewall of the island-like semiconductor layer, and a control gate; A semiconductor memory device manufacturing method is provided for manufacturing a semiconductor memory device in which at least one of the memory cells is electrically insulated from the semiconductor substrate.
[0028]
According to the present invention, the step of forming the first insulating film on the semiconductor substrate;
Patterning the first insulating film to form island-shaped insulating films separated from each other;
Forming a control gate comprising a first conductive film on the sidewall of the island-like insulating film in a sidewall shape;
Patterning the island-like insulating film to expose a part of the surface of the semiconductor substrate and the side walls of the first conductive film;
Forming a charge storage layer made of a laminated insulating film on the exposed sidewall of the first conductive film;
Forming an island-like semiconductor layer by epitaxial growth so as to be in contact with the charge storage layer;
A step of introducing an impurity into a region of the island-shaped semiconductor layer facing the first conductive film,
A semiconductor substrate, and at least one island-like semiconductor layer, at least one memory cell including a charge storage layer formed on all or part of the periphery of the sidewall of the island-like semiconductor layer, and a control gate; A semiconductor memory device manufacturing method is provided for manufacturing a semiconductor memory device in which at least one of the memory cells is electrically insulated from the semiconductor substrate.
[0029]
Furthermore, according to the present invention, the step of forming the first insulating film on the semiconductor substrate;
Patterning the first insulating film to form island-shaped insulating films separated from each other;
Forming a control gate and a capacitor electrode made of a first conductive film on the side wall of the island-shaped insulating film in a sidewall shape;
Patterning the island-like insulating film to expose a part of the surface of the semiconductor substrate and the side walls of the first conductive film;
Forming a gate insulating film on the exposed sidewall of the first conductive film;
Forming an island-shaped semiconductor layer by epitaxial growth so as to be in contact with the gate insulating film;
A step of introducing an impurity into a region of the island-shaped semiconductor layer facing the first conductive film,
A semiconductor substrate, and at least one island-like semiconductor layer, at least one memory cell including a charge storage layer formed on all or part of the periphery of the sidewall of the island-like semiconductor layer, and a control gate; A semiconductor memory device manufacturing method is provided for manufacturing a semiconductor memory device in which at least one of the memory cells is electrically insulated from the semiconductor substrate.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
In the semiconductor memory device of the present invention, a plurality of memory cells having a charge storage layer and a third electrode serving as a control gate are connected in series in a direction perpendicular to the semiconductor substrate surface, and the memory cell is connected to the semiconductor substrate and the semiconductor substrate. The impurity diffusion layer formed in the side wall portion of the plurality of island-shaped semiconductor layers arranged in a matrix form separated in a lattice pattern is used as the source or drain of the memory cell, and the impurity The semiconductor substrate and the island-shaped semiconductor layer are electrically separated by the diffusion layer, and the control gate is continuously arranged for the plurality of island-shaped semiconductor layers in one direction and horizontally with respect to the semiconductor substrate surface. And a fourth control gate line that is electrically connected to the impurity diffusion layer in a direction crossing the control gate line and is disposed in the horizontal direction with respect to the semiconductor substrate surface. Having a bit line is a line.
[0031]
Embodiment in plan view of memory cell array
A plan view of a memory cell array in the semiconductor memory device of the present invention will be described with reference to FIGS.
1 to 9 are plan views showing an EEPROM memory cell array having a floating gate as a charge storage layer, FIG. 10 is a memory cell array having a MONOS structure having a stacked insulating film as a charge storage layer, and FIG. FIG. 12 is a plan view showing a memory cell array having a DRAM structure having a MIS capacitor as a storage layer, and FIG. 12 showing a memory cell array having a SRAM structure having a MIS transistor as a charge storage layer. In these figures, as a gate electrode (hereinafter referred to as “selection gate”) for selecting a memory cell, a selection gate line as a second wiring or a fifth wiring, and a control gate as a third wiring The layout including the line, the bit line as the fourth wiring, and the source line as the first wiring will be described.
[0032]
First, a plan view showing an EEPROM memory cell array having a floating gate as a charge storage layer will be described.
FIG. 1 shows an arrangement in which cylindrical island-shaped semiconductor portions forming a memory cell are arranged, for example, at intersections where two kinds of parallel lines are orthogonal to each other. The one wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer indicate a memory cell array arranged in parallel to the substrate surface.
In addition, by changing the arrangement interval of the island-shaped semiconductor portions in the AA ′ direction that intersects the fourth wiring layer 1840 and the BB ′ direction that intersects the fourth wiring layer 1840, The second conductive film, which is the control gate of the cell, is continuously formed in one direction, in the direction AA ′ in FIG. 1, and becomes the third wiring layer. Similarly, the second conductive film which is the gate of the selection gate transistor is formed continuously in one direction to form the second wiring layer.
Further, a terminal for electrically connecting to the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is, for example, an end on the A ′ side of the memory cell connected in the AA ′ direction in FIG. For example, a terminal for electrically connecting to the second wiring layer and the third wiring layer is provided at the end on the A side of the memory cell connected in the AA ′ direction of FIG. The fourth wiring layer 1840 arranged on the opposite side of the substrate of the cylindrical semiconductor portion is electrically connected to each of the cylindrical island-shaped semiconductor portions forming the memory cell. For example, in FIG. A fourth wiring layer 1840 is formed in a direction intersecting with the second wiring layer and the third wiring layer.
Moreover, the terminal for electrically connecting with the 1st wiring layer is formed by the island-shaped semiconductor part, and the terminal for electrically connecting with the 2nd wiring layer and the 3rd wiring layer is island-shaped The second conductive film is formed by covering the semiconductor portion. Terminals for electrical connection with the first wiring layer, the second wiring layer, and the third wiring layer are the first contact portion 1910, the second contact portions 1921, 1924, and the third contact, respectively. Connected to the units 1932 and 1933.
[0033]
In FIG. 1, the first wiring layer 1810 is drawn to the upper surface of the semiconductor memory device via the first contact portion 1910. Note that the arrangement of the columnar island-shaped semiconductor portions forming the memory cell does not have to be as shown in FIG. 1. If there is a wiring layer positional relationship or electrical connection relationship as described above, the memory cell is formed. The arrangement of the cylindrical island-shaped semiconductor portions to be performed is not limited.
In FIG. 1, the island-like semiconductor portions connected to the first contact portion 1910 are arranged at all the end portions on the A ′ side of the memory cells connected in the AA ′ direction. May be disposed in part or all of the portion, or in any of the island-shaped semiconductor portions forming the memory cell connected in the direction AA ′ that is the direction intersecting the fourth wiring layer 1840 May be. In addition, the island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 1921 and 1924 and the third contact portions 1932 and 1933 is the end on the side where the first contact portion 1910 is not disposed. May be arranged in a portion, may be continuously arranged at an end portion on the side where the first contact portion 1910 is arranged, or AA ′ which is a direction intersecting with the fourth wiring layer 1840 It may be arranged in any of the island-like semiconductor parts forming the memory cells connected in the direction, or the second contact parts 1921 and 1924, the third contact part 1932, etc. may be arranged separately. Good. The first wiring layer 1810 and the fourth wiring layer 1840 may have any width and shape as long as desired wiring is obtained. When the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is formed in a self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film, Although the island-like semiconductor portion serving as a terminal for electrical connection to the wiring layer is electrically separated from the second wiring layer and the third wiring layer formed of the second conductive film, And in contact with each other through an insulating film. For example, in FIG. 1, a first conductive film is formed on a part of the side surface of the island-like semiconductor portion to which the first contact portion 1910 is connected via an insulating film. The first conductive film is a memory cell. The second conductive film is formed on the side surface of the first conductive film via the insulating film, and the second conductive film is the fourth conductive film. Are connected to the second wiring layer and the third wiring layer which are continuously formed in the AA ′ direction which is a direction intersecting with the wiring layer 1840. At this time, the shape of the first and second conductive films formed on the side surfaces of the island-shaped semiconductor portion is not limited. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is, for example, By setting the film thickness to not more than twice the film thickness of the conductive film, all of the first conductive film on the side surface of the island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer may be removed.
[0034]
In FIG. 1, the second and third contact portions are formed on the second conductive films 1521 to 1524 formed so as to cover the tops of the island-like semiconductor portions. Then, the shapes of the second and third wiring layers are not limited. In FIG. 1, the selection gate transistor and the polycrystalline silicon film 1530 as the third electrode are omitted because they are complicated. In FIG. 1, the cross section used in the manufacturing process example, that is, the AA ′ cross section, the BB ′ cross section, the CC ′ cross section, the DD ′ cross section, the EE ′ cross section, and the FF ′ cross section are shown together. is doing.
[0035]
FIG. 2 shows an arrangement in which the cylindrical island-shaped semiconductor portions forming the memory cells are arranged, for example, at points where two kinds of parallel lines intersect without intersecting each other, and each memory cell is selected and controlled. The first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer are the memory cell array arranged in parallel to the substrate surface. Further, by changing the arrangement interval of the island-shaped semiconductor portions in the AA ′ direction which is a direction intersecting the fourth wiring layer 1840 and the BB ′ direction in the drawing, it is a control gate of each memory cell. The second conductive film is formed continuously in one direction, and in FIG. 2, in the AA ′ direction, and becomes a third wiring layer. Similarly, a second conductive film, which is the gate of the select gate transistor, is continuously formed in one direction to become a second wiring layer. Further, a terminal for electrically connecting to the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is, for example, an end on the A ′ side of the memory cell connected in the AA ′ direction of FIG. 2 and provided with terminals for electrical connection with the second wiring layer and the third wiring layer, for example, at the end on the A side of the memory cell connected in the AA ′ direction in FIG. The fourth wiring layer 1840 arranged on the opposite side of the substrate of the cylindrical semiconductor portion is electrically connected to each of the cylindrical island-shaped semiconductor portions forming the memory cells. For example, in FIG. A fourth wiring layer 1840 is formed in a direction crossing the second wiring layer and the third wiring layer.
[0036]
A terminal for electrically connecting to the first wiring layer is formed by an island-shaped semiconductor portion, and a terminal for electrically connecting to the second wiring layer and the third wiring layer is an island-shaped semiconductor portion. It is formed with the 2nd electrically conductive film coat | covered by. Terminals for electrical connection with the first wiring layer, the second wiring layer, and the third wiring layer are the first contact portion 1910, the second contact portions 1921, 1924, and the third contact, respectively. Connected to the units 1932 and 1933.
In FIG. 2, the first wiring layer 1810 is drawn to the upper surface of the semiconductor memory device through the first contact portion 1910. Note that the arrangement of the columnar island-shaped semiconductor portions forming the memory cell does not have to be as shown in FIG. 2, and if there is a wiring layer positional relationship or electrical connection relationship as described above, the memory cell The arrangement of the columnar island-shaped semiconductor portions forming the layer is not limited.
[0037]
Further, in FIG. 2, the island-shaped semiconductor portion connected to the first contact portion 1910 is disposed at all end portions on the A ′ side of the memory cells connected in the AA ′ direction. Any of the island-shaped semiconductor portions forming the memory cells connected in the direction AA ′ that is the direction intersecting with the fourth wiring layer 1840 You may arrange in. Further, the island-shaped semiconductor portion covered with the second conductive film connected to the second contact portions 1921 and 1924 and the third contact portions 1932 and 1933 is on the side where the first contact portion 1910 is not disposed. May be disposed at the end of the first contact portion 1910, or may be disposed continuously at the end on the side where the first contact portion 1910 is disposed, or in the direction intersecting the fourth wiring layer 1840. It may be arranged in any of the island-shaped semiconductor parts forming the memory cells connected in the A ′ direction, or the second contact parts 1921 and 1924, the third contact part 1932 and the like are arranged separately. May be. The first wiring layer 1810 and the fourth wiring layer 1840 may have any width and shape as long as desired wiring is obtained.
[0038]
When the first wiring layer disposed on the substrate side of the island-shaped semiconductor portion is formed in a self-alignment with the second wiring layer and the third wiring layer formed of the second conductive film, Although the island-like semiconductor portion serving as a terminal for electrical connection to the wiring layer is electrically separated from the second wiring layer and the third wiring layer formed of the second conductive film, It has a state of being in contact through an insulating film. For example, in FIG. 2, the first conductive film is formed on a part of the side surface of the island-like semiconductor portion to which the first contact portion 1910 is connected via an insulating film, and the first conductive film forms a memory cell. A second conductive film is formed on the side surface of the first conductive film via an insulating film, and the second conductive film is a fourth wiring. It is connected to the second wiring layer and the third wiring layer formed continuously in the AA ′ direction which is a direction intersecting with the layer 1840. At this time, the shape of the 1st and 2nd electrically conductive film formed in an island-like semiconductor part side surface is not ask | required. In addition, the distance between the island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer and the first conductive film in the island-shaped semiconductor portion where the memory cell is formed is, for example, By setting the film thickness to not more than twice the film thickness of the conductive film, all of the first conductive film on the side surface of the island-shaped semiconductor portion serving as a terminal for electrical connection with the first wiring layer may be removed.
In FIG. 2, the second and third contact portions are formed on the second conductive films 1521 to 1524 formed so as to cover the tops of the island-shaped semiconductor portions. The shapes of the second and third wiring layers are not limited. In FIG. 2, the selection gate transistor is omitted because it is complicated. In FIG. 2, the cross sections used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are also shown.
[0039]
3 and FIG. 4 show the orientation in which FIG. 3 and FIG. 4 are arranged as an example when the cross-sectional shape of the island-shaped semiconductor portion forming the memory cell is a quadrangle compared to FIGS. Each example is different. The cross-sectional shape of the island-like semiconductor portion is not limited to a circle or a rectangle. For example, an elliptical shape, a hexagonal shape or an octagonal shape may be used. However, if the size of the island-shaped semiconductor part is near the processing limit, even if it has corners such as a square, hexagon, or octagon at the time of design, the corners are rounded by the photo process or etching process. The cross-sectional shape of the island-like semiconductor portion is close to a circle or an ellipse. Further, in FIG. 3 and FIG. 4, the selection gate transistor is omitted because it becomes complicated.
[0040]
FIG. 5 shows an example in which the number of memory cells formed in series in the island-shaped semiconductor portion forming the memory cell is two and no selection gate transistor is formed. In FIG. 5, the cross sections used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are also shown.
[0041]
FIG. 6 is an example in which the cross-sectional shape of the island-shaped semiconductor portion forming the memory cell is not a circle but an ellipse, as compared to FIG. 1, in which the major axis of the ellipse is in the BB ′ direction. FIG. 7 shows the case where the direction of the major axis of the ellipse is the AA ′ direction with respect to FIG. The direction of the major axis of the ellipse is not limited to the A-A ′ direction and the B-B ′ direction, and may be in any direction. In FIG. 6 and FIG. 7, the selection gate transistor is omitted because it is complicated.
[0042]
FIG. 8 shows an example in which the contact layer is formed in the desired wiring layer by removing the wiring layer, the insulating film, and the like above the desired wiring layer by anisotropic etching, as shown in FIG. An example in which a common contact portion is formed in the lead portion of the three wiring layers is shown. In the example of FIG. 8, a contact portion is formed in a desired wiring layer in common with memory cells arranged continuously in the HH ′ direction and memory cells arranged adjacently in the same manner. In the case where only one of the mutual memory cells is operated, selection of the memory cell is realized by applying a desired potential to every other fourth diffusion layer 1840. Further, in contrast to the example of FIG. 8, a contact portion is not formed in a desired wiring layer in common to memory cells arranged continuously in the HH ′ direction and memory cells arranged adjacently in the same manner. Alternatively, a contact portion may be formed in a desired wiring layer in each memory cell arranged continuously. In FIG. 8, the cross section used in the manufacturing example, that is, the H-H 'cross section and the I1-I1' cross section to the I5-I5 'cross section are also shown.
[0043]
9 differs from FIG. 2 in that polycrystalline silicon 1521 to 1524, which are second conductive films, are formed in a stepped manner in a region to be contacted, and an insulating film or the like above a desired wiring layer is formed by anisotropic etching. As an example of removing and forming a contact portion in a desired wiring layer, the second wiring layers 1821 and 1824, the third wiring layer 1832 and the like are respectively provided at the ends of the memory cells continuous in the AA ′ direction. An example in which a contact portion is formed is shown. In FIG. 9, the cross section used in the manufacturing example, that is, the H-H 'cross section and the I1-I1' cross section to the I5-I5 'cross section are also shown.
[0044]
Although the plan view of the semiconductor memory device having the floating gate as the charge storage layer has been described above, the arrangements and structures in FIGS. 1 to 9 may be used in various combinations.
[0045]
FIG. 10 shows an example in which a stacked insulating film is used for the charge storage layer as in the MONOS structure, for example, except that the charge storage layer is changed from a floating gate to a stacked insulating film. It is. In FIG. 10, the cross section used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section are shown together, but the selection gate transistor is omitted because it is complicated.
[0046]
FIG. 11 shows an example in which a MIS capacitor is used as a charge storage layer, such as a DRAM, as in FIG. 1, and the charge storage layer is changed from a floating gate to a MIS capacitor, and a bit line and a source line are parallel to each other. It is the same except that it is arranged. FIG. 11 also shows the cross sections used in the manufacturing process example, that is, the A-A ′ cross section and the B-B ′ cross section.
[0047]
FIG. 12 shows an example in which a MIS transistor is used as a charge storage layer, such as an SRAM. FIG. 12 shows an arrangement in which cylindrical island-shaped semiconductor portions forming a memory cell are arranged, for example, at intersections where two kinds of parallel lines are orthogonal to each other, and impurity diffusion for selecting and controlling each memory cell A first wiring layer formed of a layer 3721, a third wiring layer formed of a control gate 3514, and a fourth wiring layer serving as a bit line indicate a memory cell array arranged in parallel to the substrate surface. The second wiring layer 3840 including the second conductive film 3512 and the third conductive film 3513 is wired in two directions, the vertical direction and the horizontal direction, with respect to the substrate surface. The shapes of the second, third and fourth wiring layers are not limited as long as they can be connected to each other. In FIG. 12, the cross section used in the manufacturing process example, that is, the J1-J1 ′ cross section, the J2-J2 ′ cross section, the K1-K1 ′ cross section, and the K2-K2 ′ cross section are shown together. The wiring layer 3710, the first wiring layer 3850, the terminals for electrical connection with these wiring layers, and the fifth wiring layer 3850 are omitted. Further, in order to distinguish the island-shaped semiconductor layer 3110 from each wiring layer, the shape of the island-shaped semiconductor layer is circular, but the opposite may be possible.
[0048]
Embodiment in sectional view of memory cell array
Cross-sectional views of a semiconductor memory device having a floating gate as a charge storage layer are shown in FIGS. Of these, the odd-numbered drawing shows the A-A 'sectional view of FIG. 1, and the even-numbered drawing shows the B-B' sectional view.
In the semiconductor memory device of the present invention, a plurality of columnar island-shaped semiconductor layers 1110 are arranged in a matrix on a p-type silicon substrate 1100, and a second selection gate is provided above and below each of the island-shaped semiconductor layers 1110. A transistor having an electrode or a fifth electrode is arranged, and a plurality of memory transistors, for example, two in FIG. 13 to FIG. 36 are arranged between selection gate transistors, and each transistor is arranged along an island-shaped semiconductor layer. Are connected in series. That is, a silicon oxide film 1460, which is a ninth insulating film having a predetermined thickness, is disposed at the bottom of the groove between the island-shaped semiconductor layers, and the gate insulating film thickness is set on the island-shaped semiconductor layer side wall so as to surround the island-shaped semiconductor layer 1110. A selection gate 1500 is arranged as a selection gate transistor, and a silicon oxide film as a third insulating film is formed on the side wall of the island-shaped semiconductor layer so as to surround the island-shaped semiconductor layer 1110 above the selection gate transistor. A floating gate 1510 is disposed through 420, and a control gate 1520 is disposed outside the floating gate 1510 via an interlayer insulating film 1610 formed of a multilayer film, thereby forming a memory transistor.
Further, a transistor having the selection gate 1500 is disposed above the plurality of the memory transistors in the same manner as described above.
[0049]
As shown in FIGS. 1 and 14, the selection gate 1500 and the control gate 1520 are continuously arranged for a plurality of transistors in one direction, and the selection gate line that is the second wiring or the fifth wiring and the first gate This is the control gate line which is the third wiring. A source diffusion layer 1710 of the memory cell is arranged on the semiconductor substrate surface so that the active region of the memory cell is in a floating state with respect to the semiconductor substrate, and the active region of each memory cell is in a floating state. A diffusion layer 1720 is arranged in this manner, and a drain diffusion layer 1725 for each memory cell is arranged on the upper surface of each island-like semiconductor layer 1110. Between the memory cells thus arranged, an oxide film 1460 as a ninth insulating film is arranged so that the upper portion of the drain diffusion layer 1725 is exposed, and the drain diffusion of the memory cell in the direction intersecting the control gate line is arranged. Al wiring 1840 serving as a bit line for commonly connecting the layer 1725 is provided.
[0050]
13 and 14 show an example in which the gate insulating film thickness of the selection gate transistor is equal to the gate insulating film thickness of the memory transistor.
15 and 16 show an example in which the interlayer insulating film 1610 is formed as a single layer film with respect to FIGS. 13 and 14.
17 and 18 are different from FIGS. 13 and 14 in that the horizontal film thickness of the control gate 1520 in the memory cell is larger than the horizontal film thickness of the floating gate 1510 in the memory cell, and the third wiring layer has a lower thickness. An example in which resistance can be easily achieved is shown.
19 and 20 show an example of the case where the surface of the silicon oxide film 1420 as a third insulating film is positioned outside the periphery of the island-shaped semiconductor layer 1110 as a tunnel oxide film, as compared with FIGS. Show.
FIG. 21 and FIG. 22 show a case where the gate of the selection gate transistor is not formed by one deposition of the conductive film but formed by depositing the conductive film a plurality of times, for example, twice, as compared with FIGS. An example is shown.
FIG. 23 and FIG. 24 show an example in which materials of the control gate 1520 and the floating gate 1510 of the memory cell are different from those in FIG. 13 and FIG.
FIGS. 25 and 26 show an example in which the size of the outer periphery of the control gate 1520 of the memory cell and the size of the outer periphery of the gate 1500 of the select gate transistor are different from those of FIGS. 13 and 14.
27 and 28 show an example in which the gate insulating film thickness of the select gate transistor is larger than the gate insulating film thickness of the memory transistor.
29 and 30 are different from FIGS. 27 and 28 in that the surfaces of the silicon oxide film 1420 as the third insulating film and the silicon oxide film 1451 as the thirteenth insulating film are from the periphery of the island-shaped semiconductor layer 1110. Shows an example of the case of being positioned outward.
[0051]
FIG. 31 and FIG. 32 show an example in which the diffusion layer 1720 is not disposed between the transistors.
In FIGS. 33 and 34, the diffusion layer 1720 is not disposed, and the polycrystalline silicon film 1530 which is the third electrode disposed between the gate electrodes 1500, 1510 and 1520 of the memory transistor and the select gate transistor. An example in the case of forming is shown.
FIG. 35 and FIG. 36 show an example in which the positions of the bottom and top of the polycrystalline silicon film 1530 as the third electrode are different from the positions of the top of the gate 1500 of the selection gate transistor, respectively. Indicates.
[0052]
37 to 48 are cross-sectional views of a semiconductor memory device having a stacked insulating film as a charge storage layer. Among these, the odd-numbered drawings show the A-A ′ sectional view of the memory cell array having the MONOS structure, and the even-numbered drawings show the B-B ′ sectional view.
[0053]
The semiconductor memory device of the present invention is the same as FIGS. 13 to 36 except that the charge storage layer is changed from a floating gate to a laminated insulating film.
39 and 40 show the case where the thickness of the stacked insulating film is larger than the gate thickness of the selection gate transistor, as compared with FIGS.
41 and 42 show an example in which the thickness of the stacked insulating film is thinner than the gate thickness of the selection gate transistor, as compared with FIGS.
[0054]
49 to 54 are cross-sectional views of a semiconductor memory device having a MIS capacitor as a charge storage layer. Among these, the odd-numbered drawing shows the A-A 'sectional view of FIG. 11 showing the DRAM memory cell array, and the even-numbered drawing shows the B-B' sectional view.
In the semiconductor memory device of the present invention, the charge storage layer is changed from the floating gate to the MIS capacitor, the diffusion layer is located on the side of the memory capacitor, and the bit as the fourth wiring is different from FIGS. This is the same except that the line and the first wiring source line are arranged in parallel.
[0055]
Cross-sectional views of a semiconductor memory device having a MIS transistor as a charge storage layer are shown in FIGS. Hereinafter, embodiments of the present invention will be described with reference to the drawings. 55 to 58 are J1-J1 ', J2-J2', K1-K1 ', and K2-K2' cross-sectional views of FIG. 12, respectively, showing an SRAM memory cell array.
In the semiconductor memory device of the present invention, a plurality of columnar island-shaped semiconductor layers 3110 are arranged in a matrix on a p-type silicon substrate 3100. As shown in FIGS. Two MIS transistors are arranged in the lower part, and each transistor is connected in series along the island-like semiconductor layer. That is, the memory gate 3511 is arranged on the side wall of the island-shaped semiconductor layer via the gate insulating film thickness 3431 so as to surround the island-shaped semiconductor layer 3110, and surrounds the periphery of the island-shaped semiconductor layer 3110 above the memory gate transistor. As described above, the third electrode 3514 serving as a control gate is arranged on the side wall of the island-shaped semiconductor layer with the gate insulating film thickness 3434 interposed therebetween. As shown in FIG. 57, the control gate 3514 is continuously arranged for a plurality of transistors in one direction and serves as a control gate line which is a third wiring.
[0056]
In addition, as shown in FIGS. 55 and 57, the first common transistor electrically disposed on the lower surface of the semiconductor substrate surface so that the active region of the transistor is in a floating state with respect to the semiconductor substrate. The impurity diffusion layer 3710 is disposed, and the impurity diffusion layer 3721 is disposed in the island-shaped semiconductor layer 3110 so that the active region of each transistor is in a floating state.
Further, an impurity diffusion layer 3724 for each memory cell is disposed on the upper surface of each island-like semiconductor layer 3110. Thus, each transistor is connected in series along the island-shaped semiconductor layer 3110.
As shown in FIGS. 55 and 57, a fourth wiring layer 3840 serving as a bit line connecting the second impurity diffusion layer 3724 of the memory cell in the direction intersecting with the control gate line is provided.
In this embodiment, a memory cell is constituted by four transistors and two high resistance elements each constituted by a pair of island-like semiconductor layers, and as shown in FIG. 55 and FIG. The second impurity diffusion layer 3721 arranged in the island-shaped semiconductor layer opposite to the conductive film 3511 is connected to each other through the second conductive film 3512 and the third conductive film 3513.
Further, as shown in FIGS. 56 and 58, the third conductive film 3513 connected to the second impurity diffusion layer 3721 arranged in each island-like semiconductor layer 3110 is an impurity that becomes a high resistance element. Each of the second wiring layers 3120 is connected to a fifth wiring which is an electrically common electrode. The second wiring layer 3120 is a diffusion layer. As shown in FIGS. 56 and 58, the first impurity diffusion layer 3710 that is electrically common to the memory cells adjacent in the direction of the fourth wiring layer 3840 is an isolation insulating film, for example, eleventh. It is electrically divided by a silicon oxide film 3471 which is an insulating film.
Between the memory cells and the wirings arranged in this way, for example, an oxide film 3420 as a third insulating film is arranged and insulated from each other. In this embodiment, the memory cell is composed of four transistors and two high resistance elements formed on the side wall of the p-type island-like semiconductor layer. However, a transistor formed on an n-type semiconductor may be used instead of the high resistance element. The structure is not limited to this as long as it can have a desired function.
[0057]
Embodiments of memory cell array operating principle
The semiconductor memory device of the present invention has a memory function depending on the state of charges stored in the charge storage layer.
The operation principle of reading, writing, and erasing will be described by taking a memory cell having a floating gate as a charge storage layer as an example.
First, the read operation principle of the semiconductor memory device is shown below.
As an example of the array structure of the semiconductor memory device of the present invention, a transistor having a second electrode as a gate electrode and a transistor having a fifth electrode as a gate electrode are included as a selection gate transistor, and between the selection gate transistors A plurality of memory cells having a charge storage layer and having a third electrode as a control gate electrode, for example, L (L is a positive integer), and an island semiconductor layer connected in series. In a memory cell array having a plurality of layers, for example, M × N (M and N are positive integers), a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are formed as island-like semiconductor layers. Are connected to one end of each, a first wiring is connected to the other end, and a plurality of, for example, N, arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring × L pieces In the case where the third wiring is connected to the third electrode of the memory cell will be described an example of a reading method when the first wiring is arranged in parallel to the third wires.
[0058]
FIG. 59 shows an equivalent circuit of this memory cell array structure.
For example, in a read operation of a memory cell in which an island-shaped semiconductor layer is formed of a p-type semiconductor, 0 V is applied to all the first wirings (1-1 to 1-N), and the island-shaped semiconductor layer including the selected cell is applied. 3V is applied to the fourth wiring (4-i) connected to the fourth electrode to be connected (i is a positive integer of 1 ≦ i ≦ M), and the fourth wiring (≠ 4-i) other than this is applied. Third wiring (3-jh) connected to the third electrode connected to the selected cell by applying 0V (j is a positive integer of 1 ≦ j ≦ N, h is a positive integer of 1 ≦ h ≦ L) 0V is applied to the third wiring (3-jh) excluding the third wiring (3-jh), 3V is applied to the second wiring (2-j) connected to the second electrode. And 3 V is applied to the fifth wiring (5-j) connected to the fifth electrode, and the second wiring (≠ 2-j) or the fifth wiring excluding the second wiring (2-j) By applying 0 V to at least one of the fifth wirings (≠ 5-j) excluding (5-j), the fourth wiring Wiring by a current flowing in (4-i) current or first wiring through the (1-j) "0", determines "1".
By arranging the selection gates above and below the plurality of memory cell parts in this way, when the memory cell transistor is in an over-erased state, that is, when the threshold value is negative, the non-selected cell has a read gate voltage. The phenomenon of cell current flowing at 0 V can be prevented.
It has an island-like semiconductor layer having a charge storage layer and two memory cells each having a third electrode as a control gate electrode connected in series. A plurality of island-like semiconductor layers, for example, M × N (M , N is a positive integer), a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are connected to one end of each of the island-like semiconductor layers, and the other The first wiring is connected to the end, and a plurality of, for example, N × 2 third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring are memory cell cells. An example of a reading method when the first wiring is arranged in parallel with the third wiring in the case of being connected to the third electrode will be described.
[0059]
FIG. 60 shows an equivalent circuit of this memory cell array structure.
For example, in the read operation in which the island-shaped semiconductor layer is formed of a p-type semiconductor, 0 V is applied to all the first wirings (1-1 to 1-N), and the first connection to the island-shaped semiconductor layer including the selected cell is performed. 3V is applied to the fourth wiring (4-i) connected to the electrode 4 (i is a positive integer of 1 ≦ i ≦ M), and 0V is applied to the other fourth wiring (≠ 4-i). 5V is applied to the third wiring (3-j-1) connected to the third electrode connected to the selected cell, and 0V is applied to the third wiring (3-j-2). By applying 0 V to the third wiring (≠ 3-j-1, ≠ 3-j-2) excluding (3-j-1) and the third wiring (3-j-1), the fourth wiring “0” and “1” are determined based on the current flowing through the wiring (4-i) or the current flowing through the first wiring (1-j) (j is a positive integer of 1 ≦ j ≦ N).
[0060]
Next, the principle of writing operation of the semiconductor memory device is shown below.
As an example of the array structure of the semiconductor memory device of the present invention, a transistor having a second electrode as a gate electrode and a transistor having a fifth electrode as a gate electrode are included as a selection gate transistor, and between the selection gate transistors A plurality of memory cells each having a charge storage layer and having a third electrode as a control gate electrode, for example, L (L is a positive integer) connected in series; In a memory cell array having a plurality of, for example, M × N (M and N are positive integers), a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are provided on one of the island-shaped semiconductor layers. A plurality of (for example, N × L) first wirings connected to one end and connected to the other end in a direction parallel to the semiconductor substrate and intersecting the fourth wiring. 3 wiring is memory An example of a writing method using a FN tunneling current (hereinafter referred to as FN current) in which the first wiring is arranged in parallel with the third wiring in the case where the third wiring is connected to the third electrode. Is described.
[0061]
FIG. 59 shows an equivalent circuit of this memory cell array structure.
When writing to store a certain amount or more of negative charges in the charge storage layer of the selected cell, for example, a write operation in which the island-shaped semiconductor layer is formed of a p-type semiconductor is connected to the island-shaped semiconductor layer including the selected cell. 0V is applied to the first wiring (1-j) connected to the first electrode (j is a positive integer 1 ≦ j ≦ N), and 0V is applied to the other first wiring (≠ 1-j). 0V is applied to the fourth wiring (4-i) (i is a positive integer of 1 ≦ i ≦ M) connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell. 3V is applied to the fourth wiring (≠ 4-i) of the third wiring (3-jh) connected to the third electrode connected to the selected cell (h is a positive integer of 1 ≦ h ≦ L) 20V is applied to the third wiring (≠ 3-jh) except for the third wiring (3-jh), and 3V is applied to the second electrode connected to the island-like semiconductor layer including the selected cell. 0V is applied to the second wiring (2-j) to perform island-shaped semiconductor including the selected cell 1V is applied to the fifth wiring (5-j) connected to the fifth electrode connected to the layer, and the second wiring (≠ 2-j) except the second wiring (2-j) and the fifth wiring By applying 0V to the fifth wiring (≠ 5-j) excluding the wiring (5-j), a state in which a high potential is applied only between the channel portion of the selected cell and the control gate is created, and FN tunneling Due to the phenomenon, electrons are injected from the channel portion into the charge storage layer. A selection gate transistor having a fifth electrode in an island-like semiconductor layer that does not include a selection cell by applying 3 V to the fourth wiring (≠ 4-i) excluding the fourth wiring (4-i) Is cut off, and the electrical path between the diffusion layer of the non-selected cell connected to the third wiring (3-jh) and the fourth wiring (≠ 4-i) is cut off so that no channel is formed and writing is performed. I will not.
In addition, as an example of performing writing without cutting off the selection gate transistor including the fifth electrode in the island-shaped semiconductor layer not including the selection cell, the first electrode connected to the island-shaped semiconductor layer including the selection cell Apply 0V to the first wiring (1-j) connected to (j is a positive integer 1 ≦ j ≦ N), and apply 0V to the first wiring other than this (≠ 1-j) 0V is applied to the fourth wiring (4-i) (i is a positive integer of 1 ≦ i ≦ M) connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell. 7V is applied to the fourth wiring (≠ 4-i), and the third wiring (3-jh) (h is a positive integer of 1 ≦ h ≦ L) connected to the third electrode connected to the selected cell 20V is applied, 7V is applied to the third wiring (≠ 3-jh) excluding (3-jh) of the third wiring, and it is connected to the second electrode connected to the island-like semiconductor layer including the selected cell. Applying 0V to the second wiring (2-j), the island-shaped semiconductor including the selected cell 20V is applied to the fifth wiring (5-j) connected to the fifth electrode connected to the layer, and the second wiring (≠ 2-j) except the second wiring (2-j) and the fifth wiring By applying 0 V to the fifth wiring (≠ 5-j) excluding the wiring (5-j), a potential difference of about 20 V is generated between the channel portion of the selected cell and the control gate, and due to the FN tunneling phenomenon. Tunnel electrons are injected from the channel portion into the charge storage layer.
Note that a potential difference of about 13 V occurs between the channel portion of the non-selected cell connected to the third wiring (3-jh) and the control gate, but the threshold value of this cell is changed within the write time of the selected cell. Insufficient electron injection cannot be performed, and thus writing of this cell is not realized.
[0062]
Further, as an example of the array structure of the semiconductor memory device of the present invention, the semiconductor memory device includes an island-like semiconductor layer in which two memory cells each having a charge storage layer and a third electrode as a control gate electrode are connected in series. In a memory cell array provided with a plurality of semiconductor layers, for example, M × N (M and N are positive integers), a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are arranged in each of the island-shaped semiconductor layers. The first wiring is connected to the other end, and a plurality of, for example, N, arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring. When the two third wirings are connected to the third electrode of the memory cell, the first wiring is arranged in parallel with the third wiring, and channel hot electrons (hereinafter referred to as CHE) are used. An example of the written method will be described.
[0063]
FIG. 60 shows an equivalent circuit of the memory cell array structure.
When writing to store a certain amount or more of negative charges in the charge storage layer of the selected cell, for example, a write operation in which the island-shaped semiconductor layer is formed of a p-type semiconductor is performed on the island-shaped semiconductor layer including the selected cell. 0V is applied to the first wiring (1-j) connected to the first electrode to be connected (j is a positive integer of 1 ≦ j ≦ N), and the other first wiring (≠ 1-j) is applied 0V is applied, and 12V is applied to the fourth wiring (4-i) (i is a positive integer of 1 ≦ i ≦ M) connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell. 0 V is applied to the fourth wiring (≠ 4-i) except for 12 V, 12 V is applied to the third wiring (3-j-1) connected to the third electrode connected to the selected cell, and the third wiring By applying 5 V to the third wiring (≠ 3-j-1) excluding (3-j-1), CHE is generated near the high potential side diffusion layer of the selected cell, and the third wiring The charge storage layer of the selected cell by the high potential applied to (3-j-1) The generated electrons are injected.
[0064]
Further, the principle of erase operation of the semiconductor memory device is shown below.
As an example of the array structure of the semiconductor memory device of the present invention, a transistor having a second electrode as a gate electrode and a transistor having a fifth electrode as a gate electrode are included as a selection gate transistor, and between the selection gate transistors A plurality of memory cells having a charge storage layer and having a third electrode as a control gate electrode, for example, L (L is a positive integer), an island-shaped semiconductor layer connected in series, and an island-shaped semiconductor layer In a memory cell array having a plurality of, for example, M × N (M and N are positive integers), a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate are provided on one of the island-shaped semiconductor layers. A plurality of, for example, N × L first wirings connected to one end and connected to the other end in a direction parallel to the semiconductor substrate and intersecting the fourth wiring. 3 wiring is the memory cell In the case where the third electrode to be connected, the first wire parallel arranged to the third wiring is described an example of the erasing method using F-N current.
[0065]
FIG. 61 shows an equivalent circuit of this memory cell array structure.
The erase unit is one block or a batch of chips. When erasing is performed by changing the charge state of the charge storage layer of the selected cell and lowering the threshold value of the selected cell, for example, an erasing operation in which the island-shaped semiconductor layer is formed of a p-type semiconductor is an island-shaped structure including the selected cell. 20 V is applied to the first wiring (1-j) connected to the first electrode connected to the semiconductor layer (j is a positive integer of 1 ≦ j ≦ N), and other first wirings are connected to the first wiring (1-j). 4V connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell by applying 0V to (≠ 1-j) (i is a positive integer of 1 ≦ i ≦ M) ) Is applied with 20V, and 0V is applied to the third wiring (3-jh) (h is a positive integer of 1 ≦ h ≦ L) connected to the third electrode connected to the selected cell. The third wiring except 3-jh) is given 0 V, and the second wiring (2-j) connected to the second electrode connected to the island-like semiconductor layer including the selected cell is given 20 V, and the selected cell A fifth power connected to the island-shaped semiconductor layer containing 20V is applied to the fifth wiring (5-j) connected to the terminal, and the second wiring (≠ 2-j) excluding the second wiring (2-j) and the fifth wiring (5-j) are excluded. By applying 0 V to both of the fifth wirings (≠ 5-j), electrons in the charge storage layer of the selected cell are extracted by the FN tunneling phenomenon.
[0066]
As an example of the array structure of the semiconductor memory device of the present invention, an island-shaped semiconductor layer having two memory cells each having a charge storage layer and a third electrode as a control gate electrode connected in series is provided. A plurality of layers, for example, MN (M and N are positive integers) are provided, and in this memory cell array, a plurality of, for example, M fourth wirings arranged in parallel to the semiconductor substrate The first wiring is connected to one end of each of the semiconductor layers, and the first wiring is connected to the other end, and is arranged in a direction parallel to the semiconductor substrate and intersecting the fourth wiring. When a plurality of, for example, N × 2 third wirings are connected to the third electrode of the memory cell, the first wiring is arranged in parallel with the third wiring, and the FN current is used. An example of the erase method will be described.
FIG. 60 shows an equivalent circuit of this memory cell array structure.
When erasing is performed by changing the charge state of the charge storage layer of the selected cell and lowering the threshold value of the selected cell, for example, an erasing operation in which the island-shaped semiconductor layer is formed of a p-type semiconductor is an island-shaped structure including the selected cell. 3 V is applied to the first wiring (1-j) connected to the first electrode connected to the semiconductor layer (j is a positive integer of 1 ≦ j ≦ N), and other first wirings (≠ 1- j) 0V is applied, and the fourth wiring (4-i) (i is a positive integer of 1 ≦ i ≦ M) connected to the fourth electrode connected to the island-shaped semiconductor layer including the selected cell is open The fourth wiring (≠ 4-i) other than this is in an open state or 0 V is applied, and −12 V is applied to the third wiring (3-j-1) connected to the third electrode connected to the selected cell. Then, 5V is applied to the third wiring (3-j-2), and 0V is applied to the other third wiring, whereby the electrons in the charge storage layer of the selected cell are extracted by the FN tunneling phenomenon.
In the above read, write, and erase operations, the conductivity types of all electrodes may be switched as in the case of an island-shaped semiconductor layer formed of an N-type semiconductor. The magnitude relation of the potential at this time is opposite to that described above. Further, in each of the above read, write, and erase operation examples, the case where the first wiring is arranged in parallel with the third wiring has been described. However, the case where the first wiring is arranged in parallel with the fourth wiring. Even when the first wiring is shared by the entire array, it can be operated by applying a potential corresponding to each of the first wirings.
[0067]
A memory cell other than a memory cell having a floating gate as a charge storage layer will be described below.
62 and 63 are equivalent circuit diagrams showing a part of the memory cell array having the MONOS structure shown in FIGS. 10 and 37 to 46. 62 shows an equivalent circuit diagram of a memory cell array having a MONOS structure arranged in one island-like semiconductor layer 1110, and FIG. 63 shows an equivalent circuit when a plurality of island-like semiconductor layers 1110 are arranged.
[0068]
The equivalent circuit shown in FIG. 62 will be described below.
A transistor having a twelfth electrode 12 as a gate electrode and a transistor having a fifteenth electrode 15 as a gate electrode are selected gate transistors, and a stacked insulating film is provided as a charge storage layer between the select gate transistors. , A plurality of memory cells, for example, L, connected in series with a thirteenth electrode (13-h) (h is a positive integer of 1 ≦ h ≦ L, L is a positive integer) as a control gate electrode In the planar semiconductor layer 110, the fourteenth electrode 14 is connected to one end of each of the island-shaped semiconductor layers 1110, and the eleventh electrode 11 is connected to the other end.
[0069]
The equivalent circuit shown in FIG. 63 will be described.
In the memory cell array in which a plurality of island-like semiconductor layers 1110 are arranged, the connection relationship between the electrodes of the circuit elements arranged in the island-like semiconductor layers 1110 shown in FIG.
A plurality of, for example, M × N island-like semiconductor layers 1110 (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N). In the memory cell array, a plurality of, for example, M, 14th wirings arranged in parallel to the semiconductor substrate are connected to the 14th electrode 14 provided in each island-like semiconductor layer 1110, respectively. Further, a plurality of, for example, N × L thirteenth wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourteenth wirings 14 are the above-described thirteenth electrodes (13− h) (h is a positive integer 1 ≦ h ≦ L). A plurality of, for example, N eleventh wirings arranged in a direction intersecting with the fourteenth wiring are connected to the eleventh electrode 11 provided in each island-like semiconductor layer 1110, and the eleventh wiring Are arranged in parallel with the thirteenth wiring. A plurality of, for example, N twelfth wirings arranged in a direction parallel to the semiconductor substrate and intersecting the fourteenth wiring 14 are connected to the above-described twelfth electrode 12 of each memory cell, Similarly, a plurality of, for example, N fifteenth wirings arranged in parallel to the semiconductor substrate and intersecting the fourteenth wirings 14 are connected to the fifteenth electrode 15 of each memory cell. To do.
[0070]
64 and 65 are equivalent circuit diagrams showing a part of the memory cell array having the DRAM structure shown in FIGS. 11, 53 and 54.
FIG. 64 shows an equivalent circuit diagram of a memory cell array having a DRAM structure arranged in one island-like semiconductor layer 1110. FIG. 65 shows an equivalent circuit when a plurality of island-shaped semiconductor layers 1110 are arranged.
[0071]
Hereinafter, the equivalent circuit shown in FIG. 64 will be described.
One memory cell is formed by connecting one transistor and one MIS capacitor in series. A 23rd electrode 23 is connected to one end of the memory cell, a 21st electrode 21 is connected to the other end, and a memory cell having a 22nd electrode 22 as a gate electrode is provided. For example, two sets are connected as shown in FIG. 64, and two 21st electrodes (21-1), (21-2) and two 22nd electrodes (22-1) are connected from one island-like semiconductor layer 1110. ) And (22-2), and the 23rd electrode 23 is provided at one end of the island-like semiconductor layer 1110.
[0072]
The equivalent circuit shown in FIG. 65 will be described.
In the memory cell array in which a plurality of island-like semiconductor layers 1110 are arranged, the connection relationship between the electrodes of the circuit elements arranged in the island-like semiconductor layers 1110 shown in FIG.
A plurality of, for example, M × N island-like semiconductor layers 1110 (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N). In the memory cell array, a plurality of, for example, M, twenty-third wirings arranged in parallel to the semiconductor substrate are connected to the above-described twenty-third electrode 23 provided in each island-like semiconductor layer 1110. Further, a plurality of, for example, 2 × N, twenty-second wirings arranged in a direction parallel to the semiconductor substrate and intersecting the twenty-third wiring 23 are the above-described twenty-second electrodes (22−) of each memory cell. Connect to 1) and (22-2). In addition, a plurality of, for example, 2 × N, twenty-first wirings arranged in a direction intersecting with the twenty-third wiring are the above-mentioned twenty-first electrodes (21-1), (21-2) of each memory cell. Connect with.
64 and 65 show an example in which two memory cells are arranged in one island-shaped semiconductor layer 1110, but the number of memory cells arranged in one island-shaped semiconductor layer 1110 is three sets. The above or only one set may be used.
The equivalent circuit shown in FIGS. 64 and 65 is an example in which a MIS capacitor, a transistor, a MIS capacitor, and a transistor are arranged in order from the bottom of the island-shaped semiconductor layer 1110, but an island-shaped semiconductor is an example of another arrangement. A case where a transistor, a MIS capacitor, a MIS capacitor, and a transistor are arranged in this order from the bottom of the layer 1110 will be described below.
[0073]
66 and 67 are equivalent circuit diagrams showing a part of the memory cell array having the DRAM structure shown in FIGS. 11 and 49 to 52.
66 shows an equivalent circuit diagram of a memory cell array having a DRAM structure arranged on one island-like semiconductor layer 1110. FIG. 67 shows an equivalent circuit when a plurality of island-like semiconductor layers 1110 are arranged. .
[0074]
The equivalent circuit shown in FIG. 66 will be described.
As in the previous example, the memory cell is configured by connecting one transistor and one MIS capacitor in series to form one memory cell, and a 23rd electrode 23 is formed at one end of the memory cell. The 21st electrode 21 is connected to the other end, and the 22nd electrode 22 is connected as a gate electrode. For example, two sets of this memory cell are connected as shown in FIG. 66, and two 21st electrodes (21-1), (21-2) and two 22nd electrodes are connected from one island-like semiconductor layer 1110. (22-1) and (22-2) are provided, respectively, the 23rd electrode 23 is provided at one end of the island-shaped semiconductor layer 1110, and the 24th electrode 24 is provided at the other end. .
[0075]
The equivalent circuit shown in FIG. 67 will be described.
In the memory cell array in which the plurality of island-shaped semiconductor layers 1110 are arranged, the connection relationship between the electrodes of the circuit elements arranged in the island-shaped semiconductor layers 1110 shown in FIG. 66 and the wirings is shown.
A plurality of, for example, M × N island-like semiconductor layers 1110 (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N). In the memory cell array, a plurality of, for example, M, twenty-third wirings arranged in parallel to the semiconductor substrate are connected to the above-described twenty-third electrode 23 provided in each island-like semiconductor layer 1110. Similarly, a plurality of, for example, M, twenty-fourth wirings arranged in parallel to the semiconductor substrate are connected to the above-described twenty-fourth electrode 24 provided in each island-like semiconductor layer 1110. Further, a plurality of, for example, 2 × N twenty-second wirings arranged in a direction parallel to the semiconductor substrate and intersecting the twenty-third wiring 23 and the twenty-fourth wiring 24 are the above-mentioned second wirings of each memory cell. 22 electrodes (22-1) and (22-2) are connected. Similarly, a plurality of, for example, 2 × N twenty-first wirings arranged in a direction crossing the twenty-third wiring 23 and the twenty-fourth wiring 24 are the above-mentioned twenty-first electrodes (21 -1) Connect to (21-2).
[0076]
68 and 69 are equivalent circuit diagrams showing a part of the memory cell array shown in FIGS. 33 to 36, 47 and 48. In this memory cell array, the diffusion layer 1720 is not disposed between the transistors, and further, a polycrystal which is a third conductive film disposed between 1500, 1510 and 1520 which are the gate electrodes of the memory transistor and the selection gate transistor. A silicon film 1530 is formed. In FIG. 68, a polycrystalline silicon film 1530, which is a third conductive film disposed between the gate electrodes of each memory transistor and select gate transistor, is formed as a structure disposed in one island-like semiconductor layer 1110. FIG. 69 shows an equivalent circuit when a plurality of island-shaped semiconductor layers 1110 are arranged.
[0077]
The equivalent circuit shown in FIG. 68 will be described.
A transistor having a thirty-second electrode 32 as a gate electrode and a transistor having a thirty-fifth electrode 35 as a gate electrode are used as selection gate transistors, and a charge storage layer is provided between the selection gate transistors, and a control gate electrode A plurality of memory cells, for example, L, in series, each having a thirty-third electrode (33-h) (h is a positive integer of 1 ≦ h ≦ L), and each transistor In the island-shaped semiconductor layer 1110 in which the transistor including the 36th electrode is arranged as the gate electrode, the 34th electrode 34 is connected to one end of each of the island-shaped semiconductor layers 1110 and the other end The thirty-first electrode 31 is connected, and a plurality of 36 electrodes are all connected to one, and the thirty-sixth electrode 36 is provided in the island-shaped semiconductor layer 1110.
[0078]
The equivalent circuit shown in FIG. 69 will be described.
In the memory cell array in which a plurality of island-like semiconductor layers 1110 are arranged, the connection relationship between the electrodes of the circuit elements arranged in the island-like semiconductor layers 1110 shown in FIG.
A plurality of, for example, M × N island-like semiconductor layers 1110 (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N). In the memory cell array, a plurality of, for example, M thirty-fourth wirings arranged in parallel to the semiconductor substrate are connected to the thirty-fourth electrode 34 provided in each island-shaped semiconductor layer 1110. Further, a plurality of, for example, N × L thirty-third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the thirty-fourth wiring 34 are the above-described thirty-third electrodes (33−) of each memory cell. Connect to h). Further, a plurality of, for example, N thirty-first wirings arranged in a direction intersecting with the thirty-fourth wiring are connected to the above-described thirty-first electrode 31 provided in each island-like semiconductor layer 1110 and Are arranged in parallel with the 33rd wiring. A plurality of, for example, N thirty-second wirings arranged in a direction parallel to the semiconductor substrate and intersecting the thirty-fourth wiring 34 are connected to the above-described thirty-second electrode 32 of each memory cell, Similarly, a plurality of, for example, N thirty-fifth wirings arranged in a direction parallel to the semiconductor substrate and intersecting the thirty-fourth wiring 34 are connected to the above-described thirty-fifth electrode 35 of each memory cell. Connecting. The thirty-sixth electrodes 36 included in each island-shaped semiconductor layer 1110 are all connected to one another by the thirty-sixth wiring.
Note that the thirty-sixth electrodes 36 included in each island-shaped semiconductor layer 1110 do not have to be connected to one by the thirty-sixth wiring, and the memory cell array is divided into two or more by the thirty-sixth wiring. You may connect. That is, the 36th electrode may be connected to each block, for example.
[0079]
70 and 71 are equivalent circuit diagrams showing a part of the SRAM-structured memory cell array shown in FIGS. 12 and 55 to 58, and show an example in which the transistors constituting the memory cells are composed only of NMOS. Yes.
70 shows an equivalent circuit diagram of one SRAM structure memory cell arranged in two adjacent island-like semiconductor layers 1110, and FIG. 71 shows an equivalent circuit when a plurality of memory cells are arranged. ing.
[0080]
The equivalent circuit shown in FIG. 70 will be described.
As shown in FIG. 70, two island-shaped semiconductor layers 110 in which transistors having a 43rd electrode and a 45th electrode are arranged in series as gate electrodes are arranged adjacent to each other. Connect to each other. Specifically, the 46th electrode (46-2) and the 45th electrode (45-1) of the transistor having the 43rd electrode (43-2) as the gate electrode are connected to each other, and the 43rd electrode (43-1 ) Is connected to the 46th electrode (46-1) and 45th electrode (45-2) of the transistor. In addition, in the two adjacent island-like semiconductor layers 1110, the 44th electrode (44-1) is connected to one end of one island-like semiconductor layer 1110, and one of the other island-like semiconductor layers 1110 is connected. The 44th electrode (44-2) is connected to the end of the. In the two island-like semiconductor layers 1110, the forty-first electrode 41 is connected as a common electrode to the other end where the forty-fourth electrodes (44-1) and (44-2) are not connected. Two high-resistance elements are connected to these four transistors as shown in FIG. 70, and a forty-second electrode 42 is connected as a common electrode to the end on the side not connected to the transistor.
[0081]
The equivalent circuit shown in FIG. 71 will be described.
In the memory cell array in which the plurality of island-shaped semiconductor layers 1110 are arranged, the connection relationship between the electrodes of the circuit elements arranged in units of two adjacent island-shaped semiconductor layers 1110 shown in FIG.
A plurality of, for example, 2 × M × N island-like semiconductor layers 1110 (M and N are positive integers, i is a positive integer of 1 ≦ i ≦ M, and j is a positive integer of 1 ≦ j ≦ N. In the memory cell array, a plurality of, for example, 2 × M forty-fourth wirings arranged in parallel to the semiconductor substrate are provided in each island-shaped semiconductor layer 1110. Connect to 44-2) respectively. A plurality of, for example, N forty-third wirings arranged in a direction parallel to the semiconductor substrate and intersecting the forty-fourth wiring 44 are the 43rd electrodes (43-1) of each memory cell. ), (43-2). A plurality of, for example, N forty-first wirings arranged in a direction crossing the forty-fourth wiring are connected to the forty-first electrode 41 provided in each island-like semiconductor layer 1110. Note that the forty-first wiring may be commonly connected to the forty-first electrode 41 provided in each island-shaped semiconductor layer 1110. The above-described forty-second electrodes 42 of each high-resistance element may be all connected together by a forty-second wiring.
The transistor constituting the memory cell may be composed only of PMOS, or may be a transistor having a conductivity type opposite to the transistor having the 43rd or 45th electrode as the gate electrode, instead of the above-described high resistance element. Good.
[0082]
Further, the selection gate transistor and the memory cell adjacent to the selection gate transistor and the adjacent memory cells are not connected via the impurity diffusion layer. Instead, the interval between the selection transistor, the memory cell, and the memory cell is about 30 nm or less. The operation principle of the memory cell having a structure that is very close compared to the case where the selection transistor, the memory cell, and the memory cells are connected via the impurity diffusion layer will be described below.
When adjacent elements are sufficiently close, the channel formed by the potential higher than the threshold applied to the gate of the select gate transistor and the control gate of the memory cell is connected to the channel of the adjacent element, and the gates of all elements are connected. When a potential higher than the threshold value is applied, the channel is connected to all the elements. Since this state is almost equivalent to the case where the selection transistor and the memory cell or memory cell are connected via the impurity diffusion layer, the operation principle is that the selection transistor and the memory cell or memory cell are connected via the impurity diffusion layer. It is the same as when
Further, the memory cell has a structure in which the selection gate transistor and the memory cell are not connected via the impurity diffusion layer, and a third conductive film is disposed between the selection transistor and the gate electrode of the memory cell or the memory cell instead. The operation principle of is described.
The third conductive film is located between the elements and is connected to the island-shaped semiconductor layer through an insulating film, for example, a silicon oxide film. That is, the third conductive film, the insulating film, and the island-shaped semiconductor layer form a MIS capacitor. When a potential is applied to the third conductive film so that an inversion layer is formed at the interface between the island-shaped semiconductor layer and the insulating film, a channel is formed. The formed channel functions in the same way as an impurity diffusion layer connecting each element for adjacent elements. Therefore, when a potential capable of forming a channel is applied to the third conductive film, the operation is similar to that in the case where the selection gate transistor and the memory cell are connected through the impurity diffusion layer. Further, even when a potential capable of forming a channel is not applied to the third conductive film, for example, when the island-shaped semiconductor layer is a p-type semiconductor, when the electrons are extracted from the charge storage layer, the selection gate transistor and the memory cell are The operation is similar to that in the case of connection through the impurity diffusion layer.
[0083]
Embodiment of Memory Cell Array Manufacturing Method
After forming the charge storage layer or control gate, an insulating film formed between the charge storage layer and the semiconductor substrate or semiconductor layer is formed at once, and a semiconductor layer serving as an active region is formed in a columnar shape on the side surface of the insulating film The method of doing will be described below. In addition, when a sidewall-shaped gate electrode is formed, an insulating film is embedded in an adjacent groove portion in advance, and etching of the lateral component is performed using this insulating film as a mask, so that the gate electrode material is deposited to a thickness of about the thickness. The gate electrode is formed with good control.
[0084]
Production Example 1
In the semiconductor memory device formed in this embodiment, a plurality of floating gates are formed as charge storage layers, a selection gate and a control gate are formed, a tunnel oxide film is formed, and islands are formed in a columnar shape by selective epitaxial silicon growth. In a semiconductor memory device in which an island-shaped semiconductor layer is formed, the island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically floated, the island-shaped semiconductor layer Select gate transistors are arranged at the upper and lower portions of the transistor, a plurality of, for example, two memory transistors are arranged between the select gate transistors, and a tunnel oxide film of each memory transistor is formed in a lump. Are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is the memory Of equal structure and the gate insulating film thickness of the transistor.
[0085]
Such a semiconductor memory device can be formed by the following manufacturing method.
72 to 96 and FIGS. 97 to 121 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1 showing the memory cell array of the EEPROM, respectively.
First, a silicon oxide film 1410 is deposited as a first insulating film on the surface of the p-type silicon substrate 1100, for example, 2 to 20 nm as a first insulating film, and a first impurity is deposited on the p-type silicon substrate 1100 using ion implantation. The layer 1710 is introduced (FIGS. 72 and 97). For example, implantation energy of 5 to 100 keV from a direction inclined about 0 to 7 °, arsenic 1 × 10¹⁴~ 1x10¹⁶/ Cm²About a dose. Further, instead of ion implantation, an oxide film containing arsenic may be deposited by CVD, and arsenic diffusion from the oxide film may be used. The first impurity layer 1710 may not be introduced into the outermost surface of the p-type silicon substrate 1100.
[0086]
Subsequently, using the resist R5 patterned by a known photolithography technique as a mask (FIGS. 73 and 98), for example, the first insulating film 1410 and the p-type silicon substrate 1100 are formed by the reactive ion etching. Etching is performed to 200 nm to 2000 nm so that the impurity layer 1710 is divided, so that a second groove portion 1220 is formed.
After removing the resist R5 (FIGS. 74 and 99), for example, a silicon oxide film 1420 is deposited as a fifth insulating film in the second trench 1220 to a thickness of 100 nm to 300 nm and buried by etch back. The method of embedding the silicon oxide film 1420 as the fifth insulating film may be an etch back using isotropic etching, an etch back using anisotropic etching, or a flattening embedding using CMP. However, various combinations may be used. At this time, the silicon oxide film 1420 as the fifth insulating film may be a silicon nitride film. Further, the silicon oxide film 1410 which is the first insulating film may be removed or may remain.
For example, when the silicon oxide film 1410 which is the first insulating film is removed, a silicon nitride film 1310, for example, 2000 to 20000 nm is formed as a second insulating film on the p-type silicon substrate 1100 or the first impurity layer 1710. It forms (FIGS. 75 and 100).
[0087]
Next, using the resist R6 patterned by a known photolithography technique as a mask (FIGS. 76 and 101), the silicon nitride film 1310 as the second insulating film is etched by, for example, reactive ion etching, A checkered fourth groove 1240 is formed. Thereafter, for example, a silicon oxide film 1421 is deposited to a thickness of 50 to 500 nm as a fifth insulating film in the lattice-patterned fourth groove 1240 by a CVD method.
Thereafter, the oxide film 1421 which is the fifth insulating film is buried by, for example, isotropic etching to the desired depth of the fourth groove portion 1240 (FIGS. 77 and 102), and the silicon nitride film 1310 which is the second insulating film. As a fourth insulating film, for example, a silicon oxide film 1431 is deposited to a thickness of 1 to 10 nm, and then a first conductive film, for example, a polycrystalline silicon film 1511 is deposited to a thickness of about 100 to 500 nm (see FIGS. 78 and 78). 103).
[0088]
Next, the polycrystalline silicon film 1511 which is the first conductive film is etched back to form a sidewall having a desired height (FIGS. 79 and 104). At this time, by setting the AA ′ direction in FIG. 1 below a predetermined value in advance, it is formed as a second wiring layer that becomes a selection gate line continuous in that direction without using a mask process. The
Thereafter, for example, a silicon oxide film 1422 is deposited in the fourth groove 1240 as a fifth insulating film by 50 to 500 nm. After that, the silicon oxide film 1422 as the fifth insulating film is buried to the desired depth of the fourth groove portion 1240 by, for example, isotropic etching, and then is formed on the surface of the silicon nitride film 1310 as the second insulating film. As the fourth insulating film, for example, a silicon oxide film 1432 is deposited by 1 to 10 nm (FIGS. 80 and 105), and then, for example, a polycrystalline silicon film 1512 to be a first conductive film is deposited by about 50 to 200 nm. (FIGS. 81 and 106).
[0089]
Similarly, the polysilicon film 1512 which is the first conductive film is etched back to form a sidewall having a desired height (FIGS. 82 and 107). At this time, the polycrystalline silicon film 1512 as the first conductive film is formed around the silicon nitride film 1310 as the second insulating film, and around each of the silicon nitride films 1310 as the second insulating film. The formed polycrystalline silicon film 1512 as the first conductive film is in a separated state.
Subsequently, an interlayer insulating film 1612 is formed on the surface of the polycrystalline silicon film 1512 which is the first conductive film (FIGS. 83 and 108). The interlayer insulating film 1612 is, for example, an ONO film. Specifically, a 5 to 10 nm silicon oxide film, a 5 to 10 nm silicon nitride film, and a 5 to 10 nm silicon oxide film are sequentially deposited on the surface of the polycrystalline silicon film by a thermal oxidation method.
[0090]
Next, for example, a polycrystalline silicon film 1522 to be a second conductive film is deposited in a thickness of 15 to 150 nm (FIGS. 84 and 109), and etched back corresponding to the deposited film thickness, thereby forming silicon as a fifth insulating film. While exposing the interlayer insulating film 1612 on the oxide film 1422, the polycrystalline silicon film 1522 as the second conductive film is formed on the side of the polycrystalline silicon film 1512 as the first conductive film with the interlayer insulating film 1612 interposed therebetween. Arrange. At this time, the polycrystalline silicon film 1526 which is the second conductive film remains around the silicon nitride film 1310 which is the second insulating film, and the polycrystalline silicon film 1522 which is the second conductive film and the polycrystalline silicon film 1522 remain. The silicon film 1526 is preferably separated (FIGS. 85 and 110). At this time, by setting the AA ′ direction in FIG. 1 to a predetermined value or less in advance, a third wiring layer serving as a control gate line continuous in that direction is formed without using a mask process. The
Thereafter, for example, a silicon oxide film 1423 is deposited to a thickness of 50 to 500 nm as a fifth insulating film in the fourth groove portion 1240. After that, after filling the oxide film 1423 which is the fifth insulating film to the desired depth of the fourth groove portion by, for example, isotropic etching (FIGS. 86 and 111), silicon oxide which is the fifth insulating film Using the film 1423 as a mask, the polycrystalline silicon film 1526 which is the second conductive film exposed by isotropic etching or the like is removed (FIGS. 87 and 112). At this time, it is sufficient to etch about the thickness of the polycrystalline silicon film 1526 which is the second conductive film, and thereby process variations can be reduced.
[0091]
Subsequently, the polycrystalline silicon film 1526 which is the second conductive film remaining in the portion sandwiched between the silicon nitride film 1310 which is the second insulating film and the silicon oxide film 1423 which is the fifth insulating film is isotropically etched. Alternatively, it is removed by anisotropic etching (FIGS. 88 and 113).
After that, as a sixth insulating film, for example, a silicon oxide film 1483 is 8 to 80 nm so as to be embedded in a portion sandwiched between the silicon nitride film 1310 as the second insulating film and the silicon oxide film 1423 as the fifth insulating film. accumulate. At this time, the film thickness of the silicon oxide film 1483 as the sixth insulating film may be about half or more than the deposited film thickness of the polycrystalline silicon film 1522 as the second conductive film (FIGS. 89 and 114).
Next, isotropic etching corresponding to the deposited film thickness is performed to expose the interlayer insulating film 1612 on the side portion of the silicon nitride film 1310 that is the second insulating film, while exposing the sixth groove portion 1240 to the sixth groove portion 1240. A silicon oxide film 1483 which is an insulating film is buried.
Note that although the polycrystalline silicon film 1522 is formed as the second conductive film, it may be formed in a sidewall shape by a combination of deposition and anisotropic etching. Thereafter, using the silicon oxide film 1423 as the fifth insulating film as a mask, the interlayer insulating film 1612 is partially removed by, for example, isotropic etching (FIGS. 90 and 115).
[0092]
By repeating similarly, for example, a polycrystalline silicon film 1523 serving as a second conductive film is disposed on the side of the polycrystalline silicon film 1513 via an interlayer insulating film 1613, and the second conductive film is further formed. The polycrystalline silicon film 1523 which is the conductive film is buried with a silicon oxide film 1424 which becomes the fifth insulating film and a silicon oxide film 1484 which becomes the sixth insulating film (FIGS. 91 and 116). For example, in the polycrystalline silicon film 1514 which becomes the uppermost first conductive film, the polycrystalline silicon film 1514 which is the first conductive film is formed in the same manner as the polycrystalline silicon film 1511 which is the lowermost first conductive film. Etch back.
[0093]
Thereafter, for example, a silicon oxide film 1425 to be a fifth insulating film is deposited to a thickness of 50 to 500 nm, and the upper portion of the silicon nitride film 1310 that is the second insulating film is exposed by, for example, etch back or CMP. (FIGS. 92 and 117). At this time, the silicon oxide film 1425 as the fifth insulating film may be, for example, a silicon nitride film.
Next, the silicon nitride film 1310 that is the second insulating film is selectively removed by, for example, isotropic etching to form the first groove portion 1210. Subsequently, a silicon oxide film 1440 is formed as a third insulating film to be a tunnel oxide film of, for example, about 10 nm on the inner wall of the first groove portion 1210 by using, for example, a CVD method (FIGS. 93 and 118). Here, the silicon oxide film 1440 as the third insulating film is not limited to the CVD oxide film, but may be a thermal oxide film or a nitrogen oxide film.
Subsequently, the silicon oxide film 1440 that is the third insulating film on the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 is selectively removed. For example, the silicon oxide film 1440, which is the third insulating film, is left only in the side wall portion of the first groove portion 1210 by anisotropic etching (FIGS. 94 and 119).
[0094]
Thereafter, a treatment process or the like of the silicon oxide film 1440 that is the third insulating film is performed by heat treatment or the like. For example, annealing is performed for 10 to 100 minutes in a nitrogen atmosphere at 800 to 1000 ° C. At this time, a gas other than nitrogen, such as oxygen, may be added. The thickness of the silicon oxide film 1440 that is the third insulating film is preferably about 10 nm after processing.
Next, the first impurity diffusion layer 1710 or the oxide film formed on the surface of the p-type silicon substrate 1100 is optionally removed by, for example, diluted HF, and island-like semiconductor layers 1721 to 1725 and 1111 are formed in the first groove 1210. Embed ~ 1114. For example, the semiconductor layer is selectively epitaxially grown from the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1721, a P-type semiconductor layer 1111, an N-type semiconductor layer 1722, a P-type semiconductor layer 1112, an N-type semiconductor layer 1723, a P-type semiconductor layer 1113, an N-type semiconductor layer 1724, and a P-type semiconductor layer from the lower layer. 1114 and an N-type semiconductor layer 1725 are sequentially stacked (FIGS. 95 and 120). The concentration of the N-type semiconductor layers 1721 to 1725 is arsenic 1 × 10¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe P-type semiconductor layers 1111 to 1114 are formed with a dose of about 1 × 10 10 boron.¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1721 and 1722 preferably overlap with each other through a polycrystalline silicon film 1511 which is a first conductive film and a silicon oxide film 1440 which is a third insulating film. The layers 1722 and 1723 are the first conductive film polycrystalline silicon film 1512, the N-type semiconductor layers 1723 and 1724 are the first conductive film polycrystalline silicon film 1513, and the N-type semiconductor layers 1724 and 1725 are the first conductive film. It is preferable that the polycrystalline silicon film 1514 which is a conductive film overlaps with the silicon oxide film 1440 which is a third insulating film.
[0095]
Thereafter, the N-type semiconductor layer 1725 is retracted by, for example, an etch back method or a CMP method to expose the silicon oxide film 1425 as the fifth insulating film, and the N-type semiconductor layers 1725 are formed separately. Thereafter, the fourth wiring layer is connected to the upper portion of the N-type semiconductor layer 1725 so that the direction intersects with the second or third wiring layer.
Next, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed. Thus, a semiconductor memory device having a memory function is completed depending on the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate.
[0096]
In this manufacturing example, a film formed on the surface of a semiconductor substrate or a polycrystalline silicon film such as the silicon nitride film 1310 as the second insulating film is a multilayer film of silicon oxide film / silicon nitride film from the silicon surface side. It is good. Further, the introduction of impurities into the polycrystalline silicon films 1511 to 1514 as the first conductive film and the polycrystalline silicon films 1522 and 1523 as the second conductive film may be performed at the time of forming the polycrystalline silicon film. It may be performed after film formation or after sidewall formation, and the introduction time is not limited as long as it is a conductive film.
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
[0097]
Further, by arranging selection gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented.
The charge storage layer does not necessarily have a floating gate structure, and charge storage may be realized by trapping in a stacked insulating film. For example, this manufacturing example is also effective in the case of MNOS and MONOS structures. Examples of the laminated insulating film herein include a laminated structure of a tunnel oxide film and a silicon nitride film or a structure in which a silicon oxide film is further formed on the surface of the silicon nitride film.
[0098]
Production Example 2
In the semiconductor memory device formed in this embodiment, after forming a selection gate and a control gate, a stacked insulating film is formed as a charge storage layer, and an island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth. In the semiconductor memory device in which the semiconductor semiconductor layer is electrically floating with respect to the semiconductor substrate and the active region of each memory cell is electrically floating, the selection gates are formed above and below the island-like semiconductor layer. A plurality of, for example, two memory transistors are arranged between the select gate transistors, and a tunnel oxide film of each memory transistor is formed in a lump, and each transistor is arranged along the island-shaped semiconductor layer. Connected in series, and the gate insulating film thickness of the select gate transistor is the gate insulating film of the memory transistor. When a equal structure.
[0099]
Such a semiconductor memory device can be formed by the following manufacturing method. 122 to 139 and 140 to 157 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 10, respectively, showing an NMOS or MONOS memory cell array. Using the resist R6 as a mask, the silicon nitride film 1310, which is the second insulating film, is etched by, for example, reactive ion etching to form a lattice-patterned fourth groove 1240 (FIGS. 122 to 126 and 140). To 144) are the same as those in Production Example 1 (FIGS. 72 to 96 and FIGS. 97 to 121).
[0100]
Thereafter, for example, a silicon oxide film 1421 is deposited in a thickness of 50 to 500 nm as a fifth insulating film in the lattice-patterned fourth groove 1240 by a CVD method.
Thereafter, the oxide film 1421 which is the fifth insulating film is buried by, for example, isotropic etching to the desired depth of the fourth groove portion 1240 (FIGS. 127 and 145), and silicon nitride which is the second insulating film As the fourth insulating film, for example, a silicon oxide film 1431 is deposited on the surface of the film 1310 by 1 to 10 nm, and then, for example, a polycrystalline silicon film 1511 to be a first conductive film is deposited to a thickness of about 100 to 500 nm (FIG. 128 and FIG. FIG. 146).
[0101]
Next, the polycrystalline silicon film 1511 which is the first conductive film is etched back to form a sidewall having a desired height (FIGS. 129 and 147). At this time, by setting the AA ′ direction in FIG. 10 below a predetermined value in advance, it is formed as a second wiring layer that becomes a selection gate line continuous in that direction without using a mask process. The
Thereafter, for example, a silicon oxide film 1422 is deposited in the fourth groove 1240 as a fifth insulating film by 50 to 500 nm. Next, the silicon oxide film 1422 which is the fifth insulating film is embedded to the desired depth of the fourth groove 1240 by, for example, isotropic etching (FIGS. 130 and 148).
[0102]
By repeating similarly, the first conductive film, for example, the polycrystalline silicon film 1512, the fifth insulating film, for example, the silicon oxide film 1423, the first conductive film, for example, the polycrystalline silicon film 1513, the first conductive film, etc. For example, a silicon oxide film 1424 to be a fifth insulating film, a polycrystalline silicon film 1514 to be a first conductive film, for example, and a silicon oxide film 1425 to be a fifth insulating film are sequentially formed (FIGS. 131 and 131). 149).
Thereafter, the upper portion of the silicon nitride film 1310 as the second insulating film is exposed by, for example, etch back or CMP (FIGS. 132 and 150). At this time, the silicon oxide film 1425 as the fifth insulating film may be, for example, a silicon nitride film.
Next, the silicon nitride film 1310 that is the second insulating film is selectively removed by, for example, isotropic etching to form the first groove portion 1210.
Subsequently, a silicon oxide film 1440 is formed on the inner wall of the first groove portion 1210 by using, for example, a CVD method as a third insulating film that becomes a gate oxide film of about 10 nm, for example. Here, the silicon oxide film 1440 as the third insulating film is not limited to the CVD oxide film, but may be a thermal oxide film or a nitrogen oxide film.
Next, the silicon oxide film 1440 which is the third insulating film on the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 is selectively removed. For example, the silicon oxide film 1440 that is the third insulating film is left in a sidewall shape only on the side wall portion of the first groove 1210 by anisotropic etching (FIGS. 133 and 151).
[0103]
Thereafter, a treatment process or the like of the silicon oxide film 1440 that is the third insulating film is performed by heat treatment or the like. For example, annealing is performed for 10 to 100 minutes in a nitrogen atmosphere at 800 to 1000 ° C. At this time, a gas other than nitrogen, such as oxygen, may be added. The thickness of the silicon oxide film 1440 that is the third insulating film is preferably about 10 nm after processing.
Furthermore, the oxide film formed on the surface of the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 is optionally removed by, for example, diluted HF, and island-like semiconductor layers 1721 to 1722-1 are formed in the first groove portion 1210. And 1111 are embedded. For example, a semiconductor layer is selectively epitaxially grown from the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1721, a P-type semiconductor layer 1111 and an N-type semiconductor layer 1722-1 are sequentially stacked from the lower layer (FIGS. 134 and 152). The concentration of the N-type semiconductor layers 1721-1722-1 is arsenic 1 × 10¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe P-type semiconductor layer 1111 formed with a dose of about 1 is boron 1 × 10¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1721 and 1722-1 preferably overlap with each other through a polycrystalline silicon film 1511 which is a first conductive film and a silicon oxide film 1440 which is a third insulating film. Further, it is preferable that the N-type semiconductor layer 1722-1 be formed so as not to overlap with the polycrystalline silicon film 1512 which is the first conductive film.
[0104]
Thereafter, the silicon oxide film 1440 as the third insulating film is partially removed using the N-type semiconductor layer 1722-1 as a mask.
Subsequently, a laminated insulating film 1620 serving as a charge storage layer is formed on the inner wall of the first groove 1210 (FIGS. 135 and 153). Here, when the laminated insulating film has an MNOS structure, a 4 to 10 nm silicon nitride film and a 2 to 5 nm silicon oxide film may be sequentially deposited on the surface of the polycrystalline silicon film by, for example, a CVD method. A silicon nitride film having a thickness of 4 to 10 nm may be deposited on the surface of the crystalline silicon film, and a silicon oxide film having a thickness of 2 to 5 nm may be formed by oxidizing the surface of the silicon nitride film. In the case of the MONOS structure, for example, a 2 to 5 nm silicon oxide film, a 4 to 8 nm silicon nitride film and a 2 to 5 nm silicon oxide film are sequentially deposited on the surface of the polycrystalline silicon film by the CVD method. Alternatively, a silicon oxide film of 2 to 5 nm and a silicon nitride film of 4 to 10 nm are sequentially deposited on the surface of the polycrystalline silicon film by a CVD method, and further a silicon oxide film of 2 to 5 nm is formed by oxidizing the surface of the silicon nitride film. It may be formed, or the surface of the polycrystalline silicon film may be oxidized to form a 2 to 5 nm silicon oxide film, or the above methods may be combined in various ways.
Next, the stacked insulating film 1620 over the N-type semiconductor layer 1722-1 is selectively removed. For example, the laminated insulating film 1620 is left in a sidewall shape only on the side wall portion of the first groove portion 1210 by anisotropic etching (FIGS. 136 and 154). After that, treatment treatment or the like of the stacked insulating film 1620 may be performed by heat treatment or the like.
Subsequently, the island-shaped semiconductor layers 1722-2 to 1724-1 and 1112 to 1113 are embedded in the first groove portion 1210 in the same manner as described above. For example, the semiconductor layer is selectively epitaxially grown from the island-shaped semiconductor layer 1722-1 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1722-2, a P-type semiconductor layer 1112, an N-type semiconductor layer 1723, a P-type semiconductor layer 1113, and an N-type semiconductor layer 1724-1 are sequentially stacked from the lower layer. The concentration of the N-type semiconductor layers 1722-2 to 1724-1 is 1 × 10 arsenic as before.¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe P-type semiconductor layers 1112 to 1113 are formed with a dose of about 1 × 10 10 boron.¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. Further, the N-type semiconductor layers 1722-2 and 1723 preferably overlap with each other through the polycrystalline silicon film 1512 which is the first conductive film and the stacked insulating film 1620. Similarly, the N-type semiconductor layers 1723 and 1724- 1 preferably overlaps with the polycrystalline silicon film 1513 which is the first conductive film, and the laminated insulating film 1620. Further, it is preferable that the N-type semiconductor layer 1724-1 is formed so as not to overlap with the polycrystalline silicon film 1514 which is the first conductive film.
[0105]
Thereafter, the stacked insulating film 1620 is partially removed using the N-type semiconductor layer 1724-1 as a mask. Subsequently, a silicon oxide film 1444 is formed as a third insulating film that becomes a gate oxide film of, for example, about 10 nm on the inner wall of the first groove portion 1210 by using, for example, a CVD method. Here, the silicon oxide film 1444 as the third insulating film is not limited to the CVD oxide film, but may be a thermal oxide film or a nitrogen oxide film.
Subsequently, the silicon oxide film 1444 which is the third insulating film on the island-shaped semiconductor layer 1724-1 is selectively removed. For example, the silicon oxide film 1444 that is the third insulating film is left in a sidewall shape only on the side wall portion of the first groove portion 1210 by anisotropic etching (FIGS. 137 and 155).
Thereafter, a treatment treatment or the like of the silicon oxide film 1444 which is the third insulating film is performed by heat treatment or the like. Subsequently, the island-shaped semiconductor layers 1724-2 to 1725 and 1114 are embedded in the first groove portion 1210 as described above. For example, the semiconductor layer is selectively epitaxially grown from the island-shaped semiconductor layer 1724-1 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1724-2, a P-type semiconductor layer 1114, and an N-type semiconductor layer 1725 are sequentially stacked from the lower layer (FIGS. 138 and 156). The concentration of the N-type semiconductor layers 1724-2 to 1725 is 1 × 10 arsenic as before.¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe semiconductor layer 1114 formed with a dose of about P type is boron 1 × 10¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1724-2 and 1725 preferably overlap with each other through a polycrystalline silicon film 1514 which is a first conductive film and a silicon oxide film 1444 which is a third insulating film. Thereafter, the N-type semiconductor layer 1725 is retracted by, for example, an etch back method or a CMP method to expose the silicon oxide film 1425 as the fifth insulating film, and the N-type semiconductor layers 1725 are formed separately. Thereafter, the fourth wiring layer is connected to the upper portion of the N-type semiconductor layer 1725 so that the direction intersects with the second or third wiring layer.
Further, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer formed of the stacked insulating film.
[0106]
In this manufacturing example, the silicon nitride film 1310 that is the second insulating film formed on the surface of the semiconductor substrate or the polycrystalline silicon film may be a multilayer film of silicon oxide film / silicon nitride film from the silicon surface side. The introduction of impurities into the polycrystalline silicon films 1511 to 1514 as the first conductive film and the polycrystalline silicon films 1522 and 1523 as the second conductive film may be performed at the time of forming the polycrystalline silicon film, It may be performed after film formation or after sidewall formation, and the introduction time is not limited as long as it is a conductive film.
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
Further, by arranging selection gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented.
[0107]
Production Example 3
In the semiconductor memory device formed in this manufacturing example, a gate oxide film is formed after forming a gate serving as a MIS capacitor and a selection gate as a charge storage layer, an island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth, In the semiconductor memory device in which the island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate and the active region of each memory cell is electrically floated, the upper and lower portions of the island-shaped semiconductor layer are selected. A plurality of, for example, two memory transistors are arranged between a selection gate transistor and a gate oxide film of each memory transistor is formed at one time, and each transistor is connected to the island-like semiconductor layer. And the gate insulating film thickness of the select gate transistor is a memory transistor. The gate insulating film thickness to be equal structure.
[0108]
Such a semiconductor memory device can be formed by the following manufacturing method. FIGS. 158 to 171 and FIGS. 172 to 185 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 11, respectively, showing a memory cell array of a DRAM.
Using the resist R5 patterned by a known photolithography technique as a mask (see FIGS. 73 and 98), for example, the first insulating film 1410 and the p-type silicon substrate 1100 are formed into the first impurity layer by reactive ion etching. Etching Example 2 (FIGS. 122 to 133), except that etching is performed to 200 to 2000 nm so that 1710 is divided and second groove 1220 is formed in a direction intersecting with a second wiring layer to be a continuous gate line later. 140 to 151) (FIGS. 158 to 169 and FIGS. 172 to 183).
Thereafter, the first impurity diffusion layer 1710 or the oxide film formed on the surface of the p-type silicon substrate 1100 is optionally removed by, for example, diluted HF, and island-like semiconductor layers 1721, 1726, 1727 are formed in the first groove portion 1210. , 1725 and 1111, 1120, 1114 are embedded. For example, a semiconductor layer is selectively epitaxially grown from the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1721, a P-type semiconductor layer 1111, an N-type semiconductor layer 1726, a P-type semiconductor layer 1120, an N-type semiconductor layer 1727, a P-type semiconductor layer 1114, and an N-type semiconductor layer 1725 are sequentially stacked from the lower layer ( 170 and 184). The concentration of the N-type semiconductor layers 1721, 1726, 1727, and 1725 is arsenic 1 × 10¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe semiconductor layers 1111, 1120, and 1114 that are formed at a dose of about P type are boron 1 × 10¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1721 and 1726 preferably overlap with each other through the polycrystalline silicon film 1511 which is the first conductive film and the silicon oxide film 1440 which is the third insulating film. The polycrystalline silicon film 1512 which is one conductive film and the silicon oxide film 1440 which is a third insulating film preferably overlap with each other. Similarly, the N-type semiconductor layer 1727 is a multi-layer which is the first conductive film. It is preferable that the crystal silicon film 1513 overlap with the silicon oxide film 1440 which is a third insulating film. The N-type semiconductor layers 1727 and 1725 preferably overlap with each other through a polycrystalline silicon film 1514 which is a first conductive film and a silicon oxide film 1444 which is a third insulating film.
[0109]
Next, the N-type semiconductor layer 1725 is retracted by, for example, etch back or CMP to expose the silicon oxide film 1425 as the fifth insulating film, and the N-type semiconductor layers 1725 are formed separately.
Thereafter, the fourth wiring layer is connected to the upper portion of the N-type semiconductor layer 1725 so that the direction intersects with the second or third wiring layer.
Further, an interlayer insulating film is formed by a known technique to form a contact hole and a metal wiring.
Thereby, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer formed of the MIS capacitor.
[0110]
In this manufacturing example, a film formed on the surface of a semiconductor substrate or a polycrystalline silicon film, such as a silicon nitride film 1310 as a second insulating film, is formed as a silicon oxide film / silicon nitride film multilayer film from the silicon surface side. Also good. The introduction of impurities into the polycrystalline silicon films 1511 to 1514 as the first conductive film and the polycrystalline silicon films 1522 and 1523 as the second conductive film may be performed at the time of forming the polycrystalline silicon film, It may be performed after film formation or after sidewall formation, and the introduction time is not limited as long as it is a conductive film.
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning process by photolithography.
[0111]
Production Example 4
In the semiconductor memory device formed in this manufacturing example, a plurality of floating gates are formed as charge storage layers, a selection gate and a control gate are formed, a tunnel oxide film is formed, and a columnar island shape is formed by selective epitaxial silicon growth. In a semiconductor memory device in which a semiconductor layer is formed, the island-shaped semiconductor layer is electrically floated with respect to a semiconductor substrate, and an active region of each memory cell is electrically floated, an island-shaped semiconductor layer Select gate transistors are arranged on the upper and lower sides of the transistor, and a plurality of, for example, two memory transistors are arranged between the select gate transistors, and a tunnel oxide film of each memory transistor is formed at one time. Are connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is - a larger structure than the thickness of the gate insulating film of the transistor.
[0112]
Such a semiconductor memory device can be formed by the following manufacturing method. 186 to 195 and 196 to 205 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, the polycrystalline silicon films 1522 and 1523 which are the second conductive films through the formation of the polycrystalline silicon films 1511 to 1514 and the interlayer insulating films 1612 and 1613, which become the first conductive films at each stage, for example. And a silicon oxide film 1425 to be a fifth insulating film, for example, is deposited to a thickness of 50 to 500 nm, and is manufactured until the upper portion of the silicon nitride film 1310 which is the second insulating film is exposed by, for example, etch back or CMP. This is the same as Example 1 (FIGS. 72 to 92 and FIGS. 97 to 117) (FIGS. 186 and 196).
Thereafter, the silicon nitride film 1310 as the second insulating film is selectively removed by, for example, isotropic etching to form the first groove portion 1210.
[0113]
Subsequently, a silicon oxide film 1451 is formed on the inner wall of the first groove portion 1210 by using, for example, a CVD method as a thirteenth insulating film that becomes a gate oxide film of, eg, about 20 nm (FIGS. 187 and 197). Here, the silicon oxide film 1451 which is the thirteenth insulating film is not limited to the CVD oxide film but may be a thermal oxide film or a nitrogen oxide film.
Next, the silicon oxide film 1451 which is the thirteenth insulating film on the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 is selectively removed. For example, the silicon oxide film 1451 that is the thirteenth insulating film is left in a sidewall shape only on the side wall portion of the first groove portion 1210 by anisotropic etching (FIGS. 188 and 198).
Thereafter, a treatment process or the like of the silicon oxide film 1451 that is the thirteenth insulating film is performed by heat treatment or the like, as in Production Example 1.
Subsequently, if necessary, the oxide film formed on the surface of the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 is removed by, for example, dilute HF, and island-like semiconductor layers 1721 to 1722 are formed in the first groove 1210. -1 and 1111 are embedded. For example, a semiconductor layer is selectively epitaxially grown from the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1721, a P-type semiconductor layer 1111 and an N-type semiconductor layer 1722-1 are sequentially stacked from the lower layer (FIGS. 189 and 199). The concentration of the N-type semiconductor layers 1721-1722-1 is arsenic 1 × 10¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe P-type semiconductor layer 1111 is formed with a dose of about 1 × 10¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1721 and 1722-1 preferably overlap with each other through a polycrystalline silicon film 1511 which is a first conductive film and a silicon oxide film 1451 which is a thirteenth insulating film. Further, it is preferable that the N-type semiconductor layer 1722-1 be formed so as not to overlap with the polycrystalline silicon film 1512 which is the first conductive film.
[0114]
Thereafter, the silicon oxide film 1451 which is the thirteenth insulating film is partially removed using the N-type semiconductor layer 1722-1 as a mask (FIGS. 190 and 200). For example, a silicon oxide film 1440 is formed on the inner wall of the first groove portion 1210 using a CVD method as a third insulating film that becomes a tunnel oxide film of about 10 nm, for example (FIGS. 191 and 201).
Subsequently, the silicon oxide film 1440 which is the third insulating film on the N-type semiconductor layer 1722-1 is selectively removed. For example, the silicon oxide film 1440 that is the third insulating film is left in a sidewall shape only on the side wall portion of the first groove portion 1210 by anisotropic etching (FIGS. 192 and 202).
Thereafter, a treatment process or the like of the silicon oxide film 1440 that is the third insulating film may be performed by heat treatment or the like.
Subsequently, the island-shaped semiconductor layers 1722-2 to 1724-1 and 1112 to 1113 are embedded in the first groove portion 1210 in the same manner as described above. For example, the semiconductor layer is selectively epitaxially grown from the island-shaped semiconductor layer 1722-1 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1722-2, a P-type semiconductor layer 1112, an N-type semiconductor layer 1723, a P-type semiconductor layer 1113, and an N-type semiconductor layer 1724-1 are sequentially stacked from the lower layer (FIGS. 193 and 203). The concentration of the N-type semiconductor layers 1722-2 to 1724-1 is 1 × 10 arsenic as before.¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe P-type semiconductor layers 1112 to 1113 are formed with a dose of about 1 × 10 10 boron.¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1722-2 and 1723 preferably overlap with each other through the polycrystalline silicon film 1512 which is the first conductive film and the silicon oxide film 1440 which is the third insulating film. The type semiconductor layers 1723 and 1724-1 preferably overlap with each other through a polycrystalline silicon film 1513 which is a first conductive film and a silicon oxide film 1440 which is a third insulating film. Further, it is preferable that the N-type semiconductor layer 1724-1 is formed so as not to overlap with the polycrystalline silicon film 1514 which is the first conductive film.
[0115]
Thereafter, the silicon oxide film 1440 which is the third insulating film is partially removed using the N-type semiconductor layer 1724-1 as a mask.
Subsequently, a silicon oxide film 1454 is formed on the inner wall of the first groove portion 1210 using, for example, a CVD method as a thirteenth insulating film that becomes a gate oxide film of, for example, about 20 nm. Here, the silicon oxide film 1454 as the thirteenth insulating film is not limited to the CVD oxide film, but may be a thermal oxide film or a nitrogen oxide film.
Next, the silicon oxide film 1454 that is the thirteenth insulating film on the island-shaped semiconductor layer 1724-1 is selectively removed. For example, the silicon oxide film 1454 that is the thirteenth insulating film is left in a sidewall shape only on the side wall of the first groove 1210 by anisotropic etching.
Thereafter, the silicon oxide film 1454 which is the thirteenth insulating film is treated by heat treatment or the like.
Subsequently, the island-shaped semiconductor layers 1724-2 to 1725 and 1114 are embedded in the first groove portion 1210 as described above. For example, the semiconductor layer is selectively epitaxially grown from the island-shaped semiconductor layer 1724-1 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1724-2, a P-type semiconductor layer 1114, and an N-type semiconductor layer 1725 are sequentially stacked from the lower layer (FIGS. 194 and 204). The concentration of the N-type semiconductor layers 1724-2 to 1725 is 1 × 10 arsenic as before.¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe semiconductor layer 1114 formed with a dose of about P type is boron 1 × 10¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1724-2 and 1725 preferably overlap with each other through the polycrystalline silicon film 1514 which is the first conductive film and the silicon oxide film 1454 which is the thirteenth insulating film.
[0116]
Thereafter, the N-type semiconductor layer 1725 is retracted by, for example, an etch back method or a CMP method to expose the silicon oxide film 1425 as the fifth insulating film, and the N-type semiconductor layers 1725 are formed separately.
Subsequently, the fourth wiring layer is connected to the upper portion of the N-type semiconductor layer 1725 so that the direction intersects with the second or third wiring layer.
Thereafter, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed.
According to this manufacturing example, the same effects as those of Manufacturing Example 1 (FIGS. 72 to 96 and FIGS. 97 to 121) can be obtained.
[0117]
Production Example 5
The semiconductor memory device formed in this manufacturing example includes a semiconductor substrate in which an oxide film is inserted,
For example, a plurality of floating gates are formed as charge storage layers on a semiconductor portion of an SOI substrate, a selection gate and a control gate are formed, a tunnel oxide film is formed, and an island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth. In the semiconductor memory device, the island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically floated. A selection gate transistor is arranged at the bottom, and a plurality of, for example, two memory transistors are arranged between the selection gate transistors, and a tunnel oxide film of each memory transistor is formed in a lump, and each transistor is connected to the island. The gate insulating film thickness of the select gate transistor is connected to the memory transistor in series along the semiconductor layer. Of equal structure and the gate insulating film thickness of the register.
[0118]
Such a semiconductor memory device can be formed by the following manufacturing method.
206 and 207 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing an EEPROM memory cell array.
This manufacturing example is substantially the same as manufacturing example 1 except that an SOI substrate is used as the substrate (FIGS. 206 and 207), and the same effect can be obtained. Further, the junction capacitance of the impurity diffusion layer 1710 serving as the first wiring layer is suppressed or excluded. In addition, the use of an SOI substrate as the substrate can be applied to all the embodiments of the present invention.
Production Example 6
In the semiconductor memory device formed in this manufacturing example, a plurality of floating gates are formed as a charge storage layer, and after forming a control gate, a tunnel oxide film is formed, and an island-shaped semiconductor layer is formed in a columnar shape by selective epitaxial silicon growth. In the semiconductor memory device, the island-shaped semiconductor layer is electrically floated with respect to the semiconductor substrate, and the active region of each memory cell is electrically floated. An embodiment of the present invention will be described in which two transistors are arranged, the tunnel oxide film of each memory transistor is formed in a lump, and each transistor is connected in series along the island-like semiconductor layer.
[0119]
Such a semiconductor memory device can be formed by the following manufacturing method. 208 to 228 and FIGS. 229 to 249 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 5, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, a silicon oxide film 1410 is deposited on the surface of the p-type silicon substrate 1100 as a first protective film, for example, 2 to 20 nm as a first insulating film, and the first type is formed on the p-type silicon substrate 1100 using ion implantation. One impurity layer 1710 is introduced (FIGS. 208 and 229). For example, implantation energy of 5 to 100 keV from a direction inclined about 0 to 7 °, arsenic 1 × 10¹⁴~ 1x10¹⁶/ Cm²About a dose. Instead of ion implantation, an oxide film containing arsenic may be deposited by CVD, and arsenic diffusion from the oxide film may be used. Further, the first impurity layer 1710 may not be introduced into the outermost surface of the p-type silicon substrate 1100.
[0120]
Subsequently, the first impurity layer 1710 is divided into the first insulating film 1410 and the p-type silicon substrate 1100 by, for example, reactive ion etching using the resist R5 patterned by a known photolithography technique as a mask. In this manner, the second groove 1220 is formed by etching at 200 to 2000 nm (FIGS. 209 and 230).
After removing the resist R5, for example, a silicon oxide film 1420 is deposited to a thickness of 100 to 300 nm as a fifth insulating film in the second groove 1220, and is buried by etch back (FIGS. 210 and 231). When the silicon oxide film 1420 as the fifth insulating film is embedded, etch back using isotropic etching, etch back using anisotropic etching, or planarization embedding using CMP may be performed. However, various combinations may be used. At this time, the silicon oxide film 1420 as the fifth insulating film may be a silicon nitride film. Further, the silicon oxide film 1410 which is the fifth insulating film may be removed or may remain. For example, when the silicon oxide film 1410 as the first insulating film is removed, a silicon nitride film 1310, for example, 1000 to 10,000 nm is formed as a second insulating film on the p-type silicon substrate 1100 or the first impurity layer 1710. (FIGS. 211 and 232).
Next, using the resist R6 patterned by a known photolithography technique as a mask, the silicon nitride film 1310, which is the second insulating film, is etched by, for example, reactive ion etching, so that a fourth groove portion in a lattice pattern is formed. 1240 is formed (FIGS. 212 and 233).
[0121]
Thereafter, for example, a silicon oxide film 1421 is deposited in a thickness of 50 to 500 nm as a fifth insulating film in the lattice-patterned fourth groove 1240 by a CVD method.
Next, the oxide film 1421 that is the fifth insulating film is embedded to the desired depth of the fourth groove portion 1240 by, for example, isotropic etching (FIGS. 213 and 234), and the silicon nitride film that is the second insulating film As a fourth insulating film, for example, a silicon oxide film 1431 is deposited on the surface of 1310, for example, by 1 to 10 nm, and then, for example, a polycrystalline silicon film 1511 to be a first conductive film is deposited by about 50 to 200 nm (FIG. 214 and FIG. 235).
Similarly, the polycrystalline silicon film 1511 which is the first conductive film is etched back to form a sidewall having a desired height (FIGS. 215 and 236). At this time, the polycrystalline silicon film 1512 that is the first conductive film is formed around the silicon nitride film 1310 that is the second insulating film, and is formed around each of the silicon nitride films 1310 that are the second insulating film. The polycrystalline silicon film 1511 which is the first conductive film is separated.
[0122]
Subsequently, an interlayer insulating film 1611 is formed on the surface of the polycrystalline silicon film 1511 which is the first conductive film (FIGS. 216 and 237). The interlayer insulating film 1611 is, for example, an ONO film. The ONO film can be formed in the same manner as in Production Example 1.
Next, for example, a polycrystalline silicon film 1521 to be a second conductive film, for example, is deposited by 15 to 150 nm (FIGS. 217 and 238), and etched back corresponding to the deposited film thickness, thereby forming silicon as a fifth insulating film. While exposing the interlayer insulating film 1611 on the oxide film 1421, the polycrystalline silicon film 1521 as the second conductive film is formed on the side of the polycrystalline silicon film 1511 as the first conductive film with the interlayer insulating film 1611 interposed therebetween. Arrange. At this time, the polycrystalline silicon film 1525 which is the second conductive film remains around the silicon nitride film 1310 which is the second insulating film, and the polycrystalline silicon film 1521 which is the second conductive film and the polycrystalline film The silicon film 1525 is preferably separated (FIGS. 218 and 239). By setting the AA ′ direction in FIG. 5 below a predetermined value in advance, it is formed as a third wiring layer that becomes a control gate line continuous in that direction without using a mask process. .
Thereafter, for example, a silicon oxide film 1422 is deposited in the fourth groove 1240 as a fifth insulating film by 50 to 500 nm.
[0123]
Next, the oxide film 1422 which is the fifth insulating film is buried by, for example, isotropic etching to the desired depth of the fourth groove (FIGS. 219 and 240), and the silicon oxide film 1422 which is the fifth insulating film is formed. The polycrystalline silicon film 1525 which is the second conductive film exposed to the mask by isotropic etching or the like is removed (FIGS. 220 and 241). At this time, it is sufficient to etch about the thickness of the polycrystalline silicon film 1525 which is the second conductive film, thereby reducing process variations.
Subsequently, the polycrystalline silicon film 1525 as the second conductive film remaining in the portion sandwiched between the silicon nitride film 1310 as the second insulating film and the silicon oxide film 1422 as the fifth insulating film is isotropically etched. Alternatively, it is removed by anisotropic etching (FIGS. 221 and 242).
Thereafter, for example, a silicon oxide film 1482 of 8 to 80 nm is embedded as a sixth insulating film so as to be embedded in a portion sandwiched between the silicon nitride film 1310 as the second insulating film and the silicon oxide film 1422 as the fifth insulating film. accumulate. At this time, the film thickness of the silicon oxide film 1482 as the sixth insulating film may be about half or more than the deposited film thickness of the polycrystalline silicon film 1521 as the second conductive film (FIGS. 222 and 243).
Next, isotropic etching corresponding to the deposited film thickness is performed to expose the interlayer insulating film 1611 on the side of the silicon nitride film 1310 that is the second insulating film, while the sixth groove portion 1240 has the sixth A silicon oxide film 1482 which is an insulating film is buried (FIGS. 223 and 244). Although the formation of the polycrystalline silicon film 1521 is described as the second conductive film in this way, it may be formed in a side wall shape by a combination of deposition and anisotropic etching.
[0124]
Thereafter, the interlayer insulating film 1611 is partially removed by, for example, isotropic etching using the silicon oxide film 1422 as the fifth insulating film as a mask (FIGS. 224 and 245).
By repeating similarly, for example, a polycrystalline silicon film 1522 to be a second conductive film is disposed on the side of the polycrystalline silicon film 1512 with an interlayer insulating film 1612 interposed therebetween, for example. A polycrystalline silicon film 1522 which is a second conductive film is buried with a silicon oxide film 1423 which becomes a fifth insulating film and a silicon oxide film 1483 which becomes a sixth insulating film.
Thereafter, the upper portion of the silicon nitride film 1310 as the second insulating film is exposed by, for example, etch back or CMP (FIGS. 225 and 246). At this time, the silicon oxide film 1423 which is the fifth insulating film may be, for example, a silicon nitride film.
Next, the silicon nitride film 1310 that is the second insulating film is selectively removed by, for example, isotropic etching to form the first groove portion 1210.
Subsequently, a silicon oxide film 1440 is formed on the inner wall of the first groove portion 1210 using, for example, a CVD method as a third insulating film that becomes a tunnel oxide film of about 10 nm, for example (FIGS. 226 and 247). Here, the silicon oxide film 1440 as the third insulating film is not limited to the CVD oxide film, but may be a thermal oxide film or a nitrogen oxide film.
Next, the silicon oxide film 1440 which is the third insulating film on the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 is selectively removed. For example, the silicon oxide film 1440 that is the third insulating film is left in a sidewall shape only on the side wall of the first groove 1210 by anisotropic etching.
Thereafter, a treatment process or the like of the silicon oxide film 1440 that is the third insulating film is performed by the same method as in Production Example 1 by heat treatment or the like.
Next, if necessary, the first impurity diffusion layer 1710 or the oxide film formed on the surface of the p-type silicon substrate 1100 is removed by, for example, diluted HF, and island-like semiconductor layers 1721 to 1723 and 1111 and 1112 are embedded. For example, a semiconductor layer is selectively epitaxially grown from the first impurity diffusion layer 1710 or the p-type silicon substrate 1100 located at the bottom of the first groove 1210. At this time, an N-type semiconductor layer 1721, a P-type semiconductor layer 1111, an N-type semiconductor layer 1722, a P-type semiconductor layer 1112, and an N-type semiconductor layer 1723 are sequentially stacked from below (FIGS. 227 and 248). The concentration of the N-type semiconductor layers 1721 to 1725 is arsenic 1 × 10¹⁸~ 1x10^{twenty one}/ Cm^ThreeThe P-type semiconductor layers 1111 and 1112 are formed with a dose of about 1 × 10 10 boron.¹⁵~ 1x10¹⁷/ Cm^ThreeIt is formed with a moderate dose. The N-type semiconductor layers 1721 and 1722 preferably overlap with each other through a polycrystalline silicon film 1511 which is a first conductive film and a silicon oxide film 1440 which is a third insulating film. The layers 1722 and 1723 preferably overlap with each other through a polycrystalline silicon film 1512 which is a first conductive film and a silicon oxide film 1440 which is a third insulating film.
[0125]
Thereafter, the N-type semiconductor layer 1723 is retracted by, for example, an etch back method or a CMP method to expose the silicon oxide film 1423 as the fifth insulating film, and the N-type semiconductor layers 1723 are separately formed.
Next, the fourth wiring layer is connected to the upper portion of the N-type semiconductor layer 1723 so that the direction intersects with the second or third wiring layer.
Thereafter, an interlayer insulating film is formed by a known technique, and contact holes and metal wirings are formed. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the charge storage layer having the polycrystalline silicon film serving as the first conductive film as a floating gate (FIGS. 228 and 249).
[0126]
In this manufacturing example, the film formed on the surface of the semiconductor substrate or the polycrystalline silicon film such as the silicon nitride film 1310 as the second insulating film may be formed as a silicon oxide film / silicon nitride film multilayer film from the silicon surface side. Good. The introduction of impurities into the polycrystalline silicon films 1511 and 1512 as the first conductive film and the polycrystalline silicon films 1521 and 1522 as the second conductive film may be performed at the time of forming the polycrystalline silicon film. It may be performed after film formation or after sidewall formation, and the introduction time is not limited as long as it is a conductive film.
In this manufacturing example, the control gate of each memory cell is formed to be continuous in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
[0127]
Production Example 7
In the semiconductor memory device formed in this manufacturing example, a plurality of floating gates are formed as charge storage layers, a selection gate and a control gate are formed, a tunnel oxide film is formed, and a columnar island shape is formed by selective epitaxial silicon growth. In a semiconductor memory device in which a semiconductor layer is formed, the island-shaped semiconductor layer is electrically floated with respect to a semiconductor substrate, and an active region of each memory cell is electrically common, an upper portion of the island-shaped semiconductor layer And a plurality of, for example, two memory transistors sandwiched between the select gate transistors, and a tunnel oxide film of each memory transistor is formed at one time. Connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is the memory transistor. Of equal structure and the gate insulating film thickness of.
[0128]
Such a semiconductor memory device can be formed by the following manufacturing method.
250 to 252 and FIGS. 253 to 255 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM. FIGS. 256 to 258 and FIGS. 259 to 261 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
Such a semiconductor memory device can be formed by the following manufacturing method.
In this manufacturing example, manufacturing example 1 (FIG. 1) is performed until the polycrystalline silicon film 1522 which is the second conductive film is arranged on the side portion of the polycrystalline silicon film 1512 which is the first conductive film with the interlayer insulating film 1612 interposed therebetween. 72 to 90 and FIGS. 97 to 115). However, when the silicon oxide film 1423 that is the fifth insulating film is embedded in the fourth groove portion 1240, the silicon oxide film 1423 that is the fifth insulating film is formed on the polycrystalline silicon film 1522 that is the second conductive film. Is controlled to a thickness of about 20 to 40 nm, or the polycrystalline silicon film 1522 as the second conductive film is exposed to form a thermal oxide film with a thickness of about 20 to 40 nm (FIGS. 250 and 253). ). At this time, the interval between the polycrystalline silicon films 1512 and 1513 which are the first conductive films which are the floating gates of the memory cells is set to 20 to 30 (FIGS. 251 and 254), whereby the first groove 1210 is formed in a later process. Thus, it is not necessary to form the impurity diffusion layer 1723 formed between the memory cells in the island-shaped semiconductor layers 1721 to 1725 formed in the step (FIGS. 252 and 255).
[0129]
As another production example, the same process as in Production Example 1 (FIGS. 72 to 79 and FIGS. 97 to 104) is performed until the polycrystalline silicon film 1511 which is the first conductive film is formed. However, when the silicon oxide film 1422 which is the fifth insulating film is embedded in the fourth groove portion 1240 between the select gate and the memory cell, the fifth groove 1240 is formed on the polycrystalline silicon film 1521 which is the first conductive film. The silicon oxide film 1422 as an insulating film is controlled to a thickness of about 20 to 40 nm, or the polycrystalline silicon film 1521 as a second conductive film is exposed to form a thermal oxide film with a thickness of about 20 to 40 nm. It forms (FIGS. 256 and 259).
Further, between the memory cells, when the silicon oxide film 1423 which is the fifth insulating film is embedded in the fourth groove portion 1240 in the same manner as described above, the polycrystalline silicon film 1522 which is the second conductive film is buried. In addition, the silicon oxide film 1423 which is the fifth insulating film is controlled to a thickness of about 20 to 40 nm, or the polycrystalline silicon film 1522 which is the second conductive film is exposed to have a thickness of about 20 to 40 nm. A thermal oxide film is formed (FIGS. 257 and 260). At this time, by setting the distance between the polycrystalline silicon films 1512 and 1513 which are the first conductive films which are the floating gates of the memory cells to 20 to 30 nm, an island-shaped semiconductor layer which is formed in the first groove 1210 in a later step Of 1721 to 1725, there is no need to form impurity diffusion layers 1722, 1723, and 1724 formed between the select gate and the memory cell (FIGS. 258 and 261).
[0130]
Production Example 8
In the semiconductor memory device formed in this manufacturing example, a plurality of floating gates are formed as charge storage layers, a selection gate and a control gate are formed, a tunnel oxide film is formed, and a columnar island shape is formed by selective epitaxial silicon growth. In a semiconductor memory device in which a semiconductor layer is formed, the island-shaped semiconductor layer is electrically floated with respect to a semiconductor substrate, and an active region of each memory cell is electrically common, an upper portion of the island-shaped semiconductor layer And a plurality of, for example, two memory transistors sandwiched between the select gate transistors, and a tunnel oxide film of each memory transistor is formed at one time. Connected in series along the island-shaped semiconductor layer, and the gate insulating film thickness of the select gate transistor is the memory transistor. An equal structure and the gate insulating film thickness of, placing a transfer gate between each of the transistors in order to transmit an electrical potential to the active region of each memory transistor.
Such a semiconductor memory device can be formed by the following manufacturing method.
262 and 263 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
[0131]
In this manufacturing example, after forming the polycrystalline silicon films 1521, 1522, 1523, and 1524 which are the second conductive films, the step of forming the gate electrode by the polycrystalline silicon film 1530 which is the third conductive film. Except for the addition, the same procedure as in Production Example 1 is performed.
That is, after the polycrystalline silicon films 1521, 1522, 1523, and 1524 which are the second conductive films are formed, the island-shaped semiconductor layer 1110 between the polycrystalline silicon films 1521 and 1522 which are the first conductive films is exposed. The silicon oxide films 1424 to 1422 and the interlayer insulating films 1612 and 1613 which are the fifth insulating films are removed by isotropic etching to the extent possible.
Thereafter, the oxide film 1400 that is the 21st insulating film is formed on the surface of the island-shaped semiconductor layer 1110 between the selection gate and the memory cell, and the polycrystalline silicon that is the first and second conductive films using, for example, a thermal oxide film method. After forming on the exposed portions of the films 1511, 1512, 1513, 1514, 1521, 1522, 1523 and 1524, a polycrystalline silicon film 1530 which is a third conductive film is deposited on the entire surface.
Subsequently, the polysilicon film 1530 as the third conductive film is etched back by anisotropic etching to such an extent that the space portions of the polysilicon films 1523 and 1524 as the second conductive film are not exposed.
Further, the semiconductor memory device is completed by the same method as in Production Example 1 (FIGS. 262 and 263).
[0132]
Production Example 9
This manufacturing example shows a specific manufacturing example for obtaining a structure in which the direction of the first wiring layer and the direction of the fourth wiring layer are parallel. 264 to 266 and FIGS. 267 to 269 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, the first insulating film 1410 and the p-type silicon substrate 1100 are formed by, for example, reactive ion etching using a resist R5 patterned by a known photolithography technique as a mask (see FIGS. 73 and 98). Example of manufacturing except that etching is performed to 200 to 2000 nm so that the first impurity layer 1710 is divided, and the second groove 1220 is formed in a direction intersecting with the second wiring layer to be a continuous gate line later. (FIGS. 264 to 266 and FIGS. 267 to 269).
Thus, a semiconductor memory having a memory function depending on a charge state stored in a charge storage layer having a polycrystalline silicon film serving as a first conductive film in which the first wiring layer and the fourth wiring layer are parallel as a floating gate. The device is realized.
[0133]
In this manufacturing example, a film formed on the surface of a semiconductor substrate or a polycrystalline silicon film, such as a silicon nitride film 1310 as a second insulating film, is formed as a silicon oxide film / silicon nitride film multilayer film from the silicon surface side. It doesn't matter. The introduction of impurities into the polycrystalline silicon films 1511 to 1514 as the first conductive film and the polycrystalline silicon films 1522 and 1523 as the second conductive film may be performed at the time of forming the polycrystalline silicon film, It may be performed after film formation or after sidewall formation, and the introduction time is not limited as long as it is a conductive film.
In this manufacturing example, the control gates of the memory cells are formed continuously in one direction without using a mask. This is possible only when the island-like semiconductor layers are not symmetrically arranged. That is, by separating the adjacent interval with the island-shaped semiconductor layer in the second or third wiring layer direction to be smaller than that in the fourth wiring layer direction, it is separated in the fourth wiring layer direction, A wiring layer connected in the direction of the third wiring layer is automatically obtained without a mask. On the other hand, for example, when the island-shaped semiconductor layers are arranged symmetrically, the wiring layers may be separated by a resist patterning step by photolithography.
Further, by arranging selection gates above and below the plurality of memory cell portions, the memory cell transistors are in an over-erased state, that is, the read voltage is 0V and the threshold value is in a negative state. However, the phenomenon that the cell current flows can be prevented.
[0134]
Production Example 10
This manufacturing example shows a specific manufacturing example for obtaining a structure in which the first wiring layer is electrically common to the memory array. 270 to 271 and FIGS. 272 to 273 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, the second groove portion 1220 is not formed in the semiconductor substrate 1100, and the process related to this is omitted from the manufacturing example 1.
As a result, at least the first wiring layer in the array is shared without being divided, and has a memory function depending on the charge state stored in the charge storage layer using the polycrystalline silicon film serving as the first conductive film as a floating gate. A semiconductor memory device is realized (FIGS. 270 to 271 and FIGS. 272 to 273).
[0135]
Production Example 11
This manufacturing example shows a specific manufacturing example for obtaining a structure in which a floating gate is formed in a rectangle in a method of forming an island-like semiconductor layer after forming a floating gate as a charge storage layer. FIGS. 274 to 279 and 280 to 285 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing an EEPROM memory cell array.
In this manufacturing example, when the polycrystalline silicon films 1511 to 1514 serving as the first conductive film are formed, the first polycrystalline silicon film 1512 covered with the silicon nitride film 1310 serving as the second insulating film is anisotropically formed. After the side wall is formed by etching, a silicon oxide film 1462, which is the eighth insulating film, is buried to a desired depth between the polycrystalline silicon film 1512, which is the first conductive film, and silicon, which is the eighth insulating film. Using the oxide film 1462 as a mask, the polycrystalline silicon film 1512 which is the first conductive film is partially removed by isotropic or anisotropic etching (FIGS. 274 to 277 and FIGS. 280 to 283).
Next, the silicon oxide film 1462 which is the eighth insulating film is removed, and a polycrystalline silicon film 1512 which is the first conductive film is formed in a rectangular shape. Similarly, the polycrystalline silicon film 1522 which is the second conductive film may be similarly formed. Further, the first polycrystalline silicon films 1511 and 1514 which are selection gates may be formed in the same manner (FIGS. 278 to 279 and FIGS. 284 to 285).
[0136]
Production Example 12
In this manufacturing example, in the method of forming an island-shaped semiconductor layer after forming a floating gate as a charge storage layer, a specific example for obtaining a structure in which the control gate is covered with an interlayer insulating film on the side surface and top surface of the floating gate. A typical manufacturing example is shown. 286 to 289 and FIGS. 290 to 293 are A-A ′ and B-B ′ sectional views of FIG. 1 showing the memory cell array of the EEPROM, respectively.
This manufacturing example is the same as the manufacturing example 1 until a polycrystalline silicon film 1522 to be a second conductive film, for example, 15 to 150 nm is deposited.
After that, by performing etch back corresponding to the deposited film thickness, the interlayer insulating film 1612 on the silicon oxide film 1422 as the fifth insulating film is exposed, and on the side of the polycrystalline silicon film 1512 as the first conductive film. A polycrystalline silicon film 1522 which is a second conductive film is disposed with an interlayer insulating film 1612 interposed therebetween. At this time, the polycrystalline silicon film 1522 as the second conductive film remains around the silicon nitride film 1310 as the second insulating film (FIGS. 286 and 290).
Next, for example, a silicon oxide film 1423 is deposited in the fourth groove 1240 as a fifth insulating film by 50 to 500 nm.
Thereafter, the oxide film 1423, which is the fifth insulating film, is buried by, for example, isotropic etching to the desired depth of the fourth groove (FIGS. 287 and 291), and the silicon oxide film 1423, which is the fifth insulating film, is masked. The polysilicon film 1522 which is the second conductive film exposed by isotropic etching or anisotropic etching is removed (FIGS. 288 and 292). At this time, it is sufficient to etch about the thickness of the polycrystalline silicon film 1522 which is the second conductive film, thereby reducing process variations.
Subsequently, the polycrystalline silicon film 1522 as the second conductive film remains in a portion sandwiched between the silicon nitride film 1310 as the second insulating film and the silicon oxide film 1423 as the fifth insulating film ( 289 and 293). As a result, the area of the polycrystalline silicon film 1512 that is the first conductive film in contact with the polycrystalline silicon film 1522 that is the second conductive film through the interlayer capacitance film 1612 increases, and the coupling ratio is improved.
[0137]
Production Example 13
In the method of forming the island-shaped semiconductor layer after forming the floating gate as the charge storage layer, specific manufacturing examples in which the lengths of the gates of these transistors in the vertical direction are different will be described. 294 to 295 and FIGS. 296 to 297 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing an EEPROM memory cell array.
In this manufacturing example, the lengths in the direction perpendicular to the semiconductor substrate 1100 of the polycrystalline silicon films 1511 to 1514 which are the first conductive films to be the gates or select gates of the memory cells are shown in FIGS. 294 and 296. Thus, the selection gate lengths of the polycrystalline silicon films 1511 and 1514 may be different.
As shown in FIGS. 295 and 297, even if the gate lengths of the memory cells of the polycrystalline silicon films 1512 and 1513 which are the first conductive films are different, the polycrystalline silicon films 1511 to 1511 which are the first conductive films. The lengths in the vertical direction of 1514 may not be the same length.
[0138]
Production Example 14
In the method of forming the island-shaped semiconductor layer after forming the floating gate as the charge storage layer, a specific manufacturing example in which the vertical lengths of the active regions of these transistors are different will be described. 298 and 299 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, the length in the direction perpendicular to the semiconductor substrate 1100 of the semiconductor layers 1111 to 1114 serving as the channel portion of the memory cell or the channel portion of the selection transistor is as shown in FIGS. 298 and 299. Even if the channel lengths of the selection transistors 1111, 1114 are different, the channel lengths of the memory cells of the semiconductor layers 1112, 1113 may be different.
[0139]
Production Example 15
In the method of forming an island-shaped semiconductor layer after forming a floating gate as a charge storage layer, the height of the impurity diffusion layer 1725 located at the upper end of the semiconductor layer 1110 connected to the fourth wiring layer 1840 is increased. A specific manufacturing example in the case is shown. 300 and 301 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing an EEPROM memory cell array.
In this manufacturing example, the height of the semiconductor layer 1725 connected to the fourth wiring layer 1840 may be large (FIGS. 300 and 301). At this time, the thickness of the silicon oxide film 1425 which is the fifth insulating film can be set thick, and the insulation between the polycrystalline silicon film 1514 which is the first conductive film and the fourth wiring layer 1840 is improved. Alternatively, since the exposed area can be set large when exposing the impurity diffusion layer 1725, the connection performance between the impurity diffusion layer 1725 and the fourth wiring layer 1840 is improved.
[0140]
Production Example 16
In a method of forming an island-shaped semiconductor layer after forming a floating gate as a charge storage layer, a specific example of forming the fourth wiring layer 1840 by processing the impurity diffusion layer 1725 located at the upper end of the semiconductor layer 1110 A production example is shown. 302 to 303 and 304 to 305 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, a semiconductor layer 1725 as a fourth wiring layer is processed by reactive ion etching using a resist R8 patterned by a known photolithography technique as a mask (FIGS. 302 and 304). A fourth wiring layer is formed so as to intersect the direction of the second wiring layer or the third wiring layer (FIGS. 303 and 304).
[0141]
Production Example 17
A specific manufacturing example of the shape of the island-shaped semiconductor layer formed after forming the floating gate as the charge storage layer will be described. 306 to 307 and 308 to 309 are cross-sectional views taken along lines A-A ′ and B-B ′ in FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, when the first groove portion 1210 is formed by reactive ion etching, when the upper end portion and the lower end portion of the silicon nitride film 1310 which is the second insulating film are different from each other, FIG. 306 and FIG. As shown in 308.
Further, when the horizontal position of the upper end portion and the lower end portion of the silicon nitride film 1310 which is the second insulating film is shifted, the result is as shown in FIGS. 307 and 309.
For example, when the shape of the silicon nitride film 1310 that is the second insulating film from the upper surface is circular, the former has a conical shape, and the latter has a structure having an oblique cylinder. Note that there is no particular limitation on the shape of the silicon nitride film 1310 which is the second insulating film as long as memory cells can be arranged in series in a direction perpendicular to the semiconductor substrate 1100.
[0142]
Production Example 18
A specific manufacturing example of the shape of the bottom of the semiconductor layer 1110 when the island-shaped semiconductor layer is formed after forming the floating gate as the charge storage layer will be described. FIGS. 310 to 313 and FIGS. 314 to 317 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1, respectively, showing a memory cell array of the EEPROM.
In this manufacturing example, the bottom shape of the checkered first groove portion 1210 may exhibit a linear inclined structure as shown in FIGS. 310, 314, 311 and 315.
Moreover, as shown in FIGS. 312, 316, 313, and 317, the bottom shape of the first checkered groove 1210 may have a rounded inclined structure.
Here, the lower end portion of the polycrystalline silicon film 1511 to be the first conductive film may or may not reach the inclined portion at the bottom of the first groove portion 1210.
[0143]
Production Example 19
In the method of forming the island-shaped semiconductor layer after forming the floating gate as the charge storage layer, a specific manufacturing example will be shown for the shape of the polycrystalline silicon film deposited on the base step portion. 318 to 323 and 324 to 329 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 1 showing a memory cell array of the EEPROM, respectively.
The first polycrystalline silicon films 1511 to 1514 and the second polycrystalline silicon films 1521 to 1524 covered with the silicon nitride film 1310 which is the second insulating film are shown in FIGS. 318 to 323 and 324 to 329. As shown, a structure deposited uniformly along the bottom shape of the first groove 1210 may be presented. Further, as in the manufacturing system 1, a structure in which the substrate is partially unevenly deposited may be exhibited depending on the shape of the bottom.
[0144]
Production Example 20
A specific example of manufacturing a terminal that realizes electrical connection between the first, second, and third wiring layers and the peripheral circuit in the technique of collectively forming the selection gate and the floating gate of each transistor will be described. 330 to 335 show the memory cell array of the EEPROM, respectively, taken along lines HH ′, I1-I1 ′, I2-I2 ′, and I3-I3 ′ in FIGS. 8 and 9. They are line sectional drawing, I4-I4 'sectional view, and I5-I5' sectional view. The same applies to FIGS. 336 to 341. In order to apply a voltage from the outside to the embedded wiring layer, for example, portions 1921, 1932, 1933, 1934, 1910 where the terminals arranged on the upper surface of the semiconductor device are electrically coupled can be confirmed. A sectional view at the position is shown.
In this manufacturing example, each of the first, second, and third wiring layers embedded in the wiring layer lead-out portion is arranged in a step shape as shown in FIGS. 330 to 335, and ends of the respective wiring layers. The first, second, and third wiring layers are formed by forming the first, second, and third contacts 1921, 1932, 1933, 1934, and 1910 so as not to cross the wiring layers other than the desired wiring layer. Is pulled out to the upper surface of the semiconductor device.
The first, second, and third contacts 1921, 1932, 1933, 1934, and 1910 are not formed. For example, the same effect can be obtained by arranging the conductive film to the upper surface of the semiconductor device. Also good.
Also, the first, second, and third wiring layers embedded in the wiring layer lead portion are arranged as shown in FIGS. 336 to 341, and the first, second, and third contacts 1921, 1932, After opening 1933, 1934, and 1910, as a twenty-third insulating film, a silicon oxide film 1499, for example, is deposited to 10 to 100 nm, and then etched back by the deposited film thickness to form a contact formed in the wiring layer lead portion. A sidewall of a silicon oxide film 1499, which is a twenty-third insulating film, is formed on the inner wall of the first wiring layer, and then a metal or a conductive film is embedded in the contact portion to thereby form the first wiring layer and the second and third wirings. The layer may be drawn to the upper surface of the semiconductor device (FIGS. 336 to 341). At this time, the twenty-third insulating film is not limited to a silicon oxide film, and may be a silicon nitride film, and is not limited as long as it is an insulating film.
Further, as shown in FIGS. 339 to 341, the contact for leading out the wiring layer may be formed in common with the wiring layer leading portion of the adjacent memory cells in the AA ′ direction. 330 to 335 may be formed in each wiring layer lead portion.
The method of pulling out the first wiring layer and the second and third wiring layers to the upper surface of the semiconductor as described above can be applied to all the embodiments in the present invention.
[0145]
Production Example 21
As an example of the arrangement of the transistors and capacitors constituting the DRAM, a specific manufacturing example will be described in the case where transistors, capacitors, transistors, and capacitors are arranged in this order from the top of the island-shaped semiconductor layer 1110. FIGS. 342 and 343 are cross-sectional views taken along lines A-A ′ and B-B ′ of FIG. 11 showing the memory cell array of the EEPROM, respectively.
In this manufacturing example, the structure as shown in FIGS. 342 and 343 is made in accordance with Manufacturing Example 3 except that the impurity diffusion layer 1710 is not formed and the separation step of the impurity diffusion layer is not introduced.
Accordingly, a plurality of capacitors formed in the island-shaped semiconductor layer 1110 can be separated by transistors. Further, since the impurity diffusion layer 1710 is not used as a wiring layer, the wiring capacitance is reduced.
Note that the above manufacturing example in which the island-shaped semiconductor layer 1110 is formed in a columnar shape by selective epitaxial silicon growth after a plurality of charge storage layers are formed may be used in various combinations.
[0146]
【The invention's effect】
According to the method for manufacturing a semiconductor memory device of the present invention, it is possible to avoid or prevent the back bias effect of the substrate in the vertical direction of the island-shaped semiconductor layer, and to connect the memory in series between the bit line and the source line. A semiconductor memory device capable of forming a plurality of cells can be efficiently manufactured. As a result, it is possible to create a high-performance device that prevents occurrence of variations in memory cell characteristics due to a decrease in the threshold value of each memory cell during reading due to the back bias effect from the substrate.
[0147]
Further, the vertical direction, which is a direction for determining the device performance, can be further miniaturized without depending on the minimum processing dimension.
Furthermore, the capacity can be increased. For example, when the diameter of a semiconductor substrate cylinder including a memory transistor is formed with a minimum processing dimension, and the shortest distance of the space width between each semiconductor substrate column is configured with the minimum processing dimension, the number of memory transistor stages per semiconductor substrate cylinder is If there are two stages, a capacity twice that of the conventional one can be obtained. That is, the capacity can be increased by a factor of the number of memory transistor stages per cylinder of the semiconductor substrate. In general, the larger the number of stages, the greater the capacity. As a result, the cell area per bit is reduced, and the chip can be reduced in size and cost. In addition, the vertical direction, which is the direction for determining the device performance, does not depend on the minimum processing dimension, and the device performance can be maintained.
[0148]
Further, since each memory cell is arranged so as to surround the island-shaped semiconductor layer, a device in which an improvement in driving current and an increase in S value can be manufactured.
In addition, after processing a semiconductor substrate into a columnar shape using a circular pattern, sacrificial oxidation of the side surface of the semiconductor substrate can be used as a good active region surface by removing damage, defects and irregularities on the substrate surface. it can. At this time, it is possible to control the diameter of the column by controlling the oxide film thickness, and the capacitance between the floating gate and the control gate is determined by the surface area of the tunnel oxide film and the surface area of the interlayer capacitance film of the floating gate and the control gate. Can be easily increased.
Furthermore, by using a circular pattern, the occurrence of local electric field concentration on the active region surface can be avoided, and electrical control can be easily performed. Furthermore, the drive current and the S value can be increased by disposing the gate electrode of the transistor so as to surround the columnar semiconductor substrate. By forming an impurity diffusion layer so that the active region of each memory cell is in a floating state with respect to the substrate, the back bias effect from the substrate is eliminated, and the memory cell characteristics are reduced due to a decrease in the threshold value of each memory cell during reading. Variation does not occur.
[0149]
In addition, after the tunnel oxide film and the floating gate are deposited, a plurality of sidewalls of the insulating film are formed in the vertical direction on the side wall of the floating gate, so that the floating gate can be processed at once. That is, the same tunnel oxide film can be obtained for each memory cell. By using these methods, variation in memory cell characteristics is suppressed, variation in device performance is suppressed, control is facilitated, and cost reduction is realized.
[Brief description of the drawings]
FIG. 1 is a plan view showing a memory cell array of an EEPROM having a floating gate as a charge storage layer in a semiconductor memory device of the present invention.
FIG. 2 is a plan view showing another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 3 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 4 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 5 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 6 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 7 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 8 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 9 is a plan view showing still another memory cell array of an EEPROM having a floating gate as a charge storage layer.
FIG. 10 is a plan view showing a memory cell array having a MONOS structure having a stacked insulating film as a charge storage layer.
FIG. 11 is a plan view showing a memory cell array having a DRAM structure having a MIS capacitor as a charge storage layer.
FIG. 12 is a plan view showing a memory cell array having a MONOS structure having a stacked insulating film as a charge storage layer.
13 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer in the semiconductor memory device of the present invention.
14 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of a semiconductor memory device having a floating gate as a charge storage layer.
15 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.
16 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of another semiconductor memory device having a floating gate as a charge storage layer.
17 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
18 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
19 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.
20 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
FIG. 21 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.
22 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
23 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
24 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
25 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
FIG. 26 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.
FIG. 27 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.
28 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer.
29 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
30 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
31 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
32 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
33 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
34 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
35 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
36 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 1 of still another semiconductor memory device having a floating gate as a charge storage layer. FIG.
37 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 10 of a semiconductor memory device having a stacked insulating film as a charge storage layer.
38 is a cross-sectional view corresponding to the B-B ′ cross-sectional view in FIG. 10 of the semiconductor memory device having a stacked insulating film as a charge storage layer.
39 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 10 of another semiconductor memory device having a stacked insulating film as a charge storage layer.
40 is a cross-sectional view corresponding to the B-B ′ cross-sectional view in FIG. 10 of another semiconductor memory device having a stacked insulating film as a charge storage layer.
41 is a cross-sectional view corresponding to the A-A ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer.
42 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer.
43 is a cross-sectional view corresponding to the A-A ′ cross-sectional view in FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer.
44 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer.
45 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer. FIG.
46 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer.
47 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer. FIG.
48 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 10 of still another semiconductor memory device having a stacked insulating film as a charge storage layer. FIG.
49 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 11 of the semiconductor memory device having the MIS capacitor as a charge storage layer.
50 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 11 of a semiconductor memory device having a MIS capacitor as a charge storage layer.
51 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 11 of another semiconductor memory device having a MIS capacitor as a charge storage layer.
52 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 11 of another semiconductor memory device having a MIS capacitor as a charge storage layer.
53 is a cross-sectional view corresponding to the A-A ′ cross-sectional view of FIG. 11 of still another semiconductor memory device having a MIS capacitor as a charge storage layer. FIG.
54 is a cross-sectional view corresponding to the B-B ′ cross-sectional view of FIG. 11 of still another semiconductor memory device having a MIS capacitor as a charge storage layer. FIG.
55 is a cross-sectional view corresponding to the J1-J1 ′ cross-sectional view of FIG. 12 of a semiconductor memory device having a MIS transistor as a charge storage layer.
56 is a cross-sectional view corresponding to the J2-J2 ′ cross-sectional view of FIG. 12 of a semiconductor memory device having a MIS transistor as a charge storage layer.
57 is a cross-sectional view corresponding to the cross-sectional view taken along the line K1-K1 ′ of FIG. 12 of another semiconductor memory device having a MIS transistor as a charge storage layer.
58 is a cross-sectional view corresponding to the K2-K2 ′ cross-sectional view in FIG. 12 of another semiconductor memory device having a MIS transistor as a charge storage layer.
FIG. 59 is an equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 60 is another equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 61 is yet another equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 62 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array having the MONOS structure according to the present invention.
FIG. 63 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array having the MONOS structure according to the present invention.
FIG. 64 is yet another equivalent circuit diagram of a semiconductor memory device having a memory cell array with a DRAM structure of the present invention.
FIG. 65 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention.
FIG. 66 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention.
FIG. 67 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the DRAM structure of the present invention.
FIG. 68 is yet another equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 69 is yet another equivalent circuit diagram of the semiconductor memory device of the present invention.
FIG. 70 is still another equivalent circuit diagram of a semiconductor memory device having a memory cell array of SRAM structure of the present invention.
FIG. 71 is still another equivalent circuit diagram of the semiconductor memory device having the memory cell array of the SRAM structure of the present invention.
FIG. 72 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
FIG. 73 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
74 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 75 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 76 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
77 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 78 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
79 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 80 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 81 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 82 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 83 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 84 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
85 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
86 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 87 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
88 is a cross-sectional process (line A-A ′ in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 89 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 90 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 91 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 92 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 93 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 94 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
FIG. 95 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention;
96 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 97 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention;
FIG. 98 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
99 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 100 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
FIG. 101 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
102 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 103 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
104 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
105 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.
FIG. 106 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
FIG. 107 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
FIG. 108 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
109 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
110 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 111 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
112 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 113 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention.
114 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention. FIG.
FIG. 115 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
116 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 117 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
118 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 1 of the semiconductor memory device of the present invention; FIG.
FIG. 119 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
120 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention. FIG.
FIG. 121 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 1 of the semiconductor memory device of the present invention;
122 is a sectional view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 123 is a sectional view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
124 is a cross-sectional process view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 125 is a cross-sectional (line A-A ′ line in FIG. 10) process diagram showing Manufacturing Example 2 of the semiconductor memory device of the present invention;
FIG. 126 is a cross-sectional (line A-A ′ line in FIG. 10) process diagram showing Manufacturing Example 2 of the semiconductor memory device of the present invention;
FIG. 127 is a sectional view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
128 is a cross-sectional view (taken along the line A-A ′ of FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
129 is a cross-sectional view (taken along the line A-A ′ in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention; FIG.
130 is a cross-sectional view (taken along the line A-A ′ in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 131 is a cross-sectional (line A-A ′ line in FIG. 10) process diagram showing a manufacturing example 2 of the semiconductor memory device of the present invention;
132 is a cross-sectional process view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
133 is a cross-sectional process view (A-A ′ line in FIG. 10) showing a manufacture example 2 of the semiconductor memory device of the present invention;
FIG. 134 is a sectional view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention.
FIG. 135 is a cross-sectional (line A-A ′ line in FIG. 10) process diagram showing Manufacturing Example 2 of the semiconductor memory device of the present invention;
136 is a cross-sectional process view (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
137 is a cross-sectional process diagram (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
138 is a cross-sectional process diagram (A-A ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 139 is a cross-sectional (line A-A ′ line in FIG. 10) process diagram illustrating Manufacturing Example 2 of the semiconductor memory device of the present invention;
140 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention; FIG.
FIG. 141 is a sectional view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 142 is a sectional view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
143 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
144 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
145 is a cross-sectional process view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
146 is a cross-sectional process view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
147 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
148 is a cross-sectional process view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
149 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
150 is a cross-sectional process view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
151 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
FIG. 152 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
FIG. 153 is a cross-sectional process (B-B ′ line in FIG. 10) process diagram showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 154 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
155 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
FIG. 156 is a cross-sectional process view (B-B ′ line in FIG. 10) showing the manufacture example 2 of the semiconductor memory device of the present invention;
157 is a cross-sectional process view (B-B ′ line in FIG. 10) showing a manufacturing example 2 of the semiconductor memory device of the present invention;
FIG. 158 is a cross-sectional (line A-A ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 159 is a cross-sectional (line A-A ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 160 is a cross-sectional process view (A-A ′ line in FIG. 11) showing a manufacture example 3 of the semiconductor memory device of the present invention;
161 is a sectional view (A-A ′ line in FIG. 11) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 162 is a sectional view (A-A ′ line in FIG. 11) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 163 is a cross-sectional (line A-A ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 164 is a cross-sectional process diagram (A-A ′ line in FIG. 11) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 165 is a cross-sectional process diagram (A-A ′ line in FIG. 11) showing a manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 166 is a cross-sectional (line A-A ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
167 is a cross-sectional process diagram (A-A ′ line in FIG. 11) showing a manufacture example 3 of the semiconductor memory device of the present invention; FIG.
168 is a cross-sectional view (taken along the line A-A ′ in FIG. 11) showing a manufacture example 3 of the semiconductor memory device of the present invention. FIG.
169 is a cross-sectional process (line A-A ′ in FIG. 11) showing a manufacture example 3 of the semiconductor memory device of the present invention; FIG.
FIG. 170 is a cross-sectional process view (A-A ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention;
171 is a cross-sectional (line A-A ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention; FIG.
172 is a cross-sectional process view (B-B ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention; FIG.
FIG. 173 is a cross-sectional process (B-B ′ line in FIG. 11) process diagram illustrating a manufacturing example 3 of the semiconductor memory device of the present invention;
174 is a cross-sectional process view (B-B ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention; FIG.
175 is a cross-sectional process view (B-B ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention;
176 is a cross-sectional process view (B-B ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 177 is a cross-sectional process view (B-B ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 178 is a cross-sectional process (B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 179 is a cross-sectional process (B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 180 is a sectional view (B-B ′ line in FIG. 11) showing a manufacturing example 3 of the semiconductor memory device of the present invention;
FIG. 181 is a cross-sectional (B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 182 is a cross-sectional process (B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
FIG. 183 is a cross-sectional process (B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
184 is a cross-sectional process view (B-B ′ line in FIG. 11) showing the manufacture example 3 of the semiconductor memory device of the present invention;
FIG. 185 is a cross-sectional (line B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 3 of the semiconductor memory device of the present invention;
186 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention; FIG.
187 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention. FIG.
188 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention; FIG.
189 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention; FIG.
FIG. 190 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 191 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
192 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
193 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
FIG. 194 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention;
195 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
196 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention.
197 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention. FIG.
FIG. 198 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention;
199 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
FIG. 200 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention.
FIG. 201 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
202 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 4 of the semiconductor memory device of the present invention; FIG.
FIG. 203 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention;
204 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
205 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 4 of the semiconductor memory device of the present invention; FIG.
FIG. 206 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 5 of the semiconductor memory device of the present invention;
207 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 5 of the semiconductor memory device of the present invention; FIG.
FIG. 208 is a sectional view (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 209 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacture example 6 of the semiconductor memory device of the present invention.
FIG. 210 is a sectional view (A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
FIG. 211 is a cross-sectional process view (A-A ′ line in FIG. 5) showing a manufacture example 6 of the semiconductor memory device of the present invention;
FIG. 212 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
213 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
214 is a cross-sectional view (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 215 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 216 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
217 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
218 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention; FIG.
FIG. 219 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
FIG. 220 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
FIG. 221 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
FIG. 222 is a sectional view (A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
223 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
224 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
225 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
226 is a cross-sectional process view (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 227 is a cross-sectional (line A-A ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
228 is a cross-sectional process diagram (A-A ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
FIG. 229 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
230 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
FIG. 231 is a sectional view (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
232 is a cross-sectional process diagram (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
233 is a cross-sectional process view (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention.
234 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
235 is a cross-sectional process view (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
236 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention; FIG.
237 is a cross-sectional process view (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
238 is a cross-sectional process diagram (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
FIG. 239 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
240 is a cross-sectional process view (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
FIG. 241 is a cross-sectional (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
FIG. 242 is a cross-sectional (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
FIG. 243 is a cross-sectional process diagram (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 244 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention;
245 is a cross-sectional process view (B-B ′ line in FIG. 5) showing a manufacture example 6 of the semiconductor memory device of the present invention;
246 is a cross-sectional process diagram (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention; FIG.
247 is a cross-sectional process (B-B ′ line in FIG. 5) process diagram showing Manufacturing Example 6 of the semiconductor memory device of the present invention; FIG.
248 is a cross-sectional view (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 249 is a cross-sectional process diagram (B-B ′ line in FIG. 5) showing a manufacturing example 6 of the semiconductor memory device of the present invention;
FIG. 250 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention.
FIG. 251 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 252 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 253 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 254 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 255 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
256 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention; FIG.
FIG. 257 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 258 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
FIG. 259 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention;
FIG. 260 is a sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 7 of the semiconductor memory device of the present invention.
FIG. 261 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 7 of the semiconductor memory device of the present invention;
262 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 8 of the semiconductor memory device of the present invention; FIG.
263 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 8 of the semiconductor memory device of the present invention; FIG.
FIG. 264 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
FIG. 265 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
266 is a cross-sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 267 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
268 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 9 of the semiconductor memory device of the present invention;
FIG. 269 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 9 of the semiconductor memory device of the present invention;
270 is a cross-sectional view (taken along the line A-A ′ in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention; FIG.
FIG. 271 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 10 of the semiconductor memory device of the present invention;
FIG. 272 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 273 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 10 of the semiconductor memory device of the present invention;
FIG. 274 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
275 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
276 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 277 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 278 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
279 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
280 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention; FIG.
FIG. 281 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 11 of the semiconductor memory device of the present invention;
FIG. 282 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 283 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
284 is a cross-sectional process (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention.
FIG. 285 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 11 of the semiconductor memory device of the present invention;
FIG. 286 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 287 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
288 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
289 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention; FIG.
290 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 12 of the semiconductor memory device of the present invention; FIG.
FIG. 291 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 292 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 293 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 12 of the semiconductor memory device of the present invention;
FIG. 294 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 13 of the semiconductor memory device of the present invention;
295 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 13 of the semiconductor memory device of the present invention;
296 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 13 of the semiconductor memory device of the present invention; FIG.
FIG. 297 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 13 of the semiconductor memory device of the present invention;
298 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 14 of the semiconductor memory device of the present invention;
299 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 14 of the semiconductor memory device of the present invention; FIG.
300 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 15 of the semiconductor memory device of the present invention;
FIG. 301 is a cross-sectional (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 15 of the semiconductor memory device of the present invention;
FIG. 302 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention;
FIG. 303 is a cross-sectional process view (A-A ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention;
304 is a sectional view (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 16 of the semiconductor memory device of the present invention;
FIG. 305 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 16 of the semiconductor memory device of the present invention;
FIG. 306 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
307 is a cross-sectional process diagram (A-A ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention; FIG.
FIG. 308 is a cross-sectional (line B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 17 of the semiconductor memory device of the present invention;
FIG. 309 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 17 of the semiconductor memory device of the present invention.
FIG. 310 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 18 of the semiconductor memory device of the present invention.
FIG. 311 is a sectional view (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 18 of the semiconductor memory device of the present invention;
FIG. 312 is a sectional view (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 18 of the semiconductor memory device of the present invention;
313 is a cross-sectional view (A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 18 of the semiconductor memory device of the present invention;
314 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 18 of the semiconductor memory device of the present invention;
FIG. 315 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 18 of the semiconductor memory device of the present invention;
316 is a cross-sectional view (B-B ′ line in FIG. 1) showing a manufacturing example 18 of the semiconductor memory device of the present invention;
317 is a cross-sectional process (B-B ′ line in FIG. 1) process diagram showing Manufacturing Example 18 of the semiconductor memory device of the present invention; FIG.
FIG. 318 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 319 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 320 is a sectional view (A-A ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention.
FIG. 321 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 322 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 323 is a cross-sectional (line A-A ′ line in FIG. 1) process diagram showing Manufacturing Example 19 of the semiconductor memory device of the present invention;
FIG. 324 is a cross-sectional process diagram (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention;
FIG. 325 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention;
326 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention;
327 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacture example 19 of the semiconductor memory device of the present invention; FIG.
328 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention.
329 is a cross-sectional process view (B-B ′ line in FIG. 1) showing a manufacturing example 19 of the semiconductor memory device of the present invention; FIG.
FIG. 330 is a cross-sectional (H-H ′ line in FIGS. 8 and 9) process diagram showing a manufacturing example 20 of the semiconductor memory device of the present invention;
331 is a cross-sectional process diagram (line I1-I1 'in FIGS. 8 and 9) showing a manufacture example 20 of the semiconductor memory device of the present invention; FIG.
FIG. 332 is a cross-sectional process (line I2-I2 ′ in FIGS. 8 and 9) showing a manufacture example 20 of the semiconductor memory device of the present invention;
FIG. 333 is a cross-sectional process diagram (line I3-I3 ′ in FIGS. 8 and 9) showing a manufacture example 20 of the semiconductor memory device of the present invention;
334 is a cross-sectional process diagram (line I4-I4 'in FIGS. 8 and 9) showing a manufacture example 20 of the semiconductor memory device of the present invention; FIG.
335 is a cross-sectional view (line I5-I5 'in FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention. FIG.
336 is another cross-sectional view (H-H ′ line in FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
337 is another cross-sectional view (I1-I1 ′ line in FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
338 is another cross-sectional view (line I2-I2 'in FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
339 is another cross-sectional view (line I3-I3 ′ of FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
340 is another cross-sectional view (line I4-I4 ′ in FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
341 is another cross-sectional view (line I 5 -I 5 ′ in FIGS. 8 and 9) showing a manufacturing example 20 of the semiconductor memory device of the present invention; FIG.
FIG. 342 is a cross-sectional process diagram (A-A ′ line in FIG. 11) showing a manufacturing example 21 of the semiconductor memory device of the present invention;
FIG. 343 is a cross-sectional process (B-B ′ line in FIG. 11) process diagram showing Manufacturing Example 21 of the semiconductor memory device of the present invention;
FIG. 344 is a plan view showing a conventional EEPROM.
345 is a cross-sectional view taken along A-A ′ and B-B ′ of FIG. 269.
FIG. 346 is a process cross-sectional view illustrating the conventional method of manufacturing the EEPROM.
FIG. 347 is a process cross-sectional view illustrating the conventional EEPROM manufacturing method.
FIG. 348 is a cross-sectional process diagram illustrating a conventional method of manufacturing an EEPROM;
FIG. 349 is a cross-sectional process diagram illustrating a conventional method of manufacturing an EEPROM.
FIG. 350 is a plan view of a conventional EEPROM and a corresponding equivalent circuit diagram.
FIG. 351 is a cross-sectional view of a conventional MNOS structure memory cell;
FIG. 352 is a cross-sectional view of another conventional MNOS structure memory cell;
FIG. 353 is a cross-sectional view of a semiconductor device in which a plurality of memory cells are formed in one columnar silicon layer.
[Explanation of symbols]
1100, 3100 Silicon substrate (semiconductor substrate)
1101 SOI semiconductor substrate (semiconductor substrate)
1110, 3110 island-like semiconductor layer
1210, 1220, 1230, 1240 Groove
1400, 1410, 1420, 1440, 1431, 1432, 1433, 1434, 1421, 1422, 1423, 1424, 1425, 1482, 1483, 1450, 1462, 1471, 1472, 1473, 1474, 1475, 1451, 1454, 1490, 1491, 3420, 3431, 3434, 3471 Silicon oxide film
1310, 1320, 1330, 1342, 1350, 1360, 1370, 1381, 1382, 1383, 1384, 1385, 1390 Silicon nitride film
1510, 1511, 1512, 1513, 1514, 1520, 1521, 1522, 1523, 1524, 1530, 3511, 3512, 3513, 3514 Polycrystalline silicon film
1612, 1613 Interlayer insulating film
1622, 1623 Multilayer insulating film
1710, 1721, 1722, 1723, 1724, 1725, 1726, 1727, 3710, 3721, 3724 Impurity diffusion layer
1810, 1821, 1824, 1832, 1833, 1840, 3840, 3850 Wiring layer
1910, 1921, 1932, 1933, 1924 Contact part
R5, R6R8 resist

Claims (7)

Forming a first insulating film on a surface layer of a semiconductor substrate having a conductivity type opposite to that of the semiconductor substrate ;
Patterning the first insulating film to form island-shaped insulating films separated from each other;
Forming a charge storage layer made of a first conductive film in a sidewall shape on the outer side wall of the island-shaped insulating film;
Forming a control gate made of a second conductive film in a sidewall shape on the outer side wall of the charge storage layer via an interlayer insulating film;
Etching and removing the island-like insulating film to expose a surface layer of a reverse conductivity type to the semiconductor substrate and an inner surface side wall of the first conductive film;
Forming a tunnel insulating film on the inner side wall of the exposed first conductive film;
And against the inner wall side surface of the tunnel insulating film, a step of forming by epitaxial growth of the island-shaped semiconductor layer having a region where at least the first conductive film is opposed through the tunnel insulating film is the same conductivity type as said semiconductor substrate By including
Wherein the semiconductor substrate, at least one of the island-shaped semiconductor layer as a channel layer, the tunnel insulating film formed around the sidewall of the island-like semiconductor layer, at least composed of the charge storage layer and the control gate A semiconductor memory device comprising : a plurality of memory cells, wherein the at least one memory cell is electrically insulated from the semiconductor substrate by a surface layer having a conductivity type opposite to that of the semiconductor substrate. Device manufacturing method. Forming a first insulating film on a surface layer of a semiconductor substrate having a conductivity type opposite to that of the semiconductor substrate ;
Patterning the first insulating film to form island-shaped insulating films separated from each other;
Forming a control gate made of a first conductive film on the outer side wall of the island-shaped insulating film in a sidewall shape;
Etching and removing the island-like insulating film to expose a surface layer of a reverse conductivity type to the semiconductor substrate and an inner surface side wall of the first conductive film;
Forming a charge storage layer made of a laminated insulating film on the inner sidewall of the exposed first conductive film;
And against the inner wall side surface of the charge storage layer, and forming by epitaxial growth of the island-shaped semiconductor layer having a region where at least the first conductive film are opposed via the charge storage layer is the same conductivity type as said semiconductor substrate By including
Said semiconductor substrate, at least one of the island-shaped semiconductor layer as a channel layer, and at least one memory cell comprised of the charge storage layer and the control gate is formed around the sidewall of the island-shaped semiconductor layer A method of manufacturing a semiconductor memory device, comprising: manufacturing a semiconductor memory device, wherein the at least one memory cell is electrically insulated from the semiconductor substrate by a surface layer having a conductivity type opposite to that of the semiconductor substrate. Forming a first insulating film on a surface layer of a semiconductor substrate having a conductivity type opposite to that of the semiconductor substrate ;
Patterning the first insulating film to form island-shaped insulating films separated from each other;
A step of forming a pair of first conductive films side by side in the height direction so as to form a gate and a control gate on the outer side wall of the island-shaped insulating film;
Etching away the island-like insulating film, exposing a surface layer of a reverse conductivity type to the semiconductor substrate and an inner surface side wall of the first conductive film;
Forming a gate insulating film on the inner sidewall of the exposed first conductive film;
Before and against the side of the inner wall of Kige over gate insulating film, said gate having a region facing via the gate insulating film of the semiconductor substrate and the opposite conductivity type, said control gate via said gate insulation film in a region facing the same conductivity type as the semiconductor substrate so as to have a region pixels respectively the semiconductor substrate and the opposite conductivity type in contact with the upper and lower ends of the region, to form a Rishima shaped semiconductor layer by the epitaxial growth Including the process,
Said semiconductor substrate, a memory cell formed on at least one of the island-shaped semiconductor layer, the gate has been made form around the sidewall of the island-shaped semiconductor layer, serving as the gate insulating film and the charge storage layer including transistors composed of the island-shaped semiconductor layer as the control gate, the gate insulating film and the channel layer formed around the sidewall of the island-shaped semiconductor formed of layers Ruki Yapashita and the island-shaped semiconductor layer A semiconductor memory device comprising: at least one memory cell; and wherein the at least one memory cell is electrically insulated from the semiconductor substrate by a surface layer having a conductivity type opposite to that of the semiconductor substrate. Manufacturing method of semiconductor memory device. When the first conductive film is processed into a sidewall shape, a channel layer formed immediately below the first conductive film facing the island-shaped semiconductor layer is electrically connected to an adjacent channel layer. extent to place in the first conductive film close to each other that, a method of manufacturing a semiconductor memory device according to claim 1 or 2 for dividing the first conductive film 2 or more. When processing the first conductive film into a sidewall shape, the first conductive film is divided into two or more in the height direction, and a third region is formed in a region between the adjacent divided first conductive films. by forming a gate electrode made of a conductive film, a channel layer adjacent the channel layer is formed immediately below the in side the first conductive film on the island-like semiconductor layers in the height direction of the island-shaped semiconductor layer The method for manufacturing a semiconductor memory device according to claim 1, wherein a potential for electrical connection to the island-like semiconductor layer can be applied to the island-like semiconductor layer . Side walls of said at least two have a first conductive film in the height direction, the tunnel in the insulating film formation process, one of the first conductive film located on an end portion in the height direction of the island-shaped semiconductor layer 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein a gate insulating film of a transistor for selecting the memory cell is formed, and the tunnel insulating film is formed on a side wall of the other first conductive film. Side walls of said at least two have a first conductive film in the height direction, said in the stacked insulating film formation process, wherein the one located at the end of the height direction of the island-shaped semiconductor layer and the first conductive film 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein a gate insulating film of a transistor for selecting the memory cell is formed, and the stacked insulating film is formed on a side wall of the other first conductive film.

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