KR101002293B1 - Stacked nonvolatile memory cell device having floating body, and nonvolatile memory cell stack, nonvolatile memory cell string, nonvolatile memory cell array using the cell device, and fabricating method thereof - Google Patents

Abstract

The present invention relates to a stacked nonvolatile memory cell device having a floating body, a nonvolatile memory cell device stack, a nonvolatile memory cell string, a nonvolatile memory cell string stack, and a nonvolatile memory cell string stack array. The nonvolatile memory cell string includes a stacked nonvolatile memory cell device having a plurality of floating bodies and a switching device connected to an end of the cell device. The cell device stack is implemented by stacking the stacked nonvolatile memory cell devices on a semiconductor substrate. The cell string stack is implemented by stacking the cell strings. The cell string stack is arranged to implement a cell string stack array. The cell device stack may include a semiconductor substrate; A control electrode formed on the surface of the semiconductor substrate in the form of a vertical pillar; An insulating film formed between the control electrode and the semiconductor substrate; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; And a semiconductor region formed on a side of the gate stack. The first insulating layer and the semiconductor region are alternately formed on the side of the gate stack. The present invention can significantly improve the capacity of the NAND nonvolatile memory and the performance of the cell device while reducing the manufacturing cost.

NAND, Nonvolatile, Stacked, Memory, High Density, High Capacity, String, Stack

Description

Stacked nonvolatile memory cell device having a floating body, nonvolatile memory cell stack using the cell device, nonvolatile memory cell string, nonvolatile memory cell array and manufacturing method thereof cell stack, nonvolatile memory cell string, nonvolatile memory cell array using the cell device, and fabricating method

The present invention relates to a stacked nonvolatile memory cell device having a floating body, a nonvolatile memory cell stack using the cell device, a nonvolatile memory cell string, a nonvolatile memory cell array, and a method of manufacturing the same. A novel NAND nonvolatile memory structure for improving the miniaturization characteristics and performance of nonvolatile memory devices and increasing memory capacity, comprising: a nonvolatile memory cell stack having a plurality of cell devices stacked in a stack; The present invention relates to a cell string composed of switching elements, a cell string stack composed of the cell strings, and a cell array implemented by arranging the cell string stack.

Recently, the demand for nonvolatile memory is rapidly increasing in home appliances and portable electronic devices. The density of NAND nonvolatile memory is required to increase with the development of IT technology. The degree of integration of the NAND nonvolatile memory is highly dependent on the degree of integration of the cell devices. In recent years, gate lengths of cell devices have been reduced to 50 nm or less, and memory capacities have reached tens of gigabytes. Therefore, the conventional non-volatile memory device having a flat floating channel structure having a conductive floating gate is a problem that the short channel effect is a big problem, and the manufacturing process is also very difficult. The technology having a gate length of 50 nm or less requires expensive equipment or processes and thus increases manufacturing costs. In the future, the gate length may need to be reduced to improve the density. An alternative to this situation needs to be considered.

In order to increase the integration degree of a device having a conventional floating poly electrode, a SONOS series nonvolatile memory cell using an insulating storage electrode such as a nitride film as a memory storage node has been considered. In addition, nano-floating gate memory (NFGM) cells using nano dots or nano crystals as charge storage electrodes have been considered. When a memory cell is implemented by using a charge storage electrode such as a nitride film or a nano dot in a conventional flat channel structure, the miniaturization characteristic is improved as compared with the case of using a floating gate of conductive polysilicon. However, even with such an improved charge storage electrode, the gate length of 40 nm or less faces a limit in which the characteristics are greatly reduced or cannot be reduced by the short channel effect.

SONOS (or TANOS: TaN-AlO-SiN-) with an asymmetric source / drain structure in flat channel devices to suppress short channel effects and reduce the distribution of threshold voltages when the gate length of cell devices is reduced below 40 nm. Oxide-Si cell devices (KT Park et al, A 64-cell NAND flash memory with asymmetric S / D structure for sub-40 nm technology and beyond, in Technical Digest of Symposium on VLSI Technology, p. 24, 2006) It was announced by Samsung Electronics. The cell element has a source or drain on one side and no source or drain on the other side. It is a structure that suppresses a short channel effect by forming an inversion layer using a fringing electric field from a control electrode in a region without a source or a drain. Although the miniaturization characteristic is improved compared to the conventional SONOS cell device having a flat channel having a source / drain region, since one of the source / drain of the cell device is formed to overlap the control electrode, the channel length of 40 nm or less It has a short channel effect and ultimately faces the miniaturization limit of the flat channel structure. In addition, the two structures have a limitation in improving the degree of integration since the memory is implemented in one layer only on the silicon surface.

The method of increasing the integration degree while reducing the manufacturing cost is a method of vertically arranging cell elements or cell strings. In the US patent (Registration No .: 5739567, namely: Highly compact memory device with nonvolatile vertical transistor memory cell), a trench was formed, and a tunneling insulating film, a floating gate, a blocking insulating film, and a control electrode were sequentially formed in the trench. Sources were formed in the semiconductor region near the bottom of the trench and drains in the semiconductor region near the top of the trench, respectively. In this structure, only one vertical cell element is formed, so that the memory capacity cannot be substantially increased, and due to structural problems, several cell elements cannot be formed vertically.

In a published paper (Y. Fukuzumi et al., "Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory," IEDM Tech. Dig., Pp. 449-452, 2007) To solve the problem of the US patent, several cells and two switch elements are arranged vertically. Therefore, the degree of integration can be increased. However, there is a disadvantage in that the write time is somewhat slow, especially the erase time. In addition, retention characteristics are poor. In the manufacturing process, an insulating film is formed between the control electrode layers for electrical insulation between the control electrodes of several layers stacked vertically. In this case, when forming a circular through hole to form a string, it is necessary to continuously etch alternately between the control electrode made of polysilicon and the insulating layer made of silicon oxide film, which is extremely difficult and time-consuming. Can take In addition, when forming a tube-shaped body vertically, in order to make the bottom electrically connected to the semiconductor region, only a portion of the bottom of the through hole should be etched, leaving a gate insulating film or a blocking insulating film formed on the vertical sidewall of the through hole. At this time, the insulating film may be damaged, which may lead to deterioration of memory cell characteristics, and thus yield may decrease. Electrical contact and wiring of the source region formed at the bottom of the through hole from the upper surface of the through hole may require a large mask as well as overcoming a large step. In short, there are many difficulties in terms of fairness.

As such, there is a need for developing a highly integrated / high performance nonvolatile memory device having a new structure that can solve the problems of the existing published devices.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is a stacked nonvolatile memory cell device having a floating body which is easy to manufacture and can improve memory cell characteristics, a nonvolatile memory cell stack using the cell device, and a nonvolatile memory. A cell string, a nonvolatile memory cell string stack, a nonvolatile memory cell array, and a method of manufacturing the same are provided.

A first aspect of the present invention for achieving the above technical problem relates to a stacked nonvolatile memory cell device, the cell device comprises: a semiconductor substrate; A control electrode formed on the surface of the semiconductor substrate in the form of a vertical pillar; An insulating film formed between the control electrode and the semiconductor substrate; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; And a semiconductor region formed on a side of the gate stack, wherein the first insulating film and the semiconductor region are formed adjacent to each other and simultaneously formed on one side of the gate stack.

A nonvolatile memory cell device stack according to a second aspect of the present invention includes a semiconductor substrate; A control electrode formed on the surface of the semiconductor substrate in the form of a vertical pillar; An insulating film formed between the control electrode and the semiconductor substrate; A gate stack formed on a side of the control electrode; A first insulating film formed of a plurality of layers on a side of the gate stack; And a semiconductor region formed of a plurality of layers on a side of the gate stack. The first insulating layer and the semiconductor region are alternately formed on the same side of the gate stack.

In the nonvolatile memory cell device stack according to the second aspect, the semiconductor device may further include a source and a drain region formed in a semiconductor region which does not overlap the control electrode among side surfaces of the semiconductor region.

The nonvolatile memory cell device stack according to the second aspect may further include a fifth insulating film formed on the semiconductor substrate, and the control electrode and the first insulating film may be formed on the fifth insulating film.

In the nonvolatile memory cell device stack according to the second aspect, the gate stack includes a tunneling insulating film, a charge storage node, and a control insulating film, or a tunneling insulating film and a charge storage node, or a charge storage node and a blocking insulating film. desirable.

In the nonvolatile memory cell device stack according to the second aspect, the gate stack and the control electrode formed on the side of the semiconductor region may partially surround the side of the semiconductor region.

A nonvolatile memory cell string stack according to a third aspect of the present invention includes a semiconductor substrate; And a plurality of nonvolatile memory cell strings stacked on the semiconductor substrate.

The nonvolatile memory cell string may include a plurality of nonvolatile memory cell elements arranged in a row; And a switching device connected to ends of the nonvolatile memory cell devices.

The nonvolatile memory cell device may include a control electrode; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; And a semiconductor region formed on a side of the gate stack, the semiconductor region being horizontally connected to a first insulating film of an adjacent cell element in the same layer as the first insulating layer of each cell element, wherein the semiconductor region is formed of an adjacent cell element in the same layer. The electrodes are horizontally connected to each other and the control electrodes of the cell elements are electrically isolated from each other by an insulating film between the control electrodes.

In the non-volatile memory cell string stack according to the third aspect, the switching element is configured to be the same as the cell element, or the same as the cell element, and is implemented as a gate insulating layer made of one or multiple insulating layers instead of the gate stack. When the gate insulating layer is formed of a multilayer insulating layer, adjacent layers are preferably made of materials having different band gaps.

In the nonvolatile memory cell string stack according to the third aspect, the semiconductor device may further include a source and a drain region formed in a semiconductor region which does not overlap the control electrode.

In the non-volatile memory cell string stack according to the third aspect, the width of the semiconductor region overlapping the control electrode among the side surfaces of the semiconductor region is formed to be wider or narrower than the width of the semiconductor region not overlapping the control electrode. desirable.

In the non-volatile memory cell string stack according to the third aspect, the charge storage node of the cell element is formed only on the side portion of the semiconductor region overlapping with the control electrode of the cell element or is formed on the entire side of the semiconductor region of each cell element. Can and

In the non-volatile memory cell string stack according to the third aspect, both edges of the semiconductor region of the cell string are formed in a "┗" or "-" structure, and a source / drain type is formed at both edge regions of the semiconductor region. It is preferable to further form an impurity region of and to form an electrode through the first contact window.

A nonvolatile memory cell string stack array comprising a plurality of nonvolatile memory cell string stacks arranged in a line according to a fourth aspect of the present invention, the nonvolatile memory cell string stack comprising: a semiconductor substrate; And a plurality of nonvolatile memory cell strings stacked on the semiconductor substrate.

The nonvolatile memory cell string may include a plurality of nonvolatile memory cell elements arranged in a row; And a switching device connected to ends of the nonvolatile memory cell devices.

The nonvolatile memory cell device may include a control electrode; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; And a semiconductor region formed on a side of the gate stack, wherein the first insulating film of each cell element is horizontally connected to the first insulating film of the adjacent cell element, and the semiconductor region is horizontally connected to the semiconductor region of the adjacent cell element. The control electrodes of the cell elements are electrically isolated from each other by an insulating film between the control electrodes.

In the nonvolatile memory cell string stack array according to the fourth aspect, the cell string stack preferably shares a control electrode and a semiconductor region with an adjacent cell string stack.

A non-volatile memory cell string stack array according to a fourth aspect, further comprising a third insulating film between semiconductor regions of the cell string stack adjacent to each other, wherein adjacent cell string stacks do not share the semiconductor region but share only the control electrode. You can do that.

A nonvolatile memory cell string stack array according to a fourth aspect, wherein the cell string stacks are alternately arranged with the control electrode and the semiconductor region in a direction crossing the direction in which the cell string is elongated. The third insulating layer may be further provided between adjacent control electrodes such that the semiconductor region is shared and the control electrode is not shared.

In the non-volatile memory cell string stack array according to the fourth aspect, the cell device may further include a source and a drain region formed in a semiconductor region which does not overlap the control electrode among side surfaces of the semiconductor region.

In the nonvolatile memory cell string stack array according to the fourth aspect, it is preferable to integrate the same circuit as the peripheral circuit for driving the memory.

A non-volatile memory cell string stack array according to a fourth aspect, further comprising a first well on the semiconductor substrate, the first well being different from the doping type of the semiconductor substrate, or the first well and the first well and the first well. It may further comprise a second well of a different ping type.

A method of fabricating a memory cell string stack in which cell strings including a plurality of cell elements and switching elements formed on a semiconductor substrate according to a fifth aspect of the present invention are stacked in multiple layers, wherein (a) an etch rate is Alternately forming a sacrificial semiconductor layer and a semiconductor layer made of different materials; (b) forming a trench by etching from the surface of the product of step (a) to the surface of the semiconductor substrate; (c) etching side surfaces of the sacrificial semiconductor layer and the semiconductor layer exposed through the trench forming step, but etching more of the side surface of the sacrificial semiconductor layer using an etch rate difference; (d) oxidizing the sacrificial semiconductor layer partially etched to form an insulating film, filling the insulating film on the side to complete the first insulating film, and forming a gate stack in the trench region; (e) forming a control electrode on the surface of the gate stack, removing unnecessary control electrodes and removing the exposed gate stack; (f) forming source and drain regions on the exposed side of the semiconductor layer, and filling an insulating film between control electrodes in a space from which unnecessary control electrodes and gate stacks are removed; (g) forming an insulating film, forming a contact window where a contact hole is needed, and sequentially forming a metal layer for wiring; It includes.

In the method of manufacturing a cell string stack according to the fifth aspect, the step (a) is performed on a single crystal semiconductor substrate to form the sacrificial semiconductor layer and the semiconductor layer in epitaxial form, or a fifth insulating film is formed on the semiconductor substrate. After the formation, it is preferable to form the sacrificial semiconductor layer and the semiconductor layer on the formed fifth insulating film.

In the method of manufacturing a cell string stack according to the fifth aspect, before the step (a) is performed, a sixth insulating film is formed on the surface of the semiconductor substrate and the sixth insulating film in the region where the memory array is to be formed is removed. Selectively etching the semiconductor substrate, but etching the edge portion of the memory array region in an 'undercut' shape, and the alternating sacrificial semiconductor layer and the semiconductor layer are formed in the undercut region so that the surface is aligned in the undercut region. It is desirable to.

In the cell string stack manufacturing method according to the fifth aspect, the forming of the source and drain regions of the step (f) is preferably implanted in a plasma atmosphere.

In the nonvolatile memory cell string and the manufacturing method according to the present invention, in implementing a stacked cell string stack and an array under the characteristic of NAND nonvolatile memory, it is possible to effectively use a common body on which a control electrode or a channel is formed. The advantage of increasing memory capacity is that the cell occupies nearly 2F ² . In addition to these advantages, there are the following additional advantages.

First, the manufacturing process is simpler than the conventional published stacked structure, and the process cost can be lowered or the yield of memory cells can be improved. The blocking insulating film, the charge storage node, and the tunneling insulating film included in the gate stack can be protected from damage caused by etching generated in the conventional manufacturing process, thereby improving performance and improving yield.

Second, the semiconductor region in which the channel is formed is composed of a single crystal semiconductor, so that the characteristics are excellent and the cell scattering characteristics are improved as compared with the case of the polycrystalline or amorphous structure.

Third, a program / erase voltage can be lowered by introducing a structure in which control electrodes are wrapped around side surfaces of a plurality of stacked semiconductor regions.

Fourth, since the semiconductor region of the device formed of the plurality of layers is electrically isolated by the insulating films, the problem caused by the leakage channel can be reduced.

Hereinafter, a structure of a stacked nonvolatile memory cell device, a cell device stack, a cell string, a cell string stack, and a cell string stack array according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First embodiment

FIG. 1A is a three-dimensional perspective view illustrating a stacked nonvolatile memory cell string stack array including cell strings including stacked nonvolatile memory cell devices according to a first exemplary embodiment of the present invention. Shows a top view of the array of (a). In the drawings and the following drawings, a part of the upper portion of the stacked nonvolatile memory is cut out to clearly show the structure of the present invention.

Referring to FIG. 1A, a nonvolatile memory cell string stack according to a first embodiment of the present invention is arranged in a line in the y direction. For reference, in FIG. 1A, the number of cell devices stacked in one cell device stack is eight, which is illustrated as an example, and stacking may be controlled within a range allowed by the process. A region indicated by broken lines in FIGS. 1A and 1B represents an area on a plan view of one cell device stack and has an area of approximately 2F ² . Compared to the conventional stacked memory device having a single cell occupying 6F ² , the structure according to the first embodiment of the present invention can improve the existing integration degree by about three times. Where F is the size of the minimum feasible pattern.

Stacked Nonvolatile Memory Cell Device Structure with Floating Body

Hereinafter, a structure of a stacked nonvolatile memory cell device according to a first embodiment of the present invention will be described in detail with reference to FIG. 1A. A stacked nonvolatile memory cell device having a floating body according to a first embodiment of the present invention includes a control electrode 8 and gate stacks 5, 6, and 7 formed on side surfaces of the control electrode and denoted by reference numeral 14. And a first insulating layer 9 formed on the side of the gate stack, a semiconductor region 11 and a source and drain region 13 formed on the side of the gate stack. One surface of the semiconductor region 11 and the first insulating layer 9 are in contact with each other, and a layer is formed on one side of the gate stack.

The gate stack 14 is formed on the side of the control electrode, and includes a tunneling insulating film 5, a charge storage node 6, and a blocking insulating film 7, a tunneling insulating film and a charge storage node, or a charge storage node. And a blocking insulating film. The charge storage node 6 of the cell device may be formed only on the side portion of the semiconductor region 11 overlapping the control electrode 8 of the cell device, or may be formed on the entire side surface of the semiconductor region 11 of each cell device. . The tunneling insulating film 5 or the blocking insulating film 7 may be implemented in one layer or multiple layers. When the tunneling insulating film or the blocking insulating film is implemented in multiple layers, adjacent layers may be formed of materials having different dielectric constants or band gaps. Can be. The charge storage node 6 may be formed of any one of a conductive thin film, an insulating film having a trap for charge storage, and a nano-sized dot, and may be composed of an insulating film formed by dispersing nano-sized dots therein. have.

The semiconductor region 11 is formed as a layer on the side of the gate stack and includes a source / drain 13 and a body of the device. That is, the region except for the source / drain region 13 in the semiconductor region 11 may be a body and may be doped with an impurity type different from that of the source / drain. When the cell device is turned on, a channel is formed in an area where the body and the control electrode 8 overlap. In the structure of the present invention, the body is in a floating state. Since semiconductor regions of a cell element formed of a plurality of layers are electrically isolated by an insulating film, problems due to leakage channels can be reduced. In general, when a body is floated in a NAND flash memory cell string, it is necessary to induce a charge of a type opposite to that stored in the charge storage node 6 in the erasure operation of the cell. For example, in order to remove electrons stored in the nonvolatile memory cell configured in the form of n-type MOS in the charge storage node 6, it is necessary to induce holes in the surface of the channel. Since the body is floating in the structure according to the present invention, such holes are formed by a gate induced drain leakage (GIDL) in the region of the source / drain 13 formed to overlap the end of the channel length direction of the control electrode 8. The GIDL may be generated or supplied in the source / drain region of the switching element existing at both ends of the cell string.

As shown in FIGS. 6 and 7, the width of the semiconductor region overlapping the control electrode among the side surfaces of the semiconductor region may be formed to be relatively wider or narrower than the width of the semiconductor region not overlapping the control electrode. As illustrated in FIG. 6, 7, or 8, side surfaces of the semiconductor region contacting the gate stack may be formed to have various shapes, and particularly, may be formed in a round shape. In addition, as shown in FIG. 10, the gate stack and the control electrode formed on the side of the semiconductor region may partially cover the side of the semiconductor region.

The source and drain regions 13 are formed in the semiconductor region, and a portion of the source and drain regions 13 overlap with both ends of the channel length direction of the control electrode, or the source and drain regions are formed with the control electrode. It can be formed so that it may not overlap.

Another embodiment of the stacked nonvolatile memory cell device of the present invention does not include a source and a drain region, and the source and drain regions are formed by a fringing electric field coming from a control electrode to which a pass voltage is applied in a read operation. The inversion layer is formed where it is to be formed to operate normally. As such, when there are no source and drain regions in the cell element, the semiconductor region of the cell element is composed only of a body, and the semiconductor region of the switching element of the cell string including the cell elements is a source and drain region, and the source and drain regions. It is composed of a body except the drain region.

Cell Device Stack Structure

Hereinafter, the structure of the nonvolatile memory cell device stack according to the first embodiment of the present invention will be described in detail. The nonvolatile memory cell device stack according to the first embodiment of the present invention is characterized in that the above-described stacked nonvolatile memory cell devices are stacked on the semiconductor substrate 1 so that the cell devices generally have a stack structure. The stacked nonvolatile memory cell stack having the above-mentioned characteristics includes a semiconductor substrate 1, a control electrode 8 formed in the form of a vertical column on the surface of the semiconductor substrate, between the control electrode and the semiconductor substrate. An insulating film 12 to be formed, gate stacks 5, 6 and 7 formed on the side of the control electrode, a first insulating film 9 formed as a layer on the side of the gate stack, and a layer formed on the side of the gate stack The semiconductor region 11 and the source and drain regions 13 are provided. The semiconductor region 11 and the first insulating layer 9 are formed in layers in alternating sides of the gate stack. The stacked nonvolatile memory cell device stack having the above-described configuration includes the cell devices similar to the number of layers of the semiconductor region formed along the vertical direction, and each cell device includes the control electrode, the gate stack, and the first insulating film as described above. And a semiconductor region.

The control electrode 8 is formed in the form of a vertical column on the surface of the semiconductor substrate, and the insulating interlayers 4 between the control electrodes are formed on the first side formed in the y direction and the second side opposite to the side of the control electrode. The gate stack 14 is formed on the third side surface formed along the x direction and the fourth side surface opposite thereto.

Cell string structure

The nonvolatile memory cell string according to the first exemplary embodiment of the present invention, which is composed of the above-described stacked nonvolatile memory cell elements, has a plurality of stacked nonvolatile memory cell elements having a plurality of floating bodies arranged in a row, and ends of the connected cell elements. And at least one switching element (not shown in FIG. 1) for selecting the cell string. The control electrodes of each cell element and the switching elements are electrically insulated by the insulating film 4 between the control electrodes of the adjacent cell element or switching element and the control electrode.

The switching element may be formed of the same component as the cell element of the cell stack, and the switching element may be implemented with a gate insulating layer composed of one or multiple insulating layers instead of the gate stack that is a component of the cell element. When the insulating layer is implemented in multiple layers, the layers adjacent to each other may be formed of materials having different band gaps.

A plurality of cell elements are arranged in a row to form a cell string. The first insulating layer 9 of each cell element is horizontally connected to the first insulating layer of an adjacent cell element, and the semiconductor region 11 is different from each other. The control electrodes 8, which are vertically connected to each other of the adjacent cell elements in the layer, are formed to be electrically isolated from each other by the insulating film 4 between the control electrodes.

As described above, the nonvolatile memory cell string stack according to the present invention may be implemented by stacking a nonvolatile memory cell string including a plurality of nonvolatile memory cell elements and switching elements arranged in a row in three dimensions.

Cell String Stack Structure

Non-volatile memory cell stacks according to the first embodiment of the present invention having the above-described configuration is arranged in a line along the y-axis direction of FIG. Form a string stack. In the non-volatile memory cell string stack according to the present invention, a plurality of cell strings are sequentially stacked on the semiconductor substrate 1, and each cell string includes a plurality of non-volatile memory cell elements and the connected cell elements. It is arranged at the end and consists of at least one or more switching elements (not shown in FIG. 1) for selecting the cell string. Accordingly, the cell elements and the switching elements forming the nonvolatile memory cell string according to the first embodiment of the present invention are all formed in a stack structure. The control electrodes of each cell element and the switching elements are electrically insulated by the insulating film 4 between the control electrodes of the adjacent cell element or switching element and the control electrode.

The semiconductor region 11 in each cell string of the cell string stack is operated as a floating body by not being connected to the upper electrode or the substrate electrode. The parasitic channel is not generated because the insulating layers are separated between the cell strings formed in the stack. However, in the erase operation, a GIDL may be generated in the source / drain region formed to overlap the end of the channel length direction of the control electrode 8 to perform the erase operation. Detailed description is given in the cell device structure.

As described above, the nonvolatile memory cell string stack according to the present invention may be implemented by stacking a nonvolatile memory cell string including a plurality of nonvolatile memory cell elements and switching elements arranged in a row in three dimensions.

Cell Array Structure

FIG. 1B is a plan view illustrating a portion of a nonvolatile memory cell string stack array according to a first embodiment of the present invention. The area indicated by the dashed-dotted line in FIG. 1B is shown in FIG. 1A as a three-dimensional perspective view. In FIG. 1 (b), the regions shown in gray above and below represent the word lines 15 to be formed later, passing over the control electrodes 8 arranged in a direction crossing the cell string direction (y direction). Accordingly, electrical contact can be made to the control electrode 8 below. The word line 15 indicated in the following figures is described as mentioned above.

In the nonvolatile memory cell string stack array according to the first embodiment of the present invention, a plurality of cell string stacks are arranged side by side, and each cell string stack has a plurality of cell strings stacked on a semiconductor substrate. Non-volatile cell devices are arranged in series and have switching elements at the ends of the cell devices.

The cell string stack array arranges the gate stack and the control electrode on portions of both sides of the semiconductor region of the cell string stack adjacent to each other, so that the semiconductor region can be shared by the adjacent cell string stacks as a body. The cell string stack array forms a gate stack and a semiconductor region on opposite sides of the control electrode so that adjacent cell string stacks share the control electrode.

As shown in FIG. 1, when adjacent cell string stacks commonly use the semiconductor region 11, the source and drain regions may be formed on both sides of the semiconductor region 11 to be in contact with each other. For example, when 0 V is applied to the control electrode 8 and the current is read in order to grasp the state of the cell indicated by the broken line in FIG. 1A, the semiconductor region 11 is disposed to face the opposite side. The control electrodes 8 may be applied with a voltage lower than the threshold voltage of the eraser state to turn off all cell devices so that the semiconductor region may be shared without any problem.

A nonvolatile memory cell string including a plurality of nonvolatile memory cell elements and switching elements arranged in a row may be stacked in three dimensions to form a cell string stack, and the stack may be arranged in an array to form a cell string stack array. When the cell string stacks are arranged in a cell string stack array, the control electrodes and the semiconductor regions may be alternately disposed in a direction crossing the direction in which the cell strings are elongated, and may be arranged to be shared. In FIG. 1 showing the structure of the present invention, such an array is shown.

Second embodiment

2 is a perspective view and a plan view illustrating a nonvolatile memory cell string stack array according to a second embodiment of the present invention. Referring to FIG. 2, the cell string stack array according to the second embodiment is partially similar to that of the first embodiment, but additionally includes a third insulating film 16 between semiconductor regions of the adjacent cell string stack, so as to be adjacent to each other. The cell string stacks share only the control electrode 8 and do not share the semiconductor region 11. In arranging the cell string stack in a cell string stack array, the control electrode 8 and the semiconductor region 11 are alternately arranged in a direction crossing the direction in which the cell string is formed to elongate. The third insulating film 16 is further disposed between the semiconductor region 11 and the semiconductor region 11 so that the semiconductor region 11 is not shared.

Therefore, in the first embodiment, since the cell string stacks adjacent to each other share both the control electrode 8 and the semiconductor region 11, the area occupied by one cell is 2F ² . Since the stack shares only the control electrodes, the area occupied by one cell is 4F ² , which is twice as large as that of the first embodiment. Unlike the structure of the first embodiment, cell devices are formed only on one side of the semiconductor region 11 formed horizontally to implement a cell device stack, a cell string, a cell string stack, and a cell string stack array.

The remaining components are the same as those in the first embodiment, and thus redundant descriptions are omitted.

Third embodiment

3 is a perspective view and a plan view illustrating a structure of a nonvolatile memory cell string stack array according to a third embodiment of the present invention. Referring to FIG. 3, the cell string stack array according to the third embodiment is characterized in that cell string stacks adjacent to each other share only the semiconductor region 11 and do not share the control electrode 8. Accordingly, the cell string stack array according to the third embodiment further includes a third insulating film 16 between adjacent control electrodes 8 such that adjacent cell string stacks share only a semiconductor region and not control electrodes. . In arranging the cell string stack in a cell string stack array, the control electrode 8 and the semiconductor region 11 are alternately arranged in a direction crossing the direction in which the cell string is formed to elongate. The third insulating film 16 is disposed between the control electrode 8 and the adjacent control electrode 8 so that the silver is shared and the control electrode 8 is not shared.

Since the array structure according to the first embodiment shares both the control electrode 8 and the semiconductor region 11, the area occupied by one cell is 2F ^2, but the array structure according to the third embodiment has one cell. The occupied area doubles to 4F ² . In addition, compared with the array structure according to the first embodiment, the cell elements of the third embodiment have cell elements formed on only one side of the control electrode 8 formed vertically, such that the cell element stack, cell string, cell string stack, cell string Implement a stack array. The features of all the remaining components are the same as those of the first embodiment.

4 is a plan view illustrating a modification to the nonvolatile memory cell string stack array according to the third embodiment. Referring to FIG. 4, the cell string stack array is similar to the third embodiment, but differs from the structure of the third embodiment in that a gate stack is not formed between the control electrode 8 and the third insulating film 16. .

5 is a perspective view illustrating other embodiments of a nonvolatile memory cell device stack, a cell string stack, and a string stack array according to the present invention. Referring to FIG. 5A, a fifth insulating film 25 is formed on the semiconductor substrate 1, and a stack structure according to the first embodiment is formed on the fifth insulating film 25. That is, in the structure according to the first to third embodiments described above, the fifth insulating film 25 is further provided on the semiconductor substrate.

Referring to FIG. 5B, the charge storage node 6 is formed to be limited to a region where the control electrode 8 and the semiconductor region 11 of each cell element overlap each other. All other structural features are the same as those of the first embodiment.

6 shows a slightly modified structure of the present invention. Basically, as shown in FIG. 1, the cell string stacks are arranged in an array so that both the control electrode 8 and the semiconductor region 11 are shared. Therefore, the area occupied by one cell element is 2F ² . The difference from the structure shown in FIG. 1 is that the width of the semiconductor region 11 is formed differently along the cell string direction (or the channel length direction or the y axis direction). In FIG. 6, the channel is formed by overlapping the control electrode 8 on both side surfaces of the semiconductor region 11. FIG. 7 shows the semiconductor region 11 that varies in width along the channel length direction as shown in FIG. 6. Everything is the same as in FIG. 6 except that the channel region of the cell element is formed on both sides of the narrow semiconductor region 11 region.

FIG. 8 illustrates a structure in which the width of the semiconductor region 11 is changed in the channel length direction as shown in FIG. 6. The difference is that the width of the semiconductor region 11 changes linearly and smoothly in the channel length direction. The control electrode 8 formed on both sides of the wide body has a feature that can easily control the channel by the structural effect.

FIG. 9 illustrates a portion of the semiconductor region 11 in which a channel is formed along the channel length direction in the present invention. Of course, various shapes may be possible, but only three of them are shown. 9 (b) and 9 (c) show an example in which the body width is different in the channel length direction as mentioned in FIGS. 6, 7, and 8.

Figure 10 shows a portion of a cross section for an array of cell string stacks of the present invention. 1 is a cross-sectional view taken along the control electrode 8 arranged in the x direction. In FIG. 10A, both side edges of the semiconductor region 11 are formed to have an angle, and in FIG. 10B, they are rounded. In order to improve durability of the cell device, it is preferable that the edge shape of the semiconductor region 11 is rounded. In particular, referring to FIGS. 10A and 10B, the gate stack 14 and the control electrode 8 surround part of side edges of the semiconductor region. This structure has the feature that the electric field can be concentrated from the control electrode 8, and the operation voltage for the program or eraser can be greatly reduced. Unlike (a) and (b) of FIG. 10, FIG. 10C illustrates a structure in which the side edge of the semiconductor region is not surrounded by the gate stack 14 or the control electrode 8.

FIG. 11 is a plan view and a vertical cross-sectional view showing an edge of a cell string stack array in which six semiconductor regions 11 are formed. In particular, FIG. 11 shows how a contact window for electrical contact can be formed in a layered semiconductor region 11 at the edge of the array structure. First, referring to FIG. 11A, it can be seen that the width of the semiconductor region 11 is formed in the cell string stack array part differently according to the channel length direction. In addition, the control electrode 8 may be formed on both side surfaces of the narrow region of the semiconductor region 11. A rectangular area indicated by a broken line in the left area of FIG. 11A indicates a first contact window to be formed in the future. These contact windows may be formed with metal lines or semiconductor wires connected to bit lines or ground connected to both ends of the cell string. In FIG. 11, for example, six semiconductor regions 11 are formed, and six cell strings are stacked to form a cell string stack. Therefore, in FIG. 11A, six first contact windows 17 are formed in each cell string stack. Looking at a certain layer fixedly, a plurality of cell elements are arranged in the channel length direction opposite to each other on both sides of the semiconductor region. That is, in the semiconductor region 11 formed long in the cell string direction or the channel length direction, two cell strings are formed and they share the first contact window 17 formed at the edge of the cell string. Through such sharing, the structure of the present invention improves the degree of integration. In FIG. 11A, three cell devices are shown in each cell string, and the cell device located on the leftmost side may be used as the switching device. FIG. 11B is a cross-sectional view taken along line X-X 'in FIG. 11A. The semiconductor region 11 and the first insulating film 9 are alternately formed in layers. According to the present invention, a cell string composed of stacked nonvolatile memory cell elements having the above-described structure is operated by floating the body of the cell element.

 The source / drain of the switching element formed at the end of the cell string or the source / drain of the cell element is formed at the side of the semiconductor region 11. The region except for the source / drain region in the semiconductor region 11 is called a 'body', and is doped with impurities of a different type from the source / drain. The semiconductor region 11 is generally formed in the form of “┗━┛” or “━━”, and has a type such as a source / drain at both the “┗” shaped upper edge or “━” shaped both edge regions. When the impurity region is further formed and an electrode is formed through the first contact window 17, the body formed in the semiconductor region 11 is floated. The semiconductor region 11 having a "-----" shape may be formed in the uppermost semiconductor region 11.

On the other hand, in the cell string consisting of stacked nonvolatile memory cell elements having the above-described structure, a technical scheme that can be connected without floating the body of the cell element is as follows. In a cell string consisting of stacked non-volatile memory cell elements, an edge or an upper edge of a "┗" shape on either side of the semiconductor region 11 formed entirely in a "┗━┛" or "━━" shape. By forming an electrode through the first contact window without additionally forming an impurity region of the type such as source / drain on one of both edges of the “shape, the body is not floating.

In FIG. 11B, the cell string stack forms an edge shape of the semiconductor regions 10 formed as a multilayer in a “로” or “━” shape, and has an upper surface or A first contact window may be formed at both edge regions of the "-" shape, and the first contact window may be connected to the metal or semiconductor wiring.

12 is a diagram prepared to show that the memory structure of the present invention can be integrated in a substrate like a MOS device. Also, the structure of the first contact window 17 described in FIG. 11 is clearly shown. In the memory structure of the present invention, an impurity of a type such as doping of a source / drain of a cell element may be injected into the first contact window 17 to ensure memory operation. As mentioned in the description of FIG. 1, a source / drain may be formed in a semiconductor region which is not formed to overlap with the control electrode among the side surfaces of the semiconductor region formed of the layer with the gate stack interposed therebetween. The cell string or the cell string stack or the cell string stack array requires a peripheral circuit for driving a memory and the like, and may be integrated on the same substrate as a MOS device for configuring the peripheral circuit. An MOS device is shown as an example on the left side of FIG. 12. The MOS device includes a gate electrode 22, a gate insulating film 21, a source / drain 19, 20, and an insulating insulating film 23, and is formed on the semiconductor substrate 1. The source / drain 19, 20 of the MOS device is distinct from the source / drain of the memory cell device. The contact window for the MOS device is indicated by a second contact window 18 and may be implemented in a different process than the first contact window 17.

FIG. 13 is the same as the structure of FIG. 12, but additionally includes a first well 2 and a second well 3 in a region where a nonvolatile memory array is formed. In order to facilitate operation of the cell string stack array, the semiconductor substrate may include a first well different from a doping type of the semiconductor substrate, or further include a second well different from the first well and a doping type. Can be. The remaining components are as in FIG.

Hereinafter, a process step of manufacturing a stacked memory cell string stack array according to a first embodiment of the present invention will be described with reference to FIG. 14. 14 shows the main process steps involved in fabricating a stacked nonvolatile memory according to the present invention. In order to clearly show the manufacturing process, the structure of the top of the stack array structure is cut and described accordingly.

First, referring to FIG. 14A, the sacrificial semiconductor layer and the semiconductor layer are alternately formed on the semiconductor substrate 1, and the semiconductor layer and the sacrificial semiconductor layer are made of materials having different etching rates. In addition, the sacrificial semiconductor region may be oxidized faster under the same conditions than the semiconductor layer. For example, when wet oxidation is performed with the semiconductor layer made of silicon and the sacrificial semiconductor layer made of SiGe, the SiGe is oxidized much faster.

On the other hand, step (a) is performed on the single crystal semiconductor substrate 1 to form the sacrificial semiconductor layer and the semiconductor layer in epitaxial form, or to form a fifth insulating film on the semiconductor substrate 1, The first semiconductor layer and the second semiconductor layer may be formed on the formed insulating layer. Before the step (a) is performed, a sixth insulating film is formed on the semiconductor substrate, the sixth insulating film in the region where the memory array is to be formed is removed, and the exposed semiconductor substrate 1 is selectively etched, but the edge of the memory array region is removed. The portion may be etched in an 'undercut' shape and implemented in the process of step (a) to form the alternating sacrificial semiconductor layer and the semiconductor layer so that the surface is aligned in the undercut region.

Next, referring to FIG. 14B, a trench is formed by etching from the surface of the resultant product of step (a) to the surface of the semiconductor substrate 1.

Next, referring to FIG. 14C, the side surfaces of the sacrificial semiconductor layer and the semiconductor layer exposed through the trench forming step are etched, but the side surfaces of the sacrificial semiconductor layer are more etched using an etch rate difference.

Next, referring to FIG. 14D, the etched sacrificial semiconductor layer is oxidized to form an insulating film, and an insulating film is filled in the side surface to complete the first insulating film. Alternatively, the sacrificial semiconductor layer may be completely etched, and the first insulating layer may be filled in the completely etched region to be completed. Next, a gate stack 14 is formed in the trench region.

Next, referring to FIG. 14E, a control electrode 8 is formed on the surface of the gate stack 14, and an unnecessary control electrode 8 is etched through photolithography to reveal a gate stack ( 14) Remove.

Next, referring to FIG. 14F, a first source / drain region 13 is formed on a side surface of the exposed semiconductor layer, and control is performed in a space in which unnecessary control electrodes 8 and gate stacks 14 are removed. The inter-electrode insulating film 4 is filled. Forming the source and drain regions of step (f) can be implemented by ion implantation in a plasma atmosphere.

After step (f), an insulating film may be formed, a contact window may be formed where a contact hole is needed, and a metal layer for wiring may be sequentially formed.

FIG. 15 illustrates an epitaxial process for growing the sacrificial semiconductor layer and the semiconductor layer and a process step performed before the same as described with reference to FIG. 14A. First, referring to FIG. 15A, after forming and patterning a sixth insulating layer 26 on the semiconductor substrate 1, the semiconductor substrate 1 exposed by using the patterned sixth insulating layer 26 as a mask. Selectively etch). At this time, in the case of isotropic etching of the semiconductor substrate, etching is performed not only in the vertical direction but also in the horizontal direction to form an "undercut" as shown in FIG. 15A. In this case, the surface treatment is performed to improve the quality of the epitaxial layer, and the sacrificial semiconductor layer and the semiconductor layer are alternately grown as shown in FIG. 14A to realize a shape as shown in FIG. 14A. do.

FIG. 16 is a cross-sectional view illustrating exemplary structures of the undercut that may be implemented in the selective etching process of the semiconductor substrate 1 mentioned in FIG. 15.

Although the present invention has been described above with reference to preferred embodiments thereof, this is merely an example and is not intended to limit the present invention, and those skilled in the art do not depart from the essential characteristics of the present invention. It will be appreciated that various modifications and applications which are not illustrated above in the scope are possible. And differences relating to such modifications and applications should be construed as being included in the scope of the invention as defined in the appended claims.

The technique according to the present invention can be widely used in the field of highly integrated stacked NAND nonvolatile memory.

1 is a view showing a part of a cell string stack array using stacked nonvolatile memory cell devices according to a first embodiment of the present invention, where (a) is a three-dimensional perspective view and (b) is a structure of (a) This is a plan view of the.

FIG. 2 is a view showing a part of a cell string stack array using stacked nonvolatile memory cell devices according to a second embodiment of the present invention, where (a) is a three-dimensional perspective view and (b) is a structure of (a) This is a plan view of the.

3 is a view showing a part of a cell string stack array using stacked nonvolatile memory cell devices according to a third embodiment of the present invention, where (a) is a three-dimensional perspective view and (b) is a structure of (a) This is a plan view of the.

4 is a plan view of a modified cell string stack array for the stacked nonvolatile memory of the present invention.

FIG. 5 is a three-dimensional perspective view of a portion of a modified cell string stack array for a stacked nonvolatile memory of the present invention, and FIG. (A) shows the structure of the present invention on the fifth insulating film. Shows a case where the charge storage node is separated for each cell element in the structure of the present invention.

FIG. 6 illustrates a portion of a modified cell string stack array for a stacked nonvolatile memory of the present invention, where (a) is a three-dimensional perspective view and (b) is a plan view of the structure of (a).

7 and 8 are plan views showing a part of a cell string stack array using stacked nonvolatile memory cell devices of the present invention.

9 is a diagram illustrating a semiconductor region and a first semiconductor region in a structure of a nonvolatile memory cell string according to the present invention.

10 is a vertical cross-sectional view of a portion of a cell string stack using a stacked nonvolatile memory cell device according to the present invention.

11 is a view showing the edge of the cell string stack array according to the present invention, (a) is a plan view, (b) is a cross-sectional view taken along the X-X 'direction of (a).

12 and 13 illustrate edges of a cell string stack array according to the present invention, (a) is a plan view, and (b) is a cross-sectional view taken along the line X-X 'of (a).

14 is a cross-sectional view sequentially illustrating the manufacturing process steps of the cell string stack array according to the first embodiment of the present invention.

15 is a cross-sectional view illustrating a step of forming an undercut at an edge and alternately growing first and second semiconductor layers in the structure to implement a structure of a cell string stack array according to the present invention.

16 is a cross-sectional view illustrating various types of undercut structures that may be used in the structure of a cell string stack array according to the present invention.

Description of the Related Art

1 semiconductor substrate 2 first well

3: second well 4: insulating film between control electrodes

5 tunneling insulating layer 6 storage node

7: blocking insulating film 8: control electrode

9: first insulating film 10: sacrificial semiconductor layer

11 semiconductor region 12 second insulating film

13 source and drain region 14 gate stack

15 word line 16: third insulating film

17: first contact window 18: second contact window

19, 20: source and drain regions of MOS devices

21 gate insulating film 22 gate electrode

23: insulating film 24: fourth insulating film

25: fifth insulating film 26: sixth insulating film

Claims (26)

Semiconductor substrates; A control electrode formed on the surface of the semiconductor substrate in the form of a vertical pillar; An insulating film formed between the control electrode and the semiconductor substrate; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; And A semiconductor region formed on a side of the gate stack; And the first insulating layer and the semiconductor region are formed adjacent to each other and formed on one side of the gate stack, and a floating body is formed in the semiconductor region. device. Semiconductor substrates; A control electrode formed on the surface of the semiconductor substrate in the form of a vertical pillar; An insulating film formed between the control electrode and the semiconductor substrate; A gate stack formed on a side of the control electrode; A first insulating film formed of a plurality of layers on a side of the gate stack; And A semiconductor region formed of a plurality of layers on a side of the gate stack; And the first insulating layer and the semiconductor region are alternately formed on the same side of the gate stack. The nonvolatile memory cell device stack of claim 2, wherein the nonvolatile memory cell device stack further comprises a source and a drain region formed in a semiconductor region of the side surface of the semiconductor region that does not overlap the control electrode. The nonvolatile memory cell device of claim 2, wherein the nonvolatile memory cell device stack further comprises a fifth insulating film formed on the semiconductor substrate, and the control electrode and the first insulating film are formed on the fifth insulating film. stack. The nonvolatile memory cell device of claim 2, wherein the gate stack is formed of a tunneling insulating film, a charge storage node, and a control insulating film, or comprises a tunneling insulating film and a charge storage node, or a charge storage node and a blocking insulating film. stack. The non-volatile memory cell stack of claim 2, wherein the gate stack and the control electrode formed on the side of the semiconductor region partially surround the side of the semiconductor region. Semiconductor substrates; And A plurality of nonvolatile memory cell strings stacked on the semiconductor substrate; The nonvolatile memory cell string is A plurality of nonvolatile memory cell elements arranged in a row; And And a switching device connected to ends of the nonvolatile memory cell devices. The nonvolatile memory cell device, Control electrode; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; And A semiconductor region formed on a side of the gate stack; The first insulating film of each cell element is horizontally connected with the first insulating film of the adjacent cell element in the same layer, and the semiconductor region is horizontally connected with the semiconductor region of the adjacent cell element in the same layer, and the control of each cell element And the electrodes are electrically isolated from each other by an insulating film between control electrodes. The method of claim 7, wherein the switching element is configured to be the same as the cell element, or the same as the cell element, a gate insulating film made of one or multiple insulating films in place of the gate stack, the gate insulating film is a multi-layer The non-volatile memory cell string stack, wherein the layers adjacent to each other are formed of materials having different band gaps when the insulating layer is implemented. The nonvolatile memory cell string stack of claim 7, wherein the nonvolatile memory cell string stack further comprises a source and a drain region formed in a semiconductor region of the side surface of the semiconductor region that does not overlap the control electrode. 8. The nonvolatile memory as claimed in claim 7, wherein the width of the semiconductor region formed on the side of the semiconductor region overlapping with the control electrode is formed to be wider or narrower than the width of the semiconductor region formed without overlapping with the control electrode. Cell string stack. The nonvolatile memory cell of claim 7, wherein the gate stack includes a tunneling insulating layer, a charge storing node, and a blocking insulating layer, a tunneling insulating layer, a charge storing node, or a charge storing node and a blocking insulating layer. String stack. 12. The nonvolatile memory cell of claim 11, wherein the charge storage node of the cell element is formed only at a side portion of the semiconductor region overlapping the control electrode of the cell element or is formed at the entire side of the semiconductor region of each cell element. String stack. The semiconductor region of claim 7, wherein the semiconductor region of each cell device comprises a source / drain region and a body doped with impurities of a different type from the source / drain region. And forming an impurity region of the same type as a source / drain region in both edge regions of the semiconductor region of the cell string and forming an electrode through a first contact window, thereby floating the body of the semiconductor region. Nonvolatile Memory Cell String Stack. The semiconductor region of claim 7, wherein the semiconductor region of each cell device comprises a source / drain region and a body doped with impurities of a different type from the source / drain region. Forming an electrode through the first contact window without additionally forming an impurity region of the same type as a source / drain region at one of both edges of the semiconductor region of the cell string so that the body of the semiconductor region does not float. A nonvolatile memory cell string stack. The cell string stack of claim 7, wherein the cell string stack forms an edge shape of the semiconductor regions in a “┗” or “━” shape, and a top surface of the “┗” shape structure or both edges of a “━” shape. And forming a first contact window in said region, said first contact window being connected to a metal or semiconductor wiring. 10. A nonvolatile memory cell string stack array comprising a plurality of nonvolatile memory cell string stacks arranged in a row. The nonvolatile memory cell string stack is Semiconductor substrates; And A plurality of nonvolatile memory cell strings stacked on the semiconductor substrate; The nonvolatile memory cell string is A plurality of nonvolatile memory cell elements arranged in a row; And And a switching device connected to ends of the nonvolatile memory cell devices. The nonvolatile memory cell device, Control electrode; A gate stack formed on a side of the control electrode; A first insulating film formed on a side of the gate stack; A semiconductor region formed on a side of the gate stack; The first insulating film of each cell element is horizontally connected with the first insulating film of the adjacent cell element, and the semiconductor region is horizontally connected with the semiconductor region of the adjacent cell element, and the control electrode of each cell element is an insulating film between control electrodes. And a non-volatile memory cell string stack array formed electrically isolated from each other. 17. The non-volatile memory cell string stack array of claim 16, wherein the cell string stack shares a control electrode and a semiconductor region with an adjacent cell string stack. The method of claim 16, wherein the nonvolatile memory cell string stack array further includes a third insulating layer between semiconductor regions of a cell string stack adjacent to each other, such that adjacent cell string stacks share only a control electrode without sharing a semiconductor region. And a non-volatile memory cell string stack array. The cell string stacks of claim 16, wherein the control electrode and the semiconductor region are alternately arranged in a direction crossing the direction in which the cell string is elongated, wherein the semiconductor regions of adjacent cell string stacks are shared and the control electrode is shared. And a third insulating film between the control electrodes adjacent to each other so as not to be adjacent to each other. The non-volatile memory cell string stack array of claim 16, wherein the cell device further comprises a source and a drain region formed in a semiconductor region of the side of the semiconductor region that does not overlap the control electrode. 17. The non-volatile memory cell string stack array of claim 16, wherein the cell string stack array is integrated on the same substrate as a peripheral circuit for driving a memory. The method of claim 16, wherein the cell string stack array further comprises a first well on the semiconductor substrate that is different from the doping type of the semiconductor substrate, or wherein the first well and the first well and the doping type are different. And a second second well. A method of manufacturing a memory cell string stack in which cell strings including a plurality of cell elements and switching elements formed on a semiconductor substrate are stacked in multiple layers, (a) alternately forming a sacrificial semiconductor layer and a semiconductor layer formed of materials having different etching rates on the semiconductor substrate; (b) forming a trench by etching from the surface of the product of step (a) to the surface of the semiconductor substrate; (c) etching side surfaces of the sacrificial semiconductor layer and the semiconductor layer exposed through the trench forming step, but etching more of the side surface of the sacrificial semiconductor layer by using an etching rate difference; (d) oxidizing the sacrificial semiconductor layer to form an insulating film, filling an insulating film on a side thereof to complete a first insulating film, and forming a gate stack in the trench region; (e) forming a control electrode on the surface of the gate stack, removing unnecessary control electrodes and removing the exposed gate stack; (f) forming source and drain regions on the exposed side of the semiconductor layer, and filling an insulating film between control electrodes in a space from which unnecessary control electrodes and gate stacks are removed; (g) forming an insulating film, forming a contact window where a contact hole is needed, and sequentially forming a metal layer for wiring; Nonvolatile memory cell string stack manufacturing method comprising a. The method of claim 23, wherein the step (a) is performed on a single crystal semiconductor substrate to form the sacrificial semiconductor layer and the semiconductor layer in epitaxial form, or after forming a fifth insulating layer on the semiconductor substrate. 5. The method of claim 1, wherein the sacrificial semiconductor layer and the semiconductor layer are formed on an insulating film. 24. The method of claim 23, wherein before the step (a) is performed, forming a sixth insulating film on the surface of the semiconductor substrate, removing the sixth insulating film in the region where the memory array is to be formed, and then selectively etching the exposed semiconductor substrate. Etching the edge portion of the memory array region in an 'undercut' shape, and the non-volatile, characterized in that the sacrificial semiconductor layer and the semiconductor layer formed in the process of the step (a) so that the surface is aligned in the undercut region A method of manufacturing a memory cell string stack. 24. The method of claim 23, wherein the forming of the source and drain regions of step (f) comprises ion implantation in a plasma atmosphere.

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