KR101329586B1 - 3d vertical type memory cell string with weighting electrode, memory array using the same and fabrication method thereof - Google Patents

Abstract

The present invention relates to a vertical semiconductor memory cell string, a memory array using the same, and a method of manufacturing the same. More particularly, the present invention relates to a neighboring body sharing a body for improving performance and miniaturization of MOS-based flash memory devices. A three-dimensional vertical memory cell string having a floating gate type weight electrode, a tunneling insulating layer, and a weight control electrode between cell stacks, a memory array using the same, and a method of manufacturing the same.

Description

3D vertical memory cell string with weighted electrodes, memory array using same and method for manufacturing the same {3D VERTICAL TYPE MEMORY CELL STRING WITH WEIGHTING ELECTRODE, MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF}

The present invention relates to a vertical semiconductor memory cell string, a memory array using the same, and a method of manufacturing the same.

Recently, flash memory is expected to grow rapidly due to the rapid increase in demand in home appliances and portable electronic devices.

The density of NAND flash memory is required to increase with the development of IT technology. However, the degree of integration of NAND flash memory is largely determined by the degree of integration of cell devices. In recent years, gate lengths of cell devices have been reduced to 50 nm or less, and memory capacities have reached tens of gigabytes. However, the NAND flash device of the flat channel structure having the conductive floating gate has faced the limitation that the gate length can no longer be reduced because of the short channel effect. In addition, the demand for multi-level cells is increasing, and the short channel effect due to the reduction of the device may increase or decrease the threshold voltage in implementing the multi-level cell, which may be very limited or impossible to use. The technology having a gate length of 50 nm or less requires a high-cost equipment or process, which also increases manufacturing costs. In the future, the gate length should be continuously reduced to improve the density, and an alternative to cope with this situation should be considered.

In order to increase the integration of cell devices, a SONOS-based flash memory cell using an insulating storage node such as a nitride film is considered instead of a memory cell having a conventional floating gate. In addition, nano-floating gate memory (NFGM) cells using nano dots or nano crystals as charge storage nodes have been considered. When a memory cell is implemented by using a charge storage node such as a nitride film or a nano dot in a conventional flat channel structure, the miniaturization characteristic is improved as compared with the case of using a floating gate of conductive polysilicon. However, even when the improved charge storage node is used, the characteristics of the gate length of 40 nm or less are greatly reduced due to the short channel effect, and thus the limit of the reduction is impossible.

SONOS or TANOS (TaN-AlO-SiN-) with an asymmetric source / drain structure in a flat channel structure to suppress short channel effects and reduce threshold voltages caused by reducing the gate length of the cell device to 40 nm or less. Oxide-Si) cell devices have been published by Samsung Electronics (see Non-Patent Document 1). The impurity doped region corresponding to the source / drain is formed on one side of the gate of the cell device, but the impurity doped region for the source / drain is not formed on the other side. This structure suppresses short channel effects by forming a virtual source / drain into an inversion layer formed by fringing electric fields from neighboring control electrodes instead of impurity doping. Although the reduction characteristics are improved compared to SONOS cell devices having flat channels that form both sources / drains by conventional impurity doping, one of the two sources / drains of the cell devices is formed to overlap the control electrode. Short channel effects are still seen at the following channel lengths and ultimately face the miniaturization limitation of flat channel structures.

In order to reduce the short channel effect occurring in the conventional flat channel structure, a flash device structure in which a channel is recessed and a conductive floating gate is applied as a storage node has been announced by Samsung Electronics (see Non-Patent Document 2). Even by this, in order to improve the degree of integration, the width of the recessed area should be reduced, and in this case, there is a problem that the nonuniformity of the device increases.

One way to increase the degree of integration while reducing manufacturing costs is to form cell elements or cell strings vertically. In Patent Document 1, a trench is formed, and a tunneling insulating film, a floating gate, a blocking insulating film, and a control electrode are sequentially formed in the trench to implement the trench. Sources were formed in the semiconductor region near the bottom of the trench, and drains in the semiconductor region near the top of the trench, respectively. In this structure, only one vertical cell element is formed to substantially increase the memory capacity, and due to structural problems, it is impossible to form multiple cell elements vertically.

In a recently published paper (Non-Patent Document 3), in order to solve the problem of Patent Document 1, several cells and two switching elements are arranged vertically. According to this, although the degree of integration can be increased, the write time is rather slow, and in particular, the erase time is slow. In addition, the retention characteristics are poor. In the manufacturing process, an insulating layer is formed for electrical insulation between control layers of various layers stacked vertically. In this case, when forming a via via of a circle to form a string, it is necessary to continue to etch alternately between the control electrode made of polysilicon and the insulating layer made of silicon oxide. It can be difficult and time consuming. In addition, in order to form a tube-shaped body vertically, only the bottom of the via hole may be etched, leaving a gate insulating film or a blocking insulating film formed on the vertical sidewall of the via hole so that the bottom is electrically connected to the semiconductor region. At this time, the insulating film on the sidewall may be damaged, which may result in deterioration of the memory cell characteristics and, in turn, lower the yield. The electrical contact and wiring of the source region formed at the bottom of the via hole from the upper surface of the via hole may require a large mask as well as overcoming a large step. In short, there are many difficulties in terms of fairness.

In order to solve the problems of the existing devices as described above, the present inventor has developed a new integrated high-performance / high performance flash memory device has been filed a Korean patent application of the following Patent Document 2. According to this, there is a significant improvement in the degree of integration by forming a plurality of electrically insulated multi-layer electrode stack in the vertically formed cell string, cross-talk in the body constituting the cell string in operation is a problem, In particular, there is a problem in that electrical interference occurs between semiconductor bodies formed in adjacent stack structures during a read operation, thereby increasing distribution of cell characteristics.

In addition, there is a problem that a threshold voltage distribution may occur even between cell stacks formed on both sidewalls of the same electrode stack.

Patent Document 1: US Patent No. 5,739,567 (Highly compact memory device with nonvolatile vertical transistor memory cell) 1998. 4. 14. Patent Document 2: Korean Unexamined Patent Publication No. 10-2010-0119625 (Highly Integrated Vertical Semiconductor Memory Cell String, Cell String Array, and Manufacturing Method Thereof) 2010. 11. 10.

[Non-Patent Document 1] K. T. Park et al., A 64-cell NAND flash memory with asymmetric S / D structure for sub-40 nm technology and beyond, in Technical Digest of Symposium on VLSI Technology, p. 24, 2006 [Non-Patent Document 2] S.-P. Sim et al., Full 3-dimensional NOR flash cell with recessed channel and cylindrical floating gate-A scaling direction for 65 nm and beyond, in Technical Digest of Symposium on VLSI Technology, p. 22, 2006 [Non-Patent Document 3] Y. Fukuzumi et al., Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory, IEDM Tech. Dig., Pp. 449-452, 2007

The present invention was devised to solve the above-mentioned problems of the prior art, and is capable of being highly integrated but between neighboring cell stacks that share a body to eliminate cross-talk or interference between bodies in a cell string. Positioning the weighting electrode in the form of a floating gate and interposing a tunneling insulating film on each weighting electrode to solve the problem of threshold voltage distribution between the cell stacks by weighting by various charge injection and emission to the weighting electrode. An object of the present invention is to provide a three-dimensional vertical memory cell string in which charge injection electrodes are formed, a memory array using the same, and a method of manufacturing the same.

In order to achieve the above object, the three-dimensional vertical memory cell string according to the present invention is spaced at a predetermined distance in the horizontal first direction by one or more trenches on the semiconductor substrate, and the insulating film and the conductive material layer are alternately repeatedly stacked in the vertical direction. Two or more electrode stacks formed; A gate insulating layer stack including upper and sidewalls of the electrode stacks and a charge storage layer formed on the spaced spaces of the substrate; A semiconductor body formed on the gate insulating film stack; At least one weighted electrode formed on each of the trenches with a first isolation insulating layer interposed therebetween on the semiconductor body; A second isolation insulating film electrically separating the respective weighted electrodes in a horizontal second direction perpendicular to the horizontal first direction; A tunneling insulating layer formed on each of the weighted electrodes; And a weight control electrode formed on the tunneling insulating film.

In addition, the memory array according to the present invention is characterized in that two or more vertical memory cell strings are formed spaced apart at regular intervals in the horizontal second direction.

The method of manufacturing a 3D vertical memory cell string may include: a first step of depositing a sacrificial semiconductor layer and an electrode semiconductor layer alternately n times on a semiconductor substrate and then depositing a hard mask material layer; Patterning the hard mask material layer and etching the n-stacked sacrificial semiconductor layer and the electrode semiconductor layer based thereon to form one or more trenches spaced apart from each other in a horizontal first direction to expose the semiconductor substrate; ; A third step of selectively etching the sacrificial semiconductor layer exposed by each of the trenches and filling two or more electrode stacks with a predetermined insulating material to form an insulating film on the etched portion; Forming a gate insulating layer stack including a charge storage layer on each of the trenches and surrounding the electrode stack; A fifth step of depositing and patterning a semiconductor layer on the gate insulating layer stack to form a semiconductor body; A sixth step of covering the semiconductor body to form a first isolation insulating layer on each of the trenches; Depositing and etching a conductive material over an entire surface of the semiconductor substrate to form a weight electrode on the first isolation insulating layer in each of the trenches; And an eighth step of etching the weight electrode at a predetermined interval in a horizontal second direction perpendicular to the horizontal first direction and filling the weighted electrode with an insulating film to form a second separation insulating film.

According to the above configuration, the vertical memory cell string according to the present invention includes a weighting electrode in the form of a floating gate, a tunneling insulating layer, and a weight control electrode between adjacent cell stacks that share a body, thereby preventing interference between bodies. -talk or interference) can be eliminated, and the problem of threshold voltage distribution between cell stacks can be solved by weighting various charge injection and emission to the weight electrode.

In addition, the vertical memory cell string according to the present invention can arbitrarily adjust the amount of charge stored in the weighted electrode, thereby arbitrarily adjusting the threshold voltage of the programmed or erased cell for each cell stack sharing the weighted electrode. It also offers the possibility to increase.

Meanwhile, in the method of manufacturing a vertical memory cell string according to the present invention, a gate insulating layer stack, a semiconductor body, and a first isolation insulating layer are sequentially formed to surround each electrode stack, and then the weighted electrodes are filled, and then the weighted electrodes are moved in the respective trench directions. By etching at a predetermined interval to fill the second isolation insulating film, the second mask may be realized with a minimum mask.

1 is a plan view of a portion of a memory array using a cell string according to the present invention, in order to show the internal structure, a horizontal cut of the uppermost conductive material layer in a three-dimensional stack structure formed in the z-axis direction perpendicular to the x and y planes. One cross section.
FIG. 2 is a cross-sectional view similar to FIG. 1, but shows that the first insulating film is formed without cutting the first insulating film among the cell stacks in the y-axis direction among the gate insulating film stacks.
3 and 4 are perspective views corresponding to the portion B of FIG. 1, and show a case in which the gate insulating layer stack is etched and remains in the cell strings spaced apart in the trench direction, respectively. In each drawing, for example, one cell stack includes eight switching elements and cell elements.
FIG. 5 is a perspective view similar to FIG. 3, but shows that the first insulating film / charge storage layer of the gate insulating film stack is removed so that the insulating film between each electrode is in contact with the second insulating film.
FIG. 6 is a perspective view similar to FIG. 5, but showing that memory cells and both sources / drains of the first and second selection transistors are formed as a doping layer in the semiconductor body.
FIG. 7 is a perspective view similar to FIG. 3, but shows that a buried electrode is formed along the bottom of the trench in the semiconductor substrate.
FIG. 8 is a perspective view similar to FIG. 3, but shows that a buried insulating film is formed between the bottom insulating film and trench bottom of each electrode stack and the semiconductor substrate.
9 to 12 are cross-sectional views each showing a cross section of a cell string structure according to the present invention, and a power supply symbol for showing the operation of a cell in a flash memory array using the same is illustrated by way of example.
13 through 16 are cross-sectional views of main parts illustrating various embodiments of a cell string structure according to the present invention.
17 is a diagram illustrating a memory array using a cell string according to an exemplary embodiment of the present invention, in which (a) is a cross-sectional view of a horizontally cut top conductive material layer in a vertically stacked stack structure, and (b) is an electrode stack in (a). It is sectional drawing cut perpendicularly along the XX 'line of longitudinal direction. As an example in FIG. 17B, six conductive layers (first and second electrodes and control electrodes) are shown.
18 is an exemplary view showing that a cell string or a memory array and a MOS device for driving the same may be integrated into a peripheral circuit according to the present invention, (a) is one layout (top view), and (b) is (a) ) Is a vertical cross-sectional view taken along the line YY 'of the electrode stack in the longitudinal direction.
19 is a layout (top view) illustrating a specific example of a structure, a contact, and a wiring of the memory array according to the present invention.
20 to 25 are process perspective views illustrating a manufacturing process of a cell string or a memory array using the same according to the present invention.
26 and 27 are patterned and etched with an insulating film on a semiconductor substrate to form a contact (contact) of each electrode on the upper side of the electrode stack during the manufacturing process of a cell string or a memory array using the same according to the present invention A process cross-sectional view showing an example in which a sacrificial semiconductor layer and an electrode semiconductor layer are alternately grown as epitaxial layers.
28 and 29 are cross-sectional views illustrating another example of an edge etching profile of a semiconductor substrate etched in an etching process of the semiconductor substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a plan view of a portion of a memory array using a cell string according to the present invention, and is a cross-sectional view of the topmost conductive material layer horizontally cut in a vertically stacked stack structure to show an internal structure.

In FIG. 1, region A represents an area occupied by one cell in a cell stack structure, and region B represents a portion of a memory array composed of 2 × 3 cell stacks to describe the structure of each of the embodiments described below. Area C represents a portion of one vertical cell string consisting of 6 x 1 cell stacks, and 'F', shown at the top right, represents the minimum line width in a given technique.

As used herein, the term "cell stack" refers to an electrode stack to be described later, a gate insulating layer stack on one sidewall of the electrode stack, and a vertical stacked structure of memory cell elements formed in a semiconductor body, and a "cell string" is a region in FIG. 1. As shown in C, the cell stacks are connected to one semiconductor body in the x direction, and the “memory array using a cell string” refers to a cell string (eg, region C) formed at a predetermined interval in the y direction as shown in FIG. 1. .

Hereinafter, an embodiment according to the present invention will be largely divided into a 3D vertical memory cell string, a memory array using the cell string, and a method of manufacturing the cell string.

[The structure of the cell string Example ]

First, the structure of the memory cell string according to the present invention basically has a horizontal direction (eg, x direction: horizontal first direction) to form one or more trenches on the semiconductor substrate 1, as shown in region C of FIG. 1 and FIG. 3. Spaced apart by a predetermined distance, and the insulating films 7 and 9 and the conductive material layers 8, 10 and 11 are alternately stacked n times in a vertical direction (for example, directions perpendicular to the x and y directions, respectively) In FIG. 3, for example, two or more electrode stacks 40 are formed after the eight repeated laminations and the insulating layers 12 are stacked one more time. A gate insulating layer stack 50 including an upper and sidewalls of each electrode stack and a charge storage layer 3 formed on the spaced space of the substrate (that is, surrounding each trench between the two or more electrode stacks); A semiconductor body 5 formed on the gate insulating film stack; At least one weight electrode 27 formed on each of the trenches with a first isolation insulating film 6 interposed therebetween on the semiconductor body 5; A second isolation insulating film 28 electrically separating the respective weighted electrodes in the respective trench directions (eg, the y-direction: the second horizontal direction); A tunneling insulating layer 29 formed on each of the weight electrodes; And a weight control electrode 30 formed on the tunneling insulating film.

Here, the semiconductor body, the gate insulating layer stack, and any conductive material layer of the electrode stack constitute one cell element having a vertical channel, and as a result, a plurality of cell elements are vertically stacked along one side of the electrode stack 40. This results in a cell stack .

The cell stacks formed along the sidewalls of the electrode stacks 40 are cells in which the weight electrodes 27 are formed to adjust the threshold voltage while eliminating electrical cross-talk of the semiconductor bodies 5 facing each trench in the x direction. Will form a string.

In addition, the periphery of the weight electrode 27 is completely surrounded by an insulating film, that is, both sides of the bottom of the weight electrode 27 and the x direction are the first separation insulating films 6, and both sides of the y direction, which are the respective trench directions, An upper portion of the second isolation insulating layer 28 is surrounded by the tunneling insulating layer 29 so that the weight electrode 27 functions as a floating electrode.

The weight electrode 27 is formed of a conductive material to remove electrical cross-talk of the semiconductor body 5 facing each other, as well as charges (eg, electrons) through the weight control electrode 30 and the tunneling insulating layer 29. Since it is possible to inject or withdraw, it is possible to adjust the threshold voltage independently giving different weightings for each cell stack sharing the weight electrode 27.

In order to inject electrons into the weight electrode 27, for example, a channel is not formed in the semiconductor body 5 in each of the uppermost conductive material layers 11 of the both electrode stacks 40 sharing the weight electrode 27. A voltage (as described below, a voltage at which the select transistor at the top of each stack is to be turned off) is applied, and a high positive voltage is applied to the remaining conductive material layers 8 and 10 and a low negative voltage is applied to the weight control electrode 30. The voltage of (ie, the negative voltage with a large absolute value) can be applied respectively. In this case, a positive coupling voltage is induced in the weight electrode 27 so that electrons are injected into the weight electrode 27 from the weight control electrode 30 through the tunneling insulating layer 29. At this time, the magnitude of the coupling voltage of the weight electrode 27 can be easily adjusted by applying a voltage of all or a part of the conductive material layers 8 and 10 serving as gates of each stack cell, and as a result, the weight electrode The amount of electron inflow (weighting degree) into (27) can be adjusted easily.

On the contrary, in order to extract the electrons injected into the weight electrode 27 to the weight control electrode 30, for example, all the conductive material layers 8, 10, and 11 of both electrode stacks 40 sharing the weight electrode 27. In the semiconductor body 5, a voltage such that a channel is formed in the semiconductor body 5, and a low negative voltage (i.e., a negative voltage having a large absolute value) is applied to the semiconductor body 5a (an impurity doped body contact portion) on each electrode stack. In addition, a high amount of voltage may be applied to the weight control electrode 30, respectively.

In addition, although the first isolation insulating film 6, the second isolation insulating film 28, and the tunneling insulating film 29 may all be formed of an oxide film, the first isolation insulating film 6 may be easily coupled to the weight electrode 27. It is preferable to form a high dielectric constant film (for example, an aluminum oxide film) so that it can be formed.

On the other hand, all the conductive material layers 8, 10, and 11 of each electrode stack 40 may be gates of memory cells, but the lowermost conductive material layer 8 and the uppermost conductive layer may be used to facilitate independent access of each cell. The material layer 11 serves as a gate of the first and second selection transistors (switching elements) for selecting a line (for example, a bit line or a ground line) connected to the semiconductor body 5a on the electrode stack. The remaining conductive material layers 10 in between may be used as gates of the memory cells.

Of course, only the uppermost conductive material layer 11 of each electrode stack 40 serves as a gate of the selection transistor (switching element), and the conductive material layers 8 and 10 under the selection transistor gate 11 are all memory. It may be used as each gate of cell elements.

Between each element (memory element or switching element) gated by the conductive material layers 8, 10, 11 of each electrode stack 40 is formed in the semiconductor body 5 as a fringing field of a neighboring gate. A virtual source / drain may be formed as an inversion layer or an accumulation layer, and as shown in FIG. 3, the uppermost conductive material layer 11 above the uppermost conductive material layer 11 to be electrically connected to an external line. Except for the semiconductor body 5a, a high concentration doping layer may not be formed.

In this case, a predetermined voltage is applied to the lowermost conductive material layer 8 and / or the semiconductor substrate 1 of each electrode stack 40 between the cell stacks sharing the weight electrodes 27 at the bottom of each trench. It is electrically connected to each other by an inversion layer or an accumulation layer formed by the inversion layer.

The gate insulating layer stack 50 may be formed of two or more insulating layers including the charge storage layer 3, which may be variously implemented as described below. It is preferable to form the first insulating film 2 / the charge storage layer 3 / the second insulating film 4 from each electrode stack 40 in order, and all of them are cut to a size similar to that of the semiconductor body 5.

This is because it is possible to fundamentally eliminate an error in cell operation due to the charge stored in the charge storage layer 3 spreading to the cells of the neighboring cell string depending on the surrounding environment such as heat.

In addition, the charge storage layer 3 may be any material as long as it can store electrons or holes injected into a channel or a gate, but the injected charge is difficult to move around, and there are many traps that can store charge. Nitride and the like are preferable.

The cell string structure according to the present embodiment may be variously embodied according to or partially changing the basic structure. Examples of the cell string structure will be described below with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view similar to that of FIG. 1, but the first insulating film 6 may be formed without cutting the first insulating film 2a between the cell stacks in the y-axis direction among the gate insulating film stacks 50a. Shows.

4 is a perspective view similar to that of FIG. 3, but the first insulating film 2a / the charge storage layer 3a / the second insulating film 4a constituting the gate insulating film stack 50b are shared with the neighboring cell strings in an array configuration. Shows that it can be.

FIG. 5 is a perspective view similar to that of FIG. 3, but in order to fundamentally eliminate errors in cell operation due to movement of charges stored in the charge storage layer 3 to upper and lower cells connected to the same cell string, the insulating film 7 of each electrode stack is shown. 9 shows that the first insulating film 2b / charge storage layer 3b of the gate insulating film stack 50c can be removed at all.

In this case, unlike the previous embodiment, the charge storage layer 3b is formed only at the intersection of the conductive material layers 8a, 10a, 11a and the semiconductor body 5 of each electrode stack 40a, and is isolated from neighboring cells. Therefore, there is an advantage that can be formed of a conductive material (for example, metal). However, for this purpose, the manufacturing process is changed compared to the structure of FIG. 3 and some additional process is required.

Fig. 6 is a perspective view similar to that of Fig. 5, but includes a semiconductor body 5c between each element (memory element or switching element) gated by conductive material layers 8a, 10a and 11a of each electrode stack 40a. It is shown that the semiconductor body 5b between the cell stacks sharing the weight electrode 27 of the trench bottom may form a source / drain with a high concentration of doping layer as usual.

In this way, the semiconductor bodies 5b and 5c between the elements are reinforced with an inversion layer or an accumulation layer generated by a fringing field such as a neighboring gate, thereby providing electrical connection between the elements. The resistance can be reduced, which can be mainly used when the gap between the conductive material layers 8a, 10a, 11a of the electrode stack 40a, that is, the thickness of the insulating films 7, 9 is large.

7 is a perspective view similar to that of FIG. 3, but in order to reduce the resistance of the semiconductor body 5, a buried electrode 14 is further formed in the semiconductor substrate 1 along the bottom of each trench so that voltage can be applied. It can be configured.

8 is a perspective view similar to that of FIG. 3, but a buried insulating film 15 is further formed between the lowermost insulating film 7 of each electrode stack 40 and the bottom of each trench and the semiconductor substrate 1 to form a semiconductor substrate ( It can be configured to prevent leakage current to 1).

In addition, an embodiment of the configuration for suppressing the movement between the upper and lower cells on the same cell string in which the charge stored in the charge storage layer 3 is further shown in FIGS. 14 to 16.

FIG. 13 is a diagram illustrating main parts of the cell stack structure of FIG. 3, and in contrast, looks at FIGS. 14 to 16.

14 to 16, unlike FIG. 13, the insulating film 9b of each electrode stack is smaller than the conductive material layers 10 and 10a so that grooves are formed between the conductive material layers and the grooves are formed. As a result, at least the first insulating film / charge storage layer of the gate insulating film stack is formed to be bent, thereby showing that charge transfer between the upper and lower cells can be suppressed. The same applies to FIGS. 10 and 12.

As shown in FIGS. 14 and 15, when the conductive material layer protrudes on both sides of each electrode stack, unlike in FIG. 13, the first insulating films 2d and 2f are formed as tunneling insulating films in the gate insulating film stacks 50e and 50f. The second insulating films 4e and 4f preferably operate to function as blocking insulating films.

This is because the electric field is concentrated on the conductive material layer side than the channel side formed on the semiconductor bodies 5 'and 5' 'by the edges or rounded surfaces of the conductive material layers 10 and 10a protruding to both sides of each electrode stack. This is because charge injection or removal from the conductive material layers 10 and 10a to the charge storage layers 3d and 3f is easy.

14 and 15, the semiconductor bodies 5 ′ and 5 ″ may also be bent along the grooves, but the grooves may be formed as the gate insulating film stack or as shown in FIG. 16. Filled with a separate insulating material 28a to planarize the side and then form the semiconductor body 5, thereby storing or removing unwanted charges between the semiconductor body 5 and the charge storage layer 3d between the cells. Can be suppressed.

FIG. 15 shows only the rounded surface of the conductive material layer 10a protruding to both sides of each electrode stack, but is filled with a gate insulating film stack or a separate insulating material 28a as shown in FIG. The semiconductor body 5 can then be formed.

A reference numeral 28a of FIG. 16 may be a separate insulating material, but may be formed of the same material as the second insulating film 4 that is part of the gate insulating film stack 50g.

Meanwhile, the first isolation insulating layer 6 formed on the semiconductor body may be formed by filling the grooves as shown in FIG. 14 or bent together as shown in FIG. 15.

Lastly, as shown in FIGS. 3 to 10, a third insulating film 12 may be further formed on the uppermost conductive material layer 11 of each electrode stack, but as shown in FIGS. 11 and 12, the third insulating film 12 may be formed. The gate insulating film stack 50d may be formed immediately.

Here, when the third insulating film 12 is further formed, the upper source / drain of the second transistor having the uppermost conductive material layer 11 as the gate is like the upper portion 5a of each electrode stack for contacting the semiconductor body. It is preferable to form a high concentration impurity doping layer.

In the semiconductor body formed near the bottom of each trench, buried electrodes 14-1 and 14-2 are further formed on the semiconductor substrate 1 as shown in Fig. 9, or as shown in Figs. The impurity doped layer 5b may be formed to increase conductivity of the semiconductor body. Of course, without forming a buried electrode or an impurity doped layer, as described above, by applying a voltage to the semiconductor substrate 1 itself or by applying a fringing electric field of the lowermost conductive material layer 8, The conductivity can be improved.

In addition, the conductive material layer constituting the electrode stack may be a metal as well as a semiconductor material (eg, crystalline silicon, amorphous silicon, polysilicon, etc.) doped with a high concentration of impurities.

In accordance with the technical spirit of the embodiment of the structure of the cell string, it is shown that the configuration can be implemented in a variety of different shapes of the configuration, in order to distinguish between the different objects in the accompanying drawings to refer to the reference numerals when some shapes are changed. Since differently given, it will be understood by those skilled in the art that the present invention pertains to the above-described contents and drawings, and thus, various embodiments that can be modified can be fully understood and practiced.

Next, referring to FIG. 9, the operation of the cell string according to the present invention will be briefly described.

First, a predetermined voltage is applied to a semiconductor body (for example, 5a-1 and 5a-2) formed on an upper side of the neighboring electrode stack and does not share the weight electrode 27, that is, to each electrode stack. After confirming that a difference occurs in the turn-on voltage of the device to be formed, where a threshold voltage difference occurs, a predetermined charge (electron or hole) is injected into the corresponding weight electrode 27 (charge to the weighted electrode). Method of injecting is as described above), the threshold voltage of the cell stack sharing the weight electrode 27 is shifted and adjusted in a batch.

In addition, in order to program a specific cell (cell 1 in a circle indicated by a broken line at the second electrode stack for convenience), the conductive material layer (control electrode of a specific cell) passing through the specific cell is first shared as in the conventional method. Precharge is performed to all cell channels. This precharge step is to prevent the unwanted cell from being programmed when the high voltage required for the program is applied to all cells shared through the control electrode of the specific cell.

The method of programming the specific cell described later is an example and more combinations may be possible. For convenience, in FIG. 9, the semiconductor body 5a-2 formed on the top of the center electrode stack is connected to the ground, and the semiconductor bodies 5a-1, 5a-3 formed on the left and right of the electrode stack are formed of bit lines. Assume that it is connected to line). As described above, all select transistors (switching elements) are turned off while all cells are precharged. In this state, the first selection transistor located at the bottom of the center electrode stack is turned on, and 0 V or a specific voltage is applied to the semiconductor body at the top of the right electrode stack (the electrode stack on the right side of the center electrode stack) and at the same time, the right electrode Turn on the first and second select transistors in the stack and turn off the first and second select transistors in the left electrode stack (the electrode stack on the left of the center electrode stack). In this state, when the program voltage V _PGM is applied to the control electrode of the specific cell and the pass voltage V _PASS is applied to each control electrode (conductive material layer) of the remaining cells in the center electrode stack, A carrier is supplied from the semiconductor body connected to the bit line on the upper part of the electrode stack to the body of the specific cell element, and only the specific cell can be programmed by the program voltage V _PGM . In this case, the cells on the opposite side of the cell sharing the control electrode (cell 2 in a broken line in FIG. 9: Cell 2) are floated in the precharged state because all of the select transistors in the adjacent left electrode stack are turned off. Will not be programmed.

On the other hand, in order to read the specific cell, for example, in FIG. 9, 0 V is applied to the body on the top of the center electrode stack, and the first and second selection transistors in the same stack are turned on. The two select transistors in the left electrode stack are turned off and the select transistors in the right electrode stack are turned on. The read voltage V _READ is applied to the semiconductor body formed on the upper side of the right electrode stack to read the current flowing from the bit line at the top of the right electrode stack to the ground line at the top of the center electrode stack to check the state of the specific cell. I can figure it out.

Incidentally, in order to explain the erasing operation of the cell, for convenience of explanation, it is assumed that the structure of each cell element operates as an n-type MOSFET. In order to erase all the cells at once, a negative voltage V _ERS is applied to each control electrode of all the corresponding cells. In the first or second selection transistors (switching elements) located in each cell stack, holes are generated by generating gate induced drain leakage (GIDL) in a region where the n + source / drain not adjacent to the cell elements overlaps with the gate electrode of the selection transistor. . To this end, for example, a negative voltage is applied to the gate electrode of the second selection transistor and a positive voltage is applied to the n + source / drain. The generated holes flow into the body of the cell devices, enter the charge storage layer by applying a negative voltage (V _ERS ) to the control electrode of each cell device, and consequently the electrons stored in the charge storage layer of each cell device. Is removed from the body and erased in batches.

In addition, it is also possible to selectively delete a specific cell. For the purpose of explanation, it is assumed that the structure of each cell element acts as an n-type MOSFET, and for example, the original cell (Cell 1) indicated by a broken line in FIG. 9 is identified. The process of selectively erasing into cells will be described. With all of the select transistors off, a voltage of 0 V or an arbitrary voltage is applied to the bit line connected to the top of the right electrode stack adjacent to the specific cell, all of the select transistors of the right electrode stack are turned on, and the left electrode stack is selected. Turn off all transistors In the second selection transistor (switching element) on the upper side of the right electrode stack, holes are generated by GIDL only in the region where the n + source / drain and gate electrode overlapping the cell element do not overlap to provide holes, and the specific cell is provided. Only the first selection transistor at the bottom of the center electrode stack is turned on so that the generated holes reach the body of the specific cell. In this state, a negative voltage V _ERS is applied to the control electrode of the specific cell, and holes generated by GIDL are supplied to the body of the specific cell in the cell element control electrodes (conductive material layers) of the center electrode stack. When voltage is applied as much as possible, it is possible to selectively erase only the specific cell.

Of course, in the operation of the cell string, since the first selection transistor at the bottom of each electrode stack may be used as a cell element, only one second selection transistor may be used as a switching element on the top of each electrode stack.

As described above, according to the cell string structure according to the present embodiment, the weight electrode 27 can eliminate the interference between the body in the cell string, and furthermore, through the weight control electrode 30, the appropriate charge is transferred to the weight electrode. By implanting in (27), the memory capacity can be increased by solving the threshold voltage distribution problem between cell stacks or by arbitrarily changing the threshold voltages of the cell elements. In addition, the area occupied by the cells in the three-dimensional stack structure can be reduced to about 4F ² or less, which is about half that of 6F ² (see FIG. 1), and since the structure is vertically stacked, there is an advantage in that it can be highly integrated.

[A Memory Array Structure Using Cell Strings] Example ]

Next, an embodiment of a memory array structure using the cell string will be described with reference to the accompanying drawings.

As shown in FIG. 1, the memory array structure according to the present exemplary embodiment has a structure in which a plurality of cell strings (regions C) formed in the x direction are spaced at regular intervals in the y direction in each trench direction.

In this case, the plurality of cell strings spaced apart from each other in the y direction may be formed to have independent electrode stacks, but may be configured to be shared with the neighboring cell strings as shown in FIG. 1. However, the plurality of cell strings may be electrically separated from neighboring cell strings with the second isolation insulating layer 28 interposed therebetween in the y direction.

Further, when the charge storage layer of the gate insulating film stack of each cell string is formed of an insulating film with a trap like a nitride film, as shown in FIG. 4, the gate insulating film stack 50b may also be configured to be shared with a neighboring cell string. .

Each electrode stack shared with the neighboring cell string may be formed by horizontally protruding a portion for contacting each conductive material layer (a portion in which a contact hole is formed, hereinafter referred to as a “contact portion”), or FIG. 17B. As shown in 42, each conductive material layer 8 and 10 may be formed to be extended and stacked to protrude upward from each electrode stack 40. The electrode layer contact hole 16 ′ is formed on the contact portion 42 formed as described above with reference to FIG. 18B, and the electrode layer contact 16 is formed by filling a conductive material in the electrode layer contact hole 16 ′. .

19 shows a specific example of the structure, contacts, and wiring of the memory array according to the present embodiment.

As shown in FIG. 19, a memory array is formed in such a manner that the weight electrode 27 is separated by the first isolation insulating layer 28 and the electrode stack 40 is shared with the neighboring cell strings. The semiconductor body of each cell string is formed. 5a is alternately connected to a bit line ("B") and a ground line ("G": ground line, 31) through body contacts 36 and 37 formed on the top of each electrode stack. do.

The wirings in which the semiconductor body 5a of each cell string is alternately connected to the bit line 33 and the ground line 31 may be implemented in various ways. However, as shown in FIG. 19, the body contacts of the neighboring cell strings may be implemented. (36, 37) are connected to the bit line 33 and the ground line 31 alternately wired in an oblique direction, respectively (see bold solid line), and the body contacts of the cell strings located at both edges are in the diagonal direction in another layer. It may be connected to the bit line 33 and the ground line 31 alternately wired in the direction crossing with each other (see the thick dashed line).

In addition, although wiring for electrical connection of each electrode layer (conductive material layer: 8, 10, 11) constituting the electrode stack 40 may be implemented in various ways, as shown in FIG. Each electrode layer contact 16, 35, 35 ′ is formed at the left end, and even electrode stacks are formed with the electrode layer contacts 16, 35, 35 ′ at the right end, and each electrode layer contact 16, 35, 35 ') to be connected to the word line 32 and the first and second select lines 39', which are wired in an independent form for each electrode stack. Can be.

Meanwhile, as shown in FIG. 3, the weight control electrode 30 is formed on the weight electrode 27 with the tunneling insulating layer 29 interposed therebetween, and as shown in FIG. 19, neighbors of the same cell string are provided. It is preferable to wire so as not to be electrically connected to the weight control electrode formed on one trench. This is because independent weighting is possible between the weighting electrodes 27 formed on neighboring trenches of the same cell string (ie, by varying the amount of charge injected), so that threshold voltages between the cell stacks formed on both sides of each electrode stack can be independently controlled. to be.

The wiring for connecting the weight control electrode 30 may be various, but as shown in FIG. 19, the wires may be connected in the same diagonal direction along the wiring directions of the bit line 33 and the ground line 31. have. Since the detailed wiring method of the weight control electrode 30 is the same as the wiring method for connecting the semiconductor body 5a of each cell string to the bit line 33 and the ground line 31, a description thereof will be omitted. do.

When wiring for connecting the weight control electrode 30 as described above, the number of wirings is equal to the number of cell strings (see F1 to F8 in Fig. 19).

In FIG. 19, for example, each electrode stack 40 includes six electrode layers (conductive material layers: 8, 10, and 11). Among the six electrode layers, the lowermost electrode layer 8 and the uppermost electrode layer 11 The gate electrodes of the first and second selection transistors are respectively used, and the remaining four electrode layers 10 are used as control electrodes of the cell elements. However, if necessary, the first selection transistor formed at the lowermost end of each electrode stack may be used as a cell device.

In addition, the memory array according to the present exemplary embodiment may be formed on one semiconductor substrate together with driving elements formed in a portion etched at a predetermined depth on the semiconductor substrate and formed in an unetched region. As described above, each electrode stack, each weight electrode, and each vertical memory cell string are formed by etching to the semiconductor substrate 1 to a predetermined depth, and the left or / and right side of each electrode stack or each weight electrode is formed. Therefore, it is possible to integrate together drive elements that neighbor the electrical connection to them.

FIG. 18 is an exemplary view illustrating that an array driving device may be integrated with a memory array on the same semiconductor substrate. FIG. 18B is a cross-sectional view taken along a line YY ′ of the electrode stack in (a). , Reference numerals 18 and 18 ', which are not described, are the source / drain 22 and 23 contacts of the driving element and the contact hole therefor, respectively, 19 is the gate of the driving element, 20 The interlayer insulating film formed during the silver wiring process, 21 is a gate insulating film of the driving element, and 24 is an insulating insulating film.

[Method of manufacturing cell string Example ]

Hereinafter, a description will be given of an embodiment of a method of manufacturing the cell string. However, for convenience of understanding, a portion of a memory array using the cell string, that is, a process step in which region B is manufactured in FIG. It demonstrates with reference to 20-30.

First, as shown in FIG. 20, the sacrificial semiconductor layer 25 and the electrode semiconductor layers 8 ′, 10 ′, and 11 ′ are alternately n times (as shown in FIG. 21) on the prepared semiconductor substrate 1. After lamination, the hard mask material layer 12 'is deposited to form a lamination stack 40' (first step).

Here, the semiconductor substrate 1 alternately n times the sacrificial semiconductor layer 25 and the electrode semiconductor layers 8 ', 10', 11 'by an epitaxial method by using a single crystal semiconductor substrate. In Fig. 21, the lamination is preferably performed 7 times.

However, since the electrode semiconductor layers 8 ', 10' and 11 'are intended to form gate electrodes rather than bodies of cell elements or switching elements (e.g., first and second transistors), the epitaxial single crystal It is not necessary to form the semiconductor layer. In addition, the electrode semiconductor layers 8 ', 10', and 11 'are simply replaced with a conductive material layer, and an insulating film for isolating the conductive material layer may replace the sacrificial semiconductor layer 25.

Therefore, in order to manufacture the structure as shown in FIG. 8, the buried insulating film 15 is first formed on the semiconductor substrate 1, and the sacrificial semiconductor layer 25 is formed on the buried insulating film 15 in an amorphous or polycrystalline state. The electrode semiconductor layers 8 ', 10', and 11 'may be alternately formed n times.

In addition, since the sacrificial semiconductor layer 25 is removed by selective etching in a subsequent process and filled with an insulating layer, the sacrificial semiconductor layer 25 should have a larger etching rate than that of the electrode semiconductor layers 8 ', 10', and 11 '. For example, when the semiconductor substrate 1 and the electrode semiconductor layers 8 ', 10', and 11 'are made of silicon, the sacrificial semiconductor layer 25 may be silicon germanium.

Since the electrode semiconductor layers 8 ', 10', and 11 'must be conductive, dopants with a high concentration of n-type or p-type impurities at each layer deposition in this step, or, After the selective etching of the sacrificial semiconductor layer 25, the impurities may be doped into the electrode semiconductor layers 8, 10, 11 exposed by plasma doping or the like.

Meanwhile, before the first step, as shown in FIG. 26, an insulating film is formed on the semiconductor substrate 1 by etching and forming an insulating film mask 26 at a portion where a contact of each electrode stack is to be formed; And etching the corresponding region of the semiconductor substrate 1 on which the electrode stacks are to be formed using the insulating layer mask 26 in an under cut shape, and then proceeding to the first step. Referring to FIG. 27, a stack stack 40 ′ having a portion where a contact of each electrode stack is to be formed at a height corresponding to an upper portion of the electrode stack may be formed.

At this time, the etching of the semiconductor substrate 1 under the insulating film mask 26 in the form of an under cut (under cut) is caused by the isotropic etching, the etching profile of the substrate edge according to the degree of isotropic etching is only Rather, the reference numeral 1a of FIG. 28 and the reference numeral 1b of FIG. 29 may be variously generated.

In addition, the hard mask material layer 12 ′ may be any material that may remain when the sacrificial semiconductor layer 25 and the electrode semiconductor layers 8 ′, 10 ′, and 11 ′ are etched. It may be a nitride film.

Next, as shown in FIG. 22, the hard mask material layer 12 ′ is patterned and the n-th sacrificial semiconductor layer 25 and the electrode semiconductor layers 8 ′, 10 ′, and 11 ′ are etched based thereon. Thereby forming one or more trenches to expose the semiconductor substrate 1 (second step).

Next, as shown in FIG. 22, the sacrificial semiconductor layer 25 exposed by each of the trenches is selectively etched, and two or more electrode stacks 40 are filled with an insulating material for forming the insulating films 7 and 9 in the etched portion. Form (third step). In this step, the semiconductor substrate 1 is etched using the insulating film mask 26, and the first and second steps are performed. Then, in the structure as shown in FIG. 27, the exposed sacrificial semiconductor layer 25 is selectively etched. When the etched portion is filled with an insulating material for forming the insulating layers 7 and 9, the insulating layer mask 26 may support the structure from which the sacrificial semiconductor layer 25 is removed.

In this case, as described above, before the sacrificial semiconductor layer 25 is selectively etched and filled with a predetermined insulating material to form the insulating layers 7 and 9, the electrode semiconductor layer 8 exposed by plasma doping or the like is formed. , 10, 11) may be doped with a high concentration of n-type or p-type impurities.

In addition, the selective etching of the sacrificial semiconductor layer 25 and the process of forming the insulating layers 7 and 9 may be sequentially performed in order to partially support the electrode semiconductor layers 8, 10 and 11.

In other words, after the trench is formed in the second step, an additional photolithography process is performed to block part of the stack structure with a predetermined mask material and to open part of the stack structure, and to sequentially select and etch the sacrificial semiconductor layer 25 partly. It is preferable to advance the formation process (7, 9).

Thereafter, as shown in FIG. 23, the gate insulating layer stack 50 including the charge storage layer 3 is formed on each trench surrounding the electrode stack 40 (fourth step).

In this case, the gate insulating film stack 50 surrounds the electrode stack separated by the trench, and the first insulating film 2, the charge storage layer 3, and the second insulating film 4 are sequentially formed.

Here, the first insulating film 2 may be formed of a thermal oxide film, and the charge storage layer 3 may be formed of an insulating material having a charge trap layer, such as nitride.

Next, as shown in FIG. 23, the semiconductor body 5 is formed by depositing and patterning a semiconductor layer on the gate insulating film stack 50 at a predetermined thickness (a fifth step).

In this case, as shown in FIG. 23, the semiconductor layers may be patterned and spaced apart in a trench direction (y direction), thereby distinguishing the bodies 5 of each cell string and implementing a memory array.

Here, when the gate insulating film stack 50 is further etched using the semiconductor body 5 of each cell string as a mask, as shown in FIG. 3, the gate insulating film stack 50 between neighboring cell strings can be removed. do.

Next, as shown in FIG. 24, the first isolation insulating layer 6 is formed on each of the trenches while surrounding the semiconductor body 5 (sixth step).

The impurity ion implantation process may be further performed before or after the formation of the first isolation insulating film 6, so that the highly doped impurity doping layer 5a is formed on the semiconductor body 5 on the upper side of each electrode stack and the lower portion of each trench. , 5b).

Next, as shown in FIG. 24, the conductive material is deposited on the entire surface of the semiconductor substrate and etched to form a weight electrode 27 on the first isolation insulating layer 6 in each trench (7th step).

Next, as shown in FIG. 25, the weight electrode 27 is etched at predetermined intervals in the trench direction (y direction) and filled with an insulating film to form a second separation insulating film 28 (Eighth Step).

Subsequently, the tunneling insulating layer 29 is formed on the weight electrode 27 and the conductive material is deposited again to form the weight control electrode 30.

In addition, after the weight control electrode 30 is formed, a separate impurity ion implantation process is further performed, and a high concentration impurity doping layer is formed on the semiconductor body 5 and the weight control electrode 30 formed on each electrode stack. May be formed.

As mentioned above, although preferred embodiments of the present invention have been described, those of ordinary skill in the art may variously implement the bar, and further description thereof will be omitted.

The technique according to the present invention can be widely used in the field of NAND flash memory.

1: substrate 2: first insulating film
3: charge storage layer 4: second insulating film
5: semiconductor body 6: first isolation insulating film
7: bottommost insulating film 8: gate of first selection transistor
9: interlayer insulating film 10: conductive material layer
11: gate of second selection transistor 12: third insulating film
14: investment electrode 15: investment insulating film
16, 35, 35 ': electrode layer contact 16': contact hole
19: gate of drive element 20: insulating film for wiring
21: gate insulating film of driving element 22: source of driving element
23: drain of driving element 24: isolation insulating film
25: sacrificial semiconductor layer 26: insulating film mask
27: weight electrode 28: second separation insulating film
29 tunneling insulating film 30 weight control electrode
31: ground line 32: word line
33: bitline 36, 37: body contact
38: weight control electrode contact 39: first selection line
39 ': second selection line 40: electrode stack
50; Gate insulating film stack

Claims (31)

Two or more electrode stacks formed on the semiconductor substrate by one or more trenches spaced apart from each other in a horizontal first direction and formed by alternately stacking an insulating layer and a conductive material layer in a vertical direction;
A gate insulating layer stack including upper and sidewalls of the electrode stacks and a charge storage layer formed on the spaced spaces of the substrate;
A semiconductor body formed on the gate insulating film stack;
At least one weighted electrode formed on each of the trenches with a first isolation insulating layer interposed therebetween on the semiconductor body;
A second isolation insulating film electrically separating the respective weighted electrodes in a horizontal second direction perpendicular to the horizontal first direction;
A tunneling insulating layer formed on each of the weighted electrodes; And
And a weight control electrode formed on the tunneling insulating layer.
The method of claim 1,
And a buried electrode further formed along the bottom of each trench in the semiconductor substrate.
The method of claim 1,
And a buried insulating film formed between the lowermost insulating film of each electrode stack and the bottom of each trench and the semiconductor substrate.
The method of claim 1,
The gate insulating film stack is formed in the order of the first insulating film / charge storage layer / second insulating film from each electrode stack,
3. The three-dimensional vertical memory cell string of claim 1, wherein both the first insulating film, the charge storage layer, and the second insulating film or the charge insulating layer and the second insulating film of the gate insulating film stack are cut to the same size as the semiconductor body.
5. The method of claim 4,
And a first insulating film / charge storage layer of the gate insulating film stack is removed from the insulating film of each electrode stack.
5. The method of claim 4,
The insulating film of each electrode stack has a width smaller than that of the conductive material layer, and grooves are formed between the conductive material layers.
And at least a first insulating film / charge storage layer of the gate insulating film stack is bent along the groove.
The method according to claim 6,
And the gate insulating film stack and the semiconductor body are bent along the groove, respectively.
The method of claim 7, wherein
And a conductive material layer of each electrode stack having rounded portions protruding from the grooves.
The method according to claim 6,
And the groove is filled with an insulating material separate from the gate insulating layer stack to planarize a side surface thereof.
10. The method according to any one of claims 1 to 9,
Each of the lowermost conductive material layer and the uppermost conductive material layer of each electrode stack is a gate of a first selection transistor and a gate of a second selection transistor,
And the conductive material layers of each electrode stack between the gate of the first select transistor and the gate of the second select transistor are each gate of memory cell elements.
11. The method of claim 10,
Wherein the memory cell elements are connected to each other by an inversion layer or an accumulation layer formed in a fringing field in the semiconductor body.
11. The method of claim 10,
The memory cell elements and the first and second selection transistors each have a source / drain as an impurity doped layer in the semiconductor body.
10. The method according to any one of claims 1 to 9,
The uppermost conductive material layer of each electrode stack is a gate of a selection transistor,
And the conductive material layers of each electrode stack under the selection transistor gate are each gate of memory cell elements.
The method of claim 13,
Wherein the memory cell elements are connected to each other by an inversion layer or an accumulation layer formed in a fringing field in the semiconductor body.
The method of claim 13,
And each of the memory cell elements and the selection transistor has a source / drain formed in the semiconductor body as an impurity doping layer.
2. The memory array of claim 1, wherein two or more vertical memory cell strings are formed spaced apart from each other in the horizontal second direction.
Two or more vertical memory cell strings according to claim 1 are spaced apart at regular intervals in the horizontal second direction to form a memory array, wherein the weight electrode between adjacent cell strings is separated with the second isolation insulating layer therebetween. And a memory array.
The two or more vertical memory cell strings of claim 1 are spaced apart at regular intervals in the horizontal second direction to form a memory array by separating the weight electrodes between neighboring cell strings with the second isolation insulating film interposed therebetween. And the two or more vertical memory cell strings of claim 1 share the gate insulating film stack.
19. The method according to any one of claims 16 to 18,
And each electrode stack is stacked with at least one end of the conductive material layer so as to protrude horizontally, or is formed so as to protrude upward from the electrode stack.
The method of claim 19,
And the semiconductor body of each cell string is alternately connected to a bit line and a ground line through body contacts formed on the electrode stack.
21. The method of claim 20,
The semiconductor body of each cell string is alternately connected to a bit line and a ground line, and the cell contacts of neighboring cell strings are connected to bit lines and ground lines alternately wired in an oblique direction, respectively, and located at both edges of the cell. And the body contacts of the strings are connected to bit lines and ground lines alternately wired in directions intersecting the diagonal directions at different layers.
22. The method of claim 21,
In the wiring for electrical connection of each conductive material layer constituting the electrode stack, odd-numbered electrode stacks of each of the two or more electrode stacks have respective electrode layer contacts formed at left ends, and even-numbered electrode stacks at right ends thereof. An electrode layer contact is formed and connected to each of the word lines vertically connected to the length direction of each electrode stack through the electrode layer contacts, and to the first selection line and the second selection line, each of which is wired in an independent form for each electrode stack. And a memory array.
22. The method of claim 21,
The weight control electrode is formed for each trench of each string with the tunneling insulating layer interposed on the weight electrode, and is not electrically connected to the weight control electrode formed on a neighboring trench of the same cell string. Memory array.
24. The method of claim 23,
The wiring for connecting the weight control electrode is connected to the diagonal direction along the wiring direction of the bit line and the ground line.
25. The method of claim 24,
The number of wires for connecting the weight control electrode is the same as the number of the cell string.
17. The method of claim 16,
And the array is formed on the semiconductor substrate together with driving elements formed in a portion etched at a predetermined depth on the semiconductor substrate and formed in an unetched region.
A first step of depositing a sacrificial semiconductor layer and an electrode semiconductor layer alternately n times on a semiconductor substrate and then depositing a hard mask material layer;
Patterning the hard mask material layer and etching the n-stacked sacrificial semiconductor layer and the electrode semiconductor layer based thereon to form one or more trenches spaced apart from each other in a horizontal first direction to expose the semiconductor substrate; ;
A third step of selectively etching the sacrificial semiconductor layer exposed by each of the trenches and filling two or more electrode stacks with a predetermined insulating material to form an insulating film on the etched portion;
Forming a gate insulating layer stack including a charge storage layer on each of the trenches and surrounding the electrode stack;
A fifth step of depositing and patterning a semiconductor layer on the gate insulating layer stack to form a semiconductor body;
A sixth step of covering the semiconductor body to form a first isolation insulating layer on each of the trenches;
Depositing and etching a conductive material over an entire surface of the semiconductor substrate to form a weight electrode on the first isolation insulating layer in each of the trenches; And
And an eighth step of etching the weight electrode at a predetermined interval in a horizontal second direction perpendicular to the horizontal first direction and filling the insulating layer with an insulating film to form a second isolation insulating film. Manufacturing method.
The method of claim 27,
Depositing and etching an insulating film on the semiconductor substrate prior to the first step to form an insulating film mask at a portion where a contact of each electrode stack is to be formed; And
And etching the corresponding region of the semiconductor substrate on which the electrode stack is to be formed in an under cut shape using the insulating film mask.
29. The method of claim 27 or 28,
The sacrificial semiconductor layer and the electrode semiconductor layer of the first step may be formed in a single crystal form by epitaxial, or a buried insulating film is first formed on the semiconductor substrate and then stacked to form an amorphous or polycrystalline form. A method of manufacturing a three-dimensional vertical memory cell string, characterized in that.
30. The method of claim 29,
The electrode semiconductor layer is a semiconductor material having a lower etch rate than the sacrificial semiconductor layer, and is stacked in the first step and doped with impurities, or in the third step, the sacrificial semiconductor layer is selectively etched and then doped with impurities. A method of manufacturing a three-dimensional vertical memory cell string, characterized in that.
31. The method of claim 30,
In the third step, the selective etching of the sacrificial semiconductor layer and the insulating film forming process are sequentially performed in order to partially support the electrode semiconductor layer, the manufacturing method of the three-dimensional vertical memory cell string.

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