JP2003007721A - Semiconductor element using polycrystalline thin film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the leakage current of a semiconductor element using a polycrystalline thin film. SOLUTION: The ratio of the center line mean roughness of an insulation film surface formed on a silicon film, to the thickness of a polycrystalline thin film containing silicon as a main component, is set 0.5 or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element such as a thin film transistor used as a switching element of an image display device, and more particularly to improvement of a polycrystalline thin film used therein.

[0002]

2. Description of the Related Art Thin film transistors are used, for example, as driving elements for active matrix type liquid crystal display panels and various sensors.

Conventionally, amorphous silicon has been used for a semiconductor layer of a thin film transistor, but in recent years, development of a thin film transistor using polycrystalline silicon, which has much higher mobility than amorphous silicon, as a semiconductor layer has been actively pursued.

Various proposals have been made to improve the thin film transistor in order to improve the characteristics of the thin film transistor, and particularly to reduce the leakage current.

As a proposal for improving a polycrystalline thin film, JP-A-8-1
According to the publication, the average film thickness polycrystallized by laser irradiation is 150 to 800Å.
It is said that a silicon film having unevenness with a height difference of 100 to 700 Å on the surface has high crystallinity, and by using it, a thin film transistor having excellent characteristics can be obtained. In addition, the same publication discloses that the preferred height difference of the unevenness is 50 to 1 of the average film thickness.
It is supposed to be 00%.

It is considered that the main cause of the unevenness on the film surface is the shrinkage of the film after heating, and the difference in height between the crystallinity and the unevenness is not uniquely associated. Rather,
On the contrary, the unevenness becomes a factor that influences the electric field concentration. Therefore, a thin film transistor having satisfactory characteristics cannot be obtained by the proposal of the publication.

[0007]

As described above, when the unevenness of the upper insulating film or the metal film serving as an electrode is small as compared with the unevenness of the silicon surface caused by the improvement of the crystallinity, the convex portion of the silicon film surface is formed. In the above, there was a problem such as a decrease in breakdown voltage due to concentration of electrolysis.

Further, when the unevenness of the film surface of silicon is alleviated by coating with an insulating film or a metal film as an upper layer, the above breakdown voltage failure is remarkable.

[0009]

[Means for Solving the Problems] Insulating films to be disposed on the recesses on the silicon film surface and the upper layer, surface recesses on the metal film, and insulating films to be disposed on the projections on the silicon film surface and the upper layer, and to the gold film. The convex portions on the surface are located almost at the same position, and the film thickness distributions of the respective layers of the insulating film and the metal film are made equal in the cross section of the concave and convex portion.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

The thin film transistor is manufactured, for example, as follows.

[0012] First, as shown in FIG. 1a, is formed on a substrate 1 made of quartz or the like for example, an insulating layer 2 made of SiO _2. Next, as shown in FIG. 1b, an amorphous silicon layer 3a is formed on the insulating layer 2.

The amorphous silicon layer 3a thus formed or the layer 3a further subjected to furnace annealing or the like is irradiated with an excimer laser to polycrystallize the amorphous silicon layer 3a as shown in FIG. 1c. Convert to silicon layer 3b.

After processing the obtained polycrystalline silicon layer 3b into a predetermined shape, an insulating layer 4a is formed so as to cover the layer 3b as shown in FIG. 1d, and the gate electrode 5 is formed on the upper surface of the insulating layer 4.
After patterning a, the polycrystalline silicon layer 3b is doped with an impure impurity through the insulating layer 4a to form a source region 3c and a drain region 3d, as shown in FIG. 1e.

Next, as shown in FIG. 1f, the gate electrode 5
Offset regions 3e and 3f are formed in the source region 3c and the drain region 3d by doping using the mask processed into b. Next, after forming the insulating layer 7 so as to cover the surface of the substrate 1, the contact holes 6a, 6b and 6c are formed. A thin film transistor is obtained by forming the source electrode 8a and the drain electrode 8b.

Here, the annealing condition has a great influence on the smoothness of the surface of the obtained polycrystalline thin film. Since amorphous silicon contracts due to crystallization, stress is generated inside the thin film. The stress generated in this film causes unevenness on the surface of the thin film. This is based on a new finding that the irregularities generated on the surface of the thin film have a great influence on the characteristics of the thin film, especially the characteristics of the thin film transistor.

Specific examples of the present invention will be described below.

As an insulating layer 2 on a substrate 1 made of quartz,
S of 600 Å thickness is obtained by the atmospheric pressure CVD method under the following conditions.
An iO ₂ layer was formed.

[0019]

[Table 1]

Further, an amorphous silicon layer 3 having a thickness of 500Å was formed on the upper surface thereof by the low pressure CVD method under the following conditions.

[0021]

[Table 2]

Then, the substrate 1 is annealed in an N ₂ atmosphere at 600 ° C. for 10 to 48 hours to solid-phase grow the amorphous silicon layer 3a formed on the surface thereof, and further is irradiated with excimer laser to be polycrystallized. .

320 mJ / cm ² , 390 mJ / cm ² ,
The surface of the polycrystalline thin film obtained by annealing at an energy of 440 mJ / cm ² was observed with an atomic force microscope.
Using a Si cantilever having a tip radius of curvature of 30 nm of the probe, measurement was performed in a tapping mode in a region having a width of 5 μm. The radius of curvature of the tip of the probe is preferably 50 nm or less. The cross-section curves of the thin film after annealing are shown in Figures 2a, 2b and 2c.

In annealing at 320 mJ / cm ² , it is presumed that the undulation of the thin film surface is severe and the progress of crystallization is insufficient.

In the case of annealing at 390 mJ / cm ² , the surface of the thin film is almost flat in consideration of noise, and it is presumed that the crystallization proceeded sufficiently. According to the laser annealing, the crystal grains mainly grow on the surface irradiated with the laser. Therefore, as the crystal grain size increases, the proportion of the convex boundary region occupies decreases, so that the surface of the film becomes smoother.

In the case of annealing at 440 mJ / cm ² , the surface of the thin film is highly uneven. Since the energy required for sufficient crystallization is given, it is speculated that this undulation is due to sublimation of silicon.

[0027] were extracted arbitrary 10 points than the cross section curve and calculates the center line average roughness R _a as indicated by the following equation (1).

[0028]

[Equation 1]

Here, ˜y is an average value and L is the length of the measuring range.

As shown in FIG. 3, the value of the center line average roughness R _a of the thin film surface varies depending on the energy of the laser irradiated in the annealing treatment.

As is clear from the figure, R _a is about 390.
It becomes smaller as the energy of the laser to be irradiated increases until it reaches mJ / cm ² , but thereafter it becomes larger. That, R _a, after which decreased with the progress of crystallization, increased on the contrary extends to excessive processing. Note that when the intensity of the irradiated laser is high, _Ra increases due to sublimation of silicon.

The mobility of the silicon layer 3b polycrystallized by the annealing treatment was measured. The result is shown in FIG. As is apparent from the figure, the mobility increases as the energy of the laser to be irradiated increases until it reaches approximately 390 mJ / cm ² , but thereafter decreases. The relationship between the centerline average roughness _Ra and the mobility is shown in FIG. The larger R _{a, the} smaller the mobility. Further, FIG. 6 shows the relationship between the center line average roughness _Ra and the breakdown voltage. The smaller _Ra is, the higher the breakdown voltage is.

From these results, it is understood that the smaller the center line average roughness R _{a, the} higher the crystallinity of the polycrystalline thin film, and the higher the breakdown voltage.

However, these are expressed by the average roughness Ra. Even in the case of a polycrystalline thin film having high crystallinity, as described above, the origin of the film surface, that is, the protrusion due to the thermal contraction of silicon is observed by the excimer laser irradiation. Since the ridges are caused by the crystallinity of silicon, it is assumed that if the crystallinity is nonuniform, the ridges also exist nonuniformly in the plane (see FIG. 7).

From the above, in order to prevent the concentration of electrolysis and the occurrence of withstand voltage failure in the unevenly scattered raised portions, an insulating film or an electrode film synchronized with the unevenness of the silicon film surface may be coated. is important. That is, it is desirable that each of the silicon layer, the insulating layer, and the electrode layer has a uniform single-film thickness in the cross section of the laminated film (see FIG. 8).

Thin film thickness and R _a after annealing of the film
Of the irradiation laser energy when is minimized,
And shows the relationship between the thickness and R _a thin film at this time is shown in FIG. As it is apparent from the figure, the center line average roughness R _a of the obtained semiconductor film increases as the film thickness increases.
That is, the thick film has a larger value of the center line average roughness and the fluctuation range thereof with the progress of crystallization than the thin film. In addition, since a large amount of energy is required for crystallization, silicon is sublimated during annealing to roughen the surface and the breakdown voltage of the film is likely to decrease.

FIG. 10 shows the relationship between the breakdown voltage of the film and the value obtained by dividing the center line average roughness _Ra by the film thickness t. As is clear from the figure, if the value of _Ra / t is 0.2 or less, it becomes almost constant at a high value. When the value exceeds 0.5, the withstand voltage of the film is greatly reduced.

The characteristics of the film also depend on the crystal grain size. When the particle size is large, the mobility is large because the crystallinity is improved. However, on the other hand, the OFF current also increases.

FIG. 11 shows the relationship between the value obtained by dividing the center line average roughness _Ra by the crystal grain size φ and the breakdown voltage of the film, and the relationship between the value and the mobility of the film. Here, the crystal grain size is obtained, for example, by the intercept method. Alternatively, a value obtained by dividing the number of crystal grains existing on a straight line having a predetermined length by the length can be used.

Both the breakdown voltage and the mobility of the film show good values when R _a / φ is 0.2 or less, and sharply decreases when R _a / φ is more than that.

FIG. 12 shows the relationship between the value obtained by further dividing the above R _a / t by the grain size φ and the breakdown voltage of the film, and the relationship between the value and the mobility of the film. As is clear from the figure, the withstand voltage and the mobility of the film are such that _Ra / (t · φ) is 6.8 × 1.
If it is 0 ^-3 nm ^-1 or less, a good value is shown, and if it is more than that, it drops sharply.

FIG. 13 shows the relationship between the value obtained by dividing the crystal grain diameter φ by the film thickness and the mobility of the film, and the relationship between the value and the leak current of the transistor using the film.

As is clear from the figure, both the mobility and the leakage current show a good value when φ / t is 1.2 or less, and sharply decrease when φ / t is more than that.

Thus, the state of the silicon surface shows its characteristics. Therefore, in the case of an insulating film with good coverage, or even in the upper electrode film, the surface condition after the insulating film is formed or after the electrode film is formed is monitored to evaluate the crystallinity of silicon and the coverage of the insulating film. It can be performed. By evaluating the surface after the silicon crystal and the surface after the insulation film is coated by the roughness as described above, the coverage of the insulation film, that is, the pressure resistance can be monitored.

[0045]

According to the present invention, it is possible to provide a high breakdown voltage polycrystalline silicon element suitable for a semiconductor element. Therefore, it is possible to improve the performance and reliability of the semiconductor element and the display panel using the semiconductor element.

[Brief description of drawings]

FIG. 1 is a schematic longitudinal sectional view showing a state of a silicon film in a schematic manufacturing flow of the present invention.

FIG. 2 is a roughness curve diagram of an annealed polycrystalline silicon film surface obtained by using the atomic force microscope of the present invention.

FIG. 3 is a characteristic diagram showing the relationship between the energy of the excimer laser irradiated during the annealing of the present invention and the center line average roughness of the surface of the polycrystalline silicon film after the annealing.

FIG. 4 is a characteristic diagram showing the relationship between the energy of an excimer laser irradiated during annealing and the mobility of a polycrystalline silicon film after annealing.

FIG. 5 is a characteristic diagram showing the relationship between the centerline average roughness of the polycrystalline silicon film surface after annealing and the mobility of the film.

FIG. 6 is a characteristic diagram showing the relationship between the center line average roughness of the surface of the polycrystalline silicon film after annealing according to the present invention and the breakdown voltage of the film.

FIG. 7 is a schematic cross-sectional view of crystallized silicon.

FIG. 8 is a cross-sectional view of an upper layer laminated film motivated by the unevenness of the surface of crystallized silicon.

FIG. 9 is a characteristic diagram showing the relationship between the thickness of the silicon film, the optimum value of the energy of the excimer laser for annealing the film, and the center line average roughness of the surface of the film.

FIG. 10 is a characteristic diagram showing the relationship between the center line average roughness and the thickness of the polycrystalline silicon film surface after annealing and the breakdown voltage of the film.

FIG. 11 is a characteristic diagram showing the relationship between the centerline average roughness of the surface of the polycrystalline silicon film after annealing, the ratio of the crystal grain size of the film to the mobility of the film, and the relationship between the ratio and the breakdown voltage of the film.

FIG. 12 is a characteristic showing the relationship between the centerline average roughness of the surface of the polycrystalline silicon film after annealing, the crystal grain size, the thickness of the film and the mobility of the film, and the relationship between these and the breakdown voltage of the film. Figure

FIG. 13 shows the relationship between the crystal grain size and the thickness of the polycrystalline silicon film after annealing, the withstand voltage of the film, and the relationship between the ratio and the leakage current of a thin film transistor using the film. Characteristic diagram

[Explanation of symbols]

1 substrate 2 insulating layers 3a Amorphous silicon layer 3b polycrystalline silicon layer 3c Source area 3d drain region 4a insulating layer 5a Gate electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/20 H05B 33/08 29/786 33/10 H05B 33/08 33/14 A 33/10 H01L 29 / 78 618Z 33/14 626C 617S (72) Inventor Teru Nishitani 1006 Daimon Kadoma, Kadoma City, Osaka Prefecture F-term (reference) inside Matsushita Electric Industrial Co., Ltd. 2H092 JA24 JB57 KA04 MA07 NA21 3K007 AB11 AB17 CA03 EB00 FA00 5C094 AA02 AA21 BA03 BA29 BA43 CA19 DA14 DA15 DB04 EA04 EA07 EB05 5F052 AA02 AA17 BB07 CA07 DA01 DA02 DB02 EA03 EA11 FA19 JA01 5F110 AA12 AA13 BB01 BB09 CC02 DD03 DD13 FF12 GG02 GG13 GG25 GG47 HM15 PP01 PP03 PP10 PP03 PP10 PP03 PP10 PP03 PP10

Claims (45)

[Claims] 1. The ratio of the center line average roughness of the surface of the insulating film formed on the silicon film is 0.5 or less, where the thickness of the polycrystalline thin film mainly containing silicon is 1. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the ratio is 0.2 or less. 3. The ratio is divided by the average grain size of silicon crystals.
Value is 6.8 × 10 ^-3nm^-1Claim 2 below
Semiconductor device. 4. The semiconductor device according to claim 1, wherein the center line average roughness is 10 nm or less. 5. The semiconductor device according to claim 1, wherein the thickness of the polycrystalline thin film containing silicon as a main component is 20 to 100 nm. 6. The semiconductor device according to claim 1, wherein the polycrystalline thin film containing silicon as a main component is formed on the surface of an insulator having a thickness of 100 nm or more and a center line roughness of 3 nm or less. 7. A semiconductor device comprising silicon as a main component and having a surface centerline average roughness and a surface of an insulating film formed on the silicon film having a centerline average roughness of 10 nm or less. 8. The semiconductor device according to claim 7, wherein the polycrystalline thin film containing silicon as a main component has a thickness of 20 to 100 nm. 9. The semiconductor device according to claim 7, which is formed on the surface of an insulator having a thickness of 100 nm or more and a center line roughness of 3 nm or less. 10. A semiconductor element having a center line average roughness of the surface of an insulating film formed on the silicon film as 0.2 or less, where silicon is the main component and the average crystal grain size is 1. 11. The semiconductor device according to claim 10, wherein the polycrystalline thin film mainly containing silicon has a thickness of 20 to 100 nm. 12. The insulating film having a thickness of 100 nm or more and a center line roughness of 3 nm or less.
The semiconductor device described in 0. 13. A substrate, and a plurality of semiconductor elements for controlling the pixels, which are arranged in respective pixel regions on the substrate, and the semiconductor elements are mainly composed of silicon and have a thickness of 1 or less. The array substrate in which the ratio of the center line average roughness of the surface and the surface of the insulating film coated on the silicon surface is 0.5 or less. 14. The ratio is 0.2 or less.
3. The array substrate according to 3. 15. The value obtained by dividing the ratio by the average grain size of silicon crystals is 6.8 × 10 ⁻³ nm ⁻¹ or less.
The array substrate described. 16. The array substrate according to claim 13, wherein the center line average roughness is 10 nm or less. 17. The polycrystalline thin film has a thickness of 20 to 100.
14. The array substrate according to claim 13, which is nm. 18. The polycrystalline thin film has a thickness of 100 nm.
14. The array substrate according to claim 13, which is formed on the surface of an insulator having a surface centerline roughness of 3 nm and a core wire roughness of 3 nm or less. 19. A substrate, and a plurality of semiconductor elements for controlling the pixels, which are arranged in respective pixel areas on the substrate, the semiconductor element mainly includes silicon and a surface and a silicon surface. An array substrate having a center line average roughness of 10 nm or less on the surface of the insulating film coated with. 20. The thickness of the polycrystalline thin film is 20-100.
20. The array substrate according to claim 19, which is nm. 21. The polycrystalline thin film has a thickness of 100 nm.
20. The array substrate according to claim 19, which is formed on the surface of the insulator having a center line roughness of 3 nm or less on the surface. 22. A substrate and a plurality of semiconductor elements for controlling the pixels, which are arranged in respective pixel regions on the substrate, the semiconductor elements being mainly composed of silicon and having an average crystal grain size. An array substrate in which the ratio of the center line average roughness of the surface is 0.2 or less when the diameter is 1, and the ratio of the center line average roughness of the insulating film surface that covers the polycrystalline thin film is also 0.2 or less. . 23. The thickness of the polycrystalline thin film is 20-100.
23. The array substrate according to claim 22, which has a thickness of nm. 24. The polycrystalline thin film has a thickness of 100 nm.
23. The array substrate according to claim 22, which is formed on the surface of the insulator having a centerline roughness of 3 nm or less on the surface. 25. A semiconductor element for controlling a pixel is provided, and the semiconductor element is mainly composed of silicon and has a thickness of 1 or less.
And the ratio of the center line average roughness of the surface and the center line average roughness of the surface of the insulating film covering the silicon surface are 0.
A display panel of 5 or less. 26. The ratio is 0.2 or less.
The display panel described in 5. 27. The value obtained by dividing the ratio by the average grain size of silicon crystals is 6.8 × 10 ⁻³ nm ⁻¹ or less.
Display panel described. 28. The display panel according to claim 25, wherein the center line average roughness is 10 nm or less. 29. The polycrystalline thin film has a thickness of 20 to 100.
26. The display panel according to claim 25, which has a thickness of nm. 30. The polycrystalline thin film has a thickness of 100 nm.
26. The display panel according to claim 25, which is formed on the surface of the insulator having a center line roughness of 3 nm or less. 31. A semiconductor device further comprising a liquid crystal layer and a pixel electrode for applying a voltage to the liquid crystal,
26. The display panel according to claim 25, wherein a voltage applied to the liquid crystal layer in a region corresponding to the pixel electrode is controlled. 32. The display panel according to claim 25, further comprising an organic electroluminescence element that emits light when a voltage is applied, wherein the semiconductor element controls a voltage applied to the organic electroluminescence element. 33. A display panel comprising a semiconductor element for controlling a pixel, wherein the semiconductor element is mainly composed of silicon and a center line average roughness of a surface of the silicon and a surface of an insulating film coated on the silicon is 10 nm or less. . 34. The thickness of the polycrystalline thin film is 20-100.
34. The display panel according to claim 33, which has a thickness of nm. 35. The polycrystalline thin film has a thickness of 100 nm.
34. The display panel according to claim 33, which is formed on the surface of an insulator having a center line roughness of 3 nm or less. 36. The display panel according to claim 33, further comprising an organic electroluminescence element that emits light when a voltage is applied, wherein the semiconductor element controls a voltage applied to the organic electroluminescence element. 37. The display panel according to claim 33, further comprising an organic electroluminescence element that emits light when a voltage is applied, wherein the semiconductor element controls a voltage applied to the organic electroluminescence element. 38. A semiconductor element for controlling a pixel is provided, wherein the semiconductor element is mainly composed of silicon and has a center line average roughness of the surface and an insulation covering the silicon surface when the average grain size of crystals is 1. A display panel having a polycrystalline thin film having a center line average roughness ratio of 0.2 or less on the surface of the film. 39. The thickness of the polycrystalline thin film is 20-100.
39. The display panel according to claim 38, which has a thickness of nm. 40. The polycrystalline thin film has a thickness of 100 nm.
39. The display panel according to claim 38, which is formed on the surface of the insulator having a center line roughness of 3 nm or less. 41. The semiconductor device further comprises a liquid crystal layer and a pixel electrode for applying a voltage to the liquid crystal,
39. The display panel according to claim 38, wherein a voltage applied to the liquid crystal layer in a region corresponding to the pixel electrode is controlled. 42. The display panel according to claim 38, further comprising an organic electroluminescence element that emits light when a voltage is applied, and the semiconductor element controls a voltage applied to the organic electroluminescence element. 43. A step of monitoring the roughness of the undercoat film surface, a step of monitoring the film surface roughness of the crystallized silicon film, and a step of monitoring the roughness of the insulating film surface formed on the crystalline silicon film. -A method for controlling a manufacturing process, which comprises at least the step of performing-and evaluating the crystallinity of silicon and the covering property of an insulating film. 44. A step of monitoring the roughness of the undercoat film surface, a step of monitoring the film surface roughness of the crystallized silicon film, and a step of monitoring the roughness of the insulating film surface formed on the crystalline silicon film. -, And at least a step of monitoring the surface roughness of the metal film formed through the insulating film, the evaluation of the crystallinity of silicon and the coverage of the insulating film of the manufacturing process characterized by Management method. 45. By covering an insulating film synchronized with the surface irregularities of the silicon film or a metal film to be an electrode, in the cross section of the laminated film of each of the silicon layer, the insulating layer and the metal layer,
A semiconductor device having a uniform film thickness in a single film.