JP2003007708A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JP2003007708A
JP2003007708A JP2001184784A JP2001184784A JP2003007708A JP 2003007708 A JP2003007708 A JP 2003007708A JP 2001184784 A JP2001184784 A JP 2001184784A JP 2001184784 A JP2001184784 A JP 2001184784A JP 2003007708 A JP2003007708 A JP 2003007708A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
electrode wiring
surface electrode
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001184784A
Other languages
Japanese (ja)
Inventor
Keiji Maruyama
啓司 丸山
Osamu Inoue
収 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001184784A priority Critical patent/JP2003007708A/en
Publication of JP2003007708A publication Critical patent/JP2003007708A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a reliable semiconductor device that prevents the whisker- like protrusions of an upper layer film due to side etching of a lower layer film when the surface electrode wiring of a semiconductor device is to be formed, and to provide a method for manufacturing the reliable semiconductor device. SOLUTION: In surface electrode wiring that is formed on a semiconductor substrate, and has a conductive film with at least two layers, one portion of a lower layer is exposed from a terminal section of the uppermost layer of the conductive film.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置に係
り、特に表面電極配線における信頼性の改善を図った半
導体装置とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved reliability in surface electrode wiring and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来、半導体装置の表面電極配線は以下
のように形成されていた。すなわち、図2(a)に示す
ように、Si基板1上に素子領域(図示せず)、表面酸
化膜2及びコンタクトホール3を形成し、この上にNi
膜4を500nm、Au膜5を50nm順次形成する。
次いで、図2(b)に示すように、通常のPEP(ph
oto etching process)パターニン
グにて、レジスト6を塗布、所定のマスクを用いて、露
光・現像を行い、上層のAu膜5を15%塩化第二鉄水
溶液でエッチングした後、引き続き下層のNi膜4をヨ
ウ素2.9%+ヨウ化カリウム10.8%水溶液でエッ
チングしてNi/Auの2層からなる表面電極配線を形
成する。
2. Description of the Related Art Conventionally, the surface electrode wiring of a semiconductor device has been formed as follows. That is, as shown in FIG. 2A, a device region (not shown), a surface oxide film 2 and a contact hole 3 are formed on a Si substrate 1, and a Ni film is formed on the device region.
The film 4 is sequentially formed to have a thickness of 500 nm, and the Au film 5 is sequentially formed to have a thickness of 50 nm.
Then, as shown in FIG. 2B, a normal PEP (ph
The resist 6 is applied by photo-etching process patterning, exposure and development are performed using a predetermined mask, the upper Au film 5 is etched with a 15% ferric chloride aqueous solution, and then the lower Ni film 4 is continuously formed. Is etched with an aqueous solution of 2.9% iodine + 10.8% potassium iodide to form a surface electrode wiring consisting of two layers of Ni / Au.

【0003】しかしながら、このようにして形成された
表面電極配線においては、Ni膜の膜厚が500nmと
厚く、このような等方性エッチングでは壁面が大きくエ
ッチングされてしまい、図3(a)のようにパターニン
グされたAu膜の終端部がヒサシ状に浮き上がる、とい
う現象が発生する。そして、図3(b)に示すように、
このヒサシ状のAu膜がNiとの界面で折れてヒゲ状に
表面に張り出して、他の電極と接触してショート不良を
起こしてしまう。さらに、このヒゲ状のAu膜は、接触
したり離れたりするので、ショート不良として確実に検
出することが困難であるという問題があった。
However, in the surface electrode wiring thus formed, the Ni film has a large film thickness of 500 nm, and the wall surface is largely etched by such isotropic etching, and as shown in FIG. There occurs a phenomenon in which the end portion of the Au film patterned as described above floats up like a square. Then, as shown in FIG.
The pitted Au film is broken at the interface with Ni and bulges out to the surface like a whiskers, and contacts with other electrodes to cause a short circuit defect. Further, the beard-shaped Au film comes into contact with or separates from each other, and thus there is a problem that it is difficult to reliably detect a short circuit defect.

【0004】[0004]

【発明が解決しようとする課題】この様に、従来は、半
導体装置の表面電極配線を形成する際、下層膜がサイド
エッチされるため上層膜がヒゲ状に張り出し、半導体装
置の信頼性が低下するという問題があった。
As described above, conventionally, when the surface electrode wiring of the semiconductor device is formed, since the lower layer film is side-etched, the upper layer film bulges out like a beard and the reliability of the semiconductor device is deteriorated. There was a problem of doing.

【0005】従って本発明は、このような従来の半導体
装置の表面電極配線における欠点を取り除き、信頼性の
高い半導体装置と、その製造方法を提供することを目的
とするものである。
Therefore, an object of the present invention is to provide a semiconductor device having high reliability and a method of manufacturing the semiconductor device by eliminating the drawbacks in the surface electrode wiring of the conventional semiconductor device.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に形成された表面電極配線を備え、前記表
面電極配線は少なくとも2層以上の導電性膜を有し、最
上層の終端部より下層の一部が露出していることを特徴
とするものである。
The semiconductor device of the present invention comprises:
A surface electrode wiring formed on a semiconductor substrate, wherein the surface electrode wiring has a conductive film of at least two layers, characterized in that a part of the lower layer is exposed from the terminal end of the uppermost layer. It is a thing.

【0007】また、本発明の半導体装置の製造方法は、
半導体基板上に第1、第2の導電性膜を順次形成する工
程と、第2の導電性膜を第1の形状にパターニングする
工程と、前記第1の導電性膜を、その一部が前記第1の
形状の終端部より露出する第2の形状にパターニングす
ることにより、表面電極配線を形成する工程とを具備す
ることを特徴とするものである。
A method of manufacturing a semiconductor device according to the present invention is
A step of sequentially forming first and second conductive films on a semiconductor substrate; a step of patterning the second conductive film into a first shape; and a part of the first conductive film. And forming a surface electrode wiring by patterning into a second shape exposed from the end portion of the first shape.

【0008】[0008]

【発明の実施の形態】以下本発明の実施形態について、
図1を参照して説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
This will be described with reference to FIG.

【0009】図1(a)に示すように、Si基板1上に
素子領域(図示せず)、表面酸化膜2及びコンタクトホ
ール3を形成し、この上に第1の導電性膜であるNi膜
4を500nm、第2の導電性膜であるAu膜5を50
nm、スパッタ等公知の成膜方法で順次形成した後、通
常のPEPパターニングを用いて、レジスト6を塗布、
第1のパターンの形成されたフォトマスクを用いて露光
・現像し、15%塩化第二鉄水溶液を用いてエッチング
することにより、Au膜を図1(b)に示すような形状
にパターニングする。
As shown in FIG. 1A, a device region (not shown), a surface oxide film 2 and a contact hole 3 are formed on a Si substrate 1, and a Ni film which is a first conductive film is formed thereon. The film 4 has a thickness of 500 nm, and the Au film 5 as the second conductive film has a thickness of 50 nm.
nm, sputtering, or other known film forming method, and then the resist 6 is applied using normal PEP patterning.
The Au film is patterned into a shape as shown in FIG. 1B by exposing and developing using a photomask on which the first pattern is formed and etching using a 15% ferric chloride aqueous solution.

【0010】次いで、図1(c)に示すように、Ni
膜、パターニングされたAu膜5'上にレジスト6'を塗
布、第2のパターンの形成されたフォトマスクを用いて
露光・現像し、ヨウ素2.9%+ヨウ化カリウム10.
8%水溶液を用いてエッチングする。このとき、第2の
フォトマスクとして、残し寸法d=15μmとしたもの
を用いており、図1(d)に示すように、先にパターニ
ングしたAu膜5'の終端部よりNi膜4'が露出するよ
うにパターニングされる。このとき、Ni膜は従来と同
様にサイドエッチされるが、Au膜直下までエッチング
が進行することはなく、Au膜終端部よりd'=5〜1
0μm露出した状態となる。
Then, as shown in FIG.
A resist 6'is applied on the film and the patterned Au film 5 ', exposed and developed using a photomask having a second pattern formed thereon, and iodine 2.9% + potassium iodide 10.
Etch with 8% aqueous solution. At this time, a second photomask having a remaining dimension d = 15 μm is used, and as shown in FIG. 1D, the Ni film 4 ′ is removed from the end portion of the previously patterned Au film 5 ′. Patterned to be exposed. At this time, the Ni film is side-etched as in the conventional case, but the etching does not proceed to the position immediately below the Au film, and d ′ = 5-1 from the Au film end portion.
The exposed state is 0 μm.

【0011】このようにして表面電極配線の形成された
半導体装置において、外観検査を行なったところ、これ
まで8%あった不良が2%と大幅に改善された。
When a visual inspection was conducted on the semiconductor device having the surface electrode wiring formed in this manner, the defects, which had been 8% so far, were significantly reduced to 2%.

【0012】尚、本実施形態においては、電極配線材料
にNi/Auを用いたが、これら材料に限定されるもの
ではなく、種々合金を用いても良い。またこれらの下層
にV等のバリアメタル層を設けても良い。また、二層に
限定されるものではなく、下層が上層より厚い多層配線
であれば効果が得られる。
In this embodiment, Ni / Au is used as the electrode wiring material, but the material is not limited to these materials, and various alloys may be used. Further, a barrier metal layer such as V may be provided below these layers. Further, the present invention is not limited to two layers, and an effect can be obtained if the lower layer is a multilayer wiring thicker than the upper layer.

【0013】また、残し寸法について、本実施形態にお
いては15μmとしたが、サイドエッチされた後も最上
層の終端部より下層の露出する部分が残っていれば良
い。
Although the remaining dimension is set to 15 μm in this embodiment, it is sufficient that the exposed portion of the layer below the terminal end of the uppermost layer remains after the side etching.

【0014】[0014]

【発明の効果】本発明によれば、半導体装置の表面電極
配線を形成する際、下層膜がサイドエッチされることに
よる上層膜のヒゲ状張り出しのない、信頼性の高い半導
体装置及びその製造方法を提供することができる。
According to the present invention, in forming a surface electrode wiring of a semiconductor device, a highly reliable semiconductor device in which the lower layer film is not side-etched and the upper layer film has a whisker-like protrusion, and a method of manufacturing the same. Can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の表面電極配線の製造工程
を示す図。
FIG. 1 is a diagram showing a manufacturing process of surface electrode wiring of a semiconductor device of the present invention.

【図2】従来の半導体装置の表面電極配線の製造工程を
示す図。
FIG. 2 is a diagram showing a manufacturing process of a surface electrode wiring of a conventional semiconductor device.

【図3】従来の半導体装置の表面電極配線の問題点を示
す図。
FIG. 3 is a diagram showing a problem of a surface electrode wiring of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 Si基板 2 表面酸化膜 3 コンタクトホール 4、4' Ni膜 5、5' Au膜 6、6' レジスト 1 Si substrate 2 Surface oxide film 3 contact holes 4,4 'Ni film 5,5 'Au film 6,6 'resist

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F033 HH07 HH13 JJ01 JJ07 JJ13 KK01 MM05 MM08 MM13 QQ08 QQ09 QQ10 QQ19 QQ37 XX31 XX34    ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH07 HH13 JJ01 JJ07 JJ13                       KK01 MM05 MM08 MM13 QQ08                       QQ09 QQ10 QQ19 QQ37 XX31                       XX34

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された表面電極配線
を備え、前記表面電極配線は少なくとも2層以上の導電
性膜を有し、最上層の終端部より下層の一部が露出して
いることを特徴とする半導体装置。
1. A surface electrode wiring formed on a semiconductor substrate, wherein the surface electrode wiring has at least two or more conductive films, and a part of the lower layer is exposed from the end portion of the uppermost layer. A semiconductor device characterized by the above.
【請求項2】 半導体基板上に第1、第2の導電性膜を
順次形成する工程と、第2の導電性膜を第1の形状にパ
ターニングする工程と、前記第1の導電性膜を、その一
部が前記第1の形状の終端部より露出する第2の形状に
パターニングすることにより、表面電極配線を形成する
工程とを具備することを特徴とする半導体装置の製造方
法。
2. A step of sequentially forming first and second conductive films on a semiconductor substrate, a step of patterning the second conductive film into a first shape, and a step of forming the first conductive film. And forming a surface electrode wiring by patterning a second shape, a part of which is exposed from the end portion of the first shape.
JP2001184784A 2001-06-19 2001-06-19 Semiconductor device and its manufacturing method Pending JP2003007708A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001184784A JP2003007708A (en) 2001-06-19 2001-06-19 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001184784A JP2003007708A (en) 2001-06-19 2001-06-19 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003007708A true JP2003007708A (en) 2003-01-10

Family

ID=19024489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001184784A Pending JP2003007708A (en) 2001-06-19 2001-06-19 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2003007708A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018137368A (en) * 2017-02-22 2018-08-30 住友電工デバイス・イノベーション株式会社 Semiconductor device manufacturing method
US10957591B2 (en) 2018-02-16 2021-03-23 Sumitomo Electric Device Innovations, Inc. Process of forming semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018137368A (en) * 2017-02-22 2018-08-30 住友電工デバイス・イノベーション株式会社 Semiconductor device manufacturing method
US10957591B2 (en) 2018-02-16 2021-03-23 Sumitomo Electric Device Innovations, Inc. Process of forming semiconductor device
US11515208B2 (en) 2018-02-16 2022-11-29 Sumitomo Electric Device Innovations, Inc. Semiconductor device and semiconductor apparatus

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