JP2001057369A - Semiconductor device having metal wiring and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form precisely a wiring of a fine pattern and prevent a disconnection of a gold film in an undercut etching part by a method wherein there are provided the gold film patterned, and a first silicon oxide film formed in the same pattern as in the gold film in an upper part of the gold film, thereby constituting a semiconductor device having a gold wiring. SOLUTION: A silicon oxide film of thickness about 0.2 μm as an etching stop layer is formed on a substrate 1 composed of a compound semiconductor. A gold film 4 having thickness about 1 μm is formed by patterning on this silicon oxide film 2, and further a silicon oxide film 5 having the same pattern as in the gold film 4 is formed at thickness about 0.5 μm on the gold film 4. In particular, when dry etching is performed by use of a chlorine gas, a selection ratio of the silicon oxide film 5 to the gold film 4 (gold/silicon oxide film) is 10 or more. For this reason, even when a thickness of the gold film 4 is thick at 1 μm or more, it is possible to thin a thickness of the silicon oxide film 5 and to readily perform a fine process of wiring width about 1 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having gold wiring and a method of manufacturing the same, and more specifically, to a semiconductor device having gold wiring.
The present invention relates to a semiconductor device having gold wiring for performing good patterning of a gold film and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, fine processing technology has played an important role in increasing the speed of semiconductor devices, and dry etching has been performed to pattern metal wirings. Until now, aluminum (Al) has been mainly used as the material of the metal wiring, but gold is expected as a more chemically stable and low-resistance material with the increase in the speed of the device. In fact, gold (Au) is used as a wiring material for a monolithic microwave integrated circuit that requires operation in a high frequency band in order to reduce wiring resistance.

A conventional method for manufacturing a gold wiring using dry etching will be described below with reference to Japanese Patent Application Laid-Open No. Sho 64-68946.

FIG. 17 is a schematic cross-sectional view for explaining a conventional method of manufacturing a gold wiring disclosed in the above publication. Referring to FIG. 17, in a conventional method for manufacturing a gold wiring, gold film 206 is patterned by dry etching using a chlorine-based gas using register pattern 210 as a mask. More specifically, it is as follows.

First, a lower electrode 202 is formed on a semiconductor substrate 201.
Is formed, and an interlayer insulating film 203 is formed on the lower electrode 202.
Is formed. A hole exposing the lower electrode 202 is formed in the interlayer insulating film 203, and the lower electrode 202 is
A titanium (Ti) film 204, a platinum (Pt) film 205, and a gold film 206 are sequentially formed on the interlayer insulating film 203 so as to be electrically connected to the substrate. A resist pattern 210 is formed on the gold film 206, and the resist pattern 210 is used as a mask to perform dry etching with chlorine gas to thereby form the gold film 206, the platinum film 205 and the titanium film 2
04 is patterned.

[0006]

However, the conventional method of manufacturing a gold wiring has the following problems since the resist pattern 210 is used as a mask when patterning the gold film 206.

In dry etching using chlorine gas,
The selectivity (gold / resist) between the resist 210 serving as a mask and the gold film 206 is about 1. That is, the gold film 206
At the time of etching, the resist 210 is also etched away by the same amount as the gold film 206. Therefore, if the thickness of the resist 210 is small, the resist 210 is completely removed during the etching of the gold film 206, and does not serve as a mask. Therefore, when the thickness of the gold film 206 is increased in order to reduce the wiring resistance, the resist 21
It is also necessary to increase the thickness of 0.

When the resist 210 becomes thicker, the resist 2
The aspect ratio (the vertical / horizontal dimension ratio of the pattern) of the ten patterns increases. Therefore, when the pattern side surface of the resist 210 is not vertical, the dimensional accuracy of the pattern of the resist 210 with respect to the reticle pattern is significantly deteriorated, and it is difficult to increase the resolution of the resist pattern 210. Therefore, there is a problem that the above method is disadvantageous when applied to a wiring having a fine shape.

When a gold film 206 is formed on a base having large steps and irregularities as shown in FIG. 18, the surface of the gold film 206 has a large step reflecting the base step.
If the resist pattern 210 is used as a mask when such a gold film 206 is etched, the thickness of the resist 210 at the edge portion P of the step becomes thin. If the dry etching of the gold film 206 is performed in this state, the resist 210 will be lost at the edge portion P. As a result, the gold film 206 is not etched at the edge portion P as shown in FIG. 19, and there is a problem that the gold film 206 is disconnected at the edge portion P.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a gold wiring which can be easily applied to a wiring having a fine shape and which can prevent disconnection of a gold film, and a method of manufacturing the same.

[0011]

A semiconductor device having gold wiring according to the present invention comprises a patterned gold film and a first silicon oxide film formed on the gold film in the same pattern as the gold film. Have.

In the semiconductor device having gold wiring of the present invention,
Since the first silicon oxide film having the same pattern is formed on the gold film, the gold film can be patterned using the first silicon oxide film as a mask during manufacturing.
Therefore, the selectivity between the silicon oxide film and the gold film under the conditions for etching the gold film can be increased, and it is not necessary to increase the thickness of the resist even when patterning a thick gold film. Therefore, the resolution of the pattern does not decrease due to the thicker resist. Therefore, it is possible to accurately form the wiring of the fine pattern and to prevent the disconnection of the gold film at the step edge portion.

It should be noted that the same pattern in the present specification naturally causes an error in the production process. Therefore, the difference of the degree of the error is regarded as the same and is included in the present invention.

In the above-described semiconductor device having gold wiring, preferably, a second silicon oxide film having the same pattern as the gold film and a planarizing layer are sequentially provided between the gold film and the first silicon oxide film. ing.

As described above, by using the three-layer laminated film of the first and second silicon oxide films and the flattening layer as a mask, even when the step or unevenness of the base is large, the gold film at the step edge portion is formed. Disconnection can be prevented.

Preferably, in the semiconductor device having the gold wiring, a metal film made of a material different from the gold film is provided so as to be in contact with the upper surface of the gold film and have the same pattern as the gold film.

This makes it possible to improve the adhesion between the gold film and the silicon oxide film, prevent the silicon oxide film from peeling off during dry etching, and perform dry etching with good reproducibility. The material used for the metal film is at least one selected from the group consisting of titanium, aluminum, tungsten (W), copper (Cu), silver (Ag), nickel (Ni), platinum and palladium (Pd). Preferably, there is.

In the above-described semiconductor device having gold wiring, the surface of the metal film is preferably oxidized.

As a result, the adhesion of the silicon oxide film is further improved, and dry etching can be performed with good reproducibility. This is probably because the adhesion of the silicon oxide film is stronger for the metal oxide film than for the metal.

As a method of oxidizing the metal film, a method of exposing the metal film to oxygen plasma or the like is possible. However, when the metal film is made of titanium, aluminum or the like, the surface is easily oxidized. It can be oxidized and the process can be simplified. In addition, a multilayer structure or alloy of a plurality of metals is also possible. If there is a problem such as the formation of a high-resistance substance due to the reaction with gold such as aluminum, another barrier layer is further provided between the gold film and the metal film. It is effective to sandwich the metal.

In the above-described semiconductor device having gold wiring, the material of the surface of the metal film is preferably platinum or palladium.

Thus, the adhesion of the silicon oxide film is further improved, and dry etching can be performed with good reproducibility. Platinum and palladium do not form an oxide film on the surface as described above, but have good adhesion to a silicon oxide film.
In the case of dry etching of gold, since platinum or palladium has good selectivity when used as a mask, it is also effective to pattern gold as a two-layer mask using a silicon oxide film and platinum (or palladium).

In the semiconductor device having the above gold wiring, the thickness of the metal film is preferably 5 nm or less.

Thus, the upper metal film can be etched under the same dry etching conditions as the gold film, and the process can be simplified. In particular, when the metal film is made of platinum or palladium, it is difficult to dry-etch. Therefore, when the metal film is thick, it is necessary to change the etching conditions in that portion.

According to the method of manufacturing a semiconductor device having gold wiring of the present invention, a step of forming a first silicon oxide film on a gold film, a step of patterning the first silicon oxide film,
Patterning the gold film by dry-etching using the patterned first silicon oxide film as a mask.

In the method of manufacturing a semiconductor device having gold wiring according to the present invention, since the gold film is patterned using the first silicon oxide film as a mask, the selectivity between the silicon oxide film and the gold film under the etching conditions of the gold film is changed. Can be bigger. Therefore, even when patterning a thick gold film, it is not necessary to make the resist thick. Therefore, the resolution of the pattern does not decrease due to the thicker resist. Therefore, it is possible to accurately form the wiring of the fine pattern and to prevent disconnection of the gold film at the step edge portion.

In the above-described method of manufacturing a semiconductor device having gold wiring, preferably, a second silicon oxide film is formed on the gold film after the gold film is formed and before the first silicon oxide film is formed. And a step of forming a planarizing layer in order, wherein the planarizing layer, the second silicon oxide film, and the gold film are sequentially patterned by dry etching using the patterned first silicon oxide film as a mask. .

By etching the gold film using the three-layer laminated film composed of the first and second silicon oxide films and the planarizing layer as a mask as described above, even if the underlying step or unevenness is large, the step edge can be obtained. Disconnection of the gold film can be prevented.

Preferably, the above-described method of manufacturing a semiconductor device having gold wiring further includes a step of forming a metal film made of a material different from the gold film so as to be in contact with the upper surface of the gold film.

By providing a metal film between the gold film and the silicon oxide film, the adhesion between the silicon oxide film and the gold film is improved, and dry etching can be performed with good reproducibility.

Preferably, in the above-described method for manufacturing a semiconductor device having gold wiring, a step of oxidizing the surface of the metal film is further provided.

As a result, the adhesion between the silicon oxide film and the gold film is further improved, and dry etching can be performed with good reproducibility.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention. Referring to FIG. 1, a silicon oxide film 2 serving as an etching stop layer is formed with a thickness of, for example, 0.2 μm on a substrate 1 made of, for example, a compound semiconductor.
On this silicon oxide film 2, a gold film 4 having a thickness of, for example, 1 μm is formed by patterning. On this gold film 4, a silicon oxide film 5 having the same pattern as the gold film 4 is formed with a thickness of, for example, 0.5 μm.

The structure of the layers above this is omitted for convenience of explanation. Next, the manufacturing method of the present embodiment will be described.

FIGS. 2 and 3 show Embodiment 1 of the present invention.
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device in Step order. First, referring to FIG. 2, a silicon oxide film 2, a gold film 4 and a silicon oxide film 5 are deposited on substrate 1 in this order. The silicon oxide films 2 and 5 are deposited at a substrate temperature of, for example, 200 ° C. to 300 ° C.

A photoresist 10 is formed on the silicon oxide film 5.
Is applied with a thickness of, for example, 1 μm, and then patterned by a normal photolithography technique. Dry etching using CF ₄ gas is performed using the resist pattern 10 as a mask.

Referring to FIG. 3, the silicon oxide film 5 is patterned by this dry etching. In addition,
The selectivity between the resist 10 and the silicon oxide film 5 in this etching (silicon oxide film / resist) is about 1. Using the patterned silicon oxide film 5 as a mask, the gold film 4 is dry-etched using chlorine gas. This etching is performed under the condition that the selectivity between the silicon oxide film 5 (or the silicon oxide film 2) and the gold film 4 is sufficiently obtained.

This dry etching is performed by ICP (Inductiv
This is performed by a dry etching apparatus to which ely Coupled Plasma is applied. When performing dry etching of the gold film 4, the substrate temperature is set to 100 ° C. to 250 ° C. in order to promote volatilization of a reactant from the substrate. The etching is terminated when the etching reaches the silicon oxide film 2 serving as an etching stop layer.

Here, the etching gas may be a chlorine-based gas. In particular, when dry etching of the gold film 4 is performed using a chlorine gas, the selectivity between the silicon oxide film 5 and the gold film 4 is increased. (Gold / silicon oxide film) is 10
That is all. For this reason, even when the thickness of the gold film 4 is as large as 1 μm or more, the thickness of the silicon oxide film 5 can be reduced, and fine processing (wiring width 1 μm) can be easily performed. Thereby, the configuration shown in FIG. 1 is obtained.

In FIG. 3, the resist pattern 10
May be removed by ashing after patterning the silicon oxide film 5, or may be removed by etching the gold film 4.

In this embodiment, the silicon oxide film 5 is used as a mask when patterning the gold film 4. Therefore, the selectivity between the silicon oxide film 5 and the gold film 4 under the conditions for etching the gold film 4 can be made larger than the selectivity between the resist pattern 10 and the gold film 4. Therefore, the thick gold film 4
Resist pattern 1
It is not necessary to increase the thickness of 0. Therefore, resist 1
There is no decrease in the resolution of the pattern due to the increase of 0. Therefore, a fine pattern can be formed.

Further, since the selectivity between the silicon oxide film 5 and the gold film 4 in the etching can be increased, disconnection of the gold film 4 at the step edge portion of the gold film 4 can also be prevented.

The resist pattern 10 may be deformed by heat. Therefore, when the resist pattern 10 is used as a mask in patterning the gold film 4, it becomes difficult to perform fine processing of the gold film 4. However, in the present embodiment, the silicon oxide film 5 is used as a mask for patterning the gold film 4. Since the silicon oxide film 5 is less likely to be deformed by heat than a resist, it is suitable for fine processing.

When dry etching is performed using a chlorine-based gas, there is a problem that chlorine or a chlorine compound remaining after the etching has an adverse effect on the device.

Therefore, in the present embodiment, after the etching of the gold film 4 is completed, the residual chlorine or chlorine compound (Au)
Cl, AuCl ₂ , AuCl _{3 and the} like are removed. The treatment is that it is exposed to oxygen plasma, washed with water, immersed in dilute hydrochloric acid, and washed with water.
This prevents the deterioration of the device due to the diffusion of chlorine ions to peripheral devices.

An acidic aqueous solution or an alkaline aqueous solution can be used in place of the diluted hydrochloric acid. However, it is preferable to use the diluted hydrochloric acid because the chlorine compound is more easily dissolved.

In this embodiment, the dry etching of the gold film 4 is performed by using an ICP dry etching apparatus. However, an ECR (Electron Cyclotron Resonance) dry etching apparatus or RIE (Reactive Ion Etching) is used.
It can also be performed using an apparatus. In the present embodiment, by applying ICP dry etching,
A higher etching rate can be obtained as compared with normal RIE. Although chlorine gas is used as the etching gas, for example, CCl ₄ , CCl ₂ , CCl ₂ F ₂ , CClF
₃ , SiCl ₄ , BCl _3, etc. can also be used.

(Second Embodiment) FIG. 4 is a sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 4, in the semiconductor device of the present embodiment, as compared with the structure of the first embodiment shown in FIG. The difference is that a titanium film 3 is added.

The remaining structure is substantially the same as that of the first embodiment, and therefore the same members are denoted by the same reference characters and description thereof will not be repeated.

The provision of the titanium film 3 improves the adhesion between the gold film 4 and the base. The dry etching of the titanium film 3 can be performed under the same conditions as those for the gold film 4.
Further, as a treatment for removing chlorine and chlorine compounds remaining after the dry etching of the gold film 4 and the titanium film 3, the film is exposed to oxygen plasma, and then dipped in a polar organic solution containing phenol to prevent corrosion of the titanium film 3, and acetone and IPA are removed. After that, a process of exposing to oxygen plasma is performed.

In this embodiment, an HBT (Heterojunction Bipolar Transformer) is actually formed on the compound semiconductor substrate 1.
istor) and gold wiring was created. The device of the wafer on which the chlorine or chlorine compound remaining after the etching of the gold film 4 was removed had excellent device reliability as compared with the device without the removal treatment.

The same effect was obtained by using a polar organic solution containing alkylphenol or monoethanolamine instead of phenol.

This removing process is effective even in the case where only the gold film 4 is used as described in the first embodiment.

In this embodiment, the dry etching of the gold film 4 and the titanium film 3 is performed by using an ICP dry etching apparatus, but may be performed by using an ECR dry etching apparatus or an RIE apparatus. In this embodiment, by applying ICP dry etching, a higher etching rate can be obtained as compared with normal RIE. Although chlorine gas was used as the etching gas, for example, CCl ₄ , CCl ₂ , CCl ₂ F ₂ , CCl ₂
It can also be performed using ClF ₃ , SiCl ₄ , BCl ₃ or the like.

(Embodiment 3) FIG. 5 is a sectional view schematically showing a configuration of a semiconductor device according to Embodiment 3 of the present invention. Referring to FIG. 5, on compound semiconductor substrate 101,
An interlayer insulating film 102 made of, for example, polyimide and a silicon oxide film 103 having a thickness of, for example, 0.2 μm are formed. The interlayer insulating film 102 and the silicon oxide film 1
03, a contact hole reaching the surface of the substrate 101 is formed.

Titanium film 104 has a thickness of, for example, 0.1 μm so as to be in contact with the surface of substrate 101 through the contact hole.
It is formed with the thickness of. On the titanium film 104, for example, 1 μm
The gold film 105 is formed with a thickness of. This gold film 105
A silicon oxide film 1 having a thickness of, for example, 0.5 μm
06, a planarizing layer 107 made of polyimide having a thickness of, for example, 3 μm, and a silicon oxide film 108 are formed in this order, and each has the same pattern as the titanium film 104.

Next, a manufacturing method according to the present embodiment will be described. 6 and 7 are schematic sectional views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. Referring to FIG. 6, compound semiconductor substrate 101
An interlayer insulating film 102 made of, for example, polyimide and a silicon oxide film 103 are sequentially formed thereon. Thereafter, a contact hole reaching the surface of the substrate 101 is formed in the silicon oxide film 103 and the interlayer insulating film 102 by ordinary photolithography and etching. Thereafter, a titanium film 104, a gold film 105, and a silicon oxide film 106
Then, a planarizing layer 107 made of, for example, polyimide and a silicon oxide film 108 are sequentially formed. A resist pattern 110 is formed on the silicon oxide film 108 by a normal photolithography technique.
Is used as a mask to pattern silicon oxide film 108.

[0060] With reference to FIG. 7, the silicon oxide film 108 which is patterned as a mask, the planarizing layer 107 by dry etching using a mixed gas of oxygen gas and CF ₄ gas is patterned, followed by CF ₄ gas The silicon oxide film 106 is patterned by the used dry etching.

Thereafter, by using the three-layered film 120 as a mask and performing dry etching under the same conditions as in the first embodiment, the gold film 105 and the titanium film 104 are patterned, and the structure shown in FIG. can get.

When a gold wiring is formed on a base having a large step, if a gold film is etched using a photoresist or the like as a mask, a disconnection occurs at an edge portion P of the step as shown in FIGS. There is. However, in the present embodiment, the gold film 10 is formed using the three-layer laminated film 120 as a mask.
Since the etching of No. 5 is performed, disconnection can be prevented even at the edge portion of the step. Further, it was confirmed that even when the step (S in FIG. 6) was 2 μm or more, the disconnection of the gold film 105 did not occur.

The material of the flattening layer 107 is a heat treatment (baking for baking) at a relatively low temperature (400 ° C. or lower) so that the substrate 101, the gold film 105, and the titanium film 104 do not react. And silicon oxide film C
VD (Chemical Vapor Deposition) temperature (250 ° C)
In this case, a stable material is desirable. Therefore, the flattening layer 1
As a material of 07, a material which is cured by a heat treatment at 250 ° C. to 400 ° C. is preferable. In this embodiment, the case where polyimide is used as the material of the planarization layer 107 has been described; however, BCB (benzocyclobutene) can be used as the material.

Incidentally, the resist pattern 11 in FIG.
0 may be removed by ashing after patterning the silicon oxide film 108, and the flattening layer 10
7, the silicon oxide film 106 may be removed by etching.

(Fourth Embodiment) FIG. 8 is a sectional view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. Referring to FIG. 8, the semiconductor device of the present embodiment is different from the configuration of the second embodiment shown in FIG. 4 in that a titanium film 6 whose surface is oxidized is added. The titanium film 6 is formed between the gold film 4 and the silicon oxide film 5, and the material of the lower part 6a is made of titanium, and the material of the upper part 6b is made of titanium oxide. The thickness of the titanium film 6 whose surface is oxidized is, for example, 0.1 mm.
1 μm.

The remaining structure is substantially the same as that of the second embodiment described above, and therefore, the same members are denoted by the same reference characters and description thereof will not be repeated.

Next, the manufacturing method of the present embodiment will be described. FIG. 9 is a schematic sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. Referring to FIG. 9, a silicon oxide film 2 having a thickness of, for example, 0.2 μm, a titanium film 3 having a thickness of, for example, 0.1 μm, and a gold film 4 having a thickness of, for example, 1 μm are formed on compound semiconductor substrate 1. A titanium film 6 having a thickness of 0.1 μm is sequentially deposited. Next, the surface of the titanium film 6 is oxidized by being exposed to oxygen plasma. Thus, the lower portion 6a is made of titanium, and the upper portion 6b is made of a titanium film 6 made of titanium oxide.
Is formed.

On the titanium film 6, a silicon oxide film 5 having a thickness of, for example, 0.5 μm is deposited. On this silicon oxide film 5, a resist pattern 10 is formed by a usual photolithography technique. Using the resist pattern 10 as a mask, the silicon oxide film 5 is patterned by dry etching using CF ₄ gas. By performing dry etching under the same conditions as in the first embodiment using the patterned silicon oxide film 5 as a mask, titanium film 6, gold film 4 and titanium film 3 are continuously patterned, and the structure shown in FIG. Is obtained.

Referring to FIG. 8, when silicon oxide film 5 is directly deposited on gold film 4, the adhesion between gold film 4 and silicon oxide film 5 is not so good, so that a mask is formed during dry etching. There is a case where the problem that the pattern 5 is peeled off occurs. However, in the present embodiment, a titanium film 6 whose surface is oxidized is provided between the gold film 4 and the silicon oxide film 5. Therefore, the adhesion between the gold film 4 and the silicon oxide film 5 is improved, the peeling of the mask pattern 5 during the dry etching can be prevented, and the dry etching can be performed with good reproducibility.

In the present embodiment, the metal film 6 provided above and in contact with the gold film 4 is made of titanium whose surface is oxidized. However, the present invention is not limited to this. , Aluminum, tungsten, copper, silver, nickel, or a metal film of these alloys, and a similar effect can be obtained with these materials.

In particular, a titanium film and an aluminum film
If a minium film is used, these materials
However, a natural oxide film is formed on the surface. For this reason, metal film
After depositing titanium film or aluminum film as 6
By exposing it to the atmosphere, _TwoWhen exposed to plasma
Similar effects can be obtained. The metal film 6 is made of aluminum.
When using an aluminum film or a nickel film, these metals
Since it reacts with gold, as shown in FIG.
A bar made of titanium, platinum or tungsten
It is desirable to provide the rear metal 7.

(Fifth Embodiment) FIG. 11 is a sectional view schematically showing a configuration of a semiconductor device according to a fifth embodiment of the present invention. Referring to FIG. 11, the semiconductor device of the present embodiment is different from the configuration of the second embodiment shown in FIG. 4 in that a metal film 8 made of platinum or palladium is added. The metal film 8 is provided between the gold film 4 and the silicon oxide film 5 and has a thickness of, for example, 0.2 μm.

The remaining structure is substantially the same as that of the second embodiment, and therefore the same members are denoted by the same reference characters and description thereof will not be repeated.

Next, the manufacturing method of the present embodiment will be described. 12 and 13 show Embodiment 5 of the present invention.
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device in Step order. Referring to FIG. 12, a silicon oxide film 2 having a thickness of, for example, 0.2 μm is formed on a compound semiconductor substrate 1.
For example, a titanium film 3 having a thickness of 0.1 μm and
A gold film 4 having a thickness of μm, a platinum film 8 having a thickness of, for example, 0.2 μm, and a silicon oxide film 5 having a thickness of, for example, 0.5 μm are deposited in this order. A resist pattern 10 is formed on silicon oxide film 5 by a normal photolithography technique. Using this resist pattern 10 as a mask, CF ₄
Silicon oxide film 5 by dry etching using gas
Is patterned. Using the patterned silicon oxide film 5 as a mask, chlorine gas and silicon tetrachloride (SiC
l ₄ ) Dry etching of the platinum film 8 is performed using a mixed gas of gases. This etching is performed under the condition that the selectivity between the silicon oxide film 5 and the platinum film 8 is about 1.

Referring to FIG. 13, the platinum film 8 is patterned by this dry etching. Subsequently, by switching the etching gas to chlorine gas and performing dry etching under the same conditions as in the first embodiment, the gold film 4 and the titanium film 3 are patterned, and the configuration shown in FIG. 11 is obtained.

In this embodiment, a metal film 8 made of platinum or palladium is provided between the gold film 4 and the silicon oxide film 5 as shown in FIG. For this reason, the gold film 4
The adhesion between the silicon oxide film 5 and the silicon oxide film 5 is improved, and dry etching can be performed with good reproducibility.

In the etching of the gold film 4, when dry etching is performed using chlorine gas at a substrate temperature of 100 ° C. to 250 ° C., platinum chloride hardly volatilizes in this temperature range. It was found that the selectivity with respect to the gold film 4 (gold / platinum) was 20 or more. For this reason,
Even if the silicon oxide film 5 serving as a mask disappears during the etching of the gold film 4 as shown in FIG. 14, the platinum film 8 serves as a mask, so that the gold film 4 can be patterned without any problem. .

In FIG. 12, the silicon oxide film 5
Is deposited to have the same thickness as the platinum film 8,
At the stage where the etching of the gold film 4 is completed, the silicon oxide film 5 can be completely removed as shown in FIG. By doing so, the silicon oxide film 5 serving as a mask can be formed.
A separate removing step is not required, and the step can be simplified.

In this embodiment, a mixed gas of chlorine gas and silicon tetrachloride gas is used for dry etching of the platinum film 8, but argon gas, CCl ₄ , CCl ₂ , CC
Other chlorine-based gases such as l ₂ F ₂ , CCIF ₃ , and BCl ₃ can also be used.

(Embodiment 6) Referring to FIG. 11, the semiconductor device of the present embodiment differs from the configuration of Embodiment 5 in the thickness of metal film 8 made of platinum or palladium. The thickness of the metal film 8 is 0.5 nm or more and 5 nm or less.

The remaining structure is almost the same as the structure of the fifth embodiment, and a description thereof will be omitted.

Next, the manufacturing method of this embodiment will be described. Referring to FIG. 12, a silicon oxide film 2 having a thickness of, for example, 0.2 μm, a titanium film 3 having a thickness of, for example, 0.1 μm, and a gold film 4 having a thickness of, for example, 1 μm are formed on compound semiconductor substrate 1. A metal film 8 made of platinum having a thickness of 2 nm and a silicon oxide film 5 having a thickness of, for example, 0.5 μm are deposited in this order. A resist pattern 10 is formed on silicon oxide film 5 by a normal photolithography technique. Using this resist pattern 10 as a mask, CF
Dry etching using _four gases is performed on the silicon oxide film 5.

Referring to FIG. 13, the silicon oxide film 5 is patterned by this etching. By using the patterned silicon oxide film 5 as a mask, the metal film 8
The gold film 4 and the titanium film 3 are continuously patterned under the same etching conditions, and the configuration shown in FIG. 11 is obtained.

In the present embodiment, metal film 5 made of, for example, platinum or palladium is provided between gold film 4 and silicon oxide film 5. For this reason, the adhesion between the gold film 4 and the silicon oxide film 5 is improved, and the silicon oxide film 5 serving as a mask does not peel off during the etching, and etching with good reproducibility can be performed.

In the above-described manufacturing method, the thickness of the metal film 5 is 2 nm, but the thickness may be 0.5 nm or more and 5 nm or less. When the thickness of the metal film 8 is 0.5 nm or more, the effect of improving the adhesion between the silicon oxide film 5 and the gold film 4 is recognized.

The reason why the thickness of the metal film 8 is set to 5 nm or less is as follows. When the thickness of the gold film 8 is large, for example, 500 nm, the following problem may occur.

When the metal film (500 nm) made of platinum is dry-etched from the state of FIG. 12 using the silicon oxide film 5 as a mask, as shown in FIG. 15, a reactant 8a such as platinum and a chloride of platinum is formed as shown in FIG. Is redeposited on the side wall of the mask 5. When dry etching of the gold film 4 is performed in this state, as shown in FIG. 16, after the etching is completed, redeposits 8a remain and the etching shape of the gold film 4 and the like deteriorates. This deterioration of the etching shape becomes more remarkable as the thickness of the metal film 8 increases.

However, when the thickness of the metal film 8 is set to 5 nm or less, it is possible to prevent the reactant from being redeposited during the dry etching of the metal film 8 and to prevent the etching shape from being deteriorated.

Further, by setting the thickness of the metal film 8 to 5 nm or less, the metal film 8, the gold film 4, and the titanium film 3 are continuously etched under the dry etching condition of the gold film 4 described in the first embodiment. can do.

The metal films 8 of the fourth and sixth embodiments may be applied to the third embodiment shown in FIGS.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0092]

As described above, according to the present invention, since the gold film is patterned using the silicon oxide film as a mask, the selectivity between the silicon oxide film and the gold film in etching can be sufficiently increased. For this reason, even when a thick gold film is patterned, a thick resist is not required, and a fine pattern wiring can be formed with high accuracy, and disconnection of the gold film at a step edge portion can be prevented.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view showing a first step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a sectional view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 6 is a schematic sectional view showing a first step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a schematic sectional view showing a second step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 8 is a cross sectional view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device in the fourth embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view for describing a modification of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 11 is a cross sectional view schematically showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a schematic sectional view showing a first step of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 13 is a schematic sectional view showing a second step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 14 is a schematic cross sectional view for illustrating a modification of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 15 is a schematic sectional view illustrating a thickness of a metal film of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 16 is a schematic sectional view for illustrating the thickness of a metal film of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 17 is a cross-sectional view schematically showing a configuration of a conventional semiconductor device.

FIG. 18 is a first process chart for describing a problem of the conventional semiconductor device.

FIG. 19 is a second process diagram for describing the problem of the conventional semiconductor device.

[Explanation of symbols]

1,101 compound semiconductor substrate, 2,5,103,10
6,108 silicon oxide film, 3,6,104 titanium film, 4,105 gold film, 102 interlayer insulating film, 107
Planarization layer, 6,8 metal film, 7 barrier metal.

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Claims (10)

[Claims] 1. A semiconductor device having gold wiring, comprising: a patterned gold film; and a first silicon oxide film formed on the gold film in the same pattern as the gold film. 2. The method according to claim 1, wherein a second silicon oxide film having the same pattern as the gold film and a planarizing layer are sequentially provided between the gold film and the first silicon oxide film. A semiconductor device having the gold wiring described above. 3. The gold according to claim 1, wherein a metal film made of a material different from the gold film is provided so as to be in contact with the upper surface of the gold film and to have the same pattern as the gold film. A semiconductor device having a wiring. 4. The semiconductor device having gold wiring according to claim 3, wherein a surface of said metal film is oxidized. 5. The semiconductor device according to claim 3, wherein the material of the surface of the metal film is platinum or palladium. 6. The metal film has a thickness of 5 nm or less.
A semiconductor device having the gold wiring according to claim 3. 7. A step of forming a first silicon oxide film on a gold film, a step of patterning the first silicon oxide film, and a dry etching process using the patterned first silicon oxide film as a mask. And a step of patterning the gold film. 8. A second layer formed on the gold film after the formation of the gold film and before the formation of the first silicon oxide film.
Forming a silicon oxide film and a planarization layer in this order, the planarization layer and the second silicon oxide film being formed by the dry etching using the patterned first silicon oxide film as a mask. The method for manufacturing a semiconductor device having gold wiring according to claim 7, wherein the gold film and the gold film are sequentially patterned. 9. The manufacturing of a semiconductor device having gold wiring according to claim 7, further comprising a step of forming a metal film made of a material different from the gold film so as to be in contact with an upper surface of the gold film. Method. 10. The method according to claim 9, further comprising a step of oxidizing a surface of the metal film.