JP2002503844A5 - - Google Patents
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- Publication number
- JP2002503844A5 JP2002503844A5 JP2000531777A JP2000531777A JP2002503844A5 JP 2002503844 A5 JP2002503844 A5 JP 2002503844A5 JP 2000531777 A JP2000531777 A JP 2000531777A JP 2000531777 A JP2000531777 A JP 2000531777A JP 2002503844 A5 JP2002503844 A5 JP 2002503844A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12027598A | 1998-02-13 | 1998-02-13 | |
| US09/120,275 | 1998-02-13 | ||
| US09/110,518 | 1998-07-06 | ||
| US09/110,518 US6237083B1 (en) | 1998-02-13 | 1998-07-06 | Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence |
| PCT/US1999/003121 WO1999041659A1 (en) | 1998-02-13 | 1999-02-12 | Microprocessor including multiple register files occupying the same logical space |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002503844A JP2002503844A (ja) | 2002-02-05 |
| JP2002503844A5 true JP2002503844A5 (ja) | 2006-03-09 |
| JP3837289B2 JP3837289B2 (ja) | 2006-10-25 |
Family
ID=26808103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000531777A Expired - Fee Related JP3837289B2 (ja) | 1998-02-13 | 1999-02-12 | 同じ論理的空間を占有する複数のレジスタファイルを含むマイクロプロセッサ |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6237083B1 (ja) |
| EP (1) | EP1053522B1 (ja) |
| JP (1) | JP3837289B2 (ja) |
| KR (1) | KR100682635B1 (ja) |
| DE (1) | DE69901338T2 (ja) |
| WO (1) | WO1999041659A1 (ja) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205543B1 (en) * | 1998-12-03 | 2001-03-20 | Sun Microsystems, Inc. | Efficient handling of a large register file for context switching |
| US6412065B1 (en) * | 1999-06-25 | 2002-06-25 | Ip First, L.L.C. | Status register associated with MMX register file for tracking writes |
| US6647462B1 (en) * | 2000-06-29 | 2003-11-11 | Motorola, Inc. | Apparatus and a method for providing decoded information |
| US6748492B1 (en) * | 2000-08-07 | 2004-06-08 | Broadcom Corporation | Deterministic setting of replacement policy in a cache through way selection |
| US6732234B1 (en) | 2000-08-07 | 2004-05-04 | Broadcom Corporation | Direct access mode for a cache |
| US6848024B1 (en) | 2000-08-07 | 2005-01-25 | Broadcom Corporation | Programmably disabling one or more cache entries |
| US6748495B2 (en) | 2001-05-15 | 2004-06-08 | Broadcom Corporation | Random generator |
| US8578387B1 (en) * | 2007-07-31 | 2013-11-05 | Nvidia Corporation | Dynamic load balancing of instructions for execution by heterogeneous processing engines |
| US9304775B1 (en) | 2007-11-05 | 2016-04-05 | Nvidia Corporation | Dispatching of instructions for execution by heterogeneous processing engines |
| US7941644B2 (en) * | 2008-10-16 | 2011-05-10 | International Business Machines Corporation | Simultaneous multi-thread instructions issue to execution units while substitute injecting sequence of instructions for long latency sequencer instruction via multiplexer |
| US9411585B2 (en) | 2011-09-16 | 2016-08-09 | International Business Machines Corporation | Multi-addressable register files and format conversions associated therewith |
| US9727336B2 (en) * | 2011-09-16 | 2017-08-08 | International Business Machines Corporation | Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers |
| US8914615B2 (en) | 2011-12-02 | 2014-12-16 | Arm Limited | Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format |
| US20130339666A1 (en) * | 2012-06-15 | 2013-12-19 | International Business Machines Corporation | Special case register update without execution |
| GB2552154B (en) * | 2016-07-08 | 2019-03-06 | Advanced Risc Mach Ltd | Vector register access |
| US11327757B2 (en) * | 2020-05-04 | 2022-05-10 | International Business Machines Corporation | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files |
| US11561794B2 (en) * | 2021-05-26 | 2023-01-24 | International Business Machines Corporation | Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4597044A (en) | 1982-10-14 | 1986-06-24 | Honeywell Information Systems, Inc. | Apparatus and method for providing a composite descriptor in a data processing system |
| US4803622A (en) | 1987-05-07 | 1989-02-07 | Intel Corporation | Programmable I/O sequencer for use in an I/O processor |
| JP2884831B2 (ja) | 1991-07-03 | 1999-04-19 | 株式会社日立製作所 | 処理装置 |
| JPH05233281A (ja) | 1992-02-21 | 1993-09-10 | Toshiba Corp | 電子計算機 |
| EP0594240B1 (en) | 1992-10-19 | 2000-01-05 | Koninklijke Philips Electronics N.V. | Data processor with operation units sharing groups of register files |
| US5604912A (en) | 1992-12-31 | 1997-02-18 | Seiko Epson Corporation | System and method for assigning tags to instructions to control instruction execution |
| WO1994027216A1 (en) | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
| US5649174A (en) | 1994-12-09 | 1997-07-15 | Vlsi Technology Inc. | Microprocessor with instruction-cycle versus clock-frequency mode selection |
| US5956747A (en) * | 1994-12-15 | 1999-09-21 | Sun Microsystems, Inc. | Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines |
| US5701508A (en) | 1995-12-19 | 1997-12-23 | Intel Corporation | Executing different instructions that cause different data type operations to be performed on single logical register file |
| US5940859A (en) * | 1995-12-19 | 1999-08-17 | Intel Corporation | Emptying packed data state during execution of packed data instructions |
| US5889975A (en) | 1996-11-07 | 1999-03-30 | Intel Corporation | Method and apparatus permitting the use of a pipe stage having an unknown depth with a single microprocessor core |
| JP3578883B2 (ja) | 1997-01-31 | 2004-10-20 | 三菱電機株式会社 | データ処理装置 |
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1998
- 1998-07-06 US US09/110,518 patent/US6237083B1/en not_active Expired - Fee Related
-
1999
- 1999-02-12 KR KR1020007008827A patent/KR100682635B1/ko not_active IP Right Cessation
- 1999-02-12 DE DE69901338T patent/DE69901338T2/de not_active Expired - Fee Related
- 1999-02-12 WO PCT/US1999/003121 patent/WO1999041659A1/en active IP Right Grant
- 1999-02-12 EP EP99932527A patent/EP1053522B1/en not_active Expired - Lifetime
- 1999-02-12 JP JP2000531777A patent/JP3837289B2/ja not_active Expired - Fee Related