JP2002373962A - Printed wiring board and its manufacturing method - Google Patents

Printed wiring board and its manufacturing method

Info

Publication number
JP2002373962A
JP2002373962A JP2001181266A JP2001181266A JP2002373962A JP 2002373962 A JP2002373962 A JP 2002373962A JP 2001181266 A JP2001181266 A JP 2001181266A JP 2001181266 A JP2001181266 A JP 2001181266A JP 2002373962 A JP2002373962 A JP 2002373962A
Authority
JP
Japan
Prior art keywords
hole
wiring board
printed wiring
connection
terminal portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001181266A
Other languages
Japanese (ja)
Other versions
JP2002373962A5 (en
JP3994312B2 (en
Inventor
Kazumitsu Ishikawa
和充 石川
Yasuaki Nakamura
泰章 中村
Masayuki Sakurai
正幸 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc filed Critical Hitachi AIC Inc
Priority to JP2001181266A priority Critical patent/JP3994312B2/en
Publication of JP2002373962A publication Critical patent/JP2002373962A/en
Publication of JP2002373962A5 publication Critical patent/JP2002373962A5/ja
Application granted granted Critical
Publication of JP3994312B2 publication Critical patent/JP3994312B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board and its manufacturing method; in which 1) the connection reliability of the terminal parts on the upper and lower surfaces of an interposer substrate is enhanced; 2) high density micro size terminals (lands) can be designed in order to provide a fine pitch small area electrode of an electronic component or element thus realizing high density mounting; and 3) at the contact hole of the terminals on the upper and lower surface, the efficiency of boring work is enhanced while reducing the cost by reducing works for boring a micro hole and decreasing the number of contact holes significantly. SOLUTION: As a contact part for electrically conducting the connection terminal part 7 on the upper surface of a printed wiring board and the external connection terminal part on the lower surface, a contact part 16 is formed on the side face or the corner of the printed wiring board by cutting the substantially central part of a non-through contact hole where the upper and lower faces of a filler filling a plated through hole is covered with a metal conductor.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップ等の
電子部品や素子をプリント配線板であるインターポーザ
基板に実装する際に用いられるプリント配線板およびそ
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board used for mounting electronic components and elements such as semiconductor chips on an interposer substrate, which is a printed wiring board, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】例えば、半導体チップ等の電子部品やベ
アチップの素子をインターポーザ基板と呼ばれる中間基
板を介して親プリント配線板であるマザー基板上に実装
するチップ・オン・ボード(以下、COBと略称する)
実装法がある。このCOB実装法は、プリント配線板に
対面実装する面となる半導体チップの下面側の回路面に
設けられた各電極(以下、これをパッドと称する)上に
それぞれ突起状電極としてのバンプを形成し、このバン
プを形成した半導体チップをプリント配線板の部品実装
面上にフェースダウンして直接実装する実装方法であ
り、半導体チップ等を高密度で実装することができる利
点がある。
2. Description of the Related Art For example, a chip-on-board (hereinafter abbreviated as COB) in which electronic components such as semiconductor chips and bare chip elements are mounted on a mother board which is a parent printed wiring board via an intermediate board called an interposer board. Do)
There is an implementation method. In this COB mounting method, bumps are formed as protruding electrodes on each electrode (hereinafter referred to as a pad) provided on a circuit surface on the lower surface side of a semiconductor chip which is to be mounted on a printed wiring board. However, this is a mounting method in which the semiconductor chip on which the bumps are formed is directly mounted face down on the component mounting surface of the printed wiring board, and there is an advantage that the semiconductor chip and the like can be mounted at a high density.

【0003】従来は図7(a)に示すように、インター
ポーザ基板5には上面接続端子部(ランド)7と非貫通
接続穴16が設けられ、同図(b)に示すように、この
非貫通接続穴16の上端縁の全周にはリング状のランド
8が形成され、上面接続端子部(ランド)7と非貫通接
続穴16のリング状のランド8とは、配線パターン9を
介して導通されている。また、この非貫通接続穴16は
内側壁に形成したスルーホールめっきを介してインター
ポーザ基板5の下面に形成した下面の外部接続用端子部
6に電気的に接続されており、この非貫通接続穴16を
介して上下の端子部(ランド)7,6が電気的に接続さ
れている。
Conventionally, as shown in FIG. 7A, the interposer substrate 5 is provided with an upper surface connection terminal portion (land) 7 and a non-through connection hole 16, and as shown in FIG. A ring-shaped land 8 is formed all around the upper end edge of the through connection hole 16, and the upper surface connection terminal portion (land) 7 and the ring-shaped land 8 of the non-through connection hole 16 are interposed via the wiring pattern 9. Conducted. The non-through connection hole 16 is electrically connected to the external connection terminal portion 6 on the lower surface formed on the lower surface of the interposer substrate 5 through the through hole plating formed on the inner side wall. Upper and lower terminal portions (lands) 7 and 6 are electrically connected to each other through a connection 16.

【0004】また、図6に示すように、インターポーザ
基板5として、めっきスルーホール内に充填した充填材
の上下面を金属導体で覆った非貫通接続穴16、つまり
フラットスルーホールの金属導体を接続端子部となる上
面の端子部(ランド)7を形成し、電極間ピッチの狭ピ
ッチ化と図7に示す配線パターン9を省略し小面積化を
図るものである。例えば1個のインターポーザ基板5の
サイズが0.8×1.0mm、上下面の端子部のランド
7、6サイズ0.2×0.3mmの略中央部にフラット
スルーホール3を形成するため、微小穴径φ0.15
(レーザー穴明け)、10列×10段/シートとすれ
ば、穴径φ0.15のレーザー穴明けを400穴/シー
ト行わなければならない。さらに、プリント配線板の作
業サイズを330×330mm/ボードとすれば、約7
80シート/ボード=312000穴/ボードのぼうだ
いな穴数となる。
As shown in FIG. 6, a non-through connection hole 16 in which the upper and lower surfaces of a filler filled in a plated through hole are covered with a metal conductor, that is, a metal conductor of a flat through hole is connected as the interposer substrate 5. A terminal portion (land) 7 on the upper surface serving as a terminal portion is formed, and the pitch between electrodes is reduced and the wiring pattern 9 shown in FIG. 7 is omitted to reduce the area. For example, since the size of one interposer substrate 5 is 0.8 × 1.0 mm, the land 7 of the terminal part on the upper and lower surfaces, and the flat through hole 3 is formed substantially at the center of the size of 0.2 × 0.3 mm, Micro hole diameter φ0.15
(Laser Drilling) If 10 rows × 10 rows / sheet, laser drilling with a hole diameter φ0.15 must be performed 400 holes / sheet. Furthermore, if the working size of the printed wiring board is 330 × 330 mm / board, about 7
80 sheets / board = 312000 holes / board.

【0005】[0005]

【発明が解決しようとする課題】近年、エレクトロニク
ス機器は軽薄短小化の傾向がさらに強まり、高機能集積
化および信号処理の高速化が進み、これにともなって半
導体チップ等の電子部品やベアチップの素子の電極間ピ
ッチも狭ピッチ化と小面積化が進んでいる。このような
狭ピッチ化された各電子部品や素子を接続端子部に対応
させてランドや配線パターンおよび微小穴径のレーザー
穴をプリント配線板上に複数形成することは高度な特殊
技術を要するだけでなく、上面端子部(上面ランド)と
下面端子部(下面ランド)とを電気的に導通する接続信
頼性の悪化、さらにコストアップにもつながっていた。
In recent years, the trend of electronic devices to become lighter, thinner and smaller has become more and more intense, and high-performance integration and high-speed signal processing have been promoted. Also, the pitch between electrodes has been narrowed and the area has been reduced. Forming a plurality of lands, wiring patterns, and laser holes with a small hole diameter on a printed wiring board by associating each electronic component or element with such a narrow pitch with a connection terminal portion requires only advanced special technology. Instead, the reliability of the connection for electrically connecting the upper terminal portion (upper land) and the lower terminal portion (lower land) is deteriorated, and the cost is further increased.

【0006】本発明は上記した従来の問題に鑑みなされ
たものであり、第1の目的はインターポーザ基板の上下
面導体(端子部)の接続信頼性を向上させることにあ
る。第2の目的は高密度かつ微小サイズの端子部(ラン
ド)の設計を可能とし、電子部品や素子の電極間の狭ピ
ッチ化と小面積化を図り、高密度実装を可能にする。第
3の目的は上下面端子部の接続穴において、微小穴径の
加工削減と接続穴数の大幅低減により穴明け作業効率の
向上とコストダウンを図ることにある。
The present invention has been made in view of the above-mentioned conventional problems, and a first object is to improve the connection reliability of upper and lower surface conductors (terminal portions) of an interposer substrate. A second object is to enable the design of high-density and minute-sized terminal portions (lands), to reduce the pitch and the area between electrodes of electronic components and elements, and to realize high-density mounting. A third object of the present invention is to improve drilling work efficiency and reduce costs by reducing the processing of minute hole diameters and greatly reducing the number of connection holes in the connection holes of the upper and lower terminals.

【0007】[0007]

【課題を解決するための手段】この目的を達成するため
に、請求項1に係る発明は、プリント配線板の外周また
は複数に分割する分割線の近傍に位置するプリント配線
板の上面接続端子部と下面の外部接続用端子部とを電気
的に導通する接続部として、めっきスルーホール内に充
填した充填材の上下面を金属導体で覆った非貫通接続
穴、つまりフラットスルーホールの略中央部を分割切断
して該プリント配線板の側面または角部に接続部を形成
するものである。前記非貫通接続穴の端縁の一部と重ね
て(接続して)プリント配線板の上下面に端子部(ラン
ド)を形成したものである。したがって、非貫通接続穴
上の全面にランドを形成する必要がないから高密度かつ
微小サイズの端子部(ランド)の設計を可能とする。
In order to achieve this object, the invention according to claim 1 is directed to an upper surface connection terminal portion of a printed wiring board located on the outer periphery of the printed wiring board or near a dividing line for dividing the printed wiring board into a plurality of parts. Non-through connection hole, in which the upper and lower surfaces of the filler filled in the plated through hole are covered with a metal conductor, that is, approximately the center of the flat through hole Is divided and cut to form a connection portion on a side surface or a corner portion of the printed wiring board. A terminal portion (land) is formed on the upper and lower surfaces of the printed wiring board so as to be overlapped (connected) with a part of the edge of the non-through connection hole. Therefore, since it is not necessary to form a land on the entire surface of the non-through connection hole, it is possible to design a high-density and minute-sized terminal portion (land).

【0008】また、請求項2に係る発明は、プリント配
線板の上面導体である接続端子部と下面導体である外部
接続用端子部とを電気的に導通する接続部として、接続
穴1個で分割切断後の2〜8個分の接続部機能を有する
ことを特徴とするプリント配線板である。つまり、接続
穴としてフラットスルーホールの略中央部を複数に分割
切断して該プリント配線板の側面または角部に接続部を
形成するものである。但し、プリント配線板の上面の接
続部として、電子部品や素子を搭載するサイズの関係か
ら該接続部と端子部(ランド)を区別して位置を変える
こともある。
According to a second aspect of the present invention, a single connection hole is provided as a connection portion for electrically connecting a connection terminal portion as an upper surface conductor and an external connection terminal portion as a lower surface conductor of a printed wiring board. A printed wiring board having a connection portion function for 2 to 8 pieces after division and cutting. That is, a substantially central portion of the flat through hole is cut into a plurality of portions as connection holes, and connection portions are formed on side surfaces or corner portions of the printed wiring board. However, as the connection part on the upper surface of the printed wiring board, the connection part and the terminal part (land) may be distinguished from each other and their positions may be changed depending on the size of mounting electronic components and elements.

【0009】また、請求項3に係る発明は、フラットス
ルーホールを形成する工程と、前記フラットスルーホー
ルの略中央部を横切る分割線に金属導体部が接しないよ
うに分割線の両側に絶縁部(間隔)を設けるためエッチ
ングする工程と、前記分割線で各電子部品や素子を接続
端子部に実装後に分割切断する工程と、からフラットス
ルーホールの一部と接する上面接続端子部と下面の外部
接続用端子部とを形成するプリント配線板の製造方法で
ある。したがって、非貫通接続穴上の全周にランドが形
成されないから、微小サイズの端子部(ランド)とする
ことが出来、端子ピッチを極力狭くすることが可能にな
る。
According to a third aspect of the present invention, there is provided a method of forming a flat through hole, wherein insulating portions are provided on both sides of the dividing line so that the metal conductor does not come into contact with the dividing line crossing substantially the center of the flat through hole. A step of etching to provide (interval), and a step of dividing and cutting each electronic component or element on the connection terminal part after the division line, from the upper connection terminal part in contact with a part of the flat through hole and the outside of the lower surface. This is a method for manufacturing a printed wiring board for forming a connection terminal portion. Therefore, since no land is formed on the entire periphery of the non-through connection hole, a terminal portion (land) having a very small size can be obtained, and the terminal pitch can be reduced as much as possible.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。図1は本発明に係る個別のインター
ポーザ基板を10列×10段/シートとシート状に継げ
た場合の平面図である。図2は図1における個別のイン
ターポーザ基板5を拡大した本発明に係るインターポー
ザ基板の要部を示す平面図、図3(b)は本発明に係る
インターポーザ基板の図3(a)の平面図に対比する断
面図、図4は図2における個別のインターポーザ基板を
拡大して示す斜視図である。図5は本発明に係る実施例
2の個別のインターポーザ基板の平面図である。これら
の図において、上述した図6ないし図7に示す従来技術
において説明した同一または同等の部材については同一
の符号を付し詳細な説明は適宜省略する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a case where individual interposer substrates according to the present invention are joined in a sheet shape with 10 rows × 10 steps / sheet. FIG. 2 is a plan view showing an essential part of the interposer substrate according to the present invention in which the individual interposer substrate 5 in FIG. 1 is enlarged, and FIG. 3B is a plan view of FIG. 3A of the interposer substrate according to the present invention. FIG. 4 is an enlarged perspective view showing an individual interposer substrate in FIG. FIG. 5 is a plan view of an individual interposer substrate according to the second embodiment of the present invention. In these drawings, the same or equivalent members described in the prior art shown in FIGS. 6 and 7 described above are denoted by the same reference numerals, and detailed description will be appropriately omitted.

【0011】まず、図1のインターポーザ基板5をシー
ト状に継げた平面図を用いて、本発明に係るインターポ
ーザ基板の製造方法などの状況を説明する。同図におい
て、シート状基板2にNC穴明け機によってガラス基材
エポキシ樹脂やBTレジン等の絶縁基板1の外周と複数
の個別のインターポーザ基板5に分割する分割線12の
交点や分割線12相互の交点および外周の角部に貫通穴
φ0.5を穿孔し、無電解銅めっき処理、電解銅めっき
処理によって、貫通穴の内側壁と絶縁基板の表面にめっ
き導体を形成し、貫通接続穴を形成する。めっきスルー
ホールである貫通接続穴内に充填材を充填し、穴埋め・
硬化および研磨を行って、非貫通接続穴16を形成し、
第2の無電解銅めっき処理によって、めっきスルーホー
ル(貫通接続穴)内に充填した充填材の上下面を金属導
体で覆った非貫通接続穴16の表面と絶縁基板の表面に
めっき導体を形成する。つまりフラットスルーホール3
を形成する。
First, the situation of the method for manufacturing an interposer substrate according to the present invention will be described with reference to a plan view in which the interposer substrate 5 of FIG. In FIG. 1, the outer periphery of an insulating substrate 1 such as a glass-based epoxy resin or BT resin is interspersed with a plurality of individual interposer substrates 5 and the dividing lines 12 are formed on a sheet-like substrate 2 by an NC drilling machine. A through hole φ0.5 is drilled at the intersection of the outer periphery and the corner of the outer periphery, and a plating conductor is formed on the inner wall of the through hole and the surface of the insulating substrate by electroless copper plating and electrolytic copper plating to form a through connection hole. Form. Fill the filling connection holes, which are plated through holes, with filling material.
Hardening and polishing to form a non-through connection hole 16;
The second electroless copper plating process forms a plated conductor on the surface of the non-through connection hole 16 in which the upper and lower surfaces of the filler filled in the plated through hole (through connection hole) are covered with a metal conductor and on the surface of the insulating substrate. I do. In other words, flat through hole 3
To form

【0012】次に、前記フラットスルーホール3の略中
央部を横切る分割線に金属導体部が接しないように分割
線の両側にエッチング処理で絶縁部(間隔)を設け、同
時にこの分割線の近傍にプリント配線板の所定の上面接
続端子部7と下面の外部接続用端子部6となる端子部
(ランド)をエッチングによって形成する。その後、各
電子部品や素子を接続端子部に実装してから前記分割線
12をダイサーでダイシングカットして個々のインター
ポーザ基板に分割する分割切断工程と、からフラットス
ルーホールの一部と接する上面接続端子部と下面の外部
接続用端子部とを形成するプリント配線板の製造方法で
ある。
Next, insulating portions (intervals) are provided on both sides of the dividing line by etching so that the metal conductor does not come into contact with the dividing line crossing substantially the center of the flat through hole 3, and at the same time, the vicinity of the dividing line Then, terminal portions (lands) to be predetermined upper surface connection terminal portions 7 and lower surface external connection terminal portions 6 of the printed wiring board are formed by etching. After that, each electronic component or element is mounted on the connection terminal portion, and then the dividing line 12 is diced and cut with a dicer to divide it into individual interposer substrates. This is a method of manufacturing a printed wiring board in which a terminal portion and an external connection terminal portion on the lower surface are formed.

【0013】例えば、従来と同じ仕様になるように、1
個のインターポーザ基板5のサイズが0.8×1.0m
m、上下面の端子部のランドサイズ0.2×0.3m
m、10列×10段/シートとするとφ0.5の貫通穴
数が121穴/シート(94380穴/ボード)となり
従来(400穴/シート.312000穴/ボード)に
比べ約30%の穴数で上下面端子部を電気的に導通する
接続機能を達成できる。さらに穴明け加工がレーザー加
工からNC穴明け加工に変更でき、重ね枚数も1枚から
5〜10枚にすることが可能となった。つまり、図1の
本発明に係るインターポーザ基板の平面図において、個
別のインターポーザ基板5に縦.横に交差する分割線の
交点に位置するフラットスルーホール1穴(個)で片面
4個(上下面で8個)の端子部を電気的に導通する効率
のよい接続部の機能を有する。
For example, 1
The size of each interposer substrate 5 is 0.8 × 1.0 m
m, land size of the upper and lower terminals 0.2 x 0.3m
m, 10 rows × 10 steps / sheet, the number of through holes of φ0.5 is 121 holes / sheet (94380 holes / board), which is about 30% of the conventional (400 holes / sheet. 312000 holes / board). Thus, a connection function of electrically connecting the upper and lower terminals can be achieved. Furthermore, the drilling process can be changed from laser processing to NC drilling, and the number of layers can be reduced from one to five to ten. That is, in the plan view of the interposer substrate according to the present invention of FIG. One hole (piece) of the flat through hole located at the intersection of the dividing lines crossing sideways has the function of an efficient connection part that electrically connects four (eight on the top and bottom) terminals on one side.

【0014】このとき、図2に示すように、非貫通接続
穴16の上端縁の一部と重ねて接するようにして、分割
線の近傍にプリント配線板の上面接続端子部7と下面の
外部接続用端子部となる端子部(ランド)を形成する。
すなわち、個別のインターポーザ基板5の角部に4個の
端子部をプリント配線板の上下面の略同一位置に配置さ
れ、かつプリント配線板の外周端面に接しないように形
成する。非貫通接続穴16の上端縁の一部に端子部(ラ
ンド)を直接電気的に接続することにより、充填材の表
面と非貫通接続穴16の上端縁の全周に電極となるラン
ドを形成するようなことがなく、かつ端子部(ランド)
と非貫通接続穴16とを接続するための配線パターンが
不要になる。また、上面接続端子部7と下面の外部接続
用端子部6と電気的に接続する接続部の貫通穴はφ0.
5と大きい径であるため、穴明け加工、無電解銅めっき
処理、電解銅めっき処理が簡単で管理が楽になり、接続
信頼性の高いめっき導体を形成することが出来る。
At this time, as shown in FIG. 2, the upper connection terminal portion 7 of the printed wiring board and the outer surface A terminal portion (land) to be a connection terminal portion is formed.
That is, four terminal portions are formed at substantially the same positions on the upper and lower surfaces of the printed wiring board at the corners of the individual interposer substrate 5 and formed so as not to contact the outer peripheral end surface of the printed wiring board. By directly electrically connecting a terminal portion (land) to a part of the upper end edge of the non-through connection hole 16, a land serving as an electrode is formed on the entire surface of the filler and the upper end edge of the non-through connection hole 16. And the terminal part (land)
A wiring pattern for connecting the non-penetrating connection hole 16 with the wiring pattern becomes unnecessary. The through hole of the connection part electrically connected to the upper connection terminal part 7 and the external connection terminal part 6 on the lower surface has a diameter of φ0.
Since the diameter is as large as 5, drilling, electroless copper plating, and electrolytic copper plating are simple and easy to manage, and a plated conductor with high connection reliability can be formed.

【0015】このように本発明では、図3に示すよう
に、フラットスルーホールの略中央部を横切る縦.横に
交差する分割線に金属導体部が接しないように分割線の
両側にエッチング処理で絶縁部(間隔)を設けるため、
上面接続端子部7および下面の外部接続用端子部6がプ
リント配線板の外周端面に接しない。さらに、非貫通接
続穴16の端縁の約1/4円周部と重ねてプリント配線
板の上下面に端子部(ランド)を形成したもの(フラッ
トスルーホールの1/4分割)であるにもかかわらず上
下面端子部の形状は正確な方形.円形.長円形で、かつ
微小サイズの端子部(ランド)の設計を可能とする。し
たがって、高密度かつ微小サイズの端子部として、例え
ばランドサイズ0.1×0.15mm(従来サイズの1
/4の面積)、および端子ピッチを0.5mmから0.
3mmとする設計が可能となる。
As described above, according to the present invention, as shown in FIG. In order to provide insulating parts (intervals) by etching on both sides of the dividing line so that the metal conductor does not touch the dividing line that crosses sideways,
The upper surface connection terminal portion 7 and the external connection terminal portion 6 on the lower surface do not contact the outer peripheral end surface of the printed wiring board. Furthermore, the terminal portion (land) is formed on the upper and lower surfaces of the printed wiring board so as to overlap with the approximately 1/4 circumferential portion of the edge of the non-through connection hole 16 (1/4 division of the flat through hole). Nevertheless, the shape of the upper and lower terminals is an accurate square. Round. It is possible to design a terminal part (land) having an oval shape and a minute size. Therefore, as a high-density and minute-sized terminal portion, for example, a land size of 0.1 × 0.15 mm (1 size of the conventional size)
/ 4 area), and the terminal pitch from 0.5 mm to 0.5 mm.
A design of 3 mm is possible.

【0016】また、図4のインターポーザ基板を拡大し
て示す斜視図のように、前記で説明した非貫通接続穴1
6の端縁の1/4円周部以下である約1/8円周部と重
ねてプリント配線板の上下面に端子部(ランド)7,6
を形成しても高い接続信頼性が得ることが確認できた。
従って、高密度かつ微小サイズの端子部と端子ピッチを
狭くすることにより高密度実装が可能になる。つまり、
フラットスルーホール(接続穴)1個で2〜8個分の接
続部の機能を有することができる。
Further, as shown in an enlarged perspective view of the interposer substrate of FIG.
Terminal portions (lands) 7, 6 on the upper and lower surfaces of the printed wiring board so as to overlap with about 1/8 of the circumferential edge of the edge of the 6 or less.
It was confirmed that high connection reliability could be obtained even when forming.
Therefore, high-density mounting is possible by narrowing the terminal pitch between the high-density and minute-sized terminal portions. That is,
One flat through hole (connection hole) can have the function of 2 to 8 connection portions.

【0017】図5は本発明の第2の実施の形態を示す1
個分のインターポーザ基板要部を拡大して示す平面図で
ある。この第2の実施の形態においては、非貫通接続穴
16をシート状に継げたインターポーザ基板5に縦.横
に交差する分割線の交点の非貫通接続穴16aと交点以
外の直線部に非貫通接続穴16bの中心が位置するよう
に形成したものである。この場合にも、非貫通接続穴1
6bを分割切断した接続部をプリント配線板の外周側面
に設置することができるから、端子数の多い電子部品や
素子の高密度実装が可能になる。また、本実施の形態で
は、両面プリント配線板について説明したが、多層プリ
ント配線板にも適用できる。
FIG. 5 shows a second embodiment of the present invention.
It is a top view which expands and shows the principal part of an interposer board | substrate. In the second embodiment, the non-penetrating connection holes 16 are vertically connected to the interposer substrate 5 in a sheet shape. It is formed so that the center of the non-penetrating connection hole 16b is located at the non-penetrating connection hole 16a at the intersection of the dividing lines that intersect horizontally and at a straight line portion other than the intersection. In this case also, the non-through connection hole 1
Since the connection portion obtained by dividing and cutting 6b can be installed on the outer peripheral side surface of the printed wiring board, high-density mounting of electronic components and elements having a large number of terminals becomes possible. Further, in the present embodiment, the double-sided printed wiring board has been described, but the present invention can also be applied to a multilayer printed wiring board.

【0018】但し、プリント配線板の上面の接続部とし
て、電子部品や素子を搭載するサイズの関係から該接続
部と端子部(ランド)を区別して位置を変えることもあ
る。例えば、ベアチップ素子が小さくインターポーザ基
板の下面の外部接続用端子と電極間ピッチを変える必要
がある場合、上面の接続部より内側にワイヤーボンデン
グ用の端子部(ランド)を形成する。
However, as the connection portion on the upper surface of the printed wiring board, the connection portion and the terminal portion (land) may be distinguished from each other and their positions may be changed depending on the size of mounting electronic components and elements. For example, when the bare chip element is small and the pitch between the external connection terminals and the electrodes on the lower surface of the interposer substrate needs to be changed, a terminal portion (land) for wire bonding is formed inside the connection portion on the upper surface.

【0019】[0019]

【発明の効果】以上説明したように本発明によれば、接
続信頼性が向上するだけでなく、高密度設計、高密度実
装が可能になり、作業効率の向上とコストダウンも達成
できる。
As described above, according to the present invention, not only connection reliability can be improved, but also high-density design and high-density mounting can be performed, and work efficiency can be improved and cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明に係る個別のインターポーザ基板をシ
ート状に継げた場合の平面図である。
FIG. 1 is a plan view when individual interposer substrates according to the present invention are joined in a sheet shape.

【図2】 図1における1個のインターポーザ基板を拡
大した要部を示す平面図である。
FIG. 2 is a plan view showing an enlarged main part of one interposer substrate in FIG. 1;

【図3】 インターポーザ基板の平面図と断面図であ
る。
FIG. 3 is a plan view and a cross-sectional view of an interposer substrate.

【図4】 図2における個別のインターポーザ基板を拡
大して示す斜視図である。
FIG. 4 is an enlarged perspective view showing an individual interposer substrate in FIG. 2;

【図5】 本発明の第2の実施の形態を拡大して示す平
面図である。
FIG. 5 is an enlarged plan view showing a second embodiment of the present invention.

【図6】 従来のフラットスルーホールのインターポー
ザ基板を示す平面図である。
FIG. 6 is a plan view showing a conventional flat through-hole interposer substrate.

【図7】 従来のインターポーザ基板を示す平面図であ
る。
FIG. 7 is a plan view showing a conventional interposer substrate.

【符号の説明】[Explanation of symbols]

2…シート状基板、3…フラットスルーホール、5…イ
ンターポーザ基板、6、7…端子部(ランド)、16…
非貫通接続穴。
2 ... sheet-like substrate, 3 ... flat through hole, 5 ... interposer substrate, 6, 7 ... terminal (land), 16 ...
Non-through connection hole.

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA24 GG20 5E338 BB31 EE60  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E317 AA24 GG20 5E338 BB31 EE60

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 プリント配線板の外周または複数に分割
する分割線の近傍に位置するプリント配線板の上面端子
部と下面端子部とを電気的に導通する接続部として、フ
ラットスルーホール(めっきスルーホール内に充填した
充填材の上下面を金属導体で覆った非貫通接続穴)を分
割切断して該プリント配線板の側面または角部に接続部
を形成することを特徴とするプリント配線板。
A flat through-hole (plating through) is provided as a connecting portion for electrically connecting an upper surface terminal portion and a lower surface terminal portion of the printed wiring board located on the outer periphery of the printed wiring board or in the vicinity of a dividing line to be divided into a plurality of parts. A printed wiring board characterized in that a connection portion is formed on a side surface or a corner of the printed wiring board by dividing and cutting a non-through connection hole in which the upper and lower surfaces of a filler filled in a hole are covered with a metal conductor.
【請求項2】 プリント配線板の上面導体と下面導体と
を電気的に導通する接続部として、接続穴1個で分割切
断後の2〜8個分の接続部の機能を有することを特徴と
するプリント配線板。
2. A connection portion for electrically connecting an upper surface conductor and a lower surface conductor of a printed wiring board has a function of two to eight connection portions after dividing and cutting with one connection hole. Printed wiring board.
【請求項3】 フラットスルーホールを形成する工程
と、前記フラットスルーホールの略中央部を横切る分割
線の両側をエッチングする工程と、前記分割線で分割切
断する工程と、からフラットスルーホールの一部と接す
る上面接続端子部と下面の外部接続用端子部とを形成す
ることを特徴とするプリント配線板の製造方法。
3. A flat through hole comprising: a step of forming a flat through hole; a step of etching both sides of a dividing line crossing a substantially central portion of the flat through hole; and a step of dividing and cutting by the dividing line. A method for manufacturing a printed wiring board, comprising: forming an upper surface connection terminal portion in contact with a portion and a lower surface external connection terminal portion.
JP2001181266A 2001-06-15 2001-06-15 Printed wiring board, manufacturing method thereof, and interposer substrate Expired - Fee Related JP3994312B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001181266A JP3994312B2 (en) 2001-06-15 2001-06-15 Printed wiring board, manufacturing method thereof, and interposer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001181266A JP3994312B2 (en) 2001-06-15 2001-06-15 Printed wiring board, manufacturing method thereof, and interposer substrate

Publications (3)

Publication Number Publication Date
JP2002373962A true JP2002373962A (en) 2002-12-26
JP2002373962A5 JP2002373962A5 (en) 2004-10-28
JP3994312B2 JP3994312B2 (en) 2007-10-17

Family

ID=19021560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001181266A Expired - Fee Related JP3994312B2 (en) 2001-06-15 2001-06-15 Printed wiring board, manufacturing method thereof, and interposer substrate

Country Status (1)

Country Link
JP (1) JP3994312B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005029581A1 (en) 2003-09-24 2005-03-31 Ibiden Co.,Ltd. Interposer and multilayer printed wiring board
JP2011181700A (en) * 2010-03-01 2011-09-15 Molex Inc Spacer
US10056322B2 (en) 2014-03-31 2018-08-21 Toppan Printing Co., Ltd. Interposers, semiconductor devices, method for manufacturing interposers, and method for manufacturing semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005029581A1 (en) 2003-09-24 2005-03-31 Ibiden Co.,Ltd. Interposer and multilayer printed wiring board
JP2011181700A (en) * 2010-03-01 2011-09-15 Molex Inc Spacer
US10056322B2 (en) 2014-03-31 2018-08-21 Toppan Printing Co., Ltd. Interposers, semiconductor devices, method for manufacturing interposers, and method for manufacturing semiconductor devices

Also Published As

Publication number Publication date
JP3994312B2 (en) 2007-10-17

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