JP2002373952A - Method for manufacturing hermetically sealed ic package - Google Patents

Method for manufacturing hermetically sealed ic package

Info

Publication number
JP2002373952A
JP2002373952A JP2001182439A JP2001182439A JP2002373952A JP 2002373952 A JP2002373952 A JP 2002373952A JP 2001182439 A JP2001182439 A JP 2001182439A JP 2001182439 A JP2001182439 A JP 2001182439A JP 2002373952 A JP2002373952 A JP 2002373952A
Authority
JP
Japan
Prior art keywords
hermetically sealed
manufacturing
package
substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001182439A
Other languages
Japanese (ja)
Other versions
JP4813692B2 (en
Inventor
Takashi Hosaka
俊 保坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2001182439A priority Critical patent/JP4813692B2/en
Publication of JP2002373952A publication Critical patent/JP2002373952A/en
Application granted granted Critical
Publication of JP4813692B2 publication Critical patent/JP4813692B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a hermetically sealed IN package with enhanced productivity and reduced manufacturing cost. SOLUTION: A large number of chips are mounted in a substrate and after the internal electrode wiring of the substrate is connected to the electrodes of the IC chip through wires, the substrate is coated entirely with a photosensitive substance and the IC chip is surrounded by the frame of a photosensitive substance using photoetching before being bonded with a lid. Finally, the substrate is cut at an intermediate position of the photosensitive substance thus producing individual IC packages.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は気密封止ＩＣパッケ
ージの製造方法に関する。The present invention relates to a method for manufacturing a hermetically sealed IC package.

【０００２】[0002]

【従来の技術】これまでの気密封止ＩＣパッケージは図
に示すように、枠４７を有する個片の基板４１にＩＣチ
ップ４５をのせワイヤ４６をはり、枠４７にあわせるよ
うに板状のふた４９をのせていた。2. Description of the Related Art As shown in FIG. 1, a conventional hermetically sealed IC package has an IC chip 45 mounted on an individual substrate 41 having a frame 47 and a wire 46 mounted thereon. 49 was on it.

【０００３】[0003]

【発明が解決しようとする課題】従来の気密封止ＩＣパ
ッケージは、１個1個別別に製造されているため生産性
が著しく低く、それゆえ非常に高価なものとなってい
た。The conventional hermetically sealed IC packages are manufactured individually and individually, resulting in extremely low productivity and, therefore, very expensive.

【０００４】[0004]

【課題を解決するための手段】上記の問題点を解決する
ために、本発明は複数以上のＩＣチップを載せられる基
板を用い、感光性物質をＩＣチップ間に厚く形成し、板
状のふたを被せた後で、基板を切断することにより１個
1個のＩＣパッケージにする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention uses a substrate on which a plurality of IC chips are mounted, a photosensitive substance is formed thick between the IC chips, and a plate-shaped lid is provided. And then cut the board to remove
Make one IC package.

【０００５】[0005]

【発明の実施の形態】本発明は、ＩＣチップの表面を空
気などの気体で取り囲んだ気体封止型のパッケージの製
造方法に関するものである。以下にこの発明の実施例を
図面に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a method for manufacturing a gas-sealed package in which the surface of an IC chip is surrounded by a gas such as air. Embodiments of the present invention will be described below with reference to the drawings.

【０００６】図１は、本発明の製造方法の工程順を示す
ＩＣパッケージの断面図を示す。図１(ａ)に示すよう
に、外部電極１２と内部電極配線１３を有する基板１１
が用意される。この基板内には複数以上のたくさんのＩ
Ｃチップが搭載され、最終的に個片にされる。従って基
板のサイズは大型であり、外部電極１２も内部電極配線
１３も繰り返しのパターンとなっている。基板１１の材
料は、セラミックやガラスエポキシやポリイミドやガラ
スなどが挙げられる。FIG. 1 is a sectional view of an IC package showing a process sequence of the manufacturing method of the present invention. As shown in FIG. 1A, a substrate 11 having an external electrode 12 and an internal electrode wiring 13
Is prepared. There are more than one I
The C chip is mounted, and is finally divided into individual pieces. Therefore, the size of the substrate is large, and the external electrode 12 and the internal electrode wiring 13 have a repeating pattern. The material of the substrate 11 includes ceramic, glass epoxy, polyimide, glass, and the like.

【０００７】次に図１(ｂ)に示すように、ＩＣチップ１
５を内部電極配線の所望の位置に接着する。尚、ＩＣチ
ップ１５の接着する位置には、内部電極配線１３はなく
て良い場合もある。たとえば、ＩＣチップの表面をでき
るだけ低くする必要がある場合や、ＩＣチップを電気的
に導通する必要がない場合や、ＩＣチップを放熱する必
要があまりない場合などである。次にＩＣチップ１５の
表面の電極と内部電極配線とをワイヤ１６で接続する。
このワイヤの材料として、金(Ａｕ)、金合金、アルミニ
ウム(Ａｌ)、アルミニウム合金、銅(Ｃｕ)、銅合金など
の金属が使われる。次に図１(ｃ)に示すように感光性物
質１７を塗布する。この感光性物質１７は塗布する時に
は液状なので、ＩＣチップ１５を移動させたり、ＩＣチ
ップ１５にダメッジを与えたり、ワイヤ１６を曲げた
り、ワイヤにダメッジを与えたり、ワイヤと電極配線お
よびＩＣとの接着場所にダメッジを与えたりすることは
ない。この感光性物質１７として、ネガレジスト、ポジ
レジスト、感光性ポリイミドなどがある。また、塗布す
る感光性物質１７の厚みは、最終的にワイヤ１６の最も
高い所より高くなるように設計されなければならない。[0007] Next, as shown in FIG.
5 is bonded to a desired position of the internal electrode wiring. In some cases, the internal electrode wiring 13 may not be provided at the position where the IC chip 15 is bonded. For example, there is a case where the surface of the IC chip needs to be as low as possible, a case where there is no need to electrically conduct the IC chip, and a case where there is little need to radiate the heat of the IC chip. Next, the electrodes on the surface of the IC chip 15 and the internal electrode wiring are connected by wires 16.
As a material of the wire, a metal such as gold (Au), a gold alloy, aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy is used. Next, a photosensitive substance 17 is applied as shown in FIG. Since the photosensitive material 17 is in a liquid state when applied, the IC chip 15 is moved, the IC chip 15 is damaged, the wire 16 is bent, the wire is damaged, and the wire and the electrode wiring and the IC are connected. No damaging is given to the gluing place. The photosensitive material 17 includes a negative resist, a positive resist, and a photosensitive polyimide. Also, the thickness of the photosensitive material 17 to be applied must be designed so as to be finally higher than the highest point of the wire 16.

【０００８】次に図１(ｄ)に示すように、ＩＣチップ１
５、ワイヤ１６のある部分が露出されるように作成され
たマスク１８を用いて光をあてる。ネガ型の感光性物質
では光があたる所が硬化する。ポジ型の場合は、逆に光
があたらない所が硬化する。Next, as shown in FIG.
5. Light is illuminated using a mask 18 made so that a certain portion of the wire 16 is exposed. In the case of a negative-type photosensitive material, a portion exposed to light cures. In the case of the positive type, on the other hand, the area where no light is irradiated cures.

【０００９】次に図１(ｅ)に示すように、現像すること
により、ＩＣチップ１５のある所の感光性物質１７がな
くなり、ＩＣチップ１５の間にある所に厚い壁状の感光
性物質１７が形成される。これを熱処理することによ
り、感光性物質１７はさらに強固になる。この熱処理に
より感光性物質１７は縮小する場合があるが、縮小して
高さが低くなってもワイヤの最高点よりも感光性物質１
７を高くするようにしなければならない。また、ＩＣチ
ップ１５を先に搭載しワイヤ１６をはっているので、感
光性物質１７とワイヤ１６の位置および内部電極配線１
３とをかなり接近させることができる。Next, as shown in FIG. 1 (e), by developing, the photosensitive material 17 at the place where the IC chip 15 is located disappears, and the photosensitive material 17 having a thick wall shape is located at the place between the IC chips 15. 17 are formed. By subjecting this to a heat treatment, the photosensitive substance 17 is further strengthened. Although the photosensitive material 17 may be reduced by this heat treatment, even if the photosensitive material 17 is reduced in height and reduced in height, the photosensitive material 1 is higher than the highest point of the wire.
7 must be raised. Also, since the IC chip 15 is mounted first and the wire 16 is attached, the position of the photosensitive material 17 and the wire 16 and the internal electrode wiring 1
3 can be made quite close.

【００１０】次に図１(ｆ)に示すように、板状のふた１
９を接着する。この場合、感光性物質１７の上に接着材
料を付着してからふた１９を接着する方法、あるいはふ
た１９の方に感光性物質１７が来る位置に接着材を塗布
してからふた１９を接着する方法、あるいは感光性物質
１７とふた１９を熱処理で接着する方法などがある。こ
の板状のふた１９として、光を通すことが必要であれば
ガラスや透明プラスチックなどのその光に透明な物質か
らなる材料にする。光を通す必要がなければ、セラミッ
クやガラスエポキシやポリイミドなどの材料を用いるこ
とができる。またテープ状のシートでも用途によって使
うこともできる。Next, as shown in FIG.
9 is adhered. In this case, a method of bonding the lid 19 after attaching an adhesive material on the photosensitive substance 17 or applying an adhesive to a position where the photosensitive substance 17 comes to the lid 19 and then bonding the lid 19 is applied. Or a method of bonding the photosensitive substance 17 and the lid 19 by heat treatment. If it is necessary to transmit light, the plate-shaped lid 19 is made of a material made of a substance transparent to the light, such as glass or transparent plastic. If it is not necessary to transmit light, a material such as ceramic, glass epoxy, or polyimide can be used. Also, a tape-shaped sheet can be used depending on the application.

【００１１】次に図１(ｇ)に示すように、感光性物質１
７の中間地点で基板を切断する。この切断の方法とし
て、ダイシング装置を用いて行う方法やワイヤーソーを
用いて行う方法やレーザーや高圧水を用いて切断する方
法がある。また、ダイシングで行う場合、最初比較的幅
の広いブレードを用いて浅く切断しその後幅の狭いブレ
ードで切断することで、切断面にクラックが入ることを
防止する方法を用いることもできる。Next, as shown in FIG.
The substrate is cut at the midpoint of 7. Examples of the cutting method include a method using a dicing device, a method using a wire saw, and a method using a laser or high-pressure water. Further, in the case of dicing, a method of preventing a crack from entering a cut surface by first cutting shallowly with a relatively wide blade and then cutting with a narrow blade can be used.

【００１２】このようにして、図１(ｈ)に示すように、
ＩＣチップ１５が気体で封止されたＩＣパッケージを得
る。さて、ＩＣパッケージの電気特性の測定方法とし
て、従来と同じく１個のパッケージになった後で測定す
ることはもちろん可能である。そのほかに、図１(ｇ)で
基板を切断する前に測定することもできる。すなわち、
基板の電極に合せてプローブカードを作成しウエハ測定
の時と同じ方法で測定できる。従って多数のＩＣパッケ
ージを１回のプロービングで測定することも可能であ
る。In this way, as shown in FIG.
An IC package in which the IC chip 15 is sealed with a gas is obtained. Now, as a method of measuring the electrical characteristics of the IC package, it is of course possible to measure the IC package after it has been made into one package as in the conventional case. In addition, it can also be measured before cutting the substrate in FIG. That is,
A probe card is prepared in accordance with the electrodes of the substrate, and the measurement can be performed in the same manner as when measuring the wafer. Therefore, it is possible to measure many IC packages by one probing.

【００１３】図２は、図１(ｅ)の平面図を示す。基板２
１内に多数のＩＣチップ２５が搭載されている。ＩＣチ
ップ２５およびワイヤ２６は露出している。ＩＣチップ
の間には感光性物質２７が壁状に形成されている。写真
食刻法を用いているので感光性物質は精度良くパターニ
ングされている。FIG. 2 shows a plan view of FIG. Substrate 2
Many IC chips 25 are mounted in one. The IC chip 25 and the wires 26 are exposed. A photosensitive material 27 is formed between the IC chips in a wall shape. Since the photolithography method is used, the photosensitive material is accurately patterned.

【００１４】図３は、図１(ｇ)の平面図を示す。点線で
示す位置で切断される。感光性物質３７のほぼ中間位置
で切断される。FIG. 3 shows a plan view of FIG. 1 (g). It is cut at the position shown by the dotted line. The photosensitive material 37 is cut at a substantially intermediate position.

【００１５】[0015]

【発明の効果】以上、説明したように基板内に多数のＩ
Ｃパッケージを一挙に作り込み、最後に切断して１個1
個のＩＣパッケージにするので、生産性が大幅に向上し
製造費も大幅に低減する。また、切断する前に１枚の基
板になっている時に電気特性を測定できるので、ウエハ
プローバーと同様の思想で多数のＩＣの電気特性を一挙
に測定できることになり、テストに要する費用を大幅に
削減できる。As described above, as described above, a large number of I
Make C package all at once, cut at the end
Since individual IC packages are used, productivity is greatly improved and manufacturing costs are significantly reduced. In addition, since electrical characteristics can be measured when a single substrate is cut before cutting, the electrical characteristics of a large number of ICs can be measured all at once with the same concept as a wafer prober, greatly reducing the cost required for testing. Can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明のＩＣパッケージの製造方法を示す図で
ある。FIG. 1 is a diagram showing a method of manufacturing an IC package according to the present invention.

【図２】図１(ｅ)の平面図を示す図である。FIG. 2 is a plan view of FIG. 1 (e).

【図３】図１(ｇ)の平面図を示す図である。FIG. 3 is a diagram showing a plan view of FIG. 1 (g).

【図４】従来のＩＣパッケージを示す図である。FIG. 4 is a diagram showing a conventional IC package.

【符号の説明】[Explanation of symbols]

１１、２１、３１、４１ 半導体基板 １２、４２ 外部電極 １３、２３、３３、４３ 内部電極配線 １５、２５、３５、４５ ＩＣチップ １６、２６、３６、４６ ワイヤ １７、２７、３７ 感光性物質 １８ マスク １９、４９ ふた ４７ 枠 11, 21, 31, 41 Semiconductor substrate 12, 42 External electrode 13, 23, 33, 43 Internal electrode wiring 15, 25, 35, 45 IC chip 16, 26, 36, 46 Wire 17, 27, 37 Photosensitive substance 18 Mask 19, 49 Lid 47 Frame

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 外部電極と内部電極配線とを有する基板
にＩＣチップを載せてＩＣチップ内の電極と前記内部電
極配線とをワイヤで接続する工程と感光性物質を塗布す
る工程と写真食刻法を用いてＩＣチップ間に感光性物質
を形成する工程と板状のふたを前記感光性物質の厚膜に
接着する工程と前記感光性物質の中間地点で切断する工
程とからなることを特徴とする気密封止ＩＣパッケージ
の製造方法1. A step of mounting an IC chip on a substrate having external electrodes and internal electrode wiring, connecting an electrode in the IC chip to the internal electrode wiring with a wire, applying a photosensitive substance, and performing photolithography. Forming a photosensitive material between IC chips using a method, bonding a plate-like lid to a thick film of the photosensitive material, and cutting at a middle point of the photosensitive material. For manufacturing hermetically sealed IC package 【請求項２】 外部電極と内部電極配線とを有する基板
にＩＣチップを載せてＩＣチップ内の電極と前記内部電
極配線とをワイヤで接続する工程と感光性物質を塗布す
る工程と写真食刻法を用いてＩＣチップ間に感光性物質
を形成する工程と熱処理を行い前記感光性物質を硬化さ
せる工程と板状のふたを前記感光性物質の厚膜に接着す
る工程と前記感光性物質の中間地点で切断する工程とか
らなることを特徴とする気密封止ＩＣパッケージの製造
方法2. A step of mounting an IC chip on a substrate having external electrodes and internal electrode wiring, connecting electrodes in the IC chip to the internal electrode wiring with wires, applying a photosensitive substance, and performing photolithography. Forming a photosensitive material between the IC chips by using a method, heat-treating the photosensitive material by heat treatment, bonding a plate-shaped lid to the thick film of the photosensitive material, Cutting at an intermediate point. A method for manufacturing a hermetically sealed IC package, comprising: 【請求項３】 前記外部電極と前記内部電極配線とを有
する前記基板はガラスエポキシ材料であることを特徴と
する請求項１または２記載の気密封止ＩＣパッケージの
製造方法3. The method for manufacturing a hermetically sealed IC package according to claim 1, wherein said substrate having said external electrode and said internal electrode wiring is made of a glass epoxy material. 【請求項４】 前記外部電極と前記内部電極配線とを有
する前記基板はセラミック材料であることを特徴とする
請求項１または２記載の気密封止ＩＣパッケージの製造
方法4. The method for manufacturing a hermetically sealed IC package according to claim 1, wherein said substrate having said external electrode and said internal electrode wiring is made of a ceramic material. 【請求項５】 前記板状のふたは、ガラス板であること
を特徴とする請求項１または２記載の気密封止ＩＣパッ
ケージの製造方法5. The method for manufacturing a hermetically sealed IC package according to claim 1, wherein said plate-shaped lid is a glass plate. 【請求項６】 前記板状のふたは、セラミック板である
ことを特徴とする請求項１または２記載の気密封止ＩＣ
パッケージの製造方法6. The hermetically sealed IC according to claim 1, wherein said plate-shaped lid is a ceramic plate.
Package manufacturing method 【請求項７】 前記板状のふたは、テープ状のシートで
あることを特徴とする請求項１または２記載の気密封止
ＩＣパッケージの製造方法7. The method for manufacturing a hermetically sealed IC package according to claim 1, wherein the plate-shaped lid is a tape-shaped sheet. 【請求項８】 前記基板を切断する前に、ＩＣパッケー
ジの電気特性を基板全体を用いて測定する工程を含むこ
とを特徴とする請求項１または２記載の気密封止ＩＣパ
ッケージの製造方法8. The method for manufacturing a hermetically sealed IC package according to claim 1, further comprising a step of measuring electric characteristics of the IC package using the entire substrate before cutting the substrate. 【請求項９】 プローブカード状の治具を用いて電気特
性を測定することを特徴とする請求項８記載の気密封止
ＩＣパッケージの製造方法9. The method for manufacturing a hermetically sealed IC package according to claim 8, wherein the electrical characteristics are measured using a probe card-shaped jig.
JP2001182439A 2001-06-15 2001-06-15 Method for manufacturing hermetically sealed IC package Expired - Fee Related JP4813692B2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1075140A (en) * 1996-04-29 1998-03-17 Motorola Inc Acoustic wave filter package and method therefor
WO1999026289A1 (en) * 1997-11-18 1999-05-27 T.I.F. Co., Ltd. Semiconductor device and method for manufacturing the same
JP2000286354A (en) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp Manufacture of semiconductor device and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1075140A (en) * 1996-04-29 1998-03-17 Motorola Inc Acoustic wave filter package and method therefor
WO1999026289A1 (en) * 1997-11-18 1999-05-27 T.I.F. Co., Ltd. Semiconductor device and method for manufacturing the same
JP2000286354A (en) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp Manufacture of semiconductor device and semiconductor device

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