JP2002373113A - Data processor and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor and a data processing method capable of preventing the occupancy time of access to a memory from being lengthened even when the priority order of the access to the memory is set. SOLUTION: This data processor is provided with a step S2 for setting an access order as a normal or special mode, a step S3 for setting a writing access to a storage area FIFO0 the highest priority in the special mode, and steps S4-S7 for setting the access given the highest priority so as to be continuously performed the several number of times, and this data processing method is executed in this data processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention has a plurality of circuit blocks,
A first circuit block of the plurality of circuit blocks;
The present invention relates to a data processing device for transferring data via a bus between a second circuit block and a buffer memory for buffering data, and a data processing method.

[0002]

2. Description of the Related Art A conventional data processing apparatus is disclosed in
000-47930 (publication date: February 1, 2000)
On 8th), the technology disclosed will be described.

In this publication, a high-priority access request is
There is disclosed a data processing device that can be adopted without a waiting time as needed, and is capable of temporarily changing priorities in response to access requests from a plurality of bus masters.

In the prior art, the priority setting of the access request is set for the entire storage area of the memory. Therefore, when the capacity of the memory itself is large, the occupation of the access request whose priority is set due to the size of the memory is occupied. Time tends to lengthen.

[0005] The occupation time is determined depending on the capacity of the memory, irrespective of the magnitude of the code amount of the data requested to access the memory area.

In particular, a FIFO (F
When a first-in / first-out type memory is used, its high-speed access characteristics cannot be exhibited.

[0007]

As described above, in the prior art, in a system having a large memory capacity,
When the priority is set for the access, the occupation time of the memory for which the priority is set becomes long because of the large memory capacity.

In view of this problem, the present invention provides a data processing apparatus and a data processing method which can prevent the occupation time from being lengthened even if the priority of access to the memory is set. The purpose is to:

[0009]

In order to solve the above problems, a data processing device according to the present invention comprises a first circuit block,
A second circuit block, a first bus connected to the first circuit block and transferring data, a second bus connected to the second circuit block and transferring the data, A buffer memory having a plurality of storage areas for temporarily storing the data transferred via a bus or the second bus, and a buffer memory manager for controlling an operation of storing the data in the buffer memory; In the first mode in which data is written from the first block, an access to write data from the first block to at least one of a plurality of storage areas in the buffer memory is performed continuously a plurality of times. Therefore, the priority order is set.

According to another aspect of the present invention, there is provided a data processing method, comprising: a first bus connected to a first circuit block, a second circuit block, and a first circuit block for transferring data; And connected to the second circuit block,
A second bus for transferring the data, a buffer memory having a plurality of storage areas for temporarily storing the data transferred via the first bus or the second bus, and the buffer memory A data processing method used in a data processing device comprising: a buffer memory manager for controlling the data storage operation of the first block; and a first mode for writing data from the first block. A priority order is set so that an access to write data from a plurality of storage areas in the buffer memory to at least one of the plurality of storage areas is performed a plurality of times continuously.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
This will be described with reference to FIG.

FIG. 1 is a block diagram of a system employing the data processing device of the present invention.

In FIG. 1, 1 is Y / C (luminance signal /
A composite video signal S
_vi is entered. This Y / C (luminance signal / color signal)
The separation circuit 1 separates an analog luminance signal and a video signal from the composite video signal S _vi and transfers them to a subsequent stage.

A video AD (analog-to-digital) converter 2 is connected to a stage subsequent to the Y / C (luminance signal / color signal) separation circuit 1. This video AD converter 2
, A luminance signal and a video signal are transferred, and the video A
The D converter 2 transfers these to the subsequent stage as digitized video data.

In the subsequent stage of the video AD converter 2, a DVD
(Digital versatile disk) The stream encoder 3 is connected.

In FIG. 1, reference numeral 4 denotes an audio AD converter. The audio AD converter 4 receives analog audio signals S _ALI and S _ARI. The audio signals S _ALI and S _ARI are digitized and then converted as audio data to an audio encoder 5 connected to a subsequent stage. Will be transferred.

In the audio encoder 5,
The audio data is processed to adjust the data length so that it becomes audio sample data specified by the DVD video recording format, and one sample data is linear PCM (pulse code modulation) data in units of 16 bits, 20 bits or 24 bits. Is connected to the subsequent stage and transferred to the DVD audio / video stream encoder 3.

In the DVD audio / video stream encoder 3, the transferred video data and audio data are buffered once in the buffer memory 6, and then the code amount in the DVD audio / video stream defined by the DVD video recording format is set. Performs encoding processing on a video pack and an audio pack each having a unit of 2048 bytes.

The DVD audio / video stream encoder 3 also combines the recorded video data with the data for synchronously reproducing the recording time, the display control data, and the copy protection data together with the RDI (Real Time).
e Data Information) encoding processing.

In the DVD audio / video stream encoder 3, a video pack, an audio pack, and an RDI pack, which have been packed and time-division multiplexed by encoding, are connected to an encoder interface 7 connected to the subsequent stage of the DVD audio / video stream encoder 3. Is forwarded to

The encoder interface 7 transfers the transferred video pack, audio pack and RDI pack to a block connected at a later stage at an appropriate timing.

In the subsequent stage of the encoder interface 7, a buffer memory manager 9,
Stream output interface 10, IDE
(Integrated Dive Electro
nics) Each block of the interface controller 11 is connected, and between each block, a video pack, an audio pack, or an RDI pack is transferred via a data bus.

A buffer memory 10 is connected to the buffer memory manager 9 connected to the data bus, and the video pack, audio pack and RDI pack transferred via the data bus are temporarily stored in the buffer memory 10. Buffering is performed, and input / output from / to the buffer memory 10 is controlled by the control of the buffer memory manager 9.

Further, the buffer memory manager 9
The programmable controller 8, the IDE interface controller 12, and each block of the stream output interface 11 are connected to each other via a data bus.

Further, a DVD audio / video decoder 15 is connected downstream of the stream output interface 11.

In particular, the buffer memory manager 9
And the IDE interface controller 12 are connected to the data buses 28, 29, and 35, and enable data transfer therebetween.

The data bus 28 is connected to a primary IDE port inside the IDE interface controller 12, and the data bus 29 is connected to the primary IDE port.
Connected to port.

Further, IDE is set to the primary IDE port.
The hard disk drive 30 is connected via a bus 26, and the secondary IDE port is connected to a DVD-RAM drive 31 via an IDE bus 27.

The primary IDE port and the hard disk drive 30 can mutually transfer data via the IDE bus 26.
Data can be transferred to and from the D-RAM drive 31 via the IDE bus 27.

The IDE interface controller 12 is provided with a sub-IDE port 34, which is connected to the sub-IDE port 34 via a sub-IDE bus 36.
The EE1394 IDE bridge 37 is connected.
A cable 38 is connected to the IEEE1394I IDE bridge 37, and an external input interface connector 39 is provided at a distal end of the cable 38.

The buffer memory manager 9 transfers data such as video packs, audio packs, and RDI packs buffered in the buffer memory to the hard disk drive 30 or the DVD-RAM drive 31 via the IDE interface controller 12. Can be.

When the buffer memory manager 9 transfers data, a video pack, an audio pack, and an RDI pack can be recorded on the recording medium of the hard disk drive 30 or the DVD-RAM drive 31.

Further, the hard disk drive 30
A video pack on a recording medium of the VD-RAM drive 31,
When recording audio packs and RDI packs,
From the VD-RAM drive 31 to the recording medium of the hard disk drive 30, a video pack, an audio pack,
Also in the case of recording the DI pack, the buffer memory manager 9 transfers the data so that the data is buffered in the buffer memory 10, so that the data can be mutually recorded between the hard disk drive 30 and the DVD-RAM drive 31. .

When reproducing data read from the recording medium of the hard disk drive 30 or the DVD-RAM drive 31, the hard disk drive 3
0 or the data is transferred from the DVD-RAM drive 31, and the buffer memory manager 9 buffers the data in the buffer memory 10 and then transfers the data to the stream output interface 11.

At the subsequent stage of the stream output interface 11, a video pack, an audio pack, an RD
DV for decoding I-pack and extracting and reproducing video data, audio data, and control data as reproduction data
A D audio video decoder 15 is connected.

Video data is MPEG2 (Motion)
n Picture Expert Group 2), which is video data that has been compressed, and the DVD audio / video decoder 15 decompresses the video data that has been compressed.

A buffer memory 16 is connected to the DVD audio / video decoder 15, and the DVD audio / video decoder 15 decodes a video pack, an audio pack, and an RDI pack while buffering data in the buffer memory 16.

The video data and audio data separated and demodulated by the DVD audio / video decoder 15 are transferred to a video encoder 18 or an audio DA converter 17 connected to a stage subsequent to the DVD audio / video decoder 15.

The audio DA converter 17 converts the audio data into an analog audio signal into S _ALO and S _ARO and outputs it from an audio output terminal.

The video encoder 18 converts video data into an analog video signal, performs processing such as adding a synchronization signal, and outputs a synchronization signal S _Y , a color signal S _C , and a composite video signal S _NTSC from a video signal output terminal. I do.

On the other hand, the control data extracted from the RDI pack is transferred to the host MPU 19 via the host MPU bus 22 to which the host MPU 19 is connected.

The control data transferred to the host MPU 19 is transferred to the system RAM 20 via the host MPU bus 22.
And buffered in the system RAM 20.

The host MPU 19 includes a host MP
The system ROM 21 is connected via the U bus 22, and the host MPU 19 fetches instructions and data constituting a control program from the system ROM 21.

A button input / display control circuit 25 is connected to the host MPU 19. The button input / display control circuit 25 includes an operation button 2 as a user interface.
3 and a display 24 for displaying the state of the system.

The host MPU 19 includes the DVD audio / video trim encoder 3 and the IEEE1394 I
Each block of the DE bridge 37, the IDE interface controller 12, and the DVD audio / video decoder 15 is connected via the host MPU bus 22.

The host MPU 19 has a system ROM 21
The operation according to the control data of the RDI pack and the control data corresponding to the user operation input via the button input / display control circuit 25 is performed by the control program stored in the host MPU bus 22. It is realized by controlling.

In the present invention, the buffer memory manager 9 includes a video pack, an audio pack, and an RD
The data such as the I-pack is transferred to the buffer memory 10 and the hard disk drive 30 or the DVD-RAM drive 31 via the IDE interface controller 12.
This operation is performed by a command output from the programmable controller 8.

Next, the operation of the data processing apparatus of the present invention will be described with reference to FIGS.

FIG. 2 is a connection diagram of the internal circuit of the buffer memory 10 and the buffer memory manager 9. FIG. 3 is a flowchart showing the operation of the data processing device of the present invention. FIG. 4 is a timing chart showing the operation of the data processing device of the present invention.

The data processing apparatus according to the present invention operates in a write mode when data is written from a predetermined block by a buffer memory manager 9 to a buffer memory 10 having a storage area for temporarily storing data. The priority order is set so that write access to at least one of the areas can be continuously performed a plurality of times.

Here, the internal structure of the buffer memory 10 of the present invention will be described with reference to FIG. In the figure,
Buffer memory manager 9, buses 28, 29, 35
Is the same as each block shown in FIG.

Of the buses connected to the buffer memory manager 9, 28, 29, and 35 are IDE interface controllers 12 (not shown), and the other buses, which are not connected to the buffer memory manager 9 and are denoted by reference numerals, are programmable controllers. 8 and the stream output interface 11.

The buffer memory 10 includes a memory controller 10MC, a memory switcher 10S, a plurality of storage areas (FIFO0) 10M0, and a storage area (FIFO1) 10.
M1 and boundary registers 10R0 and 10R1.

A plurality of storage areas (FIFO0) 10M0,
The storage area (FIFO1) 10M1 is originally a single storage area. However, by storing the address values at the boundaries of the single storage area in the boundary registers 10R0 and 10R1, the individual storage areas become independent. , Two F each
It is set to function as an IFO area.

This setting is performed based on a command issued by the programmable controller 8 which operates according to a control instruction from the host MPU 19.
Performed by

That is, the memory controller 10MC sets a boundary address value in the boundary registers 10R0 and 10R1 in advance and refers to the boundary address to virtually store a single storage area and a plurality of storage areas (FIFO0).
The management operation is performed by dividing the storage area into 10M0 and a storage area (FIFO1) 10M1.

As described above, the memory controller 10
The MC functions as a slave block according to a command issued by the programmable controller 8.

The memory controller 10MC and the buffer memory manager 9 are connected by a bus, and the programmable controller 8 transfers information necessary for the memory controller 10MC to control the buffer memory 10 via the buffer memory manager 9. .

Then, the storage area (FIFO0) 10M
0, the storage area (FIFO1) 10M1 functions as a FIFO memory having an address set in the boundary address registers 10R0 and 10R1 as an upper limit value.

The feature of the FIFO memory is that the data to be accessed after passing through the bus and the memory switcher 10S stores a plurality of storages constituting one of the storage area (FIFO0) 10M0 and the storage area (FIFO1) 10M1. The data is simultaneously written to the elements, and the storage of the data is completed instantaneously.

However, due to the structure of the bus, each storage area (FIF
O0) 10M0 and the storage area (FIFO1) 10M1 are accessed at one time for either writing or reading, and are not performed simultaneously for both.

The storage area (FIFO 0) 10M0,
Access to both of the storage areas (FIFO 1) 10M1 is not performed at the same time, and after access to one of the two storage areas or one of the storage areas is completed,
Access to the next storage area becomes possible.

This data access is performed via the buffer memory manager 9 for both writing and reading.

At this time, the memory controller 1
0MC is a storage area (FIFO0) 10M0 and a storage area (FIFO
1) The status information indicating the storage state of the 10M1 data is transferred via the buffer memory manager 9.

As shown in FIG. 1, the buffer memory 10
, Data write or read access is performed from a plurality of circuit blocks connected to the buffer memory manager 9.

For example, when recording a television broadcast,
From the DVD audio / video stream encoder 3 via the encoder interface 7, a DV including video data generated by encoding a television broadcast signal is output.
The D audio video stream is transferred to the buffer memory manager 9.

At this time, the programmable controller 8
, The buffer memory manager 9 transfers the transferred DVD audio / video stream to the storage area (FIFO0) 10M0 of the storage area of the buffer memory 10 for write access.

The memory controller 10MC in the buffer memory 10 inputs the serially transferred data to the bases of a plurality of transistors provided in the memory switcher 10S in bit units, and stores the data in a storage area (FIFO 0) 10
Data is simultaneously written to the storage elements provided in M0.

The storage area (FIF) in the buffer memory 10
O0) Data is written to 10M0 until the storage element of the boundary address value is addressed, and after the data is temporarily buffered, read access from the buffer memory manager 9 causes the data in the buffer memory 10 to be written. The data is again transferred from the storage area (FIFO0) 10M0 to the buffer memory manager 9.

The DVD audio / video stream transferred to the buffer memory manager 9 is further transferred to the IDE interface controller 12 via the bus 28 or the bus 29.

The buses 28 and 29 are connected to the primary IDE port and the bus 29 to the secondary IDE port in the IDE interface controller 12, and the DVD audio / video stream is transferred to each port. Is done.

The DVD audio / video streams transferred to the primary IDE port and the secondary IDE port are respectively transmitted to the hard disk drive 30 via the IDE bus 26 and to the hard disk drive 30 via the IDE bus 27.
The data is transferred to the VD-RAM drive 31.

At this time, the DVD audio / video stream transferred to the hard disk drive 30 and the DVD-RAM drive 31 is recorded on the recording medium in the hard disk drive 30 and the DVD-RAM drive 31.

By recording the DVD audio / video stream in this manner, a television broadcast is recorded.

As described above, when a large amount of data is continuously transmitted, the processing must be performed so that the transfer of the data is not interrupted. In particular, recording of a real-time video that cannot be retaken, such as recording of a television broadcast, requires that video data based on the encoded television signal be transferred to a storage device such as a hard disk drive 30 or a DVD-RAM drive 31 without interruption. No.

Therefore, in the data processing device of the present invention, the DV
When data including video data such as a D audio video stream is transferred from an encoder to a hard disk drive 30 or a DVD-RAM drive 31 as a recording device, the following operation is performed.

Here, FIG. 3 is used to explain this operation.

The flowchart of FIG. 3 includes steps S1 to S11.

In this flowchart, step S
1 is a START step indicating the start of the operation of the system.

Immediately after the START step, the system operation proceeds to a determination step S2 for determining the access order mode. At this time, the determination of the access order mode is performed based on a command given from the programmable controller 8 to the buffer memory manager 9.

In this access order mode, one of two types, normal and special, can be selected.

Of these two modes, the normal mode is a storage area (FIFO0) and a storage area (FIFO).
In this mode, the access order is set so that access to O1) is performed substantially equally.

On the other hand, the special mode is a mode in which access to the storage area (FIFO0) is set to be performed continuously.

In step S2, the access mode is determined based on the command given from the programmable controller 8 to the buffer memory manager 9, as described above.

Here, the programmable controller 8
Sends a command to the DVD audio / video stream encoder to
, The DVD audio / video stream is transferred to the buffer memory manager 9.

At this time, in order to prevent interruption of the transfer of the DVD audio / video stream, the programmable controller 8 can continuously access the storage area (FIFO 0) 10M0 to the buffer memory manager 9. A command for setting a special priority and selecting and executing a special mode is transferred.

The buffer memory manager 9 determines that the access order mode is the special mode, and the operation of the system shifts to step S3.

At this time, the buffer memory manager 9
Operates according to steps S3 to S7 to execute the special mode.

First, in step S3, a storage area (FIFO0) which is a storage area for storing the DVD audio / video stream transferred from the DVD audio / video stream encoder interface 3
Write access to is set to the highest priority over other access modes.

The buffer memory manager 9 operated according to the processing in step S3 performs the processing in step S4.

In step S4, the buffer memory manager 9 initializes a variable I for counting the number of repetitions by performing an initial value “ 1 "is substituted.

In step S5, the buffer memory manager 9 accesses the buffer memory 10.

As described above, the storage area (FIFO 0) 10
Since the write access to M0 is set to the highest priority, the write access to the storage area (FIFO0) 10M0 and the access to be executed even if the other access conflicts with the storage area (FIFO0).
0) Write access to 10M0, and writing of a DVD audio video stream to the storage area (FIFO0) 10M0 is performed.

The buffer memory manager 9 keeps accessing the buffer memory until all the DVD audio / video streams being transferred are written to the storage area (FIFO 0) 10M0, and then the operation of the system shifts to step S6.

In step S6, the buffer memory manager 9 sets the variable I for counting the number of repetitions.
, The current value is incremented by “1”.

That is, the variable I for counting the number of repetitions
Is to count up a variable each time the buffer memory manager 9 accesses the buffer memory 10 in step S5.

After the end of step S6, the operation of the system shifts to step S7.

In step S7, the value of the variable I and
The buffer memory manager 9 continuously compares the storage area (FIFO 0) 10M0 with the value “3” set as the number of times that the write access is permitted.

As a result, when the value of the variable I is equal to "3" (I = 3), the buffer memory manager 9 has reached the number of times that the write access to the storage area (FIFO0) 10M0 should be prioritized. Then, the system operation is shifted to the subsequent step S8.

On the other hand, when the value of the variable I is “3”
If not, the system shifts to the process of step S5 again, and the buffer memory manager 9 sets the access to the storage area (FIFO0) 10M0 to the highest priority again in the next time.

Thereafter, the operation of the system shifts to the processing of step S6, and the buffer memory manager 9 stores the variable I
Count up. In step S7, it is determined whether or not the value of the variable I has reached the number of repetitions “3”.

That is, according to steps S5 to S7, D
VD audio video stream encoder 3 to DV
In the write mode for writing the D audio / video stream, one of the plurality of storage areas in the buffer memory 10 is a storage area (FIFO).
0) It is possible to continuously perform write access to 10M0 a plurality of times.

Next, in step S2, the programmable controller 8 sends the buffer memory manager 9
If the command given to set the normal access mode, the operation of the system shifts to step S10.

At this time, the buffer memory manager 9
Operates according to steps S10 to S11 to execute the normal mode.

First, in step S10, the buffer memory manager 9 sets the storage area (FIFO1) 1
The read access to the storage area (FIFO 1) 10M1 is set to the highest priority over the other access modes so that the data stored in 0M1 is read and transferred to the buffer memory manager 9 side.

The priorities of the other access modes are set so as to be equally performed.

Further, the operation of the system is performed in step S11.
Move to.

In step S11, the buffer memory manager 9 accesses the buffer memory 10.

As described above, the storage area (FIFO 1) 10
Since the read access to the M1 is set to the highest priority, even if the read access to the storage area (FIFO1) 10M1 and the other access conflict, the access to be executed is the storage area (FIFO1).
O0) Read access to 10M0, and only reading of the DVD audio video stream from the storage area (FIFO0) 10M0 is performed only once as execution access.

As described above, the normal mode differs from the special mode in that the priority order of access to the buffer memory 10 is not continuously set.

After the end of step S11, the operation of the system shifts to step S8. Step S8 is a step for determining whether or not the access to the buffer memory 10 has been stopped after the access to the buffer memory 10 of the memory manager 9 in the normal mode / special mode has been completed.

Here, the programmable controller 8
Then, based on the command transferred to the buffer memory manager 9, it is determined whether or not access to the buffer memory 10 has been stopped.

If the programmable controller 8 has not transmitted a command to the buffer memory manager 9 to stop access to the buffer memory 10, the system operation proceeds to step S2 again. The buffer memory manager 9 repeats access to the buffer memory 10 in one of the normal mode and the special mode.

On the other hand, when a command for stopping access to the buffer memory 10 is transferred from the programmable controller 8 to the buffer memory manager 9, the buffer memory manager 9 stops the access to the buffer memory 10. Then, the operation of the system shifts to the subsequent step S9.

Step S9 is an END step for ending the operation of the system.

The flow of the access process of the memory manager 9 to the buffer memory 10 has been described above.

Next, the transition of the access state of the buffer memory manager 9 to the buffer memory 10 will be described with reference to FIG.

In FIG. 4, (a) shows a read flag set in the buffer memory manager 9 and
6 is a timing chart showing a change in a write flag. Also, (b) is a table for setting the priority of access to the buffer memory 10 set in the buffer memory manager 9.

In this table, the first column shows the priority of access, and the first column shows the access executed by the buffer memory manager 9.

Further, in (a) and (b), it is assumed that the state transition proceeds from left to right in the figure.

First, in the state (1), the highest priority is given to data read access from the storage area (FIFO 1) 10M1.

At this time, as indicated by the read flag, the execution access is performed in the storage area (FIFO 1) 10M1.
Read FI, which is an access to read data from
FO1 mode is set.

In the next state (2), the highest priority is given to data write access to the storage area (FIFO 0) 10M0.

At this time, as shown in the Write Flag, the execution access is made to the storage area (FIFO 0) 10
Write, which is a data write access to M0
The mode becomes FIFO0.

In the next state (3), the data write access to the storage area (FIFO 0) 10M0 is given the highest priority.

At this time, Read access and Wri
Since there was no contention for te access, Read Fla
g, the execution access is performed in the storage area (FIFO).
0) R which is a data read access from 10M0
The mode becomes the read FIFO0 mode.

In the next state (4), the highest priority is given to data write access to the storage area (FIFO 0) 10M0.

At this time, the execution access is limited to the storage area (FIFO0) 10M as shown in the Write Flag.
Write F, which is a data write access to 0
The mode becomes IFO0.

As described above, in the states (2) to (4), the access of the memory manager 9 is performed in the storage area (FI).
FO0) The special mode in which the state in which the data write access to 10M0 is given the highest priority continues.

At this time, as described above, the DVD transferred from the DVD audio / video stream encoder 3
The audio video stream data is being transferred to the buffer memory manager 9.

In the following state (5), the data write access to the storage area (FIFO 1) 10M1 has the highest priority.

At this time, execution access is limited to the storage area (FIFO 1) 10M as shown in the Write Flag.
Write F, which is a data write access to
The mode becomes IFO0.

In the next state (6), the highest priority is given to data read access from the storage area (FIFO 1) 10M1.

At this time, as indicated by the read flag, the execution access is performed in the storage area (FIFO 1) 10M1.
Read FI, which is an access to read data from
FO1 mode is set.

In the next state (7), again
As for the priority, the data write access to the storage area (FIFO 0) 10M0 has the highest priority.

At this time, execution access is limited to the storage area (FIFO0) 10M as shown in the Write Flag.
Write F, which is a data write access to 0
The mode becomes IFO0.

In the next state (8), the highest priority is given to data read access from the storage area (FIFO 0) 10M1.

At this time, as shown in the Read Flag, the execution access is made to the storage area (FIFO0) 10M1.
Read FI, which is an access to read data from
The mode becomes FO0.

In the next state (9), again
As for the priority, the data write access to the storage area (FIFO 0) 10M0 has the highest priority.

At this time, execution access is limited to the storage area (FIFO0) 10M as shown in the Write Flag.
Write F, which is a data write access to 0
The mode becomes IFO0.

In the states (6) to (9), the normal mode in which a single mode is not continuously given the highest priority is set as the access order set by the memory manager 9.

As described above, in the present invention, when data having a large code amount such as video data included in a DVD audio / video stream is written to the buffer memory 10, the write mode for a specific storage area is given the highest priority. Therefore, even if the priority of access to the memory is set, the capacity of the storage area to be accessed becomes relatively small.

Accordingly, high-speed writing and high-speed reading, which are the characteristics of the FIFO memory, can be performed. When buffering real-time video data such as video data included in a DVD audio / video stream, data transfer is interrupted. Nothing.

Further, since the capacity of the storage area to be accessed is relatively small, the occupation time of the storage area in the buffer memory 10 can be prevented from being lengthened.

[0145]

According to the present invention, it is possible to provide a data processing apparatus and a data processing method that can prevent the occupation time from being lengthened even if the priority of access to the memory is set.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system employing a data processing device of the present invention.

FIG. 2 is a connection diagram of an internal circuit of a buffer memory 10 and a buffer memory manager 9;

FIG. 3 is a flowchart showing the operation of the data processing device.

FIG. 4 is a timing chart showing the operation of the data processing device of the present invention.

[Explanation of symbols]

 19 Host MPU 10 Buffer memory 9 Buffer memory manager 8 Programmable controller 10M0 Storage area (FIFO0) 10M1 Storage area (FIFO1)

Claims (8)

[Claims] A first circuit block connected to the second circuit block and the first circuit block;
A first bus for transferring data; a second bus connected to a second circuit block for transferring the data; and the data transferred via the first bus or the second bus. A first mode for writing data from the first block, comprising: a buffer memory having a plurality of storage areas for temporarily storing data; and a buffer memory manager for controlling an operation of storing the data in the buffer memory. A data processing method, wherein a priority order is set so that an access to write data from a first block to at least one of a plurality of storage areas in the buffer memory is performed a plurality of times continuously. apparatus. 2. The buffer memory manager is capable of switching between the first mode and a second mode,
In the second mode, the number of accesses to write data from the first block and the number of accesses to write data from the second block to the storage area of the buffer memory are equal. 2. The data processing apparatus according to claim 1, wherein the control is performed in such a manner as to be performed. 3. The data processing device according to claim 1, wherein the data from the first block is video data. 4. The data processing apparatus according to claim 1, wherein the data from the first block is data continuously transmitted from a remote place in real time. 5. A circuit connected to a first circuit block, a second circuit block, and a first circuit block,
A first bus for transferring data; a second bus connected to a second circuit block for transferring the data; and the data transferred via the first bus or the second bus. A buffer memory having a plurality of storage areas for temporarily storing data, and a buffer memory manager controlling a data storage operation of the buffer memory, a data processing method used in a data processing device, comprising: In the first mode in which data is written from the first block, priority is given to making access to write data from the first block to at least one of the plurality of storage areas in the buffer memory a plurality of times continuously. A data processing method characterized by setting an order. 6. A switchable mode between the first mode and the second mode. In the second mode, data from the first block is stored in a storage area of the buffer memory. 6. The data processing method according to claim 5, wherein control is performed such that the number of accesses for writing and the number of accesses for writing data from the second block are performed equally. 7. The data processing apparatus according to claim 5, wherein the data from the first block is video data. 8. The data processing apparatus according to claim 5, wherein the data from the first block is data continuously transmitted from a remote place in real time.