JP2006050077A - Data transfer control apparatus and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer control apparatus capable of efficiently realizing special reproduction etc. <P>SOLUTION: The data transfer control apparatus includes a first memory access controller DMAC1 for writing stream packets into a first memory SDRAM, a second memory access controller DMAC2 for extracting a packet including a specific kind of picture from among the stream packets written into the SDRAM and writing the read packet into a second SRAM, and a transfer controller 40 for performing control to add a header to the packet written in the SRAM and transfer the packet via a bus. A time stamp updating circuit 100 rewrites a time stamp value added to each packet read from the SDRAM into a new value corresponding to the kind of special reproduction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer control device and an electronic device.

  In recent years, digital recording / reproducing apparatuses capable of recording / reproducing MPEG (Moving Picture Experts Group) streams distributed by digital broadcasting such as BS digital and CS digital have been in the spotlight. The digital recording / reproducing apparatus includes a recording medium such as an HDD (Hard Disk Drive) for AV (Audio Visual). The MPEG stream from the digital tuner is recorded in the AV HDD during recording, and the MPEG stream is read from the AV HDD during playback and sent to the digital tuner. As conventional techniques of such a digital recording / reproducing apparatus, there are JP-A-9-247623 and JP-A-2000-224534.

Such a digital recording / reproducing apparatus can perform trick play such as fast forward and rewind. Therefore, in a data transfer control apparatus incorporated in a digital recording / reproducing apparatus, a technique for realizing such a special reproduction support function without increasing the processing load of the processing unit (CPU, firmware) so much. It becomes a subject.
Japanese Patent Laid-Open No. 9-247623 JP 2000-224534 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a data transfer control device and an electronic apparatus that can efficiently realize special reproduction and the like.

  The present invention relates to a data transfer control device for controlling data transfer via a bus, a first memory access controller for writing a stream packet to a first memory, and a stream written to the first memory. A packet including a specific type of picture is extracted from the packet, read out, a second memory access controller for writing the read packet into the second memory, and a header for the packet written in the second memory. In addition, the present invention relates to a data transfer control device including a transfer controller that performs control of transfer via a bus.

  In the present invention, a packet including a specific type of picture is extracted from the stream packet of the first memory, written to the second memory, and a header is added to the packet written to the second memory. , Transferred via the bus. In this way, since only packets containing a specific type of picture can be transferred via the bus, an efficient special playback support function and the like can be realized. Further, since the transfer controller does not need to be aware of the type of picture included in the packet of the second memory, the processing of the transfer controller can be simplified.

  In the present invention, the identification information of the picture included in the packet written in the first memory is detected, and the identification information and the storage address of the packet in the first memory are written in the picture information area. A detection circuit, wherein the second memory access controller reads out the identification information and the storage address from the stream packet written in the first memory in accordance with an instruction from the processing unit A packet including a specific type of picture may be extracted and read.

  In this way, the second memory access controller only needs to read the packet from the first memory in accordance with an instruction from the processing unit capable of performing a complicated determination process, so that the processing efficiency can be improved. .

  In the present invention, the identification information of the picture included in the packet written in the first memory in the current DMA transfer cycle is detected, and the identification information and the storage address of the packet in the first memory are obtained. Includes a detection circuit for overwriting the information written in the previous DMA transfer cycle and writing it in the picture information area, and identifying information of a picture included in the packet last written in the first memory in the previous DMA transfer cycle And the storage address of the packet in the first memory may be saved in the save area in the current DMA transfer cycle.

  In this way, the use size of the picture information area can be reduced, and the end part of a specific type of picture can be detected using the identification information and storage address saved in the save area.

  In the present invention, the first memory access controller reads a stream packet from a recording medium and writes the stream packet to the first memory, and the second memory access controller performs the first reproduction during the special reproduction of the stream packet. A packet including a specific type of picture necessary for the special reproduction may be extracted and read from the stream packet of one memory.

  In this way, it is possible to realize a data transfer control device that is optimal for special reproduction of stream packets.

  The present invention may further include a time stamp update circuit for rewriting a time stamp value added to each packet read from the first memory to a new value corresponding to the type of special reproduction.

  In this way, the time stamp value included in the packet can be rewritten to an optimum value according to the type of special reproduction (reproduction direction, reproduction speed, etc.).

  Also, in the present invention, the time stamp update circuit has the same difference value between the time stamp values added to adjacent packets and the difference value between the rewritten time stamp values in one picture. The time stamp value may be rewritten so that

  In this way, in one picture, the difference value of the original time stamp value is maintained even after the rewriting process, and an appropriate image can be generated during special reproduction.

  In the present invention, the time stamp update circuit performs a time stamp value rewriting process so that a difference value between pictures of the time stamp value after rewriting changes according to the speed of the special reproduction. May be.

  In this way, it becomes possible to rewrite the time stamp value of the packet to an appropriate time stamp value corresponding to the speed of special reproduction.

  According to the present invention, the time stamp update circuit temporarily stores a packet read from the first memory and outputs the packet to the second memory, and the previous read from the first memory. A time stamp value storage register for storing a time stamp value added to the issued packet, a current time stamp value added to the packet read from the first memory, and the time stamp value storage Each time a DMA transfer of a packet from the first memory to the second memory is performed, a difference value calculation circuit that calculates a difference value from the previous time stamp value stored in the register, and the current DMA An offset value register in which an initial value of a time stamp in transfer is set as an offset value, and an offset from the offset value register A difference value from the difference value calculation circuit is added to the data value, and an addition circuit that outputs the value obtained by the addition as an update time stamp value to the transmission FIFO and writes it back to the offset value register is included. Good.

  The present invention also includes a cycle timer for counting a cycle time for determining a transfer cycle, wherein the transfer controller adds a time stamp value added to the packet written in the second memory and a given setting. Compare the value, and for the packet whose time stamp value matches the set value, rewrite the time stamp value to a value obtained by adding the offset value to the current cycle time, transfer it via the bus, and The value may be updated.

  In this way, it is possible to rewrite the time stamp value of the packet to an appropriate time stamp value corresponding to the current cycle time.

  In the present invention, the first memory may be a memory having a larger capacity than the second memory and capable of sequential access at a higher speed than the second memory.

  In the present invention, data transfer conforming to the IEEE 1394 standard may be performed.

  The present invention also relates to an electronic apparatus including any one of the data transfer control devices described above and a recording medium for recording stream data.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Electronic Device FIGS. 1A and 1B show an example of an electronic device 16 (digital recording / reproducing device) including the data transfer control device 30 of this embodiment. The electronic device 16 includes an HDD (Hard Disk Drive) and a data transfer control device 30. Also included is an operation unit 12 for the user to operate the electronic device. Moreover, the display part 14 (LCD) which displays various information to a user is included.

  The user can designate a reproduction mode (normal reproduction, special reproduction) by operating the operation unit 12. Further, by viewing information displayed on the display unit 14, the current playback mode and the like can be confirmed.

  The electronic device 16 is connected to a digital tuner 20 (or a digital video camera) via a first bus BUS1 such as IEEE 1394 (or USB 2.0). The digital tuner 20 includes an MPEG (Moving Picture Experts Group) decoder 21 which decodes MPEG stream packets (stream packets in a broad sense, first layer packets) received by the antenna 26 and the like. To do. Based on the decoded data, the television 24 (display unit) displays video or outputs audio. Further, the user can select a channel (broadcast station), specify a playback mode (normal playback, special playback), and the like using the operation unit 22 (remote controller or the like).

  When recording an MPEG stream packet to an AV (Audio Visual) HDD (storage medium in a broad sense), the MPEG stream packet (TS packet) received by the antenna 26 is BUS1 (IEEE 1394, USB 2.0), The data is written to the HDD via the data transfer control device 30.

  On the other hand, when reproducing the MPEG stream of the HDD, the MPEG stream packet is read from the HDD via the second bus BUS2 such as IDE (Integrated Device Electronics). Then, the read MPEG stream packet is transferred to the digital tuner 20 via the data transfer control device 30 and BUS1, and the MPEG decoder 21 of the digital tuner 20 decodes it. Thereby, an image is displayed on the television 24.

  Note that electronic devices to which the present embodiment is applied are not limited to those shown in FIGS. For example, the present invention can be applied to various electronic devices such as a video tape recorder (built-in HDD), an optical disk (DVD) recorder, a digital video camera, a personal computer, or a portable information terminal. In the following, the case where BUS1 is an IEEE1394 bus will be described as an example, but BUS2 may be another high-speed serial bus such as USB 2.0.

2. Stream Structure Next, a stream structure (hierarchical structure) of MPEG2 (hereinafter, simply referred to as MPEG) will be described with reference to FIG.

  In an MPEG TS (Transport Stream) packet, an I picture (intra-frame encoded data in a broad sense), a B picture and a P picture (inter-frame encoded data or predictive encoded data in a broad sense), audio data (sound Data, non-video data) and the like are multiplexed into one bit stream and packetized. As shown in FIG. 2, in the MPEG stream packet, a PES (Packetized Elementary Stream) packet (packet in the second layer in a broad sense) is formed by concatenating the payload of the TS packet. Specifically, by combining the payloads of TS packets having the same PID (Packet IDentification), a variable-length PES packet including a PES header and a PES payload is configured.

  An ES (Elementary Stream) is a component of content such as video and audio. This ES with a header added is called PES. In MPEG2, two types of multiplexed streams, TS (Transport Stream) and PS (Program Stream), are defined for multiplexing PES.

  TS is a stream in which TS packets having a fixed length of 188 bytes are continuous. A TS packet is composed of a TS header and a TS payload. By using PID (packet identification information) included in the TS header, about 8000 types of TS packets can be identified. As shown in FIG. 2, the PES is divided and arranged into TS packets having the same PID. On the receiving side, the original PES can be restored by connecting the payloads of TS packets having the same PID. The head of the PES packet is arranged so as to start from the head of the TS payload identified by PUSI (payload part start indicator).

3. Isochronous transfer In IEEE 1394, as a packet transfer method, an asynchronous transfer suitable for data transfer that requires reliability and an isochronous transfer suitable for transfer of data such as moving images and audio that require real-time performance are used. ) Transfer is prepared. FIG. 3A schematically shows the state of the bus at the time of data transfer in IEEE1394. Isochronous transfer starts when the cycle master generates a cycle start packet at regular intervals. As a result, at least one isochronous (ISO) packet can be transferred every 125 μs (each isochronous transfer cycle) per channel. As a result, it is possible to transfer data that requires real-time properties such as moving images and sounds. On the other hand, asynchronous transfer is performed between isochronous transfers. That is, in IEEE 1394, isochronous transfer has a higher priority than asynchronous transfer, and an asynchronous (ASY) packet is transferred using the remaining period after the end of isochronous transfer.

  FIG. 3B shows a format example of an isochronous transfer packet when an MPEG stream is transferred via the IEEE1394 bus. In FIG. 3B, the ISO header corresponds to the header of the IEEE 1394 format packet, and the CIP (common isochronous packet) header, the SP (source packet) header, and the TS (Transport Stream) packet are data of the IEEE 1394 format packet ( Equivalent to payload).

  Examples of formats of the SP header and CIP header are shown in FIGS. These SP header (SPH) and CIP header (CPH) are defined by the ISO / IEC61883 standard that defines a protocol for transferring MPEG stream packets on the IEEE 1394 bus. For example, the SP header includes a cycle count (time stamp value) and a cycle offset. The cycle count is incremented every 125 μs of isochronous transfer. Specifically, when the cycle offset overflows, the cycle count is incremented. The CIP header declares that the data to be transferred is MPEG, and specifies a method for dividing an MPEG TS packet, and includes a source node ID, a data block size, a format ID, and the like.

4). Data transfer control device In an electronic device such as a digital recording / playback device, how to realize a special playback (trick play) function such as fast-forward playback or rewind playback is an issue. In this case, for example, there is a method of repeating the track jump when reading a little data from the HDD during fast-forward playback. However, this method has problems such as the image being disturbed and the movement of the display object becoming awkward. In the prior art disclosed in JP-A-9-247623 and JP-A-2000-224534, the MPEG stream packet is not recorded as it is on the HDD, but is reconfigured and recorded in another format. There is a problem that the processing load of the CPU becomes heavy with increasing complexity.

  FIG. 4 shows a configuration example of the data transfer control device 30 (integrated circuit) of the present embodiment that can solve such problems. Note that the data transfer control device 30 of this embodiment does not have to include all the components shown in FIG. 4, and some of them may be omitted or other components may be added. For example, an SRAM (Static Random Access Memory), a physical layer circuit 49, a processing unit 60, etc. may not be provided in the apparatus. An SDRAM (Synchronous Dynamic Random Access Memory) may be provided inside the apparatus.

  The data transfer control device 30 includes an IDE interface 32 (first interface, recording medium interface in a broad sense). The IDE interface 32 realizes an interface conforming to IDE (Integrated Device Device Electronics) between the data transfer control device 30 and the hard disk drive HDD (recording medium in a broad sense). The data transfer control device 30 includes an SDRAM interface 34 for realizing an interface with the SDRAM.

  The data transfer control device includes a DMAC 1 (first memory access controller in a broad sense). The DMAC 1 performs a process for writing a stream packet transferred from the BUS 2 side (HDD, IDE) in a transmission area of the SDRAM (first memory in a broad sense). Also, the stream packet written in the receiving area of the SDRAM is read, and a process for transferring the read stream packet to the BUS2 side is performed. Specifically, the DMAC 1 generates a write request and a write address when writing to the SDRAM, and generates a read request and a read address when reading from the SDRAM. Thereby, it is possible to realize DMA (Direct Memory Access) transfer without the processing unit 60 interposed between the SDRAM and the BUS2.

  In a normal time, the DMAC 1 sequentially writes stream packets (data) corresponding to the DMA transfer size in the first to Nth areas of the SDRAM in ascending order by a ring buffer method while incrementing the address. Specifically, in the first DMA transfer cycle, a stream packet corresponding to the DMA transfer size is written in the first area of the lower address of the SDRAM while incrementing the address, and in the second DMA transfer cycle, it is larger than that in the first area. The stream packet for the DMA transfer size is written in the second area of the upper address while incrementing the address, and in the Nth DMA transfer cycle, the Nth area of the higher address than the N-1 area. In the (N + 1) th DMA transfer cycle, stream packets for the DMA transfer size are written in the first area while incrementing the address.

  On the other hand, during special playback in the reverse direction, the DMAC 1 uses the ring buffer method while incrementing the address, and stream packets (data) corresponding to the DMA transfer size in descending order to the first to Nth areas of the SDRAM. Write sequentially. Specifically, in the first DMA transfer cycle, a stream packet corresponding to the DMA transfer size is written to the Nth area of the higher address of the SDRAM while incrementing the address, and in the second DMA transfer cycle, the stream packet is larger than the Nth area. A stream packet for the DMA transfer size is written to the (N-1) th area of the lower address while incrementing the address, and the first area of the lower address than the second area in the Nth DMA transfer cycle In the (N + 1) th DMA transfer cycle, stream packets for the DMA transfer size are written to the Nth area while incrementing the address.

  The data transfer control device 30 includes a DMAC 2 (second memory access controller in a broad sense). The DMAC 2 reads a stream packet written in the transmission area of the SDRAM and performs processing for writing the read stream packet in the transmission area of the SRAM (second memory in a broad sense). In addition, a stream packet written in the SRAM reception area is read, and a process for writing the read stream packet in the SDRAM reception area is performed. Specifically, the DMAC 2 generates a read request and a read address when reading from the SRAM and SDRAM, and generates a write request and a write address when writing to the SRAM and SDRAM. As a result, DMA transfer without the processing unit 60 interposed between the SRAM and the SDRAM can be realized.

  In this embodiment, the DMAC 2 reads and reads only a packet including a specific type of picture (for example, an I picture or a combination of an I picture and another picture) from the stream packets written in the SDRAM (transmission area). The packet thus written is written in SRAM (transmission area). Specifically, at the time of special reproduction of a stream packet of the HDD (recording medium), only a packet including a specific type of picture necessary for special reproduction is extracted from the SDRAM stream packet and read out.

  In reverse special reproduction (rewind reproduction) of the stream packet (HDD), the DMAC 2 performs reverse special reproduction among packets (TS packets) including a specific type of picture (I picture) stored in the SDRAM. Packets whose playback time (scheduled playback time) is early (packets with a small time stamp value when transferred via BUS1) are written into the lower address area (first SRAM area) of the SRAM. In addition, for a packet with a late reverse special reproduction time (a packet having a larger time stamp value when transferred via BUS1), an upper address area of the SRAM (second SRAM having an upper address than the first SRAM area) Area). In other words, a packet including a specific type of picture stored in the upper address area in the SDRAM is written in the lower address area of the SRAM, and the specific type stored in the lower address area in the SDRAM. A packet including a picture is written into the upper address area of the SRAM. In the case of the ring buffer method, the upper and lower addresses substantially include the upper and lower addresses.

  The DMAC 2 includes a time stamp update circuit 100. The time stamp update circuit 100 is a circuit for rewriting a time stamp value added to each packet read from the SDRAM to a new value. Specifically, the time stamp value added to each packet read from the SDRAM is rewritten to a new value corresponding to the type of special reproduction (reproduction direction, reproduction speed). More specifically, the time stamp update circuit 100, in one picture (one frame picture), between the time stamp values added to adjacent packets (adjacent packets written in SDRAM). The rewriting process is performed so that the difference value and the difference value between the time stamp values after rewriting are the same value. Further, the difference value between pictures of the time stamp value after rewriting (the time stamp value after rewriting a specific type of picture of the I-th frame and the time after rewriting of the specific type of picture of the I-1 frame) The rewriting process is performed so that the difference value with respect to the stamp value changes according to the speed of special reproduction. For example, the rewriting process is performed so that the difference value decreases as the reproduction speed increases and the difference value increases as the reproduction speed decreases. At the time of reverse special reproduction, the time stamp value of the packet written in the lower address area of the SRAM is reduced, and the time stamp value of the packet written in the upper address area of the SRAM is reduced. Rewrite processing is performed so that becomes larger.

  Note that SDRAM (first memory, synchronous memory) is a large-capacity memory compared to SRAM. Further, it is a memory that can perform sequential access (access to consecutive addresses) at a higher speed than SRAM. In addition, it is a memory capable of inputting / outputting continuous address data (burst data) in synchronization with a clock. The SDRAM is preferably provided outside the data transfer control device, but may be provided inside the data transfer control device. Further, instead of a normal SDRAM, for example, a high-speed synchronous memory such as a DDR type SDRAM or a Rambus RDRAM may be employed. The storage area of the SDRAM may be separated into a transmission area and a reception area, or may be separated into an asynchronous area and an isochronous area.

  On the other hand, SRAM (second memory, packet memory, packet buffer) is a memory having a smaller capacity than SDRAM. The SRAM is a memory that can be randomly accessed by the processing unit 60 (CPU, MPU, system controller) or the like, and is a memory for sorting packets. The SRAM is preferably provided inside the data transfer control device, but may be provided outside the data transfer control device. The storage area of the SRAM may be separated into a header area (control information area) and a data area, a transmission area and a reception area, or an asynchronous area and an isochronous area.

  The data transfer control device 30 includes a transfer controller 40 (link controller). This transfer controller 40 controls data transmission processing and reception processing via BUS1. For example, at the time of transmission, a packet (TS packet) is read from the SRAM, and an isochronous header (a third layer header in a broad sense) is added and transferred via BUS1. At the time of reception, a packet transferred via BUS1 is received, and received data (TS packet) is written into the SRAM.

  The transfer controller 40 includes a header creation circuit 42 and a DMAC 3 (third memory access controller in a broad sense). The header creation circuit 42 reads the time stamp value (SP header) added to each packet of the SRAM and compares it with the set value of the transfer start time stamp setting register 44. If the time stamp value matches the set value, an isochronous header is created and written in the isochronous header area. When the isochronous header exists in the isochronous header area, the DMAC 3 reads the isochronous header and a packet (TS packet) serving as the payload from the SRAM and transfers them via the BUS1. On the other hand, if the isochronous header does not exist in the isochronous header area, the Null packet header is read from the SRAM, and the Null packet having no payload is transferred via BUS1.

  The data transfer control device 30 includes a pointer controller 46. The pointer controller 46 calculates the amount of data stored in the SRAM. Specifically, the link side pointer and the SDRAM side pointer are compared to calculate the remaining amount of data in the SRAM, and output to the transfer controller 40.

  The data transfer control device 30 includes a cycle timer 48. The cycle timer 48 counts the cycle time for determining the transfer cycle of BUS1. The transfer controller 40 compares the time stamp value (SPH) added to each packet of the SRAM with the set value (transfer start time stamp setting register 44). For a packet whose time stamp value matches the set value, rewrite the time stamp value of the packet to a value obtained by adding an offset value to the current cycle time, and add a header to the rewritten packet (payload). Transfer over the bus.

  For example, the current cycle time is 100 in A1 of FIG. In A2, the time stamp value of the packet is rewritten and transferred to 103, which is a value obtained by adding the offset value (= 3) to the current cycle time (= 100). Therefore, this packet is reproduced at the cycle time indicated by A3.

  The data transfer control device 30 includes a physical layer (PHY) circuit 49. The physical layer circuit 49 is a circuit that implements the IEEE 1394 physical layer protocol, and converts logical symbols used in the transfer controller 40 and the like into electrical signals.

  The data transfer control device 30 includes a detection circuit 50. The detection circuit 50 performs picture information detection processing. That is, the structure (hierarchical structure) of stream packets read from the HDD is analyzed, and picture information for selecting TS packets to be transferred via the IEEE 1394 bus is detected. Then, the detected picture information is written in the picture information area of the SRAM.

  FIG. 6 shows an example of the picture information area. As shown in FIG. 6, picture identification information (information for identifying which picture is I, B, or P) and a storage address (AD0) of a packet (TS packet) including the picture on the SDRAM ˜AD15) are written as picture information. Note that the picture information area may be realized by using an SRAM or by using the register unit 62.

  More specifically, the detection circuit 50 detects (acquires) header information (stream ID or the like) of the PES packet. As shown in FIG. 7A, this PES packet (second layer packet in a broad sense) is formed by concatenating payloads of TS packets (first layer packet in a broad sense). The detection circuit 50 detects whether or not the PID of the TS packet is a PID designated by the processing unit 60 (PID setting register). If it is the designated PID, whether or not the payload of the TS packet is the first TS payload constituting the PES packet is included in the TS header as shown in C1 of FIG. Judgment is made using a PUSI (payload part start indicator).

  If the detection circuit 50 determines that it is the leading TS payload, it acquires the stream ID from the PES header included in the leading TS payload, as indicated by C2 in FIG. Then, using the acquired stream ID, it is confirmed whether the TS packet of the video stream or the TS packet of the audio stream (non-video stream).

  When the detection circuit 50 determines that the PID of the TS packet is the PID specified by the processing unit 60 and the TS packet of the video stream, the detection circuit 50 detects the payload (data byte) of the PES, and The start code included in the payload is detected. Then, it is determined whether the detected start code is a sequence header code, a group start code, or a picture start code. When the detected start code is the picture start code indicated by C3 in FIG. 7B, the detection circuit 50 includes identification information of I, B, and P pictures that are picture coding types indicated by C4, The storage address (head address) of the TS packet containing the picture on the SDRAM is written as picture information in the picture information area of the SRAM and displayed on the processing unit 60.

  The DMAC 2 extracts a packet including a specific type of picture (I picture or the like) from the stream packet written in the SDRAM in accordance with an instruction from the processing unit 60 that has read the identification information and storage address displayed in the picture information area. And read.

  The data transfer control device 30 includes a processing unit 60. The processing unit 60 performs control of each circuit in the apparatus and overall control of the apparatus. The function of the processing unit 60 is realized by hardware such as a CPU or a system controller, or firmware (program). The processing unit 60 may be provided outside the data transfer control device 30.

  The data transfer control device 30 includes a register unit 62. In the save area (PicInfoRsv register) of the register unit 62, the information written in the picture information area is saved.

  Specifically, the detection circuit 50 detects the identification information of the picture included in the packet written in the SDRAM in the current DMA transfer cycle, and writes the identification information and the storage address of the packet in the previous DMA transfer cycle. Overwrite the recorded information and write it in the picture information area.

  For example, during forward special reproduction, the picture identification information included in the packet last written to the SDRAM in the previous DMA transfer cycle and the storage address of the packet are saved in the save area in the current DMA transfer cycle. . On the other hand, at the time of reverse special reproduction, the identification information of the picture included in the packet first written in the SDRAM in the previous DMA transfer cycle and the storage address of the packet are saved in the save area in the current DMA transfer cycle. . Note that the save area may be realized using a register or an SRAM.

  FIG. 8 shows a register configuration example of the register unit 62. As shown in FIG. 8, the register unit 62 includes an interrupt processing register, a picture information register, a time stamp rewrite processing register, and the like.

  DetectIpicStart in the interrupt processing register is a register for generating and notifying an interrupt when the detection circuit 50 detects the head of the I picture during DMA transfer from the HDD to the SDRAM. DetectIpicEnd is a register for generating and notifying an interrupt when the detection circuit 50 detects the head of the next picture (B picture or the like) after the I picture during DMA transfer from the HDD to the SDRAM. EnDetectIpicStart and EnDetectIpicEnd are registers for setting enable / disable of interrupts of DetectIpicStart and DetectIpicEnd.

  PictureAnalyzePID [4: 0] in the picture information register is a register for writing a PID register number in which a PID for performing picture analysis is set. PicInfoRsv [31: 0] is a register serving as a save area for information stored in the picture information area. PicInfoPtrClr is a register for clearing the pointer (PicInfoAreaPtr) of the picture information area. PicInfoPtrOverFlow is a register for informing that picture information overflows and data that has failed to be written appears. PicInfoAreaPtr [3: 0] is a pointer register for notifying how far information storage in the picture information area has progressed. When the value of PicInfoRsvBxT is “0”, the first (top) information of the picture information area is saved in the save register PicInfoRsv, and when the value is “1”, the last information of the picture information area is the save register PicInfoRsv. Evacuated. PicInfoDetectEnable is a register for setting enable / disable of the picture information detection / display function.

  TimeStampHead [25: 0] in the time stamp rewrite processing register is a register for setting a time stamp value to be added to the TS packet immediately after the start of DMA transfer. RenewSPHEnb is a register for setting enable / disable of update processing of the time stamp value.

5). SDRAM and SRAM
In this embodiment, an SDRAM is provided to prevent a buffer underrun error due to HDD seek. For example, even if it takes time to seek the HDD, a buffer underrun error can be prevented by providing an SDRAM. Then, after the stream packet from the HDD is once written in the SDRAM, the DMAC 2 writes a necessary packet out of the stream packet written in the SDRAM as shown in FIG. Specifically, the DMAC 2 extracts and reads out a packet including a specific type of picture from the stream packet written in the SDRAM (first memory), and reads the read packet into the SRAM (second memory). Write. For example, in FIG. 9, a packet including an I picture is extracted from the stream packets written in the SDRAM and written in the SRAM. In this way, special reproduction using an I picture can be realized efficiently.

  Note that DMA transfer via the IDE interface 32 is performed at an integer multiple of 512 bytes. On the other hand, the size of the TS packet in the MPEG2 standard is 188 bytes, and since the 4-byte SPH is added to this TS packet, the size of the TS packet on the SDRAM is 192 bytes. Therefore, it is desirable to set the DMA transfer size to a common multiple of 512 and 192 bytes (for example, 512 × 96 bytes). In this way, the boundary of the DMA transfer and the boundary of the TS packet are not shifted on the SDRAM, and efficient data transfer can be realized.

6). Special Playback Support Function In this embodiment, the data transfer control device has the following functions in order to realize special playback.

  The data transfer control device writes stream packets (data) stored in the HDD to the SDRAM. At the time of special reproduction, only the video stream packet is extracted and written into the SDRAM. In addition, the copy control information of the read packet is rewritten, and the CRC is recalculated as the information is rewritten.

  At the time of special reproduction, only I pictures are extracted from the video stream packets recorded in the SDRAM and transferred to the SRAM. In addition, rewriting is performed on necessary portions (trick mode, etc.) in the PES header. During special playback in the reverse direction, stream packets are read from the IDE (HDD) while going back to the past. At the time of special reproduction, the SPH time stamp value of the transmission packet is rewritten to a new value according to the reproduction speed (re-pasted).

  In order to realize the above functions, for example, the division of roles between the hardware circuit and the firmware (processing unit) is performed as follows.

  Firmware is activated for DMA transfer from IDE (HDD) to SDRAM. That is, the firmware starts the DMA transfer by specifying the transfer destination address and the DMA transfer size. The firmware sets the PID of the video stream packet to be passed in a register (PictureAnalyzePID in FIG. 8). The hardware circuit writes only the set PID packet to the SDRAM (PID filter processing).

  From the video stream packet written in the SDRAM, the head address of the TS packet including the head of the I picture is detected and displayed. Further, the head address of the TS packet next to the TS packet including the end of the I picture is detected from the video stream packets written in the SDRAM and displayed. The firmware then activates the DMA that transfers only the I picture from the SDRAM to the SRAM.

  From the video stream packet written in the SDRAM, the head address of the TS packet including the head of the PES header is detected and displayed. The firmware rewrites the contents of the detected PES header so as to match the special reproduction.

  The firmware rewrites the contents of the time stamp value (SPH) added in advance to the first packet of the I picture according to the setting of the playback speed. For example, in the case of double speed, the difference value between the time stamp values of adjacent I pictures is halved. In the case of quadruple speed, the difference value is ¼. The rewriting process is performed so that becomes 1/8. On the other hand, in the same I picture, the time stamp value after rewriting is increased according to the increment of the time stamp value originally added.

7). Forward Special Playback Next, the operation of the data transfer control device during forward special playback will be described with reference to FIGS. DM1, DM2, and DM3 represent first, second, and third DMA transfer cycles. Further, as described above, the DMA transfer size is set to a common multiple of 512 and 192 (for example, 512 × 96 bytes).

  First, a stream packet is DMA-transferred and written from IDE (HDD) to SDRAM. When the head of a TS packet including an I picture is detected during DMA transfer as indicated by E1 in FIG. 10, a DetectIpicStart interrupt (see FIG. 8) is generated and notified to the firmware (processing unit). As indicated by E2 in FIG. 10, when the head of the next picture after the I picture (the end of the I picture) is detected, a DetectIpicEnd interrupt (see FIG. 8) is generated and notified to the firmware.

  As shown in FIG. 11, the picture information discovered during one DMA transfer cycle is displayed (indicated) in the picture information area of the SRAM. For example, in the DMA transfer cycles DM1, DM2, and DM3, picture information is displayed as indicated by F1, F2, and F3 in FIG.

  Specifically, picture identification information included in a TS packet written in the SDRAM and a storage (head) address of the TS packet in the SDRAM are displayed as picture information. For example, in F1 of FIG. 11, it is displayed that pictures included in each TS packet are I, B, P... B pictures, and the storage address of each TS packet (TS packet including SPH) is 00000, 00384, 00576... 48960 are displayed.

  In this embodiment, I picture selection processing is performed using this picture information (identification information, storage address). That is, as shown in FIG. 10, only TS packets including I pictures (specific types of pictures in a broad sense) are extracted from the TS packets written in the SDRAM and read out and written into the SRAM.

  For example, in the DMA transfer cycle DM1, the start address 00000 of the TS packet including the I picture and the start address 00434 (end address of the I picture) of the TS packet including the next B picture are displayed in the picture information area. In addition, picture identification information of the TS packet stored at addresses 00000 to 0434 is also displayed.

  When an interrupt occurs at E1 and E2 in FIG. 10, the firmware reads the picture information of F1 in FIG. Based on the read picture information, the firmware can know that the I picture is stored in the area of addresses 00000 to 00434. Then, the firmware sets the DMA transfer start address and size using addresses 00000 and 00434, and activates the DMA transfer. Then, the DMAC 2 receiving the instruction from the firmware reads out the TS packet including the I picture stored in the area of 00000 to 0434 as shown by E5 in FIG. 10 from the SDRAM, and writes it in the SRAM.

  In the DMA transfer cycle DM2, the picture information area pointer PicInfoAreaPtr is cleared using PicInfoPtrClr in FIG. Then, the picture information in the picture information area is updated as indicated by F2 in FIG. That is, the picture information detected in the current DMA transfer cycle DM2 is overwritten on the picture information detected in the previous DMA transfer cycle DM1 and written into the picture information area. In addition, picture information detected last in the previous DMA transfer cycle DM1 is saved in the save area (PicInfoRsv). For example, F4 in FIG. 11 is the picture information detected last in the previous DMA transfer cycle DM1, and is the picture information of the TS packet last written in the SDRAM. This picture information is saved in the save area as indicated by F5.

  When an interrupt occurs at E3 in FIG. 10, the firmware reads the picture information indicated by F2 and F5 in FIG. At this time, since the head address of the picture next to the I picture has not been detected yet, DMA transfer of the I picture from the SDRAM to the SRAM is not performed. As described above, when the end portion of the I picture is not detected in one DMA transfer cycle, the end portion of the I picture is detected in the subsequent DMA transfer cycles.

  In the DMA transfer cycle DM3, the picture information detected in the current DMA transfer cycle DM3 is written over the picture information area. Further, the picture information detected last in the previous DMA transfer cycle DM2 is saved in the save area as indicated by F6 and F7 in FIG.

  When an interrupt occurs at E4 in FIG. 10, the firmware reads the picture information indicated by F3 and F7 in FIG. Based on the read picture information, the firmware can know that the I picture is stored in the area of addresses 97920 to 98496. Then, the firmware sets the DMA transfer start address and size using addresses 97920 and 98496, and activates the DMA transfer. Then, the DMAC 2 that has received the instruction from the firmware reads the TS packet including the I picture stored in the area of addresses 97920 to 98496 from the SDRAM and writes it to the SRAM, as indicated by E6 in FIG.

  As described above, in the present embodiment, after the stream packet from the BUS2 side is once written in the SDRAM, only a specific type of packet is extracted from the SDRAM, read, and written in the SRAM. In this way, a buffer underrun error due to HDD seek can be effectively prevented by using an SDRAM capable of high-capacity and high-speed sequential access in addition to a small-capacity SRAM. In addition, an inexpensive and high-speed SDRAM can be adopted as the external memory of the data transfer control device, and an SRAM having a smaller capacity than the SDRAM can be used as the built-in memory of the data transfer control device, so that the cost of the product can be reduced.

  In this embodiment, only packets including a specific type of picture are written in the SRAM. Therefore, special reproduction such as fast-forwarding and rewinding can be realized simply by the transfer controller 40 reading these packets from the SRAM, adding a header and transferring them to the BUS1 side. Therefore, the data transfer at the time of special reproduction can be made efficient. That is, in the method of selecting and reading out a packet including a specific type of picture from stream packets written in one memory (SDRAM or SRAM), pointer control or the like becomes complicated, and the efficiency of data transfer is reduced. On the other hand, in this embodiment, only packets including a specific type of picture are continuously written in the SRAM. Therefore, the packet necessary for special reproduction can be transferred to the BUS1 side only by the transfer controller 40 reading out the continuously written packets and adding a header. As a result, data transfer can be made more efficient and the processing load on the firmware can be reduced.

8). Rewriting process of time stamp value at the time of forward special reproduction In this embodiment, the time stamp value (SPH) added to the TS packet read from the SDRAM is rewritten to a new value according to the type of special reproduction. Yes.

  In G1 and G2 in FIG. 12, the time stamp values of the first TS packet and the next TS packet of the first I picture are 1000 and 1100, respectively. When these TS packets are read from the SDRAM and written to the SRAM, the time stamp value is rewritten. That is, the time stamp value of the first TS packet is rewritten to an arbitrary initial value by the firmware and written to the SRAM. For example, in G3 of FIG. 12, the initial value is rewritten to 2000. As the initial value, a value obtained by adding a given offset value to the cycle time at that time (the cycle time counted by the cycle timer 48) can be adopted. Note that the time stamp value (1000) originally added to the packet on the SDRAM may be used as it is as the initial value.

  The difference value between the time stamp values on the SRAM is maintained as the difference value between the time stamp values on the SDRAM. For example, the original time stamp values on the SDRAMs indicated by G1 and G2 in FIG. 12 are 1000 and 1100, and the difference value is 100. The time stamp values after rewriting on the SRAM indicated by G3 and G4 are 2000 and 2100, and the difference value is maintained to be 100. As described above, in the present embodiment, in one picture (in one frame), the difference value (100) between the time stamp values (1000, 1100) of adjacent TS packets on the SDRAM, and the rewritten SRAM The rewriting process is performed so that the difference value (100) between the time stamp values (2000, 2100) is the same. In this way, an appropriate image can be generated during special reproduction.

  As indicated by G5 in FIG. 12, the time stamp value of the first TS packet on the SDRAM of the next I picture (the I picture of the next frame) is 4000. In this case, as shown in G8, the time stamp value of the first TS packet on the SRAM of this I picture is rewritten to the initial value 3500. Specifically, it is rewritten according to the following formula.

InitialValueJ = InitialValueJ-1 + (StartTimeStampJ-StartTimeStampJ-1) / K
Here, InitialValueJ is the initial value of the time stamp of the current I picture on the SRAM, and InitialValueJ-1 is the initial value of the time stamp of the previous I picture on the SRAM. StartTimeStampJ is the time stamp value of the first TS packet on the SDRAM of the current I picture, and StartTimeStampJ-1 is the time stamp value of the first TS packet on the SDRAM of the previous I picture. K is a magnification of the special reproduction speed. For example, in the case of 2 × speed, 4 × speed, and 8 × speed, K = 2, 4, and 8.

  InitialValueJ-1 = 2000 as indicated by G3 in FIG. As indicated by G5, StartTimeStampJ = 4000, and as indicated by G1, StartTimeStampJ-1 = 1000. Since the reproduction speed is double speed, K = 2. Therefore, the initial value of the current time stamp is InitialValueJ = 2000 + (4000−1000) / 2 = 3500 as shown in G8. For example, when the playback speed is quadruple speed, InitialValueJ = 2000 + (4000−1000) / 4 = 2750. As described above, in this embodiment, the rewriting process is performed so that the difference value between the I pictures of the time stamp value after rewriting changes according to the reproduction speed. In this way, an appropriate time stamp value corresponding to the reproduction speed can be added to the TS packet on the SRAM. Therefore, the transfer controller 40 only needs to read the TS packet from the SRAM, rewrite it to a time stamp value corresponding to the transfer cycle, and transfer it without being aware of the playback speed of special playback. Thereby, data transfer can be made efficient.

  As shown in G5 to G7 and G8 to G10 in FIG. 12, the difference value of the time stamp value is maintained at the original value in one I picture. That is, the increment of the original time stamp value is directly reflected in the rewritten time stamp value.

9. Configuration Example of Time Stamp Update Circuit FIG. 13 shows a configuration example of the time stamp update circuit 100 included in the DMAC. The time stamp update circuit 100 includes an update control circuit 102, a time stamp value storage register 104, a difference value calculation circuit 106, an offset value register 108, an addition circuit 110, and a transmission FIFO 112. Note that some of these components may be omitted.

  In FIG. 13, a transmission FIFO 112 (FirstInFirstOut storage unit) temporarily stores a packet (SPH) read from the SDRAM and outputs it to the SRAM. The time stamp value storage register 104 stores the time stamp value added to the packet read from the SDRAM last time. The difference value calculation circuit 106 calculates a difference value between the current time stamp value added to the packet read this time from the SDRAM and the previous time stamp value stored in the time stamp value storage register 104. . The offset value register 108 is a register for storing an offset value, and an initial value of a time stamp is set as an offset value every time a DMA transfer (DM1, DM2, DM3) of a packet from the SDRAM to the SRAM is performed. The addition circuit 110 adds the difference value from the difference value calculation circuit 106 to the offset value from the offset value register 108 and outputs the addition value to the transmission FIFO 110 as an update time stamp value. The update time stamp value is written back (overwritten) in the offset value register 108 as an offset value.

  Next, the operation of the time stamp update circuit 100 will be described. The time stamp update circuit 100 operates when the update circuit enable signal from the processing unit 60 becomes active. Specifically, when data transfer (DMA) from the SDRAM to the SRAM is started, the update circuit enable signal becomes active and the operation is started. In addition, the processing unit 60 sets an initial value of the time stamp in the offset value register 108 in advance. For example, in G8 of FIG. 12, the initial value = 3500 is set.

  When the DMA count = 0, the update control circuit 102 activates only the update strobe signal without activating the addition enable signal. As a result, the offset value (= 3500) output from the offset value register 108 is output to the transmission FIFO 112 as it is as an update time stamp value. That is, the SPH time stamp value (= 4000) stored in the transmission FIFO 112 is rewritten to the initial time stamp value (= 3500) set in the offset value register 108. The SPH time stamp value (= 4000) is stored in the time stamp value storage register 104 at the timing when the SPH is input to the transmission FIFO 112.

  When the DMA count is incremented and the time stamp value (= 4100) of this SPH is input to the transmission FIFO 112, the time stamp update circuit 100 operates as follows. First, the difference value calculation circuit 106 calculates a difference value (= 100) between the current SPH time stamp value (= 4100) and the previous SPH time stamp value (= 4000) stored in the time stamp value storage register 104. ) And is output to the adder circuit 110. If the DMA count is other than 0, the update control circuit 102 activates both the update strobe signal and the addition enable signal. Then, the addition circuit 110 adds the difference value (= 100) from the difference value calculation circuit 106 and the offset value (= 3500) from the offset value register 108, and adds the addition value (= 3600) to the update time stamp value. To the transmission FIFO 112. As a result, the original time stamp value (= 4100) in the transmission FIFO 110 is rewritten to the update time stamp value (= 3600). At the same time, the update time stamp value is overwritten in the offset value register 108 and written back.

  By repeating the above process until the DMA transfer is completed, a process of rewriting to a new time stamp value while calculating a difference value between time stamp values of the original SPH is realized.

10. Rewriting the time stamp value at the time of packet transfer (1) Recording a stream packet to the HDD When recording a stream packet to the HDD, unlike the case of inputting broadcast data from the stream interface, each packet has SPH in advance. It has been added. This is because these stream packets are recorded in the HDD via IEEE1394 or the like. Therefore, at the time of recording on the HDD, the sent stream packet may be written to the HDD as it is without any modification to the SPH. When recording to the HDD, the stream packet is once written in the SDRAM. When a certain amount of packets are accumulated in the SDRAM, the accumulated packets are written to the HDD all at once regardless of the cycle time.

(2) Reproduction of HDD Stream Packets When reproducing HDD stream packets, as shown in FIG. 14A, packets are read from the HDD into the SDRAM at a stretch in a relatively large unit. As shown in FIG. 14A, the read timing in this case is a timing unrelated to the cycle time in BUS1 (IEEE1394) at that time. The SPH time stamp value (absolute value) added to the packet during recording is completely independent of the cycle time during playback. Furthermore, the time for reading packets from the HDD is much faster than the original bandwidth of MPEG TS. That is, a large number of packets can be read from the HDD to the SDRAM in a short time.

(3) DMA transfer from SDRAM to SRAM Packets accumulated in the SDRAM are DMA transferred to the SRAM. Also in this case, as shown in FIG. 14B, packets are transferred from the SDRAM to the SRAM at once. In addition, the cycle time in BUS1 at that time is irrelevant to the SPH timestamp value added to the packet (TS packet). As described above, during special reproduction, when a packet is transferred from the SDRAM to the SRAM, the SPH time stamp value is rewritten in accordance with the type of special reproduction (reproduction speed or the like). Since the cycle time and the time stamp value of the packet are irrelevant, there is no problem even if such rewriting is performed without considering the cycle time.

(4) Packet transfer from SRAM to BUS1 In BUS1 of IEEE1394, one or a plurality of packets (TS packets) are transferred for each isochronous cycle. In this case, the SPH time stamp value of each packet indicates the time at which the packet is desired to be input to the decoder (21 in FIG. 1) on the receiving side. That is, the transmission side adds a given offset value to the current cycle time (cycle time counted by the cycle timer 48) and transmits the packet to BUS1. Since the receiving side has a buffer capable of storing a certain amount of packets, the transmitting side can transmit in advance a packet to which a future time stamp value is added in this way. In the ISO / IEC61883 standard, for example, it is allowed to transmit a packet (offset value = 8) up to eight cycles ahead.

  Therefore, in the present embodiment, the time stamp value added to the packet written in the SRAM is compared with the set value, and for the packet whose time stamp value matches the set value, the time stamp value is set to the current cycle. The value is rewritten to a value obtained by adding the offset value to the time and transferred via the bus, and the set value is updated (incremented).

  Specifically, the SPH time stamp value of the packet stored in the SRAM is referred to, and when the SPH time stamp value matches a preset value, the packet is automatically transmitted via BUS1. In this case, not all the packets stored in the SRAM are transferred at once, but only packets whose time stamp value matches the set value are automatically transmitted together.

  For example, in M1 of FIG. 15, since the time stamp values of two packets in the SRAM match the set value = 2500, these two packets are automatically transmitted via BUS1. The set value is incremented by 1 to 2501. Then, as indicated by M2 in FIG. 15, in this automatic transmission, the packet time stamp value (2500) is rewritten to a value (6606) obtained by adding the offset value (= 5) to the current cycle time (6501). It is done. In addition, at the time of automatic transmission, as shown in FIG. 3B, addition processing of an ISO header and a CIP header is also performed. The set value may be updated on condition that a packet having a time stamp value that does not match the set value is detected. For example, when the maximum number of packets that can be transmitted within one cycle time is I, and the number J of packets in the SRAM whose time stamp value matches a set value (for example, 2500) is J> I , I packets are transmitted at the first cycle time, and the remaining JI packets are transmitted at the next second cycle time. The set value is updated (updated to 2501) on condition that a packet having a time stamp value (2501) that does not match the set value is detected.

  In M3 of FIG. 15, the time stamp values of the two packets in the SRAM coincide with the updated setting value = 2501, so these two packets are automatically transmitted via BUS1. The set value is incremented by 1 to 2502. Then, as indicated by M4 in FIG. 15, in this automatic transmission, the packet time stamp value (= 2501) is a value obtained by adding the offset value (= 5) to the current cycle time (= 6502) (6507). To be rewritten.

  At the time of automatic transmission, an isochronous packet obtained by connecting a plurality of TS packets is transmitted for each isochronous cycle. In this case, the number of connections is set to a given number. In the ISO / IEC61883 standard, it is allowed to transmit a packet having a time stamp value ahead of the current cycle time, for example, up to 8 cycles in advance. Therefore, TS packets can be concatenated and transmitted with the maximum concatenation number that satisfies this condition.

  As described above, in the present embodiment, the time stamp value rewriting process corresponding to the type of special reproduction is performed at the time of DMA transfer from the SDRAM to the SRAM, and the time stamp value rewriting process is adapted to the current cycle time. Is performed at the time of packet transfer from SRAM to BUS1. Accordingly, when the time stamp value is rewritten according to the type of special reproduction, the rewriting process can be performed without considering the current cycle time. Thereby, the time stamp value rewriting process corresponding to the type of special reproduction can be simplified. In addition, when the time stamp value is rewritten at the time of packet transfer via BUS1, the type of special reproduction need not be considered at all. Therefore, it is possible to simplify the process of rewriting the time stamp value suitable for the current time cycle, and to simplify the configuration and operation of the transfer controller 40.

  The present invention is not limited to that described in the above embodiment, and various modifications can be made. For example, terms in the specification or drawings have broad or synonymous terms (first memory, second memory, DMAC1, DMAC2, recording medium, intra-frame encoded data, inter-frame encoded data, first, second , Third layer packet, third layer header, etc.) (SDRAM, SRAM, first memory access controller, second memory access controller, HDD, I picture, B and P picture, (TS packet, PES packet, IEEE 1394 format packet, ISO header, etc.) can be replaced with broad or synonymous terms in the description or other description in the drawings.

  The configuration of the data transfer control device of the present invention is not limited to the configuration shown in FIG. 4, and various modifications can be made. For example, some of the components in FIG. 4 may be omitted or the connection relationship may be changed. Also, the packet writing / reading method, the time stamp value rewriting method, and the picture information detection method of the present embodiment are not limited to the methods described in the present embodiment. It is also possible to use these methods for purposes other than special reproduction of stream packets.

  In the present embodiment, the case where data of MPEG standards (MPEG2, MPEG4) is transferred via an IEEE 1394 standard bus (interface) has been described, but the present invention is not limited to this. For example, the present invention is also applicable to a case where data based on a standard based on the same idea as MPEG (MPEG2, MPEG4) or a standard developed from MPEG is transferred by a bus based on a standard based on the same concept as IEEE 1394 or a standard developed based on IEEE 1394. Is applicable. The present invention can also be applied to high-speed serial transfer (USB or the like) other than IEEE1394.

1A and 1B are configuration examples of electronic devices. Explanatory drawing of MPEG stream structure. 3A, 3B, 3C, and 3D are explanatory diagrams of isochronous transfer and packet format. 1 is a configuration example of a data transfer control device according to the present embodiment. Explanatory drawing of a time stamp value. Explanatory drawing of a picture information area. FIGS. 7A and 7B are explanatory diagrams of picture information detection processing. The register structural example of a register part. Explanatory drawing of DMA transfer from SDRAM to SRAM. Explanatory drawing of the extraction / reading method of I picture. Explanatory drawing of a picture information area | region and a save area. Explanatory drawing of the rewriting process of a time stamp value. 2 is a configuration example of a time stamp update circuit. 14A and 14B are explanatory diagrams of time stamp values added to a packet. Explanatory drawing of the rewriting process of the time stamp value at the time of packet transfer via BUS1.

Explanation of symbols

HDD Hard disk drive (recording medium),
SDRAM first memory, SRAM second memory,
DMAC1 to DAMC3 first to third memory access controllers,
12 operation units, 14 display units, 20 digital tuners,
21 MPEG decoder, 22 operation unit, 24 television, 26 antenna,
30 data transfer control device, 32 IDE interface,
34 SDRAM interface, 40 transfer controller, 42 header creation circuit,
44 Transfer start time stamp value setting register, 46 Pointer controller,
48 cycle timer, 49 physical layer circuit, 50 detection circuit,
60 processing unit (CPU), 62 register unit

Claims (12)

A data transfer control device for controlling data transfer via a bus,
A first memory access controller that writes stream packets to the first memory;
A second memory access controller that extracts and reads out a packet including a specific type of picture from the stream packets written in the first memory, and writes the read packet into the second memory;
A transfer controller that performs control of adding a header to the packet written in the second memory and transferring the packet via the bus;
A data transfer control device comprising: In claim 1,
A detection circuit for detecting identification information of a picture included in the packet written in the first memory, and writing the identification information and a storage address of the packet in the first memory in a picture information area;
The second memory access controller comprises:
In accordance with an instruction from the processing unit that has read the identification information and the storage address from the picture information area, a packet including a specific type of picture is extracted and read from the stream packet written to the first memory. A data transfer control device. In claim 1,
The identification information of the picture included in the packet written in the first memory in the current DMA transfer cycle is detected, and the identification information and the storage address of the packet in the first memory are transferred to the previous DMA transfer. Including a detection circuit for overwriting the information written in the cycle and writing to the picture information area,
The identification information of the picture included in the packet last written in the first memory in the previous DMA transfer cycle and the storage address of the packet in the first memory are saved in the save area in the current DMA transfer cycle. A data transfer control device characterized in that the data transfer control device is saved. In any one of Claims 1 thru | or 3,
The first memory access controller is
Read a stream packet from the recording medium and write it to the first memory,
The second memory access controller comprises:
A data transfer control device, wherein a packet including a specific type of picture required for the special reproduction is extracted and read out from the stream packet of the first memory during the special reproduction of the stream packet. In claim 4,
A data transfer control device comprising a time stamp update circuit for rewriting a time stamp value added to each packet read from the first memory to a new value corresponding to the type of special reproduction. . In claim 5,
The time stamp update circuit includes:
In one picture, the time stamp value rewriting process is performed so that the difference value between the time stamp values added to adjacent packets and the difference value between the time stamp values after rewriting become the same value. A data transfer control device. In claim 5 or 6,
The time stamp update circuit includes:
A data transfer control device that performs a time stamp value rewriting process so that a difference value between pictures of a time stamp value after rewriting changes in accordance with the speed of the special reproduction. In any of claims 5 to 7,
The time stamp update circuit includes:
A transmission FIFO that temporarily stores packets read from the first memory and outputs them to the second memory;
A time stamp value storage register for storing a time stamp value added to a packet read from the first memory last time;
A difference value calculation circuit for calculating a difference value between the current time stamp value added to the packet read from the first memory and the previous time stamp value stored in the time stamp value storage register When,
An offset value register in which an initial value of a time stamp in the current DMA transfer is set as an offset value each time a DMA transfer of a packet from the first memory to the second memory is performed;
The difference value from the difference value calculation circuit is added to the offset value from the offset value register, and the value obtained by the addition is output as an update time stamp value to the transmission FIFO and written back to the offset value register. A data transfer control device comprising an adder circuit. In any one of Claims 1 thru | or 8.
Including a cycle timer that counts the cycle time to determine the transfer cycle;
The transfer controller is
The time stamp value added to the packet written in the second memory is compared with a given set value. For a packet whose time stamp value matches the set value, the time stamp value is set to the current value. A data transfer control device that rewrites a value obtained by adding an offset value to a cycle time, transfers the cycle time, and updates the set value. In any one of Claims 1 thru | or 9,
The data transfer control device, wherein the first memory is a memory having a larger capacity than the second memory and capable of sequential access at a higher speed than the second memory. In any one of Claims 1 thru | or 10.
A data transfer control device that performs data transfer conforming to the IEEE 1394 standard. A data transfer control device according to any one of claims 1 to 11,
An electronic apparatus comprising: a recording medium for recording stream data.

Images