JP2002368229A - Semiconductor device and manufacturing method therefor and radiation detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, having a thin-film transistor which has superior transfer efficiency without increasing an off current, and to provide a method for manufacturing the same and a radiation detector using the same. SOLUTION: The semiconductor device, having a bottom gate type thin film transistor, comprises a semiconductor layer 4 disposed at a lower part of a source/drain electrode 6 and having a thickness t2 smaller than a thickness t1 of the layer 4, at a gap between the source and drain electrodes 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a thin film transistor used as a switching element, a method of manufacturing the same, and a radiation detector.
In particular, the present invention relates to a semiconductor device for photoelectric conversion having a pixel including a photoelectric conversion element and a thin film transistor, a method for manufacturing the same, and a radiation detection device.

[0002]

2. Description of the Related Art In recent years, modules using thin film transistors have been used in various fields. For example,
It is used for a liquid crystal display element or an organic EL display using a thin film transistor as a switching element on an insulating surface of a substrate, or a large screen flat panel sensor using a thin film transistor as a switching element on an insulating surface of a substrate. A large screen flat panel sensor is used as a device for detecting radiation such as X-rays by forming a layer called a scintillator or a phosphor on the sensor.

In the module of a semiconductor device using these thin film transistors, while the size of the substrate is increasing at present,
Conversely, there is a growing trend to be smaller and have higher definition for use as a display device in portable terminals and mobile phones. Under such circumstances, in order to improve the performance of the thin film transistor, it is desired to improve the transfer efficiency of the thin film transistor and to improve the aperture ratio of the pixel by reducing the size of the thin film transistor. This is the same for the flat panel sensor. In the flat panel sensor, it is necessary to maintain the sensitivity of the sensor while achieving high-speed driving.

At present, a bottom gate type thin film transistor in which a gate electrode is formed on an insulating substrate and a semiconductor layer is formed thereon is often used as the thin film transistor. The bottom gate thin film transistor is roughly classified into the following two types.

One type is a thin film transistor of a type called a gap-etch type, a channel-etch type or the like shown in FIG. 9, and after a gate electrode 2 is formed on an insulating substrate 1,
CVD of the insulating film 3, the semiconductor layer 4, and the semiconductor doping layer 5
And the semiconductor doping layer 5 in the gap portion of the thin film transistor is etched. In this gap-etch type thin film transistor, in order to make the semiconductor layer 4 thin, it is necessary to improve the etching distribution during gap etching and to make the layer thickness uniform when forming the semiconductor layer.

The other is a thin film transistor of a type called an etch stopper type or a channel passivation type as shown in FIG. This is because after forming the gate electrode 2 on the insulating substrate 1, the insulating film 3, the semiconductor layer 4, the channel protecting film 8 such as the insulating film are continuously formed by CVD, and then the channel protecting film 8 corresponding to the gap of the thin film transistor is formed. Etching leaving only
The semiconductor doping layer 5 is formed.

Thereafter, the semiconductor doping layer 5 in the gap portion of the thin film transistor is etched to form a thin film transistor. In this etching stopper type thin film transistor, the semiconductor layer can be formed without depending on the etching distribution at the time of the gap etching. However, it is important to control the etching of the insulating film 8. The speed of the thin film transistor has been increased by improving the distribution.

In the case of an etch stopper thin film transistor using an insulating film such as a silicon nitride film, it is possible to reduce the thickness of the semiconductor layer to produce a high performance thin film transistor. It has been pointed out that the time will be longer.

On the other hand, the manufacturing process of the gap-etch thin film transistor is relatively simple,
It has been pointed out that it is difficult to reduce the thickness of the semiconductor layer because the dopant is unintentionally injected from the surface of the semiconductor layer to a predetermined depth due to the formation of the semiconductor doping layer. In addition, the operation becomes slow when the thickness of the semiconductor layer is large.

[0010] In any type of thin film transistor, it is considered that it is difficult to sufficiently improve the film quality of a semiconductor thin film as a semiconductor layer serving as a channel in terms of manufacturing.

[0011]

In any case, a thin film transistor which can operate at high speed by using a high quality thin film as a semiconductor layer serving as a channel is desired.

An object of the present invention is to provide a semiconductor device having a thin film transistor capable of high-speed operation, a method of manufacturing the same, and a radiation detecting device using the same.

Another object of the present invention is to provide a semiconductor device having a thin-film transistor having excellent transfer efficiency without an increase in off-current, a method of manufacturing the same, and a radiation detecting device using the same.

Still another object of the present invention is to provide a semiconductor device having an inexpensive thin film transistor, which can prevent a decrease in sensitivity of the photoelectric conversion element when integrated with the photoelectric conversion element, a method of manufacturing the same, and a method of manufacturing the same. It is to provide a radiation detection device used.

[0015]

The gist of the present invention is to provide a gate electrode provided on an insulating surface of a substrate, a semiconductor layer provided on the gate electrode via a gate insulating layer, A bottom gate type thin film transistor having a pair of semiconductor doping layers adjacent to the semiconductor doping layer and a source / drain electrode made of a pair of conductors adjacent to the semiconductor doping layer;
A thickness of the semiconductor layer below the drain electrode is smaller than a thickness of the semiconductor layer in a gap between the source and drain electrodes.

In the present invention, the thickness of the semiconductor layer below the source / drain electrodes is 30 nm to 30 nm.
0 nm, and the thickness of the semiconductor layer in the gap portion is 60 nm to 1500 nm.
It is good that it is selected from the range of.

The thickness of the semiconductor layer below the source / drain electrodes may be 0 nm.

It is preferable that the surface of the gap is covered with a protective film for covering the source / drain electrodes for the purpose of passivation. Further, it is preferable that a surface of the gap portion is covered with a channel protection film, and an end of the channel protection film is covered with the source / drain electrodes.

Preferably, the semiconductor doping layer is formed on the semiconductor layer thinned by etching.

In the present invention, a photoelectric conversion element may be further provided on the insulating surface of the substrate.

The photoelectric conversion element may include a semiconductor layer having the same material and the same thickness as the semiconductor layer in the gap portion of the thin film transistor. Further, the photoelectric conversion element is a semiconductor layer of the same material and the same thickness as the semiconductor layer in the gap portion of the thin film transistor, a semiconductor doping layer of the same material and the same thickness as the semiconductor doping layer, And an insulating layer having the same material and the same thickness as the gate insulating layer.

Another gist of the present invention is a gate electrode provided on an insulating surface of a substrate, a semiconductor layer provided on the gate electrode with a gate insulating layer interposed therebetween, and a pair of semiconductor layers adjacent to the semiconductor layer. A method of manufacturing a semiconductor device including a bottom-gate type thin film transistor having a semiconductor doping layer and a source / drain electrode formed of a pair of conductors adjacent to the semiconductor doping layer, wherein the step of forming the semiconductor layer; With the surface of the semiconductor layer serving as a gap between source / drain electrodes covered with an etching mask, part or all of the semiconductor layer serving as a part where the source / drain electrodes are to be formed is removed by etching. Removing, forming the semiconductor doping layer in the portion removed by etching, the semiconductor doping layer Forming the source / drain electrodes on the substrate.

In the above manufacturing method, after the removing step, the etching mask is removed, and then, before the semiconductor doping layer is formed, (a) ammonia or hydrogen chloride is added to the portion removed by etching. At least one selected from the group consisting of surface treatment with a solution containing hydrogen peroxide, (b) surface treatment with a chelating agent, and (c) surface treatment using oxygen plasma may be performed.

Further, after the removing step, the etching mask is removed, and thereafter, before the semiconductor doping layer is formed, a surface treatment for removing an organic substance from the portion removed by the etching is performed; It is also preferable to perform surface treatment with a solution containing hydrogen fluoride.

After the removing step, the etching mask is removed, and thereafter, before forming the semiconductor doping layer, a surface treatment using hydrogen plasma is performed in an apparatus for forming the semiconductor doping layer. Good. These serve to improve the ohmic contact between the source and drain electrodes.

In the above manufacturing method, it is preferable that the discharge power of the plasma during the surface treatment using the hydrogen plasma is equal to or lower than that when forming the semiconductor layer. Further, it is preferable that the discharge power of the plasma during the surface treatment using the hydrogen plasma is equal to or smaller than that when the semiconductor doping layer is formed. These are effective for preventing deterioration of the semiconductor layer.

In the above manufacturing method, the surface of the semiconductor layer where the source / drain electrodes are to be formed is etched while the surface of the semiconductor layer where the photoelectric conversion element and the thin film transistor are to be covered with the protective film, Further, the protective film covering the surface of the semiconductor layer of the photoelectric conversion element may be etched, and the surface of the semiconductor layer where the source / drain electrodes are to be formed may be further etched.

A radiation detection apparatus according to the present invention includes the above-described semiconductor device and a control device for processing an image signal from the semiconductor device and transmitting the processed image signal to the outside.

The radiation detecting apparatus may further include a display device for displaying an image.

(Operation) In order to achieve the above-mentioned object,
It has been found that the following two points are required as a high performance thin film transistor. (1) The semiconductor layer below the source / drain is thinned. (2) The thickness of the semiconductor layer in the gap between the source and the drain is increased.

For example, in the case of a gap-etch type thin film transistor, even if a surface portion of a base semiconductor layer into which a dopant is implanted is etched at the time of etching a semiconductor doping layer in a gap portion, the semiconductor layer still has a thickness of 20 nm to 100 n.
m, sometimes a damage layer of about 20 nm to 150 nm is formed in the semiconductor layer, which may cause an increase in off-current and an increase in on-resistance due to the shift of the threshold voltage Vth of the thin film transistor. Therefore, as the thickness of the semiconductor layer is reduced, the off-current increases, and it becomes difficult to manufacture a thin film transistor having excellent transfer efficiency.

In the case of the etch stopper type, the semiconductor layer can be made relatively thin. However, for example, as the semiconductor layer becomes thinner, the characteristics of the semiconductor layer serving as a channel hardly become sufficient.

In the case of a gap-etch type thin film transistor, when the thickness of the semiconductor layer in the gap between the source and the drain is increased, there is a concern that the off-state current of the thin film transistor may increase due to a decrease in the bulk resistance of the semiconductor layer. You. However, since it was confirmed that the off-state current of the thin film transistor was determined by the leak at the interface of the etched portion during the gap etching, even if the thickness of the semiconductor layer in the gap between the source and drain was increased,
The off-state current does not increase unintentionally.

In the case of the etch stopper type, such a leak current is further suppressed.

Further, when the thin film transistor itself is used as a photoelectric conversion element or when integrated with the photoelectric conversion element, a semiconductor film having a thickness sufficient to receive light is once formed in the manufacturing process. It is desired.

For the above reasons, in the present invention,
The configuration of the above (2) is adopted.

On the other hand, in the vicinity of the source / drain electrodes,
By relatively thinning the semiconductor layer, the source
The resistance of the semiconductor layer near the drain can be reduced, and the on-resistance can be reduced.

Thus, in the present invention, the configuration of the above (1) is adopted.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the structure of an embodiment of a thin film transistor according to the present invention. In FIG. 1, reference numeral 1 denotes an insulating substrate on which a gate electrode 2, an insulating film 3, a semiconductor layer 4, a semiconductor doping layer 5, a source / drain electrode 6, and a protective film 7 are formed. The surface of the gap portion of the semiconductor layer is covered with a protective film 7 covering the source / drain electrodes 6 and is passivated.

In this embodiment, the effect of the damage layer upon etching the gap is reduced by increasing the thickness of the semiconductor layer only in the gap between the source and the drain.
In addition, the influence of the diffusion layer of the dopant from the ohmic contact layer is removed to prevent a Vth shift or an increase in off-state current. In addition, by thinning the semiconductor layer below the source / drain electrodes to be joined, the source / drain resistance is reduced, and a high-performance thin film transistor with low on-resistance is realized.

As the insulating substrate 1 used in the present invention,
A substrate that provides an insulating surface on which a thin film transistor is formed is used. Specifically, an insulating film such as glass, quartz, or alumina, or an insulating film such as silicon oxide formed on a semiconductor or conductor surface is used. Including.

The gate electrode 2 used in the present invention is composed of A
l, Cr, W, Mo, Ti, Ta, Cu, Ni, etc., or AlCr, AlTi, AlPd, AlC
u, AlNd or the like, or a conductive material such as tin oxide, indium oxide, indium tin oxide, or polycrystalline silicon doped with impurities. Further, a laminate of a plurality of types of conductive materials may be used.

The insulating film 3 used in the present invention may be any as long as it functions as a gate insulating film.
Silicon nitride, silicon oxynitride, aluminum oxide,
It can be composed of an insulating oxide such as tantalum oxide or an insulating nitride. Further, a stack of a plurality of types of insulating films may be used.

As the semiconductor layer 4 used in the present invention,
Non-single-crystal semiconductor materials such as amorphous silicon, microcrystalline silicon, amorphous silicon including microcrystal, and polycrystalline silicon may be used as long as they can provide a channel through which carriers flow by an electric field effect caused by application of a gate voltage. Is preferably used. In particular, amorphous silicon, microcrystalline silicon, and amorphous silicon including microcrystal are desirable.

Semiconductor doping layer 5 used in the present invention
As a semiconductor layer to which a dopant that determines the conductivity type of a thin film semiconductor is preferably used, amorphous silicon or microcrystalline silicon to which a group III element such as boron or a group V element such as phosphorus is added, Non-single-crystal semiconductor materials such as amorphous silicon containing microcrystals and polycrystalline silicon are preferably used. In particular, amorphous silicon doped with phosphorus, microcrystalline silicon, and amorphous silicon containing microcrystals are desirable.

The source / drain electrode 6 used in the present invention can be made of a material appropriately selected from the same materials as the above-mentioned gate electrode.

The protective film 7 used as required can be made of a material appropriately selected from the above-mentioned materials of the insulating film 3. Further, an organic insulator such as a polyimide resin or an epoxy resin can be used. It can also be used.

As described above, the gate electrode 2 on the insulating substrate 1
In the bottom gate type thin film transistor in which the insulating film 3, the semiconductor layer 4, the semiconductor doping layer 5, and the source / drain electrode 6 are laminated, the layer thickness t2 of the semiconductor layer 4 below the source / drain electrode 6 is between the source and the drain. The thickness is smaller than the thickness t1 of the semiconductor layer 4 in the gap.

As described above, according to the embodiment of the present invention, in the bottom gate type thin film transistor, by increasing the thickness of the semiconductor layer in the gap portion between the source and the drain, the dopant is formed after the formation of the semiconductor doping layer. Is injected into the semiconductor layer, a depletion layer of the thin film transistor when the thin film transistor is off can be secured, and as a result, an increase in off current of the thin film transistor can be prevented.
In addition, a thin film transistor having excellent transfer efficiency can be realized by making the lower semiconductor layer between the source and the drain thin.

Hereinafter, a method for manufacturing the thin film transistor will be described. An insulating substrate 1 having an insulating surface, such as a silicon substrate coated with glass or a silicon oxide film, is prepared.

On the insulating surface of the insulating substrate 1, Al, Cr, W, Mo, Ti, Ta, AlT
i, a film formed of at least one layer of a conductive material such as AlNd is formed by sputtering so that the gate electrode 2 has a thickness of 70 nm to 500 nm, more preferably 70 nm to 500 nm.
The film is formed to have a thickness of 0 nm. Photolithography is used for patterning the gate electrode 2. Specifically, a photoresist is applied, a pattern of a gate electrode is exposed and developed, and thereafter, a film of a conductive material is wet-etched using the photoresist as a mask.

A silicon oxide film or a silicon nitride film is formed as the insulating film 3 by a CVD method, and a non-single-crystal semiconductor layer (i-layer) such as non-doped hydrogenated amorphous silicon is formed as the semiconductor layer 4 thereon. Form. At this time, the insulating film 3 and the semiconductor layer 4 are continuously formed without breaking the vacuum. At this time, the thickness of the insulating film 3 is 150 nm to 400 n.
m, more preferably 200 nm to 350 nm, and the layer thickness of the semiconductor layer 4 is 100 nm to 150 nm.

Here, in order to make the lower portion of the source / drain of the i-layer thinner than the gap portion, only the lower portion of the source / drain is etched. Specifically, a resist is formed in the gap between the source and the drain, and the resist is patterned by an exposure apparatus so as to remove the resist below the source and the drain. After patterning the resist,
The portion of the i-layer where the resist is not formed is etched by a dry etching device.

As an etching method at this time, a plasma etching apparatus of an anode coupling, a reactive ion etching performed using an apparatus for applying an RF bias voltage to the substrate side, or a gas at a distance from the reaction chamber is used. Chemical dry etching using an apparatus or the like for generating an active tumor can be used. After this etching, the thickness of the semiconductor layer 4 under the source / drain electrodes is controlled to be 30 nm to 70 nm, and the semiconductor layer 4 in the gap between the source and drain is controlled.
Is 100 nm to 150 which is the layer thickness at the time of the first film formation.
nm.

After the resist is removed after the etching, the insulating substrate is treated with a mixed solution of ammonia and hydrogen peroxide or a mixed solution of hydrochloric acid and hydrogen peroxide to remove the organic film attached to the surface. I do. The surface treatment may be performed with a solution containing a chelating agent. Furthermore, it has been confirmed that equivalent effects can be obtained by using a plasma treatment performed in an atmosphere containing at least oxygen instead of the chemical solution treatment. After this treatment, a chemical treatment composed of about 1% by volume of hydrofluoric acid and about 99% by volume of water is performed to remove the surface oxide film of the i-layer oxidized by hydrogen peroxide. At this time, acetic acid may be added to hydrofluoric acid. Further, an aqueous solution of hydrogen fluoride and ammonium fluoride may be used.

The semiconductor doping layer 5 is formed by the CVD method similarly to the insulating film 3 and the semiconductor layer 4. Specifically, a doping layer of a non-single-crystal semiconductor such as amorphous silicon or microcrystalline silicon doped with phosphorus is formed by a plasma CVD method using a gas containing phosphine diluted with hydrogen in silane gas. In addition, before the film formation, the hydrogen plasma treatment is performed in the film formation chamber at the same pressure and the same or lower film formation power as during the film formation of the doped semiconductor layer 5.
By doing so, the surface of the semiconductor layer 4 is hydrogenated, and the contact at the interface between the semiconductor doping layer 5 and the semiconductor layer 4 is further improved.

The thickness of the semiconductor doping layer 5 is 20 nm to
70 nm. After the formation of the semiconductor doping layer, a source / drain electrode 6 made of a conductive material having a lower resistance than the semiconductor doping layer 5 and a film of a conductive material to be a wiring are formed. As the conductive material, Al, Cr, W, Mo, T
A metal such as i, Ta, AlTi, AlNd, SnO, ITO, or a conductive metal oxide is used.
A with a layer thickness of about 1000 nm
1 film is preferably used.

Similarly to the gate electrode, patterning of the source / drain electrodes 6 and wiring is performed by photolithography, and etching is performed by wet etching.
Then, after forming the source / drain electrodes 6 and the wiring, the doping semiconductor layer 5 is etched using the same resist. For the etching, anode-coupled plasma etching or chemical dry etching is suitable because the plasma damage of the etched portion is small, but reactive etching may be used. At the stage where the thin film transistor has been formed, the protective film 7 is formed by a CVD method. As the protective film 7, a silicon nitride film is used. The thickness of the layer depends on the level difference of the pattern in which the thin film transistor is formed, but is in the range of about 500 nm to 2000 nm.

As described above, in this embodiment, the thickness of the semiconductor layer 4 below the source / drain electrode 6 is set to 30 nm to 70 nm.
When the thin film transistor is formed as thin as nm, the series resistance due to the layer thickness component of the semiconductor layer of the thin film transistor can be reduced, the on-resistance can be significantly reduced, and the transfer efficiency can be improved. At the same time, regarding the gap between the source and the drain, by increasing the thickness of the semiconductor layer 4 to 100 nm to 150 nm, even if a dopant is injected into the semiconductor layer after the formation of the doping semiconductor layer 5, the thickness is increased. Therefore, a depletion layer can be secured, and off current can be prevented by the secured depletion layer.

As a result, a thin film transistor having excellent transfer efficiency and excellent characteristics can be realized. Further, an increase in off-state current due to surface damage formed during gap etching can be prevented. Further, compared with a thin film transistor of an etching stopper type using a silicon nitride film or a silicon oxide film, there is no need to separately form a film serving as an etching stopper, so that an improvement in tact time can be expected.

(Embodiment 2) A semiconductor device according to another embodiment of the present invention will be described.

FIG. 2 is a cross-sectional view showing the configuration of an embodiment of a flat panel sensor (photoelectric conversion device) using a thin film transistor having the same configuration as that shown in FIG. In FIG. 2, a sensor unit (photoelectric conversion element) 11 and a thin film transistor unit 12 are arranged side by side on the insulating substrate 1, and at least one pair constitutes one pixel.

Although the sensor section 11 can be constituted by a PIN type sensor, in FIG. 2, the simplification of the process is achieved by constituting the sensor section 11 by an MIS type sensor which can be formed of the same film as the thin film transistor section 12.

The thin film transistor section 12 is formed by forming a gate electrode 2, an insulating film 3, a semiconductor layer 4, a semiconductor doping layer 5, a source / drain electrode 6, and a protective film 7 on an insulating substrate 1. The structure can be the same as that of the thin film transistor shown in FIG. The portions denoted by the same reference numerals are formed of the same material and in the same process. Semiconductor layer 4
Is formed using a semiconductor film formed by the same film forming process for both the sensor section 11 and the thin film transistor section 12, and only the lower portion of the source / drain electrode 6 of the thin film transistor section is thinned by etching or the like. I have.

Further, the lower sensor electrode 9 can be formed of the same material and in the same step as the gate electrode 2, and the upper electrode wiring 10 can be formed of the same material and in the same step as the source / drain electrodes 6.

The thickness of the semiconductor layer 4 in the gap portion of the thin film transistor is equal to or different from the thickness of the semiconductor layer 4 in the sensor portion by about the amount of over-etching when the semiconductor doping layer is removed by etching.

Reference numeral 18 denotes a layer provided as necessary. Here, a layer called a phosphor or a scintillator, which receives radiation such as X-rays and generates light having a different wavelength such as visible light, is used. Become. When such a layer 18 is used, a flat panel sensor can be used as a radiation detection device.

FIG. 3 is a diagram showing a circuit configuration including the flat panel sensor (photoelectric conversion device) of FIG. 2 and its driving circuit. The sensor section 11 and the thin film transistor section 12 in the figure correspond to FIG. In FIG. 3, first, the sensor unit 1
1 and the thin film transistor section 12 are two-dimensionally arranged as a pair. The generated light is captured by the MIS type sensor unit 11, and electrons or holes are accumulated. After that, the thin film transistor section 12 is controlled by the gate line 13 by driving the thin film transistor section 12 by the gate driver circuit section 17, and the accumulated electrons or holes are transferred to the signal line 1.
4 to the signal processing circuit unit 15. afterwards,
A configuration is adopted in which electrons or holes accumulated in the MIS type sensor section 11 are removed via the common electrode wiring 10 by driving the common electrode driver circuit section 16.

Reference numeral 21 denotes a signal processing circuit section 15, a common electrode driver circuit section 16, and a gate driver circuit section 17.
Is a control device (CONTROLLER) for controlling the driving of the image processing device, processing the obtained image signal, and transmitting the processed image signal to the outside. Reference numeral 22 denotes a computer (PC) for receiving data such as an image signal transmitted from the control device 21 and reproducing and displaying the image signal on a display device (DP) 23.

In this embodiment, the thin film transistor section 12
By reducing the thickness of only the semiconductor layer below the source / drain, a high-performance thin film transistor having excellent transfer efficiency and small off-current can be manufactured. As a result, the thin film transistor section 12 is made small, the aperture ratio of the sensor section 11 is improved, and a highly sensitive flat panel sensor can be realized. In addition, by forming the semiconductor layer of the sensor unit 11 that performs light accumulation to have the same thickness as the gap between the source and the drain of the thin film transistor or to have a thickness larger than that, the light absorption rate can be improved, and high sensitivity radiation can be achieved. A sensor can be realized.

Next, the manufacturing process of the flat panel sensor will be described with reference to FIGS. 4A to 4E.

An insulating substrate 1 having an insulating surface, such as a glass or a silicon substrate coated with a silicon oxide film, is prepared.

On the insulating surface of the insulating substrate 1, Al, Cr, W, Mo, Ti, Ta, AlT
i, a film formed of at least one layer of a conductive material such as AlNd is formed by sputtering to a thickness of the gate electrode 2 of 70 nm to 500 nm, more preferably 70 nm to 20 nm.
It is formed to have a thickness of 0 nm.

Further, wet etching is used for the etching. At this time, the sensor electrode 9 of the sensor unit 11 paired with the thin film transistor unit 12 is simultaneously formed and patterned.

The insulating film 3 is formed by depositing a silicon oxide film or a silicon nitride film by a CVD method, and a semiconductor layer 4 formed thereon is an i-layer made of non-doped hydrogenated amorphous silicon. Subsequent to the formation of the film 3, the film is continuously formed without breaking the vacuum. The layer thickness of the insulating film 3 is 150 nm to 400 nm, more preferably 200 nm to 400 nm.
350 nm, the layer thickness of the semiconductor layer 4 is 300 nm to 1500
nm, more preferably from 600 nm to 1500 nm. Note that, in this case, the insulating film 3 and the semiconductor layer 4 of the MIS type sensor unit 11 that is paired with the thin film transistor unit 12 are simultaneously formed (see FIG. 4A).

The reason why the extremely thick layer is formed in this way is to improve the light absorption of the semiconductor layer 4 of the sensor unit 11 paired with the thin film transistor unit 12. In order to make the i-layer under the source / drain thinner than the gap, only the portions S and D serving as the source / drain are etched. At this time, a resist (not shown) is formed so as to cover the gap C, and the source / drain S and D are patterned by an exposure apparatus so as to remove the resist.

Next, after patterning the resist, the surface of the i-layer not covered with the resist is etched by a dry etching apparatus. The etching may be dry etching using an anode coupling plasma etching apparatus, reactive ion etching or chemical dry etching. After this etching,
The thickness t2 of the semiconductor layer 4 below the drain electrode 6 is:
The thickness is controlled to be 50 nm to 300 nm including the process margin.
Is a layer thickness at the time of the first film formation of 300 nm to 1
500 nm, more preferably 600 nm to 1500 nm
It is. Further, the semiconductor layer of the sensor unit 11 has a gap C
Similarly to the above, since it is covered with a resist and is not etched, its layer thickness is 300 nm or more which is the layer thickness t1 at the time of the first film formation.
1500 nm, more preferably 600 nm to 1500 n
m (see FIG. 4B).

Next, the resist (not shown) is peeled off, and thereafter, the insulating substrate is treated with a solution containing a chelating agent to remove metal particles on the surface. Further, the organic film on the surface is also simultaneously peeled off by removing metal particles contained in the organic film by using a chelating agent. In addition, a mixed solution of ammonia and hydrogen peroxide, a mixed solution of hydrochloric acid and hydrogen peroxide, or the like may be used as in the above-described embodiment of the thin film transistor, without being limited to the solution containing the chelating agent. After this treatment, a surface treatment is performed with an aqueous solution containing about 1% by volume of hydrofluoric acid and about 40% by volume of ammonium fluoride to remove a natural oxide film on the surface.

At this time, acetic acid may be added to an aqueous solution comprising hydrofluoric acid and ammonium fluoride. Further, a solution of hydrofluoric acid and water may be used as in the case of the above-described embodiment, or acetic acid may be added. Further, plasma treatment may be performed in an atmosphere containing at least oxygen instead of the chemical solution treatment.

The semiconductor doping layer 5 is formed by the insulating film 3,
This is performed by the CVD method similarly to the semiconductor layer 4. The film is doped with phosphorus by adding phosphine diluted with hydrogen to silane gas. Before the film formation, the semiconductor layer 4
The hydrogen plasma treatment is performed at the same film forming pressure as that at the time of film forming and at the same or smaller power. More preferably, the film formation is performed for about 5 to 15 minutes at a film forming pressure at the time of forming the semiconductor doping layer 5 and a power (or the same power) smaller than the film forming power,
It is preferred to hydrogenate the surface. After that, a plasma treatment including phosphine is performed for 30 seconds, so that the ohmic contact at the interface is improved. The thickness of the semiconductor doping layer 5 is 20 nm to 100 nm, and more preferably 35 nm to 100 nm.

Since the semiconductor doping layer 5 is used not only as the ohmic contact layer of the source / drain electrodes of the thin film transistor but also as the transparent electrode of the MIS type sensor section 11, the layer thickness is increased and the resistance is increased. It is desirable to lower After the formation of the semiconductor doping layer 5, the source / drain electrodes 6 and the Al serving as the wiring are formed by a sputtering method. The layer thickness of Al is, for example, 1
It is about 000 nm (see FIG. 4C).

The patterning of the source / drain electrodes 6 and the wiring is performed by photolithography, and the etching is performed by wet etching (see FIG. 4D).

After forming the source / drain electrodes 6 and the wiring, the semiconductor doping layer 5 in the gap between the source / drain electrodes 6 is removed by etching using the same resist.

For this etching, anode-coupled plasma etching or dry etching is suitable because it causes less plasma damage to the etched portion, but reactive etching may also be used. Next, the common electrode wiring 10 of the sensor section 11 is patterned by photolithography (see FIG. 4E).

In this way, the thin film transistor and the photoelectric conversion element can be manufactured in substantially the same process as that of adding one photolithography mask.

At the stage where the thin film transistor has been formed, if necessary, a protective film 7 as shown in FIG. 2 is formed by a CVD method. As the protective film 7, a silicon nitride film is preferably used. The layer thickness depends on the level difference of the pattern in which the thin film transistors are formed, but is preferably in the range of about 500 nm to 2000 nm.

When manufacturing a radiation detecting device, as shown in FIG. 2, a phosphor layer 18 is formed on the protective film 7 and the radiation (X-ray, α-ray, β-ray, γ-ray, etc.) ), The phosphor layer 18 converts the light, and the MIS type sensor unit 11 disposed below detects the light conversion. The phosphor layer 18 has GOS (Gado)
linium Oxysulphide Phosph
or Screen) or cesium iodide.

In this embodiment, the thickness of the semiconductor layer 4 below the source / drain electrodes 6 of the thin film transistor is set to 50 n.
By forming the thin film as m to 300 nm, the series resistance due to the layer thickness component of the semiconductor layer of the thin film transistor is reduced,
The on-resistance is greatly reduced, and the transfer efficiency is improved. At the same time, the thickness of the semiconductor layer 4 is set to 300
nm to 1500 nm, more preferably 600 nm to 15 nm.
By increasing the thickness to 00 nm, an increase in off-state current can be prevented. As a result, a thin film transistor with excellent characteristics and excellent transfer efficiency can be realized.

Further, an increase in off-state current due to surface damage formed during gap etching can be prevented. Furthermore, the sensor part does not perform thinning to etch the whole,
Since the semiconductor layer 4 has the same layer thickness as the gap between the source and the drain or is slightly thicker than that, the light absorption in the sensor section is secured, and a highly sensitive MIS semiconductor sensor can be realized. Further, since all the thin films constituting the MIS sensor unit 11 are formed simultaneously with the film forming the thin film transistor, the manufacturing process can be greatly simplified.

In the above embodiments, the case where the thin film transistor is mainly used for the photoelectric conversion device has been described as an example. However, the thin film transistor of the present invention may be replaced with a thin film transistor such as a liquid crystal display device or an organic EL display. Can be suitably used for all semiconductor devices that use.

By using the thin film transistor of the present invention in a liquid crystal display device, the response speed can be improved, and by making the thin film transistor small, the aperture ratio of the cell can be increased and the display image can be brightened. Furthermore, by using the thin film transistor of the present invention for a photoelectric conversion device, the driving speed can be improved, and the sensor sensitivity can be improved by increasing the aperture ratio.

(Embodiment 3) FIG. 5 is a cross-sectional view showing the configuration of an embodiment of the thin film transistor of the present invention. FIG.
In FIG. 1, reference numeral 1 denotes an insulating substrate on which a gate electrode 2, an insulating film 3, a semiconductor layer 4, a channel protective film 8, a semiconductor doping layer 5, and a source / drain electrode 6 are formed.

As described above, the gate electrode 2 on the insulating substrate 1
After the insulating film 3 and the semiconductor layer 4 are formed, and the channel protective film 8 is formed, the semiconductor doping layer 5 and the source / drain electrodes 6 are laminated, so that the surface of the gap is covered with the channel protective film. A channel stopper type thin film transistor configuration in which the end of the channel protective film is covered with the source / drain electrodes.

According to the present invention, even in such a channel stopper type thin film transistor, the thickness t2 of the semiconductor layer 4 below the source / drain electrode 6 is reduced by the thickness t1 of the semiconductor layer 4 in the gap between the source / drain. By making it thinner, the following effects can be expected.

Since the semiconductor layer in the gap between the source and the drain is thick, a high-quality semiconductor film can be used.
Further, since the diffusion of the dopant from the semiconductor doping layer 5 to the gap portion is suppressed, the shift of the threshold voltage or the increase of the off current can be prevented. Further, since the semiconductor layer under the source / drain portions is thin, the resistance under the source / drain portions is reduced, and the on-resistance is also reduced.

With reference to FIGS. 6A to 6C, a description will be given of a manufacturing process for manufacturing the thin film transistor shown in FIG.

An insulating substrate 1 is prepared. A gate electrode 2 having a layer thickness of 70 nm to 500 nm, more preferably 70 nm to 200 nm, is formed on the insulating surface of the insulating substrate 1.

Then, using a plasma CVD apparatus having a cluster type multi-chamber, the insulating film 3, the semiconductor layer 4,
The channel protective film 8 is formed continuously without breaking the vacuum.

At this time, the thickness of the insulating film 3 is 150 nm to 4 nm.
00 nm, more preferably from 200 nm to 350 nm,
The thickness t1 of the semiconductor layer 4 is 60 nm to 150 nm, and the thickness of the channel protection film 8 is 30 nm to 300 nm (see FIG. 6A).

Next, the channel protective film 8 is patterned so that the channel protective film 8 remains on the semiconductor layer 4 to be the gap, and subsequently, the layer thickness under the source / drain is made smaller than the gap. Next, the source / drain portions S and D of the semiconductor layer 4 are etched. Specifically, a resist (not shown) is formed on the channel protective film 8 on the gap C, and the resist is patterned on the source / drain portions S and D by an exposure apparatus so that the resist is removed. Then, portions of the channel protective film 8 and the semiconductor layer 4 that are not covered with the resist are etched by a dry etching apparatus. Thus, the layer thickness t of the semiconductor layer 4 below the source / drain electrodes
2 is set to about 30 nm to 70 nm.

In some cases, the semiconductor layer 4 under the source / drain electrodes is entirely etched to have a layer thickness t2.
May be set to zero. On the other hand, the thickness t1 of the semiconductor layer 4 in the gap is 60 nm to 150
nm (see FIG. 6B).

After the resist is stripped off after etching, a surface treatment with a solution containing a chelating agent or a plasma treatment in an atmosphere containing oxygen is used. After this treatment, the surface oxide film is treated with hydrofluoric acid. Is removed.

Next, after the structure of FIG. 6B is subjected to a hydrogen plasma treatment as required, a semiconductor doping layer 5 having a thickness of 20 nm to 70 nm is deposited so as to cover the channel protective film 8. Then, a conductor serving as a source / drain electrode is deposited (see FIG. 6C).

Then, the source / drain electrodes 6 are patterned, and subsequently, the semiconductor doping layer 5 is etched using the same resist as that used when the source / drain electrodes 6 are formed. At this time, since the channel protective film 8 serves as an etch stop layer when the semiconductor doping layer 5 is etched, the semiconductor layer 4 in the gap C is not etched.

Thus, a thin film transistor as shown in FIG. 5 is obtained.

(Embodiment 4) A manufacturing process for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 7A to 7E.

The insulating substrate 1 is prepared. A gate electrode 2 having a thickness of 70 nm to 200 nm is formed on the insulating surface of the insulating substrate 1. At this time, the sensor electrode 9 of the sensor unit 11 is simultaneously patterned using the same material as the gate electrode 2.

Then, using a plasma CVD apparatus having a cluster type multi-chamber, the insulating film 3, the semiconductor layer 4, and the channel protective film 8 are continuously formed without breaking the vacuum.

At this time, the thickness of the insulating film 3 is 150 nm to 4 nm.
00 nm, more preferably from 200 nm to 350 nm,
The thickness t1 of the semiconductor layer 4 is 300 nm to 1500 nm, more preferably 600 nm to 1500 nm, and the thickness of the channel protective film 8 is 30 nm to 300 nm (FIG. 7A).
reference).

Next, a not-shown resist is formed on the gap portion C and the channel protective film 8 on the sensor portion 11,
After the source / drain portions S and D are patterned by an exposure apparatus so as to remove the resist, the channel protective film 8 in a portion not covered with the resist is etched by a dry etching apparatus, and further covered with the resist. The portions of the semiconductor layer 4 that have not been etched are etched.
Thus, the thickness t2 of the semiconductor layer 4 below the source / drain electrodes is reduced to about 50 nm to 300 nm.
Then, unnecessary portions of the channel protective film 8 and the semiconductor layer 4 are removed, and isolation between the thin film transistor and the sensor unit and formation of a contact hole (not shown) are performed.

In some cases, the source / drain portions S, D
The semiconductor layer 4 may be entirely etched to make the layer thickness t2 zero. On the other hand, the thickness t1 of the semiconductor layer 4 in the gap portion
Is the layer thickness at the time of the first film formation, 300 nm to 1500 n
m, more preferably from 600 nm to 1500 nm (see FIG. 7B).

Next, the channel protective film 8 on the sensor section 11 is removed (see FIG. 7C). Then, after performing the resist stripping, using a plasma treatment performed in an atmosphere containing oxygen or a surface treatment with a solution containing a chelating agent,
After this treatment, the surface oxide film is removed with hydrofluoric acid.

Next, after the structure of FIG. 7C is subjected to a hydrogen plasma treatment as necessary, the thickness of the structure is 20 nm to 100 nm.
A semiconductor doping layer 5 having a thickness of m, more preferably 35 nm to 100 nm is deposited so as to cover the channel protective film 8 in the gap (see FIG. 7D), and then a conductor serving as a source / drain electrode is deposited.

Then, the source / drain electrodes 6 are patterned, and subsequently, the semiconductor doping layer 5 is etched using the same resist as that used when the source / drain electrodes 6 are formed.

Further, the conductor on the sensor section is patterned to form the wiring electrode 10 of the sensor section.

Thus, a thin film transistor as shown in FIG. 7E is obtained.

(Embodiment 5) A manufacturing process for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. 8A to 8E.

The insulating substrate 1 is prepared. A gate electrode 2 having a layer thickness of 70 nm to 500 nm, more preferably 70 nm to 200 nm, is formed on the insulating surface of the insulating substrate 1. At this time, the sensor electrode 9 of the sensor unit 11 is simultaneously patterned using the same material as the gate electrode 2.

Then, using a plasma CVD apparatus having a cluster type multi-chamber, the insulating film 3, the semiconductor layer 4, and the channel protective film 8 are continuously formed without breaking the vacuum.

At this time, the thickness of the insulating film 3 is 150 nm to 4 nm.
00 nm, more preferably from 200 nm to 350 nm,
The layer thickness t1 of the semiconductor layer 4 is 300 nm to 1500 nm, more preferably 600 nm to 1500 nm, and the layer thickness of the channel protection film 8 is 30 nm to 300 nm (FIG. 8A).
reference).

Next, after applying a positive resist (not shown), the resist of the source / drain portions S and D of the thin film transistor portion 12 is completely exposed using a halftone mask, and the resist of the sensor portion 11 is halved. Half exposure is performed with the following light amount. The resist is developed to leave the resist on the gap C and the resist having a thickness of about half on the sensor 11.

The resist is left in the gap C by the dry etching apparatus, but at least the channel protective film 8 is etched until the resist is no longer present on the sensor portion. Also etch. In this case, the source / drain parts S, D
Then, at least the protective film 8 and, if necessary, the underlying semiconductor layer 4 are etched, so that, for example, the semiconductor layer 4 has a thickness of t1 to t3 (see FIG. 8B).

Further, the protection film 8 is etched until at least the protection film 8 on the sensor portion 11 is eliminated, and the semiconductor layer 4 of the source / drain portions S and D is etched to reduce the thickness t2 to 50 nm to 300 nm. About.

Then, unnecessary portions of the channel protective film 8 and the semiconductor layer 4 are removed, and isolation between the thin film transistor and the sensor portion and formation of a contact hole (not shown) are performed (see FIG. 8C).

In some cases, the entire semiconductor layer 4 below the source / drain electrodes is etched to have a layer thickness t2.
May be set to zero. On the other hand, the thickness t1 of the semiconductor layer 4 in the gap is the thickness at the time of the first film formation.

After the resist is stripped, a surface treatment with a solution containing a chelating agent or a plasma treatment performed in an atmosphere containing oxygen is used. After this treatment, the surface oxide film is removed with hydrofluoric acid. I do.

Next, after the structure of FIG. 8C is subjected to a hydrogen plasma treatment as necessary, the thickness of the structure is 20 nm to 100 nm.
A semiconductor doping layer 5 having a thickness of m, more preferably 35 nm to 100 nm is deposited so as to cover the channel protection film 8 in the gap (see FIG. 8D), and then a conductor serving as a source / drain electrode is deposited.

Then, the source / drain electrodes 6 are patterned, and subsequently, the semiconductor doping layer 5 is etched using the same resist as that used when the source / drain electrodes 6 are formed.

Further, the conductor on the sensor section is patterned to form the wiring electrode 10 of the sensor section.

Thus, a thin film transistor as shown in FIG. 8E is obtained.

At the stage where the thin film transistors of Embodiments 3 to 5 described above can be formed, a protective film 7 as shown in FIG. 2 is formed by a CVD method as necessary. Protective film 7
Is preferably used as a silicon nitride film. The thickness of the layer depends on the level difference of the pattern in which the thin film transistor is formed.
00 nm to 2000 nm, more preferably 500 nm to
It is good to set it in the range of 2000 nm.

When manufacturing the radiation detecting device as shown in FIG. 3 using the third to fifth embodiments, the phosphor layer 18 is formed on the protective film 7 as shown in FIG. Then, when radiation is emitted, light may be converted by the phosphor layer 18 and detected by the MIS sensor unit 11 disposed below.

In the present embodiment, by forming the semiconductor layer 4 under the source / drain electrodes 6 of the thin film transistor to be thin, the series resistance due to the layer thickness component of the semiconductor layer of the thin film transistor is reduced, and the on-resistance is increased. Lower,
Improves transfer efficiency.

At the same time, regarding the gap, the semiconductor layer 4
By increasing the layer thickness to, for example, 60 nm or more, problems due to deterioration of the film quality are prevented. As a result, a thin film transistor with excellent characteristics and excellent transfer efficiency can be realized.

Further, since the semiconductor layer in the gap is not etched, there is no increase in off-current due to surface damage formed during gap etching. Further, since the sensor portion is not thinned so as to be etched as a whole and is formed of the semiconductor layer 4 having the same or slightly smaller thickness as the gap portion between the source and the drain, the light absorption rate in the sensor portion is secured. , A highly sensitive MIS type semiconductor sensor can be realized.
Further, since all the thin films constituting the MIS sensor unit 11 are formed simultaneously with the film forming the thin film transistor, the manufacturing process can be greatly simplified.

In the fourth and fifth embodiments, the case where the thin film transistor is mainly used for the photoelectric conversion device has been described as an example. However, the thin film transistor of the present invention is not limited to the photoelectric conversion device but may be, for example, a liquid crystal display device or an organic EL display. It can be suitably used for all semiconductor devices using thin film transistors.

By using the thin film transistor of the present invention in a liquid crystal display device, the response speed can be improved, and by making the thin film transistor small, the aperture ratio of the cell can be increased and the displayed image can be brightened. Furthermore, by using the thin film transistor of the present invention for a photoelectric conversion device, the driving speed can be improved, and the sensor sensitivity can be improved by increasing the aperture ratio.

[0139]

According to the present invention, it is possible to provide a thin film transistor which is excellent in transfer efficiency without increasing off current. Thus, even when integrated with the photoelectric conversion element, a decrease in the sensitivity of the photoelectric conversion element can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of an embodiment of a thin film transistor according to the present invention.

FIG. 2 is a cross-sectional view showing one embodiment of a photoelectric conversion device using a thin film transistor according to the present invention.

FIG. 3 is a diagram illustrating an equivalent circuit including a drive circuit of the photoelectric conversion device in FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing process of one embodiment of a photoelectric conversion device using a thin film transistor according to the present invention.

FIG. 5 is a sectional view showing another embodiment of the thin film transistor according to the present invention.

FIG. 6 is a cross-sectional view showing a step of manufacturing the thin film transistor shown in FIG.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of another embodiment of the photoelectric conversion device using the thin film transistor according to the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of still another embodiment of the photoelectric conversion device using the thin film transistor according to the present invention.

FIG. 9 is a cross-sectional view showing a configuration of a conventional gap-etch type thin film transistor.

FIG. 10 is a cross-sectional view showing a configuration of a conventional etch stopper type thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Gate electrode 3 Insulating film 4 Semiconductor layer 5 Semiconductor doping layer 6 Source / drain electrode 7 Protective film 8 Channel protective film 9 Lower sensor electrode 10 Upper electrode wiring 11 Sensor part 12 Thin film transistor part 13 Gate line 14 Signal line Reference Signs List 15 signal processing circuit section 16 common electrode driver circuit section 17 gate driver circuit section 18 phosphor layer 21 control device 22 computer 23 display device

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AB01 BA05 CA14 FB03 FB13 FB16 FB24 5F088 AA01 BA18 BB03 BB07 EA04 EA08 HA15 KA03 5F110 AA01 AA06 BB10 CC07 DD01 DD02 DD03 EE01 EE02 EE03 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 EE04 FF09 FF29 GG02 GG13 GG14 GG15 GG22 GG24 GG25 GG44 GG58 HK01 HK02 HK03 HK04 HK06 HK07 HK09 HK14 HK15 HK16 HK21 HK25 HK33 HK35 HM02 NN02 NN12 NN22 NN23 Q25 NN24 Q27 NN27

Claims (21)

[Claims] A gate electrode provided on an insulating surface of a substrate; a semiconductor layer provided on the gate electrode via a gate insulating layer; and a pair of semiconductor doping layers adjacent to the semiconductor layer. In a semiconductor device including a bottom-gate thin film transistor having a pair of a source / drain electrode made of a conductor adjacent to the semiconductor doping layer, a layer thickness of the semiconductor layer below the source / drain electrode may be A semiconductor device having a thickness smaller than a thickness of the semiconductor layer in a gap between a source and a drain electrode. 2. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer below the source / drain electrodes is selected from a range of 30 nm to 300 nm, and a thickness of the semiconductor layer in the gap portion is 60 nm to 1500 nm. The semiconductor device according to claim 1, wherein the semiconductor device is selected from a range. 3. The semiconductor device according to claim 1, wherein a thickness of said semiconductor layer below said source / drain electrodes is 0 nm. 4. The surface of the gap portion is formed on the source
2. The semiconductor device according to claim 1, wherein the semiconductor device is covered with a protective film covering the drain electrode.
3. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein a surface of said gap portion is covered with a channel protective film, and an end of said channel protective film is covered with said source / drain electrodes. 6. The semiconductor device according to claim 1, wherein said semiconductor doping layer is formed on said semiconductor layer thinned by etching. 7. The semiconductor device according to claim 1, further comprising a photoelectric conversion element provided on the insulating surface of the substrate. 8. The semiconductor device according to claim 7, wherein the photoelectric conversion element has a semiconductor layer of the same material and the same thickness as the semiconductor layer in the gap portion of the thin film transistor. 9. The semiconductor device according to claim 1, wherein the photoelectric conversion element includes a semiconductor layer having the same material and the same thickness as the semiconductor layer in the gap portion of the thin film transistor, and a semiconductor doping having the same material and the same layer thickness as the semiconductor doping layer. The semiconductor device according to claim 7, comprising a layer and an insulating layer having the same material and the same thickness as the gate insulating layer. 10. The pixel including the thin film transistor and the photoelectric conversion element is two-dimensionally arranged, and a layer for converting radiation into light is provided on the light incident side of the photoelectric conversion element. 2. The semiconductor device according to 1. 11. A gate electrode provided on an insulating surface of a substrate, a semiconductor layer provided on the gate electrode via a gate insulating layer, and a pair of semiconductor doping layers adjacent to the semiconductor layer. A method for manufacturing a semiconductor device including a bottom-gate thin film transistor having a pair of source and drain electrodes formed of a pair of conductors adjacent to the semiconductor doping layer, wherein a step of forming the semiconductor layer; A removing step of etching and removing a surface of the semiconductor layer which is a portion where the source / drain electrodes are to be formed, with the surface of the semiconductor layer serving as a gap portion covered with an etching mask; Forming the semiconductor doping layer on the portion where the source / drain is formed. The method of manufacturing a semiconductor device, which comprises a step, to form a pole. 12. An etching mask is removed after the removing step, and then, before forming the semiconductor doping layer, the portion removed by etching contains ammonia or hydrogen chloride and hydrogen peroxide. Surface treatment with a solution, surface treatment with a solution containing a chelating agent, or
The method of manufacturing a semiconductor device according to claim 11, wherein at least one type of surface treatment selected from surface treatment using oxygen plasma is performed. 13. After the removing step, an etching mask is removed, and thereafter, before forming the semiconductor doping layer, a surface treatment for removing an organic substance is performed on the portion removed by the etching, and 12. The method of manufacturing a semiconductor device according to claim 11, wherein the surface treatment is performed using a solution containing hydrogen fluoride. 14. An etching mask is removed after the removing step, and thereafter, before forming the semiconductor doping layer, a surface treatment using hydrogen plasma is performed in an apparatus for forming the semiconductor doping layer. A method for manufacturing a semiconductor device according to claim 11. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the discharge power of the plasma during the surface treatment using the hydrogen plasma is equal to or smaller than that when forming the semiconductor layer. 16. The discharge power of plasma during the surface treatment using the hydrogen plasma is equal to or lower than that when forming the semiconductor doping layer.
13. The method for manufacturing a semiconductor device according to item 5. 17. The method according to claim 11, wherein a channel protective film is formed on the semiconductor layer before the removing step. 18. A photoelectric conversion element is formed on an insulating surface of the substrate, and a semiconductor layer of the photoelectric conversion element is formed of the same material and the same thickness as the semiconductor layer in the gap of the thin film transistor. The method of manufacturing a semiconductor device according to claim 11, wherein the forming is performed. 19. In a state where the surface of the semiconductor layer of the photoelectric conversion element and the surface of the semiconductor layer of the thin film transistor are covered with a protective film, the surface of the semiconductor layer to be a part where the source / drain electrodes are to be formed is removed. Etch, and
19. The semiconductor according to claim 18, wherein the protection film covering the surface of the semiconductor layer of the photoelectric conversion element is etched, and the surface of the semiconductor layer that is to be a part where the source / drain electrodes are to be formed is further deeply etched. Device manufacturing method. 20. A radiation detecting apparatus according to claim 10, wherein
3. A radiation detection apparatus comprising: the semiconductor device according to claim 1; and a control device configured to process an image signal from the semiconductor device and transmit the processed image signal to the outside. 21. The radiation detection device according to claim 20, wherein the radiation detection device further includes a display device that displays an image.